./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 07:20:31,767 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 07:20:31,770 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 07:20:31,819 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 07:20:31,820 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 07:20:31,824 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 07:20:31,826 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 07:20:31,829 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 07:20:31,830 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 07:20:31,831 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 07:20:31,832 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 07:20:31,833 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 07:20:31,834 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 07:20:31,835 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 07:20:31,836 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 07:20:31,838 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 07:20:31,839 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 07:20:31,840 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 07:20:31,842 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 07:20:31,844 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 07:20:31,845 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 07:20:31,854 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 07:20:31,855 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 07:20:31,856 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 07:20:31,859 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 07:20:31,860 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 07:20:31,860 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 07:20:31,861 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 07:20:31,862 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 07:20:31,863 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 07:20:31,863 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 07:20:31,864 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 07:20:31,865 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 07:20:31,866 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 07:20:31,872 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 07:20:31,872 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 07:20:31,872 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 07:20:31,873 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 07:20:31,873 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 07:20:31,874 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 07:20:31,874 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 07:20:31,878 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 07:20:31,901 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 07:20:31,902 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 07:20:31,902 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 07:20:31,902 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 07:20:31,903 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 07:20:31,903 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 07:20:31,904 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 07:20:31,904 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 07:20:31,904 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 07:20:31,904 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 07:20:31,905 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 07:20:31,905 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 07:20:31,905 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 07:20:31,905 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 07:20:31,906 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 07:20:31,906 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 07:20:31,906 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 07:20:31,906 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 07:20:31,906 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 07:20:31,907 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 07:20:31,907 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 07:20:31,907 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 07:20:31,907 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 07:20:31,907 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 07:20:31,908 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 07:20:31,908 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 07:20:31,908 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 07:20:31,908 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 07:20:31,909 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 07:20:31,909 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 07:20:31,909 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 07:20:31,909 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 07:20:31,910 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 07:20:31,910 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2021-11-20 07:20:32,155 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 07:20:32,185 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 07:20:32,189 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 07:20:32,190 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 07:20:32,191 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 07:20:32,193 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2021-11-20 07:20:32,272 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/data/b2bdc3ba0/f40802c78e2b4635a537dba66871eba7/FLAG158547920 [2021-11-20 07:20:32,760 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 07:20:32,761 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/sv-benchmarks/c/systemc/transmitter.15.cil.c [2021-11-20 07:20:32,773 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/data/b2bdc3ba0/f40802c78e2b4635a537dba66871eba7/FLAG158547920 [2021-11-20 07:20:33,079 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/data/b2bdc3ba0/f40802c78e2b4635a537dba66871eba7 [2021-11-20 07:20:33,082 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 07:20:33,084 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 07:20:33,086 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 07:20:33,086 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 07:20:33,089 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 07:20:33,090 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,091 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@700b223 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33, skipping insertion in model container [2021-11-20 07:20:33,091 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,098 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 07:20:33,174 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 07:20:33,334 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2021-11-20 07:20:33,455 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 07:20:33,466 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 07:20:33,477 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2021-11-20 07:20:33,578 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 07:20:33,601 INFO L208 MainTranslator]: Completed translation [2021-11-20 07:20:33,602 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33 WrapperNode [2021-11-20 07:20:33,602 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 07:20:33,603 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 07:20:33,603 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 07:20:33,603 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 07:20:33,611 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,626 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,756 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2021-11-20 07:20:33,756 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 07:20:33,757 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 07:20:33,757 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 07:20:33,757 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 07:20:33,768 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,769 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,789 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,789 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,837 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,898 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,909 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,962 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 07:20:33,963 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 07:20:33,963 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 07:20:33,963 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 07:20:33,970 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (1/1) ... [2021-11-20 07:20:33,994 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 07:20:34,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 07:20:34,028 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 07:20:34,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5f28246-8b07-45a3-9a3c-9db3f76b7034/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 07:20:34,080 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 07:20:34,080 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 07:20:34,080 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 07:20:34,080 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 07:20:34,256 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 07:20:34,258 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 07:20:36,484 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 07:20:36,503 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 07:20:36,503 INFO L301 CfgBuilder]: Removed 17 assume(true) statements. [2021-11-20 07:20:36,507 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:20:36 BoogieIcfgContainer [2021-11-20 07:20:36,507 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 07:20:36,508 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 07:20:36,508 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 07:20:36,512 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 07:20:36,513 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:20:36,513 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 07:20:33" (1/3) ... [2021-11-20 07:20:36,514 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47b484f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 07:20:36, skipping insertion in model container [2021-11-20 07:20:36,514 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:20:36,514 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:20:33" (2/3) ... [2021-11-20 07:20:36,515 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47b484f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 07:20:36, skipping insertion in model container [2021-11-20 07:20:36,515 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:20:36,515 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:20:36" (3/3) ... [2021-11-20 07:20:36,516 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2021-11-20 07:20:36,557 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 07:20:36,557 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 07:20:36,557 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 07:20:36,558 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 07:20:36,558 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 07:20:36,558 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 07:20:36,558 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 07:20:36,558 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 07:20:36,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:36,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2021-11-20 07:20:36,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:36,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:36,753 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:36,753 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:36,753 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 07:20:36,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:36,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2021-11-20 07:20:36,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:36,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:36,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:36,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:36,798 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1833#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1759#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1072#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1401#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 795#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 683#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 803#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 833#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 920#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1814#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1399#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1365#L1273-1true assume !(0 == ~T4_E~0); 1748#L1278-1true assume !(0 == ~T5_E~0); 1152#L1283-1true assume !(0 == ~T6_E~0); 1780#L1288-1true assume !(0 == ~T7_E~0); 1568#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1539#L1298-1true assume !(0 == ~T9_E~0); 1383#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1838#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1789#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 973#L1338-1true assume !(0 == ~E_4~0); 1112#L1343-1true assume !(0 == ~E_5~0); 1650#L1348-1true assume !(0 == ~E_6~0); 1667#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 999#L1363-1true assume !(0 == ~E_9~0); 1061#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1101#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729#L607true assume 1 == ~m_pc~0; 1009#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1108#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1626#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667#L1560true assume !(0 != activate_threads_~tmp~1#1); 1724#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1266#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1907#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1336#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1300#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1899#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 652#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1704#L664true assume 1 == ~t3_pc~0; 1633#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1419#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L683true assume !(1 == ~t4_pc~0); 986#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 785#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 810#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1694#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 931#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1684#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 925#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1343#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1391#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1237#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1524#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 762#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1373#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1843#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 923#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1670#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1567#L778true assume 1 == ~t9_pc~0; 1341#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1273#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 733#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1306#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1181#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 696#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1390#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1511#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L835true assume 1 == ~t12_pc~0; 705#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1783#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1442#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1081#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1230#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1240#L1406-1true assume !(1 == ~T2_E~0); 858#L1411-1true assume !(1 == ~T3_E~0); 1611#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1014#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1772#L1451-1true assume !(1 == ~T11_E~0); 1107#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 744#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1767#L1471-1true assume !(1 == ~E_2~0); 1082#L1476-1true assume !(1 == ~E_3~0); 1314#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1037#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1171#L1892-2true [2021-11-20 07:20:36,801 INFO L793 eck$LassoCheckResult]: Loop: 1171#L1892-2true assume !false; 1867#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1513#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1629#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1898#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1618#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1905#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1620#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1788#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1168#L1298-3true assume !(0 == ~T9_E~0); 1693#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1427#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1167#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 658#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1301#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1672#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1055#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1540#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1311#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1352#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1884#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 884#L1378-3true assume !(0 == ~E_12~0); 1459#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1099#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1766#L607-42true assume !(1 == ~m_pc~0); 911#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1075#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 697#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1471#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1130#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L645-42true assume 1 == ~t2_pc~0; 1415#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1695#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1252#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1661#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1623#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1474#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 832#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1787#L683-42true assume 1 == ~t4_pc~0; 1698#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 840#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1768#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1411#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1903#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1733#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1287#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume 1 == ~t6_pc~0; 123#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1619#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1587#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 650#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1895#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 673#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 808#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1749#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L797-42true assume !(1 == ~t10_pc~0); 1045#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 937#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1375#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1876#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 809#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1708#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1851#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume !(1 == ~t12_pc~0); 507#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1243#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1837#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1236#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 949#L854-42true assume 1 == ~t13_pc~0; 1781#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1854#L1401-3true assume !(1 == ~M_E~0); 1093#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1679#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1052#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume !(1 == ~T8_E~0); 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1144#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1135#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1610#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1816#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume !(1 == ~E_3~0); 1686#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1481#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 881#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 874#L1516-3true assume !(1 == ~E_11~0); 1718#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 969#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1842#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1880#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 760#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1304#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 906#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1024#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 842#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1348#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1171#L1892-2true [2021-11-20 07:20:36,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:36,809 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2021-11-20 07:20:36,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:36,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212770241] [2021-11-20 07:20:36,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:36,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:36,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:37,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:37,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:37,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212770241] [2021-11-20 07:20:37,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212770241] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:37,062 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:37,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:37,064 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411436710] [2021-11-20 07:20:37,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:37,069 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:37,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:37,070 INFO L85 PathProgramCache]: Analyzing trace with hash 1403862028, now seen corresponding path program 1 times [2021-11-20 07:20:37,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:37,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733261950] [2021-11-20 07:20:37,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:37,071 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:37,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:37,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:37,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:37,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733261950] [2021-11-20 07:20:37,136 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733261950] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:37,136 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:37,136 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:20:37,137 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533667802] [2021-11-20 07:20:37,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:37,139 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:37,140 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:37,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-20 07:20:37,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-20 07:20:37,176 INFO L87 Difference]: Start difference. First operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:37,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:37,321 INFO L93 Difference]: Finished difference Result 1919 states and 2840 transitions. [2021-11-20 07:20:37,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-20 07:20:37,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1919 states and 2840 transitions. [2021-11-20 07:20:37,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:37,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1919 states to 1914 states and 2835 transitions. [2021-11-20 07:20:37,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:37,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:37,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2021-11-20 07:20:37,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:37,385 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-20 07:20:37,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2021-11-20 07:20:37,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:37,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:37,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2021-11-20 07:20:37,508 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-20 07:20:37,508 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-20 07:20:37,509 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 07:20:37,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2021-11-20 07:20:37,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:37,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:37,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:37,533 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:37,533 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:37,534 INFO L791 eck$LassoCheckResult]: Stem: 4709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4529#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4245#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4246#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5422#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4381#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4382#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4836#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4671#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4672#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4448#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4449#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4847#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5024#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5178#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5215#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4460#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5635#L1258-2 assume !(0 == ~T1_E~0); 4754#L1263-1 assume !(0 == ~T2_E~0); 4755#L1268-1 assume !(0 == ~T3_E~0); 5058#L1273-1 assume !(0 == ~T4_E~0); 5617#L1278-1 assume !(0 == ~T5_E~0); 5478#L1283-1 assume !(0 == ~T6_E~0); 5479#L1288-1 assume !(0 == ~T7_E~0); 5715#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5703#L1298-1 assume !(0 == ~T9_E~0); 5629#L1303-1 assume !(0 == ~T10_E~0); 4274#L1308-1 assume !(0 == ~T11_E~0); 4216#L1313-1 assume !(0 == ~T12_E~0); 4217#L1318-1 assume !(0 == ~T13_E~0); 4223#L1323-1 assume !(0 == ~E_1~0); 4224#L1328-1 assume !(0 == ~E_2~0); 4391#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5350#L1338-1 assume !(0 == ~E_4~0); 5351#L1343-1 assume !(0 == ~E_5~0); 5452#L1348-1 assume !(0 == ~E_6~0); 5738#L1353-1 assume !(0 == ~E_7~0); 5077#L1358-1 assume !(0 == ~E_8~0); 5078#L1363-1 assume !(0 == ~E_9~0); 5368#L1368-1 assume !(0 == ~E_10~0); 4053#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4054#L1378-1 assume !(0 == ~E_12~0); 4340#L1383-1 assume !(0 == ~E_13~0); 4341#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5084#L607 assume 1 == ~m_pc~0; 5085#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4411#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5450#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5004#L1560 assume !(0 != activate_threads_~tmp~1#1); 5005#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4236#L626 assume !(1 == ~t1_pc~0); 4237#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4505#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4506#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4675#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4137#L645 assume 1 == ~t2_pc~0; 4253#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4887#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4888#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4980#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4981#L664 assume 1 == ~t3_pc~0; 5737#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3977#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3978#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4636#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4637#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5645#L683 assume !(1 == ~t4_pc~0); 5200#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5152#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5153#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5187#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5311#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4930#L702 assume 1 == ~t5_pc~0; 4931#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4856#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5306#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5604#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5545#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4025#L721 assume !(1 == ~t6_pc~0); 3999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4163#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4645#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4646#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5247#L740 assume 1 == ~t7_pc~0; 4074#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3887#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3888#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3877#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3878#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4581#L759 assume !(1 == ~t8_pc~0); 4582#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4611#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5304#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5305#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5436#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5714#L778 assume 1 == ~t9_pc~0; 5601#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4052#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3992#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3921#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3922#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4249#L797 assume !(1 == ~t10_pc~0); 4250#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4368#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5502#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4752#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4753#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5042#L816 assume 1 == ~t11_pc~0; 3957#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3958#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4713#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4653#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5177#L835 assume 1 == ~t12_pc~0; 5055#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4121#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4143#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4284#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4809#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4810#L854 assume !(1 == ~t13_pc~0); 4450#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4451#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4501#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4161#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4162#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5541#L1401 assume !(1 == ~M_E~0); 4640#L1401-2 assume !(1 == ~T1_E~0); 4641#L1406-1 assume !(1 == ~T2_E~0); 5236#L1411-1 assume !(1 == ~T3_E~0); 5237#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4903#L1421-1 assume !(1 == ~T5_E~0); 4446#L1426-1 assume !(1 == ~T6_E~0); 4447#L1431-1 assume !(1 == ~T7_E~0); 3995#L1436-1 assume !(1 == ~T8_E~0); 3996#L1441-1 assume !(1 == ~T9_E~0); 4743#L1446-1 assume !(1 == ~T10_E~0); 4744#L1451-1 assume !(1 == ~T11_E~0); 5449#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5103#L1461-1 assume !(1 == ~T13_E~0); 4664#L1466-1 assume !(1 == ~E_1~0); 4665#L1471-1 assume !(1 == ~E_2~0); 5434#L1476-1 assume !(1 == ~E_3~0); 5435#L1481-1 assume !(1 == ~E_4~0); 5583#L1486-1 assume !(1 == ~E_5~0); 4289#L1491-1 assume !(1 == ~E_6~0); 3929#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3930#L1501-1 assume !(1 == ~E_8~0); 4741#L1506-1 assume !(1 == ~E_9~0); 4742#L1511-1 assume !(1 == ~E_10~0); 4698#L1516-1 assume !(1 == ~E_11~0); 3873#L1521-1 assume !(1 == ~E_12~0); 3874#L1526-1 assume !(1 == ~E_13~0); 3928#L1531-1 assume { :end_inline_reset_delta_events } true; 4471#L1892-2 [2021-11-20 07:20:37,537 INFO L793 eck$LassoCheckResult]: Loop: 4471#L1892-2 assume !false; 5494#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5692#L1233 assume !false; 5675#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5007#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4987#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5145#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3971#L1046 assume !(0 != eval_~tmp~0#1); 3973#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4007#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5179#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5736#L1258-5 assume !(0 == ~T1_E~0); 4149#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4150#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5728#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5735#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4373#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4374#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5491#L1298-3 assume !(0 == ~T9_E~0); 5492#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5651#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5490#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4991#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4151#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4152#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5575#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4294#L1338-3 assume !(0 == ~E_4~0); 4295#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5407#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5580#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5581#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4947#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4507#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4508#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5264#L1378-3 assume !(0 == ~E_12~0); 5265#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5446#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5447#L607-42 assume 1 == ~m_pc~0; 5060#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4788#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4789#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4521#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4522#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5043#L626-42 assume 1 == ~t1_pc~0; 4605#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4606#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4911#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5385#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5386#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5551#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4392#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3899#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3900#L664-42 assume !(1 == ~t3_pc~0); 4426#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5678#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5213#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5214#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5379#L683-42 assume 1 == ~t4_pc~0; 5744#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5088#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5220#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5640#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5641#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5485#L702-42 assume !(1 == ~t5_pc~0); 4597#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4598#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4894#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5567#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3915#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3916#L721-42 assume 1 == ~t6_pc~0; 4069#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4089#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4553#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5720#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4725#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4571#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4705#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4706#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4979#L759-42 assume 1 == ~t8_pc~0; 4828#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4760#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4761#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4839#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4840#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4935#L778-42 assume 1 == ~t9_pc~0; 4772#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4774#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5184#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5089#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5090#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5147#L797-42 assume 1 == ~t10_pc~0; 4314#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4315#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5316#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5625#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5185#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5186#L816-42 assume 1 == ~t11_pc~0; 3863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3864#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4406#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4407#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4486#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4487#L835-42 assume 1 == ~t12_pc~0; 4891#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4784#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4461#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4462#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5544#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5328#L854-42 assume 1 == ~t13_pc~0; 5329#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4405#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4015#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4016#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4662#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L1401-3 assume !(1 == ~M_E~0); 5441#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4252#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4116#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4117#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4716#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4717#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4292#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4293#L1436-3 assume !(1 == ~T8_E~0); 3879#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3880#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5469#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4800#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4453#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4454#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5731#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4393#L1476-3 assume !(1 == ~E_3~0); 4394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4794#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4421#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4422#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4834#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4835#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5261#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5251#L1516-3 assume !(1 == ~E_11~0); 5252#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4951#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4952#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5346#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4228#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5121#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4762#L1911 assume !(0 == start_simulation_~tmp~3#1); 4763#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5285#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4353#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5223#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4057#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4058#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4287#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4288#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4471#L1892-2 [2021-11-20 07:20:37,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:37,539 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2021-11-20 07:20:37,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:37,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107919650] [2021-11-20 07:20:37,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:37,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:37,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:37,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:37,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:37,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107919650] [2021-11-20 07:20:37,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107919650] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:37,712 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:37,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:37,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082249713] [2021-11-20 07:20:37,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:37,713 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:37,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:37,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1475252753, now seen corresponding path program 1 times [2021-11-20 07:20:37,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:37,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268926497] [2021-11-20 07:20:37,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:37,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:37,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:37,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:37,876 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:37,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268926497] [2021-11-20 07:20:37,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268926497] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:37,877 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:37,877 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:37,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764900815] [2021-11-20 07:20:37,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:37,878 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:37,878 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:37,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:37,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:37,879 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:37,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:37,945 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2021-11-20 07:20:37,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:37,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2021-11-20 07:20:37,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:37,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-11-20 07:20:37,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:37,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:37,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2021-11-20 07:20:37,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:37,988 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-20 07:20:37,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2021-11-20 07:20:38,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:38,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-11-20 07:20:38,074 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-20 07:20:38,074 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-20 07:20:38,074 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 07:20:38,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2021-11-20 07:20:38,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:38,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:38,093 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,093 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,094 INFO L791 eck$LassoCheckResult]: Stem: 8544#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8364#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8080#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8081#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9257#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9258#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8216#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8217#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8671#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8506#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8507#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8283#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8284#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8682#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8859#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9013#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9050#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8294#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8295#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9470#L1258-2 assume !(0 == ~T1_E~0); 8589#L1263-1 assume !(0 == ~T2_E~0); 8590#L1268-1 assume !(0 == ~T3_E~0); 8893#L1273-1 assume !(0 == ~T4_E~0); 9452#L1278-1 assume !(0 == ~T5_E~0); 9313#L1283-1 assume !(0 == ~T6_E~0); 9314#L1288-1 assume !(0 == ~T7_E~0); 9550#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9538#L1298-1 assume !(0 == ~T9_E~0); 9464#L1303-1 assume !(0 == ~T10_E~0); 8109#L1308-1 assume !(0 == ~T11_E~0); 8051#L1313-1 assume !(0 == ~T12_E~0); 8052#L1318-1 assume !(0 == ~T13_E~0); 8058#L1323-1 assume !(0 == ~E_1~0); 8059#L1328-1 assume !(0 == ~E_2~0); 8226#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9185#L1338-1 assume !(0 == ~E_4~0); 9186#L1343-1 assume !(0 == ~E_5~0); 9287#L1348-1 assume !(0 == ~E_6~0); 9573#L1353-1 assume !(0 == ~E_7~0); 8912#L1358-1 assume !(0 == ~E_8~0); 8913#L1363-1 assume !(0 == ~E_9~0); 9203#L1368-1 assume !(0 == ~E_10~0); 7888#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7889#L1378-1 assume !(0 == ~E_12~0); 8175#L1383-1 assume !(0 == ~E_13~0); 8176#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8919#L607 assume 1 == ~m_pc~0; 8920#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8246#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9285#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8839#L1560 assume !(0 != activate_threads_~tmp~1#1); 8840#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8071#L626 assume !(1 == ~t1_pc~0); 8072#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8340#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8341#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8510#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7971#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7972#L645 assume 1 == ~t2_pc~0; 8088#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8045#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8722#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8723#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8815#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8816#L664 assume 1 == ~t3_pc~0; 9572#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8471#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8472#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9480#L683 assume !(1 == ~t4_pc~0); 9035#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8987#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8988#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9022#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9146#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8765#L702 assume 1 == ~t5_pc~0; 8766#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8691#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9141#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9439#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9380#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7860#L721 assume !(1 == ~t6_pc~0); 7834#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7835#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7998#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8480#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8481#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9082#L740 assume 1 == ~t7_pc~0; 7909#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7722#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7723#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7712#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7713#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8416#L759 assume !(1 == ~t8_pc~0); 8417#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8446#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9139#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9140#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9271#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9549#L778 assume 1 == ~t9_pc~0; 9436#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7887#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7827#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7756#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7757#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8084#L797 assume !(1 == ~t10_pc~0); 8085#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8203#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9337#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8587#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8588#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8877#L816 assume 1 == ~t11_pc~0; 7792#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7793#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8548#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8487#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8488#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9012#L835 assume 1 == ~t12_pc~0; 8890#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7956#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7978#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8119#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8644#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8645#L854 assume !(1 == ~t13_pc~0); 8285#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8286#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8336#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7996#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7997#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9376#L1401 assume !(1 == ~M_E~0); 8475#L1401-2 assume !(1 == ~T1_E~0); 8476#L1406-1 assume !(1 == ~T2_E~0); 9071#L1411-1 assume !(1 == ~T3_E~0); 9072#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8738#L1421-1 assume !(1 == ~T5_E~0); 8281#L1426-1 assume !(1 == ~T6_E~0); 8282#L1431-1 assume !(1 == ~T7_E~0); 7830#L1436-1 assume !(1 == ~T8_E~0); 7831#L1441-1 assume !(1 == ~T9_E~0); 8578#L1446-1 assume !(1 == ~T10_E~0); 8579#L1451-1 assume !(1 == ~T11_E~0); 9284#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8938#L1461-1 assume !(1 == ~T13_E~0); 8499#L1466-1 assume !(1 == ~E_1~0); 8500#L1471-1 assume !(1 == ~E_2~0); 9269#L1476-1 assume !(1 == ~E_3~0); 9270#L1481-1 assume !(1 == ~E_4~0); 9418#L1486-1 assume !(1 == ~E_5~0); 8124#L1491-1 assume !(1 == ~E_6~0); 7764#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7765#L1501-1 assume !(1 == ~E_8~0); 8576#L1506-1 assume !(1 == ~E_9~0); 8577#L1511-1 assume !(1 == ~E_10~0); 8533#L1516-1 assume !(1 == ~E_11~0); 7708#L1521-1 assume !(1 == ~E_12~0); 7709#L1526-1 assume !(1 == ~E_13~0); 7763#L1531-1 assume { :end_inline_reset_delta_events } true; 8306#L1892-2 [2021-11-20 07:20:38,094 INFO L793 eck$LassoCheckResult]: Loop: 8306#L1892-2 assume !false; 9329#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9527#L1233 assume !false; 9510#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8842#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8822#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8980#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7806#L1046 assume !(0 != eval_~tmp~0#1); 7808#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7842#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9014#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9571#L1258-5 assume !(0 == ~T1_E~0); 7984#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7985#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9563#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9569#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9570#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8208#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8209#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9326#L1298-3 assume !(0 == ~T9_E~0); 9327#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9486#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9325#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8826#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7986#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7987#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9410#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8129#L1338-3 assume !(0 == ~E_4~0); 8130#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9242#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9415#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9416#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8782#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8342#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8343#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9099#L1378-3 assume !(0 == ~E_12~0); 9100#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9281#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9282#L607-42 assume !(1 == ~m_pc~0); 8896#L607-44 is_master_triggered_~__retres1~0#1 := 0; 8623#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8624#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8356#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8357#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8878#L626-42 assume 1 == ~t1_pc~0; 8440#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8441#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8745#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8746#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8020#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8021#L645-42 assume !(1 == ~t2_pc~0); 9220#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9221#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9386#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7734#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7735#L664-42 assume !(1 == ~t3_pc~0); 8261#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8262#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9513#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9048#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9049#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9214#L683-42 assume !(1 == ~t4_pc~0); 8922#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8923#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9055#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9475#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9476#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9320#L702-42 assume !(1 == ~t5_pc~0); 8432#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8433#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8729#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9402#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7750#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7751#L721-42 assume 1 == ~t6_pc~0; 7904#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7924#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8388#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9555#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8560#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8406#L740-42 assume 1 == ~t7_pc~0; 8407#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8144#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8685#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8540#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8541#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8814#L759-42 assume 1 == ~t8_pc~0; 8663#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8595#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8596#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8674#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8675#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8770#L778-42 assume !(1 == ~t9_pc~0); 8608#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8609#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9019#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8924#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8925#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8982#L797-42 assume 1 == ~t10_pc~0; 8149#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8150#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9151#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9460#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9020#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9021#L816-42 assume 1 == ~t11_pc~0; 7698#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7699#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8241#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8242#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8321#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8322#L835-42 assume 1 == ~t12_pc~0; 8726#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8619#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8296#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8297#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9379#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9163#L854-42 assume 1 == ~t13_pc~0; 9164#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8240#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7850#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7851#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8497#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8498#L1401-3 assume !(1 == ~M_E~0); 9276#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8087#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7951#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7952#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8551#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8552#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8127#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8128#L1436-3 assume !(1 == ~T8_E~0); 7714#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7715#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9304#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8635#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8288#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8289#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9566#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8228#L1476-3 assume !(1 == ~E_3~0); 8229#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8256#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8257#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8669#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8670#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9096#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9086#L1516-3 assume !(1 == ~E_11~0); 9087#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8786#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8787#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9181#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8063#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8956#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8597#L1911 assume !(0 == start_simulation_~tmp~3#1); 8598#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9120#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8188#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9058#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7892#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7893#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8122#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8123#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8306#L1892-2 [2021-11-20 07:20:38,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,098 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2021-11-20 07:20:38,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549424897] [2021-11-20 07:20:38,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,099 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549424897] [2021-11-20 07:20:38,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549424897] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,193 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,193 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,193 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962024411] [2021-11-20 07:20:38,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,194 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:38,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,195 INFO L85 PathProgramCache]: Analyzing trace with hash 673979855, now seen corresponding path program 1 times [2021-11-20 07:20:38,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343878534] [2021-11-20 07:20:38,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,195 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343878534] [2021-11-20 07:20:38,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343878534] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,303 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,303 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380308518] [2021-11-20 07:20:38,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,308 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:38,308 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:38,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:38,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:38,309 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:38,359 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2021-11-20 07:20:38,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:38,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2021-11-20 07:20:38,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-11-20 07:20:38,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:38,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:38,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2021-11-20 07:20:38,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:38,397 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-20 07:20:38,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2021-11-20 07:20:38,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:38,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-11-20 07:20:38,439 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-20 07:20:38,439 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-20 07:20:38,439 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 07:20:38,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2021-11-20 07:20:38,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:38,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:38,453 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,453 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,454 INFO L791 eck$LassoCheckResult]: Stem: 12379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12199#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11915#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11916#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13092#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13093#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12051#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12052#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12506#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12341#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12342#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12118#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12119#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12517#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12694#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12848#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12885#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12129#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12130#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13305#L1258-2 assume !(0 == ~T1_E~0); 12424#L1263-1 assume !(0 == ~T2_E~0); 12425#L1268-1 assume !(0 == ~T3_E~0); 12728#L1273-1 assume !(0 == ~T4_E~0); 13287#L1278-1 assume !(0 == ~T5_E~0); 13148#L1283-1 assume !(0 == ~T6_E~0); 13149#L1288-1 assume !(0 == ~T7_E~0); 13385#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13373#L1298-1 assume !(0 == ~T9_E~0); 13299#L1303-1 assume !(0 == ~T10_E~0); 11944#L1308-1 assume !(0 == ~T11_E~0); 11886#L1313-1 assume !(0 == ~T12_E~0); 11887#L1318-1 assume !(0 == ~T13_E~0); 11893#L1323-1 assume !(0 == ~E_1~0); 11894#L1328-1 assume !(0 == ~E_2~0); 12061#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13020#L1338-1 assume !(0 == ~E_4~0); 13021#L1343-1 assume !(0 == ~E_5~0); 13122#L1348-1 assume !(0 == ~E_6~0); 13408#L1353-1 assume !(0 == ~E_7~0); 12747#L1358-1 assume !(0 == ~E_8~0); 12748#L1363-1 assume !(0 == ~E_9~0); 13038#L1368-1 assume !(0 == ~E_10~0); 11723#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11724#L1378-1 assume !(0 == ~E_12~0); 12010#L1383-1 assume !(0 == ~E_13~0); 12011#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12754#L607 assume 1 == ~m_pc~0; 12755#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12081#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13120#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12674#L1560 assume !(0 != activate_threads_~tmp~1#1); 12675#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11906#L626 assume !(1 == ~t1_pc~0); 11907#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12175#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12176#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12345#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11806#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11807#L645 assume 1 == ~t2_pc~0; 11923#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12557#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12558#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12650#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12651#L664 assume 1 == ~t3_pc~0; 13407#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11647#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11648#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12306#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12307#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13315#L683 assume !(1 == ~t4_pc~0); 12870#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12822#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12823#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12857#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12981#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12600#L702 assume 1 == ~t5_pc~0; 12601#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12526#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12976#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13274#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13215#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11695#L721 assume !(1 == ~t6_pc~0); 11669#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11670#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11833#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12315#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12316#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12917#L740 assume 1 == ~t7_pc~0; 11744#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11557#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11558#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11547#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11548#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12251#L759 assume !(1 == ~t8_pc~0); 12252#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12281#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12974#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12975#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13106#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13384#L778 assume 1 == ~t9_pc~0; 13271#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11722#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11662#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11591#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11592#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11919#L797 assume !(1 == ~t10_pc~0); 11920#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12038#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13172#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12422#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12423#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12712#L816 assume 1 == ~t11_pc~0; 11627#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11628#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12383#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12322#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12323#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12847#L835 assume 1 == ~t12_pc~0; 12725#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11791#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11813#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11954#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12479#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12480#L854 assume !(1 == ~t13_pc~0); 12120#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12121#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12171#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11831#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11832#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13211#L1401 assume !(1 == ~M_E~0); 12310#L1401-2 assume !(1 == ~T1_E~0); 12311#L1406-1 assume !(1 == ~T2_E~0); 12906#L1411-1 assume !(1 == ~T3_E~0); 12907#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12573#L1421-1 assume !(1 == ~T5_E~0); 12116#L1426-1 assume !(1 == ~T6_E~0); 12117#L1431-1 assume !(1 == ~T7_E~0); 11665#L1436-1 assume !(1 == ~T8_E~0); 11666#L1441-1 assume !(1 == ~T9_E~0); 12413#L1446-1 assume !(1 == ~T10_E~0); 12414#L1451-1 assume !(1 == ~T11_E~0); 13119#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12773#L1461-1 assume !(1 == ~T13_E~0); 12334#L1466-1 assume !(1 == ~E_1~0); 12335#L1471-1 assume !(1 == ~E_2~0); 13104#L1476-1 assume !(1 == ~E_3~0); 13105#L1481-1 assume !(1 == ~E_4~0); 13253#L1486-1 assume !(1 == ~E_5~0); 11959#L1491-1 assume !(1 == ~E_6~0); 11599#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11600#L1501-1 assume !(1 == ~E_8~0); 12411#L1506-1 assume !(1 == ~E_9~0); 12412#L1511-1 assume !(1 == ~E_10~0); 12368#L1516-1 assume !(1 == ~E_11~0); 11543#L1521-1 assume !(1 == ~E_12~0); 11544#L1526-1 assume !(1 == ~E_13~0); 11598#L1531-1 assume { :end_inline_reset_delta_events } true; 12141#L1892-2 [2021-11-20 07:20:38,454 INFO L793 eck$LassoCheckResult]: Loop: 12141#L1892-2 assume !false; 13164#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13362#L1233 assume !false; 13345#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12677#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12657#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12815#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11641#L1046 assume !(0 != eval_~tmp~0#1); 11643#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11677#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12849#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13406#L1258-5 assume !(0 == ~T1_E~0); 11819#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11820#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13398#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13404#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13405#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12043#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12044#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13161#L1298-3 assume !(0 == ~T9_E~0); 13162#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13321#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13160#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12661#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11821#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11822#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13245#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L1338-3 assume !(0 == ~E_4~0); 11965#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13077#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13250#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13251#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12617#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12177#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12178#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12934#L1378-3 assume !(0 == ~E_12~0); 12935#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13116#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13117#L607-42 assume 1 == ~m_pc~0; 12730#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12458#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12459#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12191#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12192#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12713#L626-42 assume 1 == ~t1_pc~0; 12275#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12276#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12580#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12581#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11855#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11856#L645-42 assume 1 == ~t2_pc~0; 13314#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13056#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13221#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12062#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11569#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11570#L664-42 assume !(1 == ~t3_pc~0); 12096#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12097#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13348#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12883#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12884#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13049#L683-42 assume !(1 == ~t4_pc~0); 12757#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12758#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12890#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13310#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13311#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13155#L702-42 assume 1 == ~t5_pc~0; 12643#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12268#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12564#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13237#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11585#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11586#L721-42 assume 1 == ~t6_pc~0; 11739#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11759#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12223#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13390#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12395#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12241#L740-42 assume 1 == ~t7_pc~0; 12242#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11979#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12520#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12375#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12376#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12649#L759-42 assume 1 == ~t8_pc~0; 12498#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12430#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12431#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12509#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12510#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12605#L778-42 assume 1 == ~t9_pc~0; 12442#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12444#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12854#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12759#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12760#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12817#L797-42 assume 1 == ~t10_pc~0; 11984#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11985#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12986#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13295#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12856#L816-42 assume 1 == ~t11_pc~0; 11533#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11534#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12076#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12077#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12156#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12157#L835-42 assume 1 == ~t12_pc~0; 12561#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12454#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12131#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12132#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13214#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12998#L854-42 assume 1 == ~t13_pc~0; 12999#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12075#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11685#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11686#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12332#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12333#L1401-3 assume !(1 == ~M_E~0); 13111#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11922#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11786#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11787#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12386#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12387#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11962#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11963#L1436-3 assume !(1 == ~T8_E~0); 11549#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11550#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13139#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12470#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12123#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12124#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13401#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12063#L1476-3 assume !(1 == ~E_3~0); 12064#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12464#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12091#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12092#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12504#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12505#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12931#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12921#L1516-3 assume !(1 == ~E_11~0); 12922#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12621#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12622#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13016#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11898#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12791#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12432#L1911 assume !(0 == start_simulation_~tmp~3#1); 12433#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12955#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12023#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12893#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11727#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11728#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11957#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11958#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12141#L1892-2 [2021-11-20 07:20:38,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,455 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2021-11-20 07:20:38,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759593223] [2021-11-20 07:20:38,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759593223] [2021-11-20 07:20:38,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759593223] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,515 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174718855] [2021-11-20 07:20:38,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,520 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:38,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,520 INFO L85 PathProgramCache]: Analyzing trace with hash 1181403475, now seen corresponding path program 1 times [2021-11-20 07:20:38,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415968765] [2021-11-20 07:20:38,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,592 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415968765] [2021-11-20 07:20:38,593 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415968765] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,593 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,593 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887768564] [2021-11-20 07:20:38,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,594 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:38,594 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:38,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:38,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:38,596 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:38,675 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2021-11-20 07:20:38,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:38,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2021-11-20 07:20:38,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-11-20 07:20:38,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:38,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:38,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2021-11-20 07:20:38,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:38,710 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-20 07:20:38,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2021-11-20 07:20:38,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:38,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-11-20 07:20:38,752 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-20 07:20:38,752 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-20 07:20:38,752 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 07:20:38,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2021-11-20 07:20:38,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:38,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:38,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,767 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,767 INFO L791 eck$LassoCheckResult]: Stem: 16214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16034#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15750#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15751#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16927#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16928#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15886#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15887#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16341#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16176#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16177#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15953#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15954#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16352#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16529#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16683#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16720#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15964#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17140#L1258-2 assume !(0 == ~T1_E~0); 16259#L1263-1 assume !(0 == ~T2_E~0); 16260#L1268-1 assume !(0 == ~T3_E~0); 16563#L1273-1 assume !(0 == ~T4_E~0); 17122#L1278-1 assume !(0 == ~T5_E~0); 16983#L1283-1 assume !(0 == ~T6_E~0); 16984#L1288-1 assume !(0 == ~T7_E~0); 17220#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17208#L1298-1 assume !(0 == ~T9_E~0); 17134#L1303-1 assume !(0 == ~T10_E~0); 15779#L1308-1 assume !(0 == ~T11_E~0); 15721#L1313-1 assume !(0 == ~T12_E~0); 15722#L1318-1 assume !(0 == ~T13_E~0); 15728#L1323-1 assume !(0 == ~E_1~0); 15729#L1328-1 assume !(0 == ~E_2~0); 15896#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16855#L1338-1 assume !(0 == ~E_4~0); 16856#L1343-1 assume !(0 == ~E_5~0); 16957#L1348-1 assume !(0 == ~E_6~0); 17243#L1353-1 assume !(0 == ~E_7~0); 16582#L1358-1 assume !(0 == ~E_8~0); 16583#L1363-1 assume !(0 == ~E_9~0); 16873#L1368-1 assume !(0 == ~E_10~0); 15558#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15559#L1378-1 assume !(0 == ~E_12~0); 15845#L1383-1 assume !(0 == ~E_13~0); 15846#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16589#L607 assume 1 == ~m_pc~0; 16590#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15916#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16955#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16509#L1560 assume !(0 != activate_threads_~tmp~1#1); 16510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15741#L626 assume !(1 == ~t1_pc~0); 15742#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16010#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16011#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16180#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15641#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15642#L645 assume 1 == ~t2_pc~0; 15758#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15715#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16392#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16393#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16486#L664 assume 1 == ~t3_pc~0; 17242#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15482#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15483#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16141#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16142#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17150#L683 assume !(1 == ~t4_pc~0); 16705#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16692#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16816#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16435#L702 assume 1 == ~t5_pc~0; 16436#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16361#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16811#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17109#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17050#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15530#L721 assume !(1 == ~t6_pc~0); 15504#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15505#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15668#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16150#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16151#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16752#L740 assume 1 == ~t7_pc~0; 15579#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15392#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15393#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15382#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15383#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16086#L759 assume !(1 == ~t8_pc~0); 16087#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16116#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16809#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16810#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16941#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17219#L778 assume 1 == ~t9_pc~0; 17106#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15557#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15497#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15426#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15427#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15754#L797 assume !(1 == ~t10_pc~0); 15755#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15873#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17007#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16257#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16258#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16547#L816 assume 1 == ~t11_pc~0; 15462#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15463#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16218#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16157#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16158#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16682#L835 assume 1 == ~t12_pc~0; 16560#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15626#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15648#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15789#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16314#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16315#L854 assume !(1 == ~t13_pc~0); 15955#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15956#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16006#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15666#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15667#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17046#L1401 assume !(1 == ~M_E~0); 16145#L1401-2 assume !(1 == ~T1_E~0); 16146#L1406-1 assume !(1 == ~T2_E~0); 16741#L1411-1 assume !(1 == ~T3_E~0); 16742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16408#L1421-1 assume !(1 == ~T5_E~0); 15951#L1426-1 assume !(1 == ~T6_E~0); 15952#L1431-1 assume !(1 == ~T7_E~0); 15500#L1436-1 assume !(1 == ~T8_E~0); 15501#L1441-1 assume !(1 == ~T9_E~0); 16248#L1446-1 assume !(1 == ~T10_E~0); 16249#L1451-1 assume !(1 == ~T11_E~0); 16954#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16608#L1461-1 assume !(1 == ~T13_E~0); 16169#L1466-1 assume !(1 == ~E_1~0); 16170#L1471-1 assume !(1 == ~E_2~0); 16939#L1476-1 assume !(1 == ~E_3~0); 16940#L1481-1 assume !(1 == ~E_4~0); 17088#L1486-1 assume !(1 == ~E_5~0); 15794#L1491-1 assume !(1 == ~E_6~0); 15434#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15435#L1501-1 assume !(1 == ~E_8~0); 16246#L1506-1 assume !(1 == ~E_9~0); 16247#L1511-1 assume !(1 == ~E_10~0); 16203#L1516-1 assume !(1 == ~E_11~0); 15378#L1521-1 assume !(1 == ~E_12~0); 15379#L1526-1 assume !(1 == ~E_13~0); 15433#L1531-1 assume { :end_inline_reset_delta_events } true; 15976#L1892-2 [2021-11-20 07:20:38,767 INFO L793 eck$LassoCheckResult]: Loop: 15976#L1892-2 assume !false; 16999#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17197#L1233 assume !false; 17180#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15476#L1046 assume !(0 != eval_~tmp~0#1); 15478#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15512#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16684#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17241#L1258-5 assume !(0 == ~T1_E~0); 15654#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15655#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17233#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17239#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17240#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15878#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15879#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16996#L1298-3 assume !(0 == ~T9_E~0); 16997#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17156#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16995#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15656#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15657#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17080#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15799#L1338-3 assume !(0 == ~E_4~0); 15800#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16912#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17085#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17086#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16452#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16012#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16013#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16769#L1378-3 assume !(0 == ~E_12~0); 16770#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16951#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16952#L607-42 assume 1 == ~m_pc~0; 16565#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16293#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16294#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16026#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16027#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16548#L626-42 assume !(1 == ~t1_pc~0); 16112#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16111#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16415#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16416#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15690#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15691#L645-42 assume !(1 == ~t2_pc~0); 16890#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16891#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17056#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15897#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15404#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15405#L664-42 assume !(1 == ~t3_pc~0); 15931#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15932#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17183#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16718#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16719#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16884#L683-42 assume !(1 == ~t4_pc~0); 16592#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16593#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16725#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17145#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17146#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16990#L702-42 assume !(1 == ~t5_pc~0); 16102#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 16103#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16399#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17072#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15420#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15421#L721-42 assume 1 == ~t6_pc~0; 15574#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15594#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17225#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16230#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16076#L740-42 assume !(1 == ~t7_pc~0); 15813#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15814#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16355#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16210#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16211#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16484#L759-42 assume 1 == ~t8_pc~0; 16333#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16265#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16266#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16344#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16345#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16440#L778-42 assume 1 == ~t9_pc~0; 16277#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16279#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16689#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16652#L797-42 assume 1 == ~t10_pc~0; 15819#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15820#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16821#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17130#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16690#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16691#L816-42 assume 1 == ~t11_pc~0; 15368#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15369#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15911#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15912#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15991#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15992#L835-42 assume !(1 == ~t12_pc~0); 16288#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16289#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15966#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15967#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17049#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16833#L854-42 assume 1 == ~t13_pc~0; 16834#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15910#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15520#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15521#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16167#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16168#L1401-3 assume !(1 == ~M_E~0); 16946#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15757#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15621#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15622#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16221#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16222#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15797#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15798#L1436-3 assume !(1 == ~T8_E~0); 15384#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15385#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16974#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16305#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15958#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 15959#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17236#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15898#L1476-3 assume !(1 == ~E_3~0); 15899#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16299#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15926#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15927#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16339#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16340#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16766#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16756#L1516-3 assume !(1 == ~E_11~0); 16757#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16456#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16457#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16851#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15733#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16267#L1911 assume !(0 == start_simulation_~tmp~3#1); 16268#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16790#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15858#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16728#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15562#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15563#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15792#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15793#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15976#L1892-2 [2021-11-20 07:20:38,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2021-11-20 07:20:38,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493475712] [2021-11-20 07:20:38,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493475712] [2021-11-20 07:20:38,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493475712] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997519053] [2021-11-20 07:20:38,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,812 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:38,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1106627154, now seen corresponding path program 1 times [2021-11-20 07:20:38,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125556835] [2021-11-20 07:20:38,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,814 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:38,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:38,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:38,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:38,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125556835] [2021-11-20 07:20:38,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125556835] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:38,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:38,866 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:38,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855194177] [2021-11-20 07:20:38,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:38,866 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:38,867 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:38,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:38,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:38,867 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:38,909 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2021-11-20 07:20:38,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:38,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2021-11-20 07:20:38,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-11-20 07:20:38,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:38,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:38,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2021-11-20 07:20:38,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:38,944 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-20 07:20:38,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2021-11-20 07:20:38,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:38,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:38,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-11-20 07:20:38,986 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-20 07:20:38,986 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-20 07:20:38,986 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 07:20:38,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2021-11-20 07:20:38,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:38,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:38,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:38,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:38,997 INFO L791 eck$LassoCheckResult]: Stem: 20049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19869#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19585#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19586#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20762#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20763#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19721#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19722#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20176#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20011#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20012#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19788#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19789#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20187#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20364#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20518#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20555#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19799#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19800#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20975#L1258-2 assume !(0 == ~T1_E~0); 20094#L1263-1 assume !(0 == ~T2_E~0); 20095#L1268-1 assume !(0 == ~T3_E~0); 20398#L1273-1 assume !(0 == ~T4_E~0); 20957#L1278-1 assume !(0 == ~T5_E~0); 20818#L1283-1 assume !(0 == ~T6_E~0); 20819#L1288-1 assume !(0 == ~T7_E~0); 21055#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21043#L1298-1 assume !(0 == ~T9_E~0); 20969#L1303-1 assume !(0 == ~T10_E~0); 19614#L1308-1 assume !(0 == ~T11_E~0); 19556#L1313-1 assume !(0 == ~T12_E~0); 19557#L1318-1 assume !(0 == ~T13_E~0); 19563#L1323-1 assume !(0 == ~E_1~0); 19564#L1328-1 assume !(0 == ~E_2~0); 19731#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20690#L1338-1 assume !(0 == ~E_4~0); 20691#L1343-1 assume !(0 == ~E_5~0); 20792#L1348-1 assume !(0 == ~E_6~0); 21078#L1353-1 assume !(0 == ~E_7~0); 20417#L1358-1 assume !(0 == ~E_8~0); 20418#L1363-1 assume !(0 == ~E_9~0); 20708#L1368-1 assume !(0 == ~E_10~0); 19393#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19394#L1378-1 assume !(0 == ~E_12~0); 19680#L1383-1 assume !(0 == ~E_13~0); 19681#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20424#L607 assume 1 == ~m_pc~0; 20425#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19751#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20790#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20344#L1560 assume !(0 != activate_threads_~tmp~1#1); 20345#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19576#L626 assume !(1 == ~t1_pc~0); 19577#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19845#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19846#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20015#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19476#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19477#L645 assume 1 == ~t2_pc~0; 19593#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19550#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20227#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20228#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20320#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20321#L664 assume 1 == ~t3_pc~0; 21077#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19317#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19318#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19976#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19977#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20985#L683 assume !(1 == ~t4_pc~0); 20540#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20492#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20493#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20527#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20651#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20270#L702 assume 1 == ~t5_pc~0; 20271#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20196#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20646#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20944#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20885#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19365#L721 assume !(1 == ~t6_pc~0); 19339#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19340#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19503#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19985#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19986#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20587#L740 assume 1 == ~t7_pc~0; 19414#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19227#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19228#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19217#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19218#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19921#L759 assume !(1 == ~t8_pc~0); 19922#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19951#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20644#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20645#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20776#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21054#L778 assume 1 == ~t9_pc~0; 20941#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19392#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19332#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19261#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19262#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19589#L797 assume !(1 == ~t10_pc~0); 19590#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19708#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20842#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20092#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20093#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20382#L816 assume 1 == ~t11_pc~0; 19297#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19298#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20053#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19992#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19993#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20517#L835 assume 1 == ~t12_pc~0; 20395#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19461#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19483#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19624#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20149#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20150#L854 assume !(1 == ~t13_pc~0); 19790#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19791#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19841#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19501#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19502#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20881#L1401 assume !(1 == ~M_E~0); 19980#L1401-2 assume !(1 == ~T1_E~0); 19981#L1406-1 assume !(1 == ~T2_E~0); 20576#L1411-1 assume !(1 == ~T3_E~0); 20577#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20243#L1421-1 assume !(1 == ~T5_E~0); 19786#L1426-1 assume !(1 == ~T6_E~0); 19787#L1431-1 assume !(1 == ~T7_E~0); 19335#L1436-1 assume !(1 == ~T8_E~0); 19336#L1441-1 assume !(1 == ~T9_E~0); 20083#L1446-1 assume !(1 == ~T10_E~0); 20084#L1451-1 assume !(1 == ~T11_E~0); 20789#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20443#L1461-1 assume !(1 == ~T13_E~0); 20004#L1466-1 assume !(1 == ~E_1~0); 20005#L1471-1 assume !(1 == ~E_2~0); 20774#L1476-1 assume !(1 == ~E_3~0); 20775#L1481-1 assume !(1 == ~E_4~0); 20923#L1486-1 assume !(1 == ~E_5~0); 19629#L1491-1 assume !(1 == ~E_6~0); 19269#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19270#L1501-1 assume !(1 == ~E_8~0); 20081#L1506-1 assume !(1 == ~E_9~0); 20082#L1511-1 assume !(1 == ~E_10~0); 20038#L1516-1 assume !(1 == ~E_11~0); 19213#L1521-1 assume !(1 == ~E_12~0); 19214#L1526-1 assume !(1 == ~E_13~0); 19268#L1531-1 assume { :end_inline_reset_delta_events } true; 19811#L1892-2 [2021-11-20 07:20:38,998 INFO L793 eck$LassoCheckResult]: Loop: 19811#L1892-2 assume !false; 20834#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21032#L1233 assume !false; 21015#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20347#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20327#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20485#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19311#L1046 assume !(0 != eval_~tmp~0#1); 19313#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19347#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20519#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21076#L1258-5 assume !(0 == ~T1_E~0); 19489#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19490#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21068#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21074#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21075#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19713#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19714#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20831#L1298-3 assume !(0 == ~T9_E~0); 20832#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20991#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20830#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20331#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19491#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19492#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20915#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19634#L1338-3 assume !(0 == ~E_4~0); 19635#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20747#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20920#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20921#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20287#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19847#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19848#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20604#L1378-3 assume !(0 == ~E_12~0); 20605#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20786#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20787#L607-42 assume 1 == ~m_pc~0; 20400#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20128#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20129#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19861#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19862#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20383#L626-42 assume 1 == ~t1_pc~0; 19945#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19946#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20250#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20251#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19525#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19526#L645-42 assume !(1 == ~t2_pc~0); 20725#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20726#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20891#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19732#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19239#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19240#L664-42 assume !(1 == ~t3_pc~0); 19766#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19767#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21018#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20553#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20554#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20719#L683-42 assume !(1 == ~t4_pc~0); 20427#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20428#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20560#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20980#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20981#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20825#L702-42 assume !(1 == ~t5_pc~0); 19937#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19938#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20234#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20907#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19255#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19256#L721-42 assume 1 == ~t6_pc~0; 19409#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19429#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19893#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21060#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20065#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19911#L740-42 assume !(1 == ~t7_pc~0); 19648#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19649#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20190#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20045#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20046#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20319#L759-42 assume 1 == ~t8_pc~0; 20168#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20100#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20101#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20179#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20180#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20275#L778-42 assume 1 == ~t9_pc~0; 20112#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20114#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20524#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20429#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20430#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20487#L797-42 assume 1 == ~t10_pc~0; 19654#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19655#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20656#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20965#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20525#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20526#L816-42 assume 1 == ~t11_pc~0; 19203#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19204#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19746#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19747#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19826#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19827#L835-42 assume 1 == ~t12_pc~0; 20231#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20124#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19801#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19802#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20884#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20668#L854-42 assume !(1 == ~t13_pc~0); 19744#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19745#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19355#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19356#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20002#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20003#L1401-3 assume !(1 == ~M_E~0); 20781#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19592#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19456#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19457#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20056#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20057#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19632#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19633#L1436-3 assume !(1 == ~T8_E~0); 19219#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19220#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20809#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20140#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19793#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19794#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19733#L1476-3 assume !(1 == ~E_3~0); 19734#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20134#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19761#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19762#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20174#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20175#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20601#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20591#L1516-3 assume !(1 == ~E_11~0); 20592#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20291#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20292#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20686#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19568#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20461#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20102#L1911 assume !(0 == start_simulation_~tmp~3#1); 20103#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20625#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19693#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20563#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19397#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19398#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19627#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19628#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19811#L1892-2 [2021-11-20 07:20:38,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:38,999 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2021-11-20 07:20:38,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:38,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673821859] [2021-11-20 07:20:38,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:38,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,059 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673821859] [2021-11-20 07:20:39,060 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673821859] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,060 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,060 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,060 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974431631] [2021-11-20 07:20:39,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,062 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:39,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,064 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 1 times [2021-11-20 07:20:39,064 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12147187] [2021-11-20 07:20:39,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,118 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12147187] [2021-11-20 07:20:39,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12147187] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,125 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058517096] [2021-11-20 07:20:39,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,126 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:39,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:39,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:39,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:39,127 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:39,167 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2021-11-20 07:20:39,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:39,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2021-11-20 07:20:39,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-11-20 07:20:39,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:39,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:39,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2021-11-20 07:20:39,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:39,202 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-20 07:20:39,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2021-11-20 07:20:39,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:39,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-11-20 07:20:39,245 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-20 07:20:39,245 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-20 07:20:39,245 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 07:20:39,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2021-11-20 07:20:39,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:39,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:39,256 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,256 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,256 INFO L791 eck$LassoCheckResult]: Stem: 23884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23704#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23420#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23421#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24597#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24598#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23556#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23557#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24011#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23846#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23847#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23623#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23624#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24022#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24199#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24353#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24390#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23634#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23635#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24810#L1258-2 assume !(0 == ~T1_E~0); 23929#L1263-1 assume !(0 == ~T2_E~0); 23930#L1268-1 assume !(0 == ~T3_E~0); 24233#L1273-1 assume !(0 == ~T4_E~0); 24792#L1278-1 assume !(0 == ~T5_E~0); 24653#L1283-1 assume !(0 == ~T6_E~0); 24654#L1288-1 assume !(0 == ~T7_E~0); 24890#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24878#L1298-1 assume !(0 == ~T9_E~0); 24804#L1303-1 assume !(0 == ~T10_E~0); 23449#L1308-1 assume !(0 == ~T11_E~0); 23391#L1313-1 assume !(0 == ~T12_E~0); 23392#L1318-1 assume !(0 == ~T13_E~0); 23398#L1323-1 assume !(0 == ~E_1~0); 23399#L1328-1 assume !(0 == ~E_2~0); 23566#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24525#L1338-1 assume !(0 == ~E_4~0); 24526#L1343-1 assume !(0 == ~E_5~0); 24627#L1348-1 assume !(0 == ~E_6~0); 24913#L1353-1 assume !(0 == ~E_7~0); 24252#L1358-1 assume !(0 == ~E_8~0); 24253#L1363-1 assume !(0 == ~E_9~0); 24543#L1368-1 assume !(0 == ~E_10~0); 23228#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23229#L1378-1 assume !(0 == ~E_12~0); 23515#L1383-1 assume !(0 == ~E_13~0); 23516#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24259#L607 assume 1 == ~m_pc~0; 24260#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23586#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24625#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24179#L1560 assume !(0 != activate_threads_~tmp~1#1); 24180#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23411#L626 assume !(1 == ~t1_pc~0); 23412#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23680#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23681#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23850#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23311#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23312#L645 assume 1 == ~t2_pc~0; 23428#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23385#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24062#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24063#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24155#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24156#L664 assume 1 == ~t3_pc~0; 24912#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23152#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23153#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23811#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23812#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24820#L683 assume !(1 == ~t4_pc~0); 24375#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24327#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24328#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24362#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24486#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24105#L702 assume 1 == ~t5_pc~0; 24106#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24031#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24481#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24779#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24720#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23200#L721 assume !(1 == ~t6_pc~0); 23174#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23175#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23338#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23820#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23821#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24422#L740 assume 1 == ~t7_pc~0; 23249#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23062#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23063#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23052#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23053#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23756#L759 assume !(1 == ~t8_pc~0); 23757#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23786#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24479#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24480#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24611#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24889#L778 assume 1 == ~t9_pc~0; 24776#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23227#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23167#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23096#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23097#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23424#L797 assume !(1 == ~t10_pc~0); 23425#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23543#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24677#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23927#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23928#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24217#L816 assume 1 == ~t11_pc~0; 23132#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23133#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23888#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23827#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23828#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24352#L835 assume 1 == ~t12_pc~0; 24230#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23296#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23318#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23459#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23984#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23985#L854 assume !(1 == ~t13_pc~0); 23625#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23626#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23676#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23336#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23337#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24716#L1401 assume !(1 == ~M_E~0); 23815#L1401-2 assume !(1 == ~T1_E~0); 23816#L1406-1 assume !(1 == ~T2_E~0); 24411#L1411-1 assume !(1 == ~T3_E~0); 24412#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24078#L1421-1 assume !(1 == ~T5_E~0); 23621#L1426-1 assume !(1 == ~T6_E~0); 23622#L1431-1 assume !(1 == ~T7_E~0); 23170#L1436-1 assume !(1 == ~T8_E~0); 23171#L1441-1 assume !(1 == ~T9_E~0); 23918#L1446-1 assume !(1 == ~T10_E~0); 23919#L1451-1 assume !(1 == ~T11_E~0); 24624#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24278#L1461-1 assume !(1 == ~T13_E~0); 23839#L1466-1 assume !(1 == ~E_1~0); 23840#L1471-1 assume !(1 == ~E_2~0); 24609#L1476-1 assume !(1 == ~E_3~0); 24610#L1481-1 assume !(1 == ~E_4~0); 24758#L1486-1 assume !(1 == ~E_5~0); 23464#L1491-1 assume !(1 == ~E_6~0); 23104#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23105#L1501-1 assume !(1 == ~E_8~0); 23916#L1506-1 assume !(1 == ~E_9~0); 23917#L1511-1 assume !(1 == ~E_10~0); 23873#L1516-1 assume !(1 == ~E_11~0); 23048#L1521-1 assume !(1 == ~E_12~0); 23049#L1526-1 assume !(1 == ~E_13~0); 23103#L1531-1 assume { :end_inline_reset_delta_events } true; 23646#L1892-2 [2021-11-20 07:20:39,257 INFO L793 eck$LassoCheckResult]: Loop: 23646#L1892-2 assume !false; 24669#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24867#L1233 assume !false; 24850#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24182#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24162#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24320#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23146#L1046 assume !(0 != eval_~tmp~0#1); 23148#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23182#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24354#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24911#L1258-5 assume !(0 == ~T1_E~0); 23324#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23325#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24903#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24909#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24910#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23548#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23549#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24666#L1298-3 assume !(0 == ~T9_E~0); 24667#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24826#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24665#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24166#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23326#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23327#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24750#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23469#L1338-3 assume !(0 == ~E_4~0); 23470#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24582#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24755#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24756#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24122#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23682#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23683#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24439#L1378-3 assume !(0 == ~E_12~0); 24440#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24621#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L607-42 assume 1 == ~m_pc~0; 24235#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23963#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23964#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23696#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23697#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24218#L626-42 assume 1 == ~t1_pc~0; 23780#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23781#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24085#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24086#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23360#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23361#L645-42 assume !(1 == ~t2_pc~0); 24560#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24561#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24726#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23567#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23074#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23075#L664-42 assume !(1 == ~t3_pc~0); 23601#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23602#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24853#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24388#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24389#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24554#L683-42 assume !(1 == ~t4_pc~0); 24262#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24263#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24395#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24815#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24816#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24660#L702-42 assume 1 == ~t5_pc~0; 24148#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23773#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24069#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24742#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23090#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23091#L721-42 assume 1 == ~t6_pc~0; 23244#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23264#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23728#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24895#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23900#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23746#L740-42 assume 1 == ~t7_pc~0; 23747#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23484#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24025#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23880#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23881#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24154#L759-42 assume 1 == ~t8_pc~0; 24003#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23935#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23936#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24014#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24015#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24110#L778-42 assume 1 == ~t9_pc~0; 23947#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23949#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24359#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24264#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24265#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24322#L797-42 assume 1 == ~t10_pc~0; 23489#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23490#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24491#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24800#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24360#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24361#L816-42 assume !(1 == ~t11_pc~0); 23040#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 23039#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23581#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23582#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23661#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23662#L835-42 assume 1 == ~t12_pc~0; 24066#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23959#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23636#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23637#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24719#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24503#L854-42 assume 1 == ~t13_pc~0; 24504#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23580#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23190#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23191#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23837#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23838#L1401-3 assume !(1 == ~M_E~0); 24616#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23427#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23291#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23292#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23891#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23892#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23467#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23468#L1436-3 assume !(1 == ~T8_E~0); 23054#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23055#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24644#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23975#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23628#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23629#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24906#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23568#L1476-3 assume !(1 == ~E_3~0); 23569#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23969#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23596#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23597#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24009#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24010#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24436#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24426#L1516-3 assume !(1 == ~E_11~0); 24427#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24126#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24127#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24521#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23403#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24296#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23937#L1911 assume !(0 == start_simulation_~tmp~3#1); 23938#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24460#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23528#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24398#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23232#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23233#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23462#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23463#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23646#L1892-2 [2021-11-20 07:20:39,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,257 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2021-11-20 07:20:39,257 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743066353] [2021-11-20 07:20:39,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,258 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,295 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743066353] [2021-11-20 07:20:39,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743066353] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,296 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,296 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339432409] [2021-11-20 07:20:39,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,296 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:39,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 1 times [2021-11-20 07:20:39,297 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163854784] [2021-11-20 07:20:39,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,372 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163854784] [2021-11-20 07:20:39,372 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163854784] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,372 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,372 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334370636] [2021-11-20 07:20:39,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,373 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:39,373 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:39,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:39,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:39,374 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:39,416 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2021-11-20 07:20:39,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:39,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2021-11-20 07:20:39,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-11-20 07:20:39,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:39,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:39,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2021-11-20 07:20:39,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:39,477 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-20 07:20:39,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2021-11-20 07:20:39,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:39,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-11-20 07:20:39,525 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-20 07:20:39,525 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-20 07:20:39,526 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 07:20:39,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2021-11-20 07:20:39,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:39,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:39,538 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,538 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,539 INFO L791 eck$LassoCheckResult]: Stem: 27719#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27539#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27255#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27256#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28432#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28433#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27391#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27392#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27846#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27681#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27682#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27458#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27459#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27857#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28034#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28188#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28225#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27469#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27470#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28645#L1258-2 assume !(0 == ~T1_E~0); 27764#L1263-1 assume !(0 == ~T2_E~0); 27765#L1268-1 assume !(0 == ~T3_E~0); 28068#L1273-1 assume !(0 == ~T4_E~0); 28627#L1278-1 assume !(0 == ~T5_E~0); 28488#L1283-1 assume !(0 == ~T6_E~0); 28489#L1288-1 assume !(0 == ~T7_E~0); 28725#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28713#L1298-1 assume !(0 == ~T9_E~0); 28639#L1303-1 assume !(0 == ~T10_E~0); 27284#L1308-1 assume !(0 == ~T11_E~0); 27226#L1313-1 assume !(0 == ~T12_E~0); 27227#L1318-1 assume !(0 == ~T13_E~0); 27233#L1323-1 assume !(0 == ~E_1~0); 27234#L1328-1 assume !(0 == ~E_2~0); 27401#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28360#L1338-1 assume !(0 == ~E_4~0); 28361#L1343-1 assume !(0 == ~E_5~0); 28462#L1348-1 assume !(0 == ~E_6~0); 28748#L1353-1 assume !(0 == ~E_7~0); 28087#L1358-1 assume !(0 == ~E_8~0); 28088#L1363-1 assume !(0 == ~E_9~0); 28378#L1368-1 assume !(0 == ~E_10~0); 27063#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27064#L1378-1 assume !(0 == ~E_12~0); 27350#L1383-1 assume !(0 == ~E_13~0); 27351#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28094#L607 assume 1 == ~m_pc~0; 28095#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27421#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28460#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28014#L1560 assume !(0 != activate_threads_~tmp~1#1); 28015#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27246#L626 assume !(1 == ~t1_pc~0); 27247#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27515#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27516#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27685#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27146#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27147#L645 assume 1 == ~t2_pc~0; 27263#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27220#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27897#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27898#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27990#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27991#L664 assume 1 == ~t3_pc~0; 28747#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26987#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26988#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27646#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27647#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28655#L683 assume !(1 == ~t4_pc~0); 28210#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28162#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28163#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28197#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28321#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27940#L702 assume 1 == ~t5_pc~0; 27941#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27866#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28316#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28614#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28555#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27035#L721 assume !(1 == ~t6_pc~0); 27009#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27010#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27173#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27655#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27656#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28257#L740 assume 1 == ~t7_pc~0; 27084#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26897#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26898#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26887#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26888#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27591#L759 assume !(1 == ~t8_pc~0); 27592#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27621#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28314#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28315#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28446#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28724#L778 assume 1 == ~t9_pc~0; 28611#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27062#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27002#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26931#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26932#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27259#L797 assume !(1 == ~t10_pc~0); 27260#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27378#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28512#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27762#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27763#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28052#L816 assume 1 == ~t11_pc~0; 26967#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26968#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27723#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27662#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27663#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28187#L835 assume 1 == ~t12_pc~0; 28065#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27131#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27153#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27294#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27819#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27820#L854 assume !(1 == ~t13_pc~0); 27460#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27461#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27511#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27171#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27172#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28551#L1401 assume !(1 == ~M_E~0); 27650#L1401-2 assume !(1 == ~T1_E~0); 27651#L1406-1 assume !(1 == ~T2_E~0); 28246#L1411-1 assume !(1 == ~T3_E~0); 28247#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27913#L1421-1 assume !(1 == ~T5_E~0); 27456#L1426-1 assume !(1 == ~T6_E~0); 27457#L1431-1 assume !(1 == ~T7_E~0); 27005#L1436-1 assume !(1 == ~T8_E~0); 27006#L1441-1 assume !(1 == ~T9_E~0); 27753#L1446-1 assume !(1 == ~T10_E~0); 27754#L1451-1 assume !(1 == ~T11_E~0); 28459#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28113#L1461-1 assume !(1 == ~T13_E~0); 27674#L1466-1 assume !(1 == ~E_1~0); 27675#L1471-1 assume !(1 == ~E_2~0); 28444#L1476-1 assume !(1 == ~E_3~0); 28445#L1481-1 assume !(1 == ~E_4~0); 28593#L1486-1 assume !(1 == ~E_5~0); 27299#L1491-1 assume !(1 == ~E_6~0); 26939#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26940#L1501-1 assume !(1 == ~E_8~0); 27751#L1506-1 assume !(1 == ~E_9~0); 27752#L1511-1 assume !(1 == ~E_10~0); 27708#L1516-1 assume !(1 == ~E_11~0); 26883#L1521-1 assume !(1 == ~E_12~0); 26884#L1526-1 assume !(1 == ~E_13~0); 26938#L1531-1 assume { :end_inline_reset_delta_events } true; 27481#L1892-2 [2021-11-20 07:20:39,540 INFO L793 eck$LassoCheckResult]: Loop: 27481#L1892-2 assume !false; 28504#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28702#L1233 assume !false; 28685#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28017#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27997#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28155#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26981#L1046 assume !(0 != eval_~tmp~0#1); 26983#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27017#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28189#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28746#L1258-5 assume !(0 == ~T1_E~0); 27159#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27160#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28738#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28744#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28745#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27383#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27384#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28501#L1298-3 assume !(0 == ~T9_E~0); 28502#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28661#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28500#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28001#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27161#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27162#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28585#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27304#L1338-3 assume !(0 == ~E_4~0); 27305#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28417#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28590#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28591#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27957#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27517#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27518#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28274#L1378-3 assume !(0 == ~E_12~0); 28275#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28456#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28457#L607-42 assume 1 == ~m_pc~0; 28070#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27798#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27799#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27531#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27532#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28053#L626-42 assume !(1 == ~t1_pc~0); 27617#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 27616#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27920#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27921#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27195#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27196#L645-42 assume !(1 == ~t2_pc~0); 28395#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28396#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28561#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27402#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26909#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26910#L664-42 assume 1 == ~t3_pc~0; 27712#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27437#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28688#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28223#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28224#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28389#L683-42 assume !(1 == ~t4_pc~0); 28097#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28098#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28230#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28650#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28651#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28495#L702-42 assume !(1 == ~t5_pc~0); 27607#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 27608#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27904#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28577#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 26925#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26926#L721-42 assume 1 == ~t6_pc~0; 27079#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27099#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27563#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28730#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27735#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27581#L740-42 assume !(1 == ~t7_pc~0); 27318#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 27319#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27860#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27715#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27716#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27989#L759-42 assume 1 == ~t8_pc~0; 27838#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27770#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27771#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27849#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27850#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27945#L778-42 assume 1 == ~t9_pc~0; 27782#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27784#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28194#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28099#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28100#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28157#L797-42 assume 1 == ~t10_pc~0; 27324#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27325#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28326#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28635#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28195#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28196#L816-42 assume 1 == ~t11_pc~0; 26873#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26874#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27416#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27417#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27496#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27497#L835-42 assume !(1 == ~t12_pc~0); 27793#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27794#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27471#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27472#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28554#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28338#L854-42 assume 1 == ~t13_pc~0; 28339#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27415#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27025#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27026#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27672#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27673#L1401-3 assume !(1 == ~M_E~0); 28451#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27262#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27126#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27127#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27726#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27727#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27302#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27303#L1436-3 assume !(1 == ~T8_E~0); 26889#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26890#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28479#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27810#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27463#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27464#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28741#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27403#L1476-3 assume !(1 == ~E_3~0); 27404#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27804#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27432#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27844#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27845#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28271#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28261#L1516-3 assume !(1 == ~E_11~0); 28262#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27961#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27962#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28356#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27238#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28131#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27772#L1911 assume !(0 == start_simulation_~tmp~3#1); 27773#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28295#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27363#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28233#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27067#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27068#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27297#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27298#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27481#L1892-2 [2021-11-20 07:20:39,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,541 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2021-11-20 07:20:39,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600258143] [2021-11-20 07:20:39,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,576 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600258143] [2021-11-20 07:20:39,576 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600258143] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,578 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142241311] [2021-11-20 07:20:39,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,579 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:39,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1427949617, now seen corresponding path program 1 times [2021-11-20 07:20:39,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888459874] [2021-11-20 07:20:39,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888459874] [2021-11-20 07:20:39,632 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888459874] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,632 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,634 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965001726] [2021-11-20 07:20:39,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,634 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:39,635 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:39,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:39,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:39,635 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:39,681 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2021-11-20 07:20:39,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:39,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2021-11-20 07:20:39,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-11-20 07:20:39,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:39,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:39,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2021-11-20 07:20:39,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:39,722 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-20 07:20:39,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2021-11-20 07:20:39,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:39,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-11-20 07:20:39,768 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-20 07:20:39,768 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-20 07:20:39,768 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 07:20:39,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2021-11-20 07:20:39,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:39,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:39,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:39,781 INFO L791 eck$LassoCheckResult]: Stem: 31554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31374#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31090#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31091#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32267#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32268#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31226#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31227#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31681#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31516#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31517#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31293#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31294#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31692#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31869#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32023#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32060#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31304#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31305#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32480#L1258-2 assume !(0 == ~T1_E~0); 31599#L1263-1 assume !(0 == ~T2_E~0); 31600#L1268-1 assume !(0 == ~T3_E~0); 31903#L1273-1 assume !(0 == ~T4_E~0); 32462#L1278-1 assume !(0 == ~T5_E~0); 32323#L1283-1 assume !(0 == ~T6_E~0); 32324#L1288-1 assume !(0 == ~T7_E~0); 32560#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32548#L1298-1 assume !(0 == ~T9_E~0); 32474#L1303-1 assume !(0 == ~T10_E~0); 31119#L1308-1 assume !(0 == ~T11_E~0); 31061#L1313-1 assume !(0 == ~T12_E~0); 31062#L1318-1 assume !(0 == ~T13_E~0); 31068#L1323-1 assume !(0 == ~E_1~0); 31069#L1328-1 assume !(0 == ~E_2~0); 31236#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32195#L1338-1 assume !(0 == ~E_4~0); 32196#L1343-1 assume !(0 == ~E_5~0); 32297#L1348-1 assume !(0 == ~E_6~0); 32583#L1353-1 assume !(0 == ~E_7~0); 31922#L1358-1 assume !(0 == ~E_8~0); 31923#L1363-1 assume !(0 == ~E_9~0); 32213#L1368-1 assume !(0 == ~E_10~0); 30898#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30899#L1378-1 assume !(0 == ~E_12~0); 31185#L1383-1 assume !(0 == ~E_13~0); 31186#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31929#L607 assume 1 == ~m_pc~0; 31930#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31256#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32295#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31849#L1560 assume !(0 != activate_threads_~tmp~1#1); 31850#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31081#L626 assume !(1 == ~t1_pc~0); 31082#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31350#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31351#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31520#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30981#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30982#L645 assume 1 == ~t2_pc~0; 31098#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31055#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31732#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31733#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31825#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31826#L664 assume 1 == ~t3_pc~0; 32582#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30822#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30823#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31481#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31482#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32490#L683 assume !(1 == ~t4_pc~0); 32045#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31997#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31998#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32032#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32156#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31775#L702 assume 1 == ~t5_pc~0; 31776#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31701#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32151#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32449#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32390#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30870#L721 assume !(1 == ~t6_pc~0); 30844#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30845#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31008#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31490#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31491#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32092#L740 assume 1 == ~t7_pc~0; 30919#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30732#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30733#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30722#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30723#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31426#L759 assume !(1 == ~t8_pc~0); 31427#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31456#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32149#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32150#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32281#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32559#L778 assume 1 == ~t9_pc~0; 32446#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30897#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30837#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30766#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30767#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31094#L797 assume !(1 == ~t10_pc~0); 31095#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31213#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32347#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31597#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31598#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31887#L816 assume 1 == ~t11_pc~0; 30802#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30803#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31558#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31497#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31498#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32022#L835 assume 1 == ~t12_pc~0; 31900#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30966#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30988#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31129#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31654#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31655#L854 assume !(1 == ~t13_pc~0); 31295#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31296#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31346#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31006#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31007#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32386#L1401 assume !(1 == ~M_E~0); 31485#L1401-2 assume !(1 == ~T1_E~0); 31486#L1406-1 assume !(1 == ~T2_E~0); 32081#L1411-1 assume !(1 == ~T3_E~0); 32082#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31748#L1421-1 assume !(1 == ~T5_E~0); 31291#L1426-1 assume !(1 == ~T6_E~0); 31292#L1431-1 assume !(1 == ~T7_E~0); 30840#L1436-1 assume !(1 == ~T8_E~0); 30841#L1441-1 assume !(1 == ~T9_E~0); 31588#L1446-1 assume !(1 == ~T10_E~0); 31589#L1451-1 assume !(1 == ~T11_E~0); 32294#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31948#L1461-1 assume !(1 == ~T13_E~0); 31509#L1466-1 assume !(1 == ~E_1~0); 31510#L1471-1 assume !(1 == ~E_2~0); 32279#L1476-1 assume !(1 == ~E_3~0); 32280#L1481-1 assume !(1 == ~E_4~0); 32428#L1486-1 assume !(1 == ~E_5~0); 31134#L1491-1 assume !(1 == ~E_6~0); 30774#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30775#L1501-1 assume !(1 == ~E_8~0); 31586#L1506-1 assume !(1 == ~E_9~0); 31587#L1511-1 assume !(1 == ~E_10~0); 31543#L1516-1 assume !(1 == ~E_11~0); 30718#L1521-1 assume !(1 == ~E_12~0); 30719#L1526-1 assume !(1 == ~E_13~0); 30773#L1531-1 assume { :end_inline_reset_delta_events } true; 31316#L1892-2 [2021-11-20 07:20:39,782 INFO L793 eck$LassoCheckResult]: Loop: 31316#L1892-2 assume !false; 32339#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32537#L1233 assume !false; 32520#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31852#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31832#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31990#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30816#L1046 assume !(0 != eval_~tmp~0#1); 30818#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30852#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32024#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32581#L1258-5 assume !(0 == ~T1_E~0); 30994#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30995#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32573#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32579#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32580#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31218#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31219#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32336#L1298-3 assume !(0 == ~T9_E~0); 32337#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32496#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32335#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31836#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30996#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30997#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32420#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31139#L1338-3 assume !(0 == ~E_4~0); 31140#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32252#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32425#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32426#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31792#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31352#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31353#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32109#L1378-3 assume !(0 == ~E_12~0); 32110#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32291#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32292#L607-42 assume 1 == ~m_pc~0; 31905#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31633#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31634#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31366#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31367#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31888#L626-42 assume 1 == ~t1_pc~0; 31450#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31451#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31755#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31756#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31030#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31031#L645-42 assume !(1 == ~t2_pc~0); 32230#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32231#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32396#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31237#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30744#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30745#L664-42 assume !(1 == ~t3_pc~0); 31271#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31272#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32523#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32058#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32059#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32224#L683-42 assume !(1 == ~t4_pc~0); 31932#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31933#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32065#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32485#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32486#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32330#L702-42 assume !(1 == ~t5_pc~0); 31442#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31443#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31739#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32412#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30760#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30761#L721-42 assume 1 == ~t6_pc~0; 30914#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30934#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31398#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32565#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31570#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31416#L740-42 assume !(1 == ~t7_pc~0); 31153#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31154#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31695#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31550#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31551#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31824#L759-42 assume 1 == ~t8_pc~0; 31673#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31605#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31606#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31684#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31685#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31780#L778-42 assume 1 == ~t9_pc~0; 31617#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31619#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32029#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31934#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31935#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L797-42 assume 1 == ~t10_pc~0; 31159#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31160#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32161#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32470#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32030#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32031#L816-42 assume 1 == ~t11_pc~0; 30708#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30709#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31251#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31252#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31331#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31332#L835-42 assume 1 == ~t12_pc~0; 31736#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31629#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31306#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31307#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32389#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32173#L854-42 assume !(1 == ~t13_pc~0); 31249#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 31250#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30860#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30861#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31507#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31508#L1401-3 assume !(1 == ~M_E~0); 32286#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31097#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30961#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30962#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31561#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31562#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31137#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31138#L1436-3 assume !(1 == ~T8_E~0); 30724#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30725#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32314#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31645#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31298#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31299#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32576#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31238#L1476-3 assume !(1 == ~E_3~0); 31239#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31639#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31266#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31267#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31679#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31680#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32106#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32096#L1516-3 assume !(1 == ~E_11~0); 32097#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31796#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31797#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32191#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31073#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31966#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31607#L1911 assume !(0 == start_simulation_~tmp~3#1); 31608#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32130#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31198#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32068#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30902#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30903#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31132#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31133#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31316#L1892-2 [2021-11-20 07:20:39,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2021-11-20 07:20:39,783 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085191260] [2021-11-20 07:20:39,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,783 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085191260] [2021-11-20 07:20:39,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085191260] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902546820] [2021-11-20 07:20:39,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:39,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:39,819 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 2 times [2021-11-20 07:20:39,819 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:39,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333042052] [2021-11-20 07:20:39,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:39,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:39,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:39,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:39,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:39,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333042052] [2021-11-20 07:20:39,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333042052] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:39,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:39,866 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:39,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005707539] [2021-11-20 07:20:39,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:39,866 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:39,866 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:39,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:39,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:39,867 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:39,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:39,903 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2021-11-20 07:20:39,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:39,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2021-11-20 07:20:39,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:39,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-11-20 07:20:39,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:39,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:39,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2021-11-20 07:20:39,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:39,932 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-20 07:20:39,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2021-11-20 07:20:40,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:40,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-11-20 07:20:40,014 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-20 07:20:40,014 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-20 07:20:40,014 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 07:20:40,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2021-11-20 07:20:40,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:40,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:40,024 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,024 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,025 INFO L791 eck$LassoCheckResult]: Stem: 35389#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35209#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34925#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34926#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36102#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36103#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35061#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35062#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35520#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35351#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35352#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35128#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35129#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35527#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35704#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35859#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35895#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35141#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35142#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36315#L1258-2 assume !(0 == ~T1_E~0); 35434#L1263-1 assume !(0 == ~T2_E~0); 35435#L1268-1 assume !(0 == ~T3_E~0); 35738#L1273-1 assume !(0 == ~T4_E~0); 36297#L1278-1 assume !(0 == ~T5_E~0); 36158#L1283-1 assume !(0 == ~T6_E~0); 36159#L1288-1 assume !(0 == ~T7_E~0); 36396#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36383#L1298-1 assume !(0 == ~T9_E~0); 36309#L1303-1 assume !(0 == ~T10_E~0); 34954#L1308-1 assume !(0 == ~T11_E~0); 34899#L1313-1 assume !(0 == ~T12_E~0); 34900#L1318-1 assume !(0 == ~T13_E~0); 34905#L1323-1 assume !(0 == ~E_1~0); 34906#L1328-1 assume !(0 == ~E_2~0); 35071#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36030#L1338-1 assume !(0 == ~E_4~0); 36031#L1343-1 assume !(0 == ~E_5~0); 36132#L1348-1 assume !(0 == ~E_6~0); 36418#L1353-1 assume !(0 == ~E_7~0); 35757#L1358-1 assume !(0 == ~E_8~0); 35758#L1363-1 assume !(0 == ~E_9~0); 36049#L1368-1 assume !(0 == ~E_10~0); 34733#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34734#L1378-1 assume !(0 == ~E_12~0); 35022#L1383-1 assume !(0 == ~E_13~0); 35023#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35764#L607 assume 1 == ~m_pc~0; 35765#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35091#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36130#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35684#L1560 assume !(0 != activate_threads_~tmp~1#1); 35685#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34916#L626 assume !(1 == ~t1_pc~0); 34917#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35187#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35188#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35357#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34819#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34820#L645 assume 1 == ~t2_pc~0; 34933#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34890#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35570#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35571#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35660#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35661#L664 assume 1 == ~t3_pc~0; 36417#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34661#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34662#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35316#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35317#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36325#L683 assume !(1 == ~t4_pc~0); 35880#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35832#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35833#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35867#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35991#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35614#L702 assume 1 == ~t5_pc~0; 35615#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35537#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35986#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36285#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36226#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34705#L721 assume !(1 == ~t6_pc~0); 34679#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34680#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35325#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35326#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35927#L740 assume 1 == ~t7_pc~0; 34754#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34567#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34568#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34557#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34558#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35262#L759 assume !(1 == ~t8_pc~0); 35263#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35291#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35984#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35985#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36116#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36394#L778 assume 1 == ~t9_pc~0; 36283#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34732#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34672#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34601#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34602#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34930#L797 assume !(1 == ~t10_pc~0); 34931#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35048#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36182#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35432#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35433#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35722#L816 assume 1 == ~t11_pc~0; 34637#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34638#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35395#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35332#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35333#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35857#L835 assume 1 == ~t12_pc~0; 35735#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34801#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34823#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34964#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35489#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35490#L854 assume !(1 == ~t13_pc~0); 35130#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35131#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35183#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34841#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34842#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36221#L1401 assume !(1 == ~M_E~0); 35320#L1401-2 assume !(1 == ~T1_E~0); 35321#L1406-1 assume !(1 == ~T2_E~0); 35916#L1411-1 assume !(1 == ~T3_E~0); 35917#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35583#L1421-1 assume !(1 == ~T5_E~0); 35126#L1426-1 assume !(1 == ~T6_E~0); 35127#L1431-1 assume !(1 == ~T7_E~0); 34675#L1436-1 assume !(1 == ~T8_E~0); 34676#L1441-1 assume !(1 == ~T9_E~0); 35423#L1446-1 assume !(1 == ~T10_E~0); 35424#L1451-1 assume !(1 == ~T11_E~0); 36129#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35783#L1461-1 assume !(1 == ~T13_E~0); 35344#L1466-1 assume !(1 == ~E_1~0); 35345#L1471-1 assume !(1 == ~E_2~0); 36114#L1476-1 assume !(1 == ~E_3~0); 36115#L1481-1 assume !(1 == ~E_4~0); 36263#L1486-1 assume !(1 == ~E_5~0); 34969#L1491-1 assume !(1 == ~E_6~0); 34609#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34610#L1501-1 assume !(1 == ~E_8~0); 35421#L1506-1 assume !(1 == ~E_9~0); 35422#L1511-1 assume !(1 == ~E_10~0); 35378#L1516-1 assume !(1 == ~E_11~0); 34553#L1521-1 assume !(1 == ~E_12~0); 34554#L1526-1 assume !(1 == ~E_13~0); 34608#L1531-1 assume { :end_inline_reset_delta_events } true; 35151#L1892-2 [2021-11-20 07:20:40,026 INFO L793 eck$LassoCheckResult]: Loop: 35151#L1892-2 assume !false; 36174#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36372#L1233 assume !false; 36355#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35687#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35667#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35825#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34651#L1046 assume !(0 != eval_~tmp~0#1); 34653#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34687#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35858#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36416#L1258-5 assume !(0 == ~T1_E~0); 34829#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34830#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36408#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36414#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36415#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35053#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35054#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36171#L1298-3 assume !(0 == ~T9_E~0); 36172#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36331#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36170#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35671#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34831#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34832#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36255#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34974#L1338-3 assume !(0 == ~E_4~0); 34975#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36087#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36260#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36261#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35627#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35185#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35186#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35944#L1378-3 assume !(0 == ~E_12~0); 35945#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36126#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36127#L607-42 assume 1 == ~m_pc~0; 35740#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35468#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35469#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35201#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35202#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35723#L626-42 assume 1 == ~t1_pc~0; 35285#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35286#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35590#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35591#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34865#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34866#L645-42 assume !(1 == ~t2_pc~0); 36065#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36066#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36231#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35072#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34579#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34580#L664-42 assume !(1 == ~t3_pc~0); 35106#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35107#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35893#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35894#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36059#L683-42 assume !(1 == ~t4_pc~0); 35767#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35768#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35900#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36320#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36321#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36165#L702-42 assume 1 == ~t5_pc~0; 35653#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35278#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35574#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36247#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34595#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34596#L721-42 assume 1 == ~t6_pc~0; 34749#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34769#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35233#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36400#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35405#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35251#L740-42 assume 1 == ~t7_pc~0; 35252#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34989#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35530#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35385#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35386#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35659#L759-42 assume 1 == ~t8_pc~0; 35508#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35440#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35441#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35518#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35519#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35613#L778-42 assume 1 == ~t9_pc~0; 35452#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35454#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35864#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35769#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35770#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35827#L797-42 assume 1 == ~t10_pc~0; 34994#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34995#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35996#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36305#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35865#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35866#L816-42 assume !(1 == ~t11_pc~0); 34545#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34544#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35086#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35087#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35166#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35167#L835-42 assume 1 == ~t12_pc~0; 35569#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35464#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35139#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35140#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36224#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36008#L854-42 assume 1 == ~t13_pc~0; 36009#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35085#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34695#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34696#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35342#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35343#L1401-3 assume !(1 == ~M_E~0); 36121#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34929#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34796#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34797#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35396#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35397#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34972#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34973#L1436-3 assume !(1 == ~T8_E~0); 34559#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34560#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36149#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35480#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35133#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35134#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36411#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35073#L1476-3 assume !(1 == ~E_3~0); 35074#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35474#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35101#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35102#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35514#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35515#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35941#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35931#L1516-3 assume !(1 == ~E_11~0); 35932#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35631#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35632#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36026#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34908#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35801#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35442#L1911 assume !(0 == start_simulation_~tmp~3#1); 35443#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35965#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35033#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35903#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34737#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34738#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34967#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34968#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35151#L1892-2 [2021-11-20 07:20:40,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,027 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2021-11-20 07:20:40,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216999333] [2021-11-20 07:20:40,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216999333] [2021-11-20 07:20:40,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216999333] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,056 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61855809] [2021-11-20 07:20:40,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,057 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:40,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 2 times [2021-11-20 07:20:40,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884570876] [2021-11-20 07:20:40,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884570876] [2021-11-20 07:20:40,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884570876] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,100 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927207521] [2021-11-20 07:20:40,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:40,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:40,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:40,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:40,102 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:40,137 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2021-11-20 07:20:40,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:40,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2021-11-20 07:20:40,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-11-20 07:20:40,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:40,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:40,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2021-11-20 07:20:40,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:40,166 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-20 07:20:40,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2021-11-20 07:20:40,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:40,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-11-20 07:20:40,205 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-20 07:20:40,205 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-20 07:20:40,205 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 07:20:40,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2021-11-20 07:20:40,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:40,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:40,216 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,216 INFO L791 eck$LassoCheckResult]: Stem: 39224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39044#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38760#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38761#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39937#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39938#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38896#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38897#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39355#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39186#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39187#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38963#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38964#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39362#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39539#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39693#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39730#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38976#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38977#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40150#L1258-2 assume !(0 == ~T1_E~0); 39269#L1263-1 assume !(0 == ~T2_E~0); 39270#L1268-1 assume !(0 == ~T3_E~0); 39573#L1273-1 assume !(0 == ~T4_E~0); 40132#L1278-1 assume !(0 == ~T5_E~0); 39993#L1283-1 assume !(0 == ~T6_E~0); 39994#L1288-1 assume !(0 == ~T7_E~0); 40231#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40218#L1298-1 assume !(0 == ~T9_E~0); 40144#L1303-1 assume !(0 == ~T10_E~0); 38789#L1308-1 assume !(0 == ~T11_E~0); 38731#L1313-1 assume !(0 == ~T12_E~0); 38732#L1318-1 assume !(0 == ~T13_E~0); 38740#L1323-1 assume !(0 == ~E_1~0); 38741#L1328-1 assume !(0 == ~E_2~0); 38906#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39865#L1338-1 assume !(0 == ~E_4~0); 39866#L1343-1 assume !(0 == ~E_5~0); 39967#L1348-1 assume !(0 == ~E_6~0); 40253#L1353-1 assume !(0 == ~E_7~0); 39592#L1358-1 assume !(0 == ~E_8~0); 39593#L1363-1 assume !(0 == ~E_9~0); 39884#L1368-1 assume !(0 == ~E_10~0); 38568#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38569#L1378-1 assume !(0 == ~E_12~0); 38857#L1383-1 assume !(0 == ~E_13~0); 38858#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39599#L607 assume 1 == ~m_pc~0; 39600#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38926#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39965#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39519#L1560 assume !(0 != activate_threads_~tmp~1#1); 39520#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38751#L626 assume !(1 == ~t1_pc~0); 38752#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39022#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39023#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39192#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38653#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38654#L645 assume 1 == ~t2_pc~0; 38768#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38725#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39405#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39406#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39495#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39496#L664 assume 1 == ~t3_pc~0; 40252#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38496#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38497#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39151#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39152#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40160#L683 assume !(1 == ~t4_pc~0); 39715#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39667#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39668#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39702#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39826#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39449#L702 assume 1 == ~t5_pc~0; 39450#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39372#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39821#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40120#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40061#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38540#L721 assume !(1 == ~t6_pc~0); 38514#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38515#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38678#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39160#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39161#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39762#L740 assume 1 == ~t7_pc~0; 38589#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38402#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38403#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38392#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38393#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39097#L759 assume !(1 == ~t8_pc~0); 39098#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39126#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39819#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39820#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39951#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40229#L778 assume 1 == ~t9_pc~0; 40118#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38567#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38507#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38436#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38437#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38765#L797 assume !(1 == ~t10_pc~0); 38766#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38883#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40017#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39267#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39268#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39557#L816 assume 1 == ~t11_pc~0; 38472#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38473#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39230#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39167#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39168#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39692#L835 assume 1 == ~t12_pc~0; 39570#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38636#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38658#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38799#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39324#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39325#L854 assume !(1 == ~t13_pc~0); 38965#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38966#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39018#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38676#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38677#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40056#L1401 assume !(1 == ~M_E~0); 39155#L1401-2 assume !(1 == ~T1_E~0); 39156#L1406-1 assume !(1 == ~T2_E~0); 39751#L1411-1 assume !(1 == ~T3_E~0); 39752#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39418#L1421-1 assume !(1 == ~T5_E~0); 38961#L1426-1 assume !(1 == ~T6_E~0); 38962#L1431-1 assume !(1 == ~T7_E~0); 38510#L1436-1 assume !(1 == ~T8_E~0); 38511#L1441-1 assume !(1 == ~T9_E~0); 39260#L1446-1 assume !(1 == ~T10_E~0); 39261#L1451-1 assume !(1 == ~T11_E~0); 39964#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39618#L1461-1 assume !(1 == ~T13_E~0); 39179#L1466-1 assume !(1 == ~E_1~0); 39180#L1471-1 assume !(1 == ~E_2~0); 39949#L1476-1 assume !(1 == ~E_3~0); 39950#L1481-1 assume !(1 == ~E_4~0); 40098#L1486-1 assume !(1 == ~E_5~0); 38804#L1491-1 assume !(1 == ~E_6~0); 38444#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38445#L1501-1 assume !(1 == ~E_8~0); 39256#L1506-1 assume !(1 == ~E_9~0); 39257#L1511-1 assume !(1 == ~E_10~0); 39213#L1516-1 assume !(1 == ~E_11~0); 38390#L1521-1 assume !(1 == ~E_12~0); 38391#L1526-1 assume !(1 == ~E_13~0); 38443#L1531-1 assume { :end_inline_reset_delta_events } true; 38986#L1892-2 [2021-11-20 07:20:40,217 INFO L793 eck$LassoCheckResult]: Loop: 38986#L1892-2 assume !false; 40009#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40207#L1233 assume !false; 40190#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39522#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39502#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39660#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38486#L1046 assume !(0 != eval_~tmp~0#1); 38488#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38522#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39694#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40251#L1258-5 assume !(0 == ~T1_E~0); 38666#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38667#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40243#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40249#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40250#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38890#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38891#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40006#L1298-3 assume !(0 == ~T9_E~0); 40007#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40166#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40005#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39506#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38668#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38669#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40090#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38809#L1338-3 assume !(0 == ~E_4~0); 38810#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39922#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40095#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40096#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39462#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39020#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39021#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39779#L1378-3 assume !(0 == ~E_12~0); 39780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39961#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39962#L607-42 assume 1 == ~m_pc~0; 39575#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39303#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39304#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39036#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39037#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39558#L626-42 assume 1 == ~t1_pc~0; 39120#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39121#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39425#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39426#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38700#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38701#L645-42 assume !(1 == ~t2_pc~0); 39900#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39901#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40066#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38907#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38414#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38415#L664-42 assume 1 == ~t3_pc~0; 39217#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38942#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40193#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39728#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39729#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39894#L683-42 assume !(1 == ~t4_pc~0); 39602#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39603#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39735#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40155#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40156#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40000#L702-42 assume 1 == ~t5_pc~0; 39488#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39113#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39409#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40082#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38430#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38431#L721-42 assume 1 == ~t6_pc~0; 38584#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38604#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39068#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40235#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39240#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39086#L740-42 assume !(1 == ~t7_pc~0); 38823#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38824#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39365#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39220#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39221#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39494#L759-42 assume !(1 == ~t8_pc~0); 39344#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 39275#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39276#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39353#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39354#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39448#L778-42 assume 1 == ~t9_pc~0; 39287#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39289#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39698#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39604#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39605#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39662#L797-42 assume 1 == ~t10_pc~0; 38829#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38830#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39831#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40140#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39700#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39701#L816-42 assume 1 == ~t11_pc~0; 38378#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38379#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38921#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38922#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39001#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39002#L835-42 assume !(1 == ~t12_pc~0); 39298#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39299#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38974#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38975#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40059#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39843#L854-42 assume 1 == ~t13_pc~0; 39844#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38918#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38530#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38531#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39177#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39178#L1401-3 assume !(1 == ~M_E~0); 39956#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38764#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38631#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38632#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39231#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39232#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38807#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38808#L1436-3 assume !(1 == ~T8_E~0); 38394#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38395#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39984#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39315#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38968#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38969#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40246#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38908#L1476-3 assume !(1 == ~E_3~0); 38909#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39309#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38936#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38937#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39349#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39350#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39776#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39766#L1516-3 assume !(1 == ~E_11~0); 39767#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39467#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39861#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38743#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39636#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39277#L1911 assume !(0 == start_simulation_~tmp~3#1); 39278#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39800#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38868#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39738#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38572#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38573#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38802#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38803#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38986#L1892-2 [2021-11-20 07:20:40,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,218 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2021-11-20 07:20:40,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362602664] [2021-11-20 07:20:40,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,219 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,248 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362602664] [2021-11-20 07:20:40,249 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362602664] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,249 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533631073] [2021-11-20 07:20:40,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,250 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:40,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,251 INFO L85 PathProgramCache]: Analyzing trace with hash -744572368, now seen corresponding path program 1 times [2021-11-20 07:20:40,251 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847376723] [2021-11-20 07:20:40,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847376723] [2021-11-20 07:20:40,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847376723] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,293 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,293 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377585901] [2021-11-20 07:20:40,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,294 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:40,294 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:40,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:40,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:40,295 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:40,331 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2021-11-20 07:20:40,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:40,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2021-11-20 07:20:40,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-11-20 07:20:40,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:40,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:40,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2021-11-20 07:20:40,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:40,359 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-20 07:20:40,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2021-11-20 07:20:40,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:40,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-11-20 07:20:40,399 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-20 07:20:40,399 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-20 07:20:40,399 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 07:20:40,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2021-11-20 07:20:40,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:40,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:40,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,410 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,411 INFO L791 eck$LassoCheckResult]: Stem: 43059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42879#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42595#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42596#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43772#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43773#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42731#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42732#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43190#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43021#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43022#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42798#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42799#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43197#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43374#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43528#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43565#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42811#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42812#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43985#L1258-2 assume !(0 == ~T1_E~0); 43104#L1263-1 assume !(0 == ~T2_E~0); 43105#L1268-1 assume !(0 == ~T3_E~0); 43408#L1273-1 assume !(0 == ~T4_E~0); 43967#L1278-1 assume !(0 == ~T5_E~0); 43828#L1283-1 assume !(0 == ~T6_E~0); 43829#L1288-1 assume !(0 == ~T7_E~0); 44066#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44053#L1298-1 assume !(0 == ~T9_E~0); 43979#L1303-1 assume !(0 == ~T10_E~0); 42624#L1308-1 assume !(0 == ~T11_E~0); 42566#L1313-1 assume !(0 == ~T12_E~0); 42567#L1318-1 assume !(0 == ~T13_E~0); 42575#L1323-1 assume !(0 == ~E_1~0); 42576#L1328-1 assume !(0 == ~E_2~0); 42741#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43700#L1338-1 assume !(0 == ~E_4~0); 43701#L1343-1 assume !(0 == ~E_5~0); 43802#L1348-1 assume !(0 == ~E_6~0); 44088#L1353-1 assume !(0 == ~E_7~0); 43427#L1358-1 assume !(0 == ~E_8~0); 43428#L1363-1 assume !(0 == ~E_9~0); 43718#L1368-1 assume !(0 == ~E_10~0); 42403#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42404#L1378-1 assume !(0 == ~E_12~0); 42692#L1383-1 assume !(0 == ~E_13~0); 42693#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43434#L607 assume 1 == ~m_pc~0; 43435#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42761#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43800#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43354#L1560 assume !(0 != activate_threads_~tmp~1#1); 43355#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42586#L626 assume !(1 == ~t1_pc~0); 42587#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42855#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42856#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43027#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42488#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42489#L645 assume 1 == ~t2_pc~0; 42603#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42560#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43240#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43241#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43330#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43331#L664 assume 1 == ~t3_pc~0; 44087#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42331#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42332#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42986#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42987#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43995#L683 assume !(1 == ~t4_pc~0); 43550#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43502#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43503#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43537#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43661#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43284#L702 assume 1 == ~t5_pc~0; 43285#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43656#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43955#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43896#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42375#L721 assume !(1 == ~t6_pc~0); 42349#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42350#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42513#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42995#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42996#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43597#L740 assume 1 == ~t7_pc~0; 42424#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42237#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42238#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42227#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42228#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42932#L759 assume !(1 == ~t8_pc~0); 42933#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42961#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43654#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43655#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43786#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44064#L778 assume 1 == ~t9_pc~0; 43951#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42402#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42342#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42271#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42272#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42600#L797 assume !(1 == ~t10_pc~0); 42601#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42718#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43852#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43102#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43103#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43392#L816 assume 1 == ~t11_pc~0; 42307#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42308#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43065#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43002#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43003#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43527#L835 assume 1 == ~t12_pc~0; 43405#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42471#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42493#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42634#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43159#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43160#L854 assume !(1 == ~t13_pc~0); 42800#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42801#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42851#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42511#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42512#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43891#L1401 assume !(1 == ~M_E~0); 42990#L1401-2 assume !(1 == ~T1_E~0); 42991#L1406-1 assume !(1 == ~T2_E~0); 43586#L1411-1 assume !(1 == ~T3_E~0); 43587#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43253#L1421-1 assume !(1 == ~T5_E~0); 42796#L1426-1 assume !(1 == ~T6_E~0); 42797#L1431-1 assume !(1 == ~T7_E~0); 42345#L1436-1 assume !(1 == ~T8_E~0); 42346#L1441-1 assume !(1 == ~T9_E~0); 43095#L1446-1 assume !(1 == ~T10_E~0); 43096#L1451-1 assume !(1 == ~T11_E~0); 43799#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43453#L1461-1 assume !(1 == ~T13_E~0); 43014#L1466-1 assume !(1 == ~E_1~0); 43015#L1471-1 assume !(1 == ~E_2~0); 43784#L1476-1 assume !(1 == ~E_3~0); 43785#L1481-1 assume !(1 == ~E_4~0); 43933#L1486-1 assume !(1 == ~E_5~0); 42639#L1491-1 assume !(1 == ~E_6~0); 42279#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42280#L1501-1 assume !(1 == ~E_8~0); 43091#L1506-1 assume !(1 == ~E_9~0); 43092#L1511-1 assume !(1 == ~E_10~0); 43048#L1516-1 assume !(1 == ~E_11~0); 42225#L1521-1 assume !(1 == ~E_12~0); 42226#L1526-1 assume !(1 == ~E_13~0); 42278#L1531-1 assume { :end_inline_reset_delta_events } true; 42821#L1892-2 [2021-11-20 07:20:40,412 INFO L793 eck$LassoCheckResult]: Loop: 42821#L1892-2 assume !false; 43844#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44042#L1233 assume !false; 44025#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43357#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43337#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43495#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42321#L1046 assume !(0 != eval_~tmp~0#1); 42323#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42357#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43529#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44086#L1258-5 assume !(0 == ~T1_E~0); 42501#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42502#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44078#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44084#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44085#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42725#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42726#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43841#L1298-3 assume !(0 == ~T9_E~0); 43842#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44001#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43840#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43341#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42503#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42504#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43925#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42644#L1338-3 assume !(0 == ~E_4~0); 42645#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43757#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43931#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43932#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43299#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42857#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42858#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43614#L1378-3 assume !(0 == ~E_12~0); 43615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43796#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43797#L607-42 assume 1 == ~m_pc~0; 43412#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43138#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43139#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42871#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42872#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43393#L626-42 assume 1 == ~t1_pc~0; 42955#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42956#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43260#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43261#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42535#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42536#L645-42 assume !(1 == ~t2_pc~0); 43734#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43735#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43901#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42742#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42249#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42250#L664-42 assume !(1 == ~t3_pc~0); 42776#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42777#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44028#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43563#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43564#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43729#L683-42 assume !(1 == ~t4_pc~0); 43437#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43438#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43569#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43990#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43991#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43835#L702-42 assume !(1 == ~t5_pc~0); 42947#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42948#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43244#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43917#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42265#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42266#L721-42 assume 1 == ~t6_pc~0; 42419#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42439#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42903#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44070#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43075#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42921#L740-42 assume !(1 == ~t7_pc~0); 42658#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42659#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43200#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43055#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43056#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43329#L759-42 assume 1 == ~t8_pc~0; 43178#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43110#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43111#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43188#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43189#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43283#L778-42 assume 1 == ~t9_pc~0; 43122#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43124#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43533#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43439#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43440#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43497#L797-42 assume 1 == ~t10_pc~0; 42664#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42665#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43666#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43975#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43535#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43536#L816-42 assume 1 == ~t11_pc~0; 42213#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42214#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42756#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42757#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42836#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42837#L835-42 assume 1 == ~t12_pc~0; 43239#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43133#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42809#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42810#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43894#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43678#L854-42 assume !(1 == ~t13_pc~0); 42752#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42753#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42365#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42366#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43012#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43013#L1401-3 assume !(1 == ~M_E~0); 43791#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42599#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42466#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42467#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43066#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43067#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42642#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42643#L1436-3 assume !(1 == ~T8_E~0); 42229#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42230#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43819#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43150#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42803#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42804#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44081#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42743#L1476-3 assume !(1 == ~E_3~0); 42744#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43144#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42771#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42772#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43183#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43184#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43611#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43601#L1516-3 assume !(1 == ~E_11~0); 43602#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43301#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43302#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43696#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42578#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43471#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43112#L1911 assume !(0 == start_simulation_~tmp~3#1); 43113#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43635#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42703#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43573#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42407#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42408#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42637#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42638#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42821#L1892-2 [2021-11-20 07:20:40,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2021-11-20 07:20:40,413 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199889737] [2021-11-20 07:20:40,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,414 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,443 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199889737] [2021-11-20 07:20:40,443 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199889737] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,443 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,444 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,444 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088320163] [2021-11-20 07:20:40,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,444 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:40,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,445 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 3 times [2021-11-20 07:20:40,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276888490] [2021-11-20 07:20:40,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,485 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276888490] [2021-11-20 07:20:40,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276888490] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335970879] [2021-11-20 07:20:40,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,487 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:40,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:40,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:40,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:40,488 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:40,524 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2021-11-20 07:20:40,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:40,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2021-11-20 07:20:40,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-11-20 07:20:40,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:40,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:40,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2021-11-20 07:20:40,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:40,573 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-20 07:20:40,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2021-11-20 07:20:40,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:40,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-11-20 07:20:40,610 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-20 07:20:40,610 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-20 07:20:40,610 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 07:20:40,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2021-11-20 07:20:40,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:40,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:40,620 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,620 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,621 INFO L791 eck$LassoCheckResult]: Stem: 46894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46714#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46430#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46431#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47607#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47608#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46566#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46567#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47025#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46856#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46857#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46633#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46634#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47032#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47209#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47363#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47400#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46646#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46647#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47820#L1258-2 assume !(0 == ~T1_E~0); 46939#L1263-1 assume !(0 == ~T2_E~0); 46940#L1268-1 assume !(0 == ~T3_E~0); 47243#L1273-1 assume !(0 == ~T4_E~0); 47802#L1278-1 assume !(0 == ~T5_E~0); 47663#L1283-1 assume !(0 == ~T6_E~0); 47664#L1288-1 assume !(0 == ~T7_E~0); 47900#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47888#L1298-1 assume !(0 == ~T9_E~0); 47814#L1303-1 assume !(0 == ~T10_E~0); 46459#L1308-1 assume !(0 == ~T11_E~0); 46401#L1313-1 assume !(0 == ~T12_E~0); 46402#L1318-1 assume !(0 == ~T13_E~0); 46410#L1323-1 assume !(0 == ~E_1~0); 46411#L1328-1 assume !(0 == ~E_2~0); 46576#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47535#L1338-1 assume !(0 == ~E_4~0); 47536#L1343-1 assume !(0 == ~E_5~0); 47637#L1348-1 assume !(0 == ~E_6~0); 47923#L1353-1 assume !(0 == ~E_7~0); 47262#L1358-1 assume !(0 == ~E_8~0); 47263#L1363-1 assume !(0 == ~E_9~0); 47553#L1368-1 assume !(0 == ~E_10~0); 46238#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46239#L1378-1 assume !(0 == ~E_12~0); 46527#L1383-1 assume !(0 == ~E_13~0); 46528#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47269#L607 assume 1 == ~m_pc~0; 47270#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46596#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47635#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47189#L1560 assume !(0 != activate_threads_~tmp~1#1); 47190#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46421#L626 assume !(1 == ~t1_pc~0); 46422#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46690#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46691#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46860#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46323#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46324#L645 assume 1 == ~t2_pc~0; 46438#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46395#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47075#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47076#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47165#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47166#L664 assume 1 == ~t3_pc~0; 47922#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46164#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46165#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46821#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46822#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47830#L683 assume !(1 == ~t4_pc~0); 47385#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47337#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47338#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47372#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47496#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47119#L702 assume 1 == ~t5_pc~0; 47120#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47042#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47491#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47790#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47731#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46210#L721 assume !(1 == ~t6_pc~0); 46184#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46185#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46348#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46830#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46831#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47432#L740 assume 1 == ~t7_pc~0; 46259#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46072#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46073#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46062#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46063#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46767#L759 assume !(1 == ~t8_pc~0); 46768#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46796#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47489#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47490#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47621#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47899#L778 assume 1 == ~t9_pc~0; 47786#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46237#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46177#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46106#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46107#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46435#L797 assume !(1 == ~t10_pc~0); 46436#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46553#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47687#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46937#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46938#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47227#L816 assume 1 == ~t11_pc~0; 46142#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46143#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46900#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46837#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46838#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47362#L835 assume 1 == ~t12_pc~0; 47240#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46306#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46328#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46469#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46994#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46995#L854 assume !(1 == ~t13_pc~0); 46635#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46636#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46686#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46346#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46347#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47726#L1401 assume !(1 == ~M_E~0); 46825#L1401-2 assume !(1 == ~T1_E~0); 46826#L1406-1 assume !(1 == ~T2_E~0); 47421#L1411-1 assume !(1 == ~T3_E~0); 47422#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47088#L1421-1 assume !(1 == ~T5_E~0); 46631#L1426-1 assume !(1 == ~T6_E~0); 46632#L1431-1 assume !(1 == ~T7_E~0); 46180#L1436-1 assume !(1 == ~T8_E~0); 46181#L1441-1 assume !(1 == ~T9_E~0); 46930#L1446-1 assume !(1 == ~T10_E~0); 46931#L1451-1 assume !(1 == ~T11_E~0); 47634#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47288#L1461-1 assume !(1 == ~T13_E~0); 46849#L1466-1 assume !(1 == ~E_1~0); 46850#L1471-1 assume !(1 == ~E_2~0); 47619#L1476-1 assume !(1 == ~E_3~0); 47620#L1481-1 assume !(1 == ~E_4~0); 47768#L1486-1 assume !(1 == ~E_5~0); 46474#L1491-1 assume !(1 == ~E_6~0); 46114#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46115#L1501-1 assume !(1 == ~E_8~0); 46926#L1506-1 assume !(1 == ~E_9~0); 46927#L1511-1 assume !(1 == ~E_10~0); 46883#L1516-1 assume !(1 == ~E_11~0); 46060#L1521-1 assume !(1 == ~E_12~0); 46061#L1526-1 assume !(1 == ~E_13~0); 46113#L1531-1 assume { :end_inline_reset_delta_events } true; 46656#L1892-2 [2021-11-20 07:20:40,622 INFO L793 eck$LassoCheckResult]: Loop: 46656#L1892-2 assume !false; 47679#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47877#L1233 assume !false; 47860#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47192#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47172#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47330#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46156#L1046 assume !(0 != eval_~tmp~0#1); 46158#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46192#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47364#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47921#L1258-5 assume !(0 == ~T1_E~0); 46336#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46337#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47913#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47919#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47920#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46560#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46561#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47676#L1298-3 assume !(0 == ~T9_E~0); 47677#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47836#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47675#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47176#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46338#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46339#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47760#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46479#L1338-3 assume !(0 == ~E_4~0); 46480#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47592#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47766#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47767#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47134#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46692#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46693#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47449#L1378-3 assume !(0 == ~E_12~0); 47450#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47631#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47632#L607-42 assume !(1 == ~m_pc~0); 47248#L607-44 is_master_triggered_~__retres1~0#1 := 0; 46973#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46974#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46706#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46707#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47231#L626-42 assume 1 == ~t1_pc~0; 46793#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46794#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47095#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47096#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46371#L645-42 assume !(1 == ~t2_pc~0); 47570#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47571#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47736#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46577#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46084#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46085#L664-42 assume !(1 == ~t3_pc~0); 46608#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46609#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47863#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47398#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47399#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47564#L683-42 assume !(1 == ~t4_pc~0); 47271#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47272#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47404#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47825#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47826#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47670#L702-42 assume 1 == ~t5_pc~0; 47158#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46782#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47079#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47752#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46098#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46099#L721-42 assume 1 == ~t6_pc~0; 46254#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46274#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46738#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47905#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46910#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46756#L740-42 assume 1 == ~t7_pc~0; 46757#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46494#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47035#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46890#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46891#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47164#L759-42 assume 1 == ~t8_pc~0; 47013#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46945#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46946#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47023#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47024#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47118#L778-42 assume 1 == ~t9_pc~0; 46957#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46959#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47368#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47273#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47274#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47332#L797-42 assume 1 == ~t10_pc~0; 46499#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46500#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47501#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47810#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47370#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47371#L816-42 assume 1 == ~t11_pc~0; 46048#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46049#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46591#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46592#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46671#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46672#L835-42 assume 1 == ~t12_pc~0; 47074#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46966#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46644#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46645#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47729#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47513#L854-42 assume 1 == ~t13_pc~0; 47514#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46588#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46200#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46201#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46847#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46848#L1401-3 assume !(1 == ~M_E~0); 47626#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46434#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46301#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46302#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46901#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46902#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46477#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46478#L1436-3 assume !(1 == ~T8_E~0); 46064#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46065#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47654#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46985#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46638#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46639#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47916#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46578#L1476-3 assume !(1 == ~E_3~0); 46579#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46979#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46606#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46607#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47018#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47019#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47446#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47436#L1516-3 assume !(1 == ~E_11~0); 47437#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47136#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47137#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47531#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46413#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47306#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46947#L1911 assume !(0 == start_simulation_~tmp~3#1); 46948#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47470#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46538#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47408#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46242#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46243#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46472#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46473#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46656#L1892-2 [2021-11-20 07:20:40,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,623 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2021-11-20 07:20:40,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909900822] [2021-11-20 07:20:40,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,624 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909900822] [2021-11-20 07:20:40,653 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909900822] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,653 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,653 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,653 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471293205] [2021-11-20 07:20:40,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,654 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:40,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,654 INFO L85 PathProgramCache]: Analyzing trace with hash -505772015, now seen corresponding path program 1 times [2021-11-20 07:20:40,655 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49037060] [2021-11-20 07:20:40,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,655 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49037060] [2021-11-20 07:20:40,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49037060] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,695 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,695 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146894866] [2021-11-20 07:20:40,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,696 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:40,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:40,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:40,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:40,696 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:40,730 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2021-11-20 07:20:40,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:40,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2021-11-20 07:20:40,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-11-20 07:20:40,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-20 07:20:40,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-20 07:20:40,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2021-11-20 07:20:40,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:40,755 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-20 07:20:40,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2021-11-20 07:20:40,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-20 07:20:40,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:40,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-11-20 07:20:40,792 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-20 07:20:40,792 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-20 07:20:40,792 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 07:20:40,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2021-11-20 07:20:40,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-20 07:20:40,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:40,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:40,802 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:40,803 INFO L791 eck$LassoCheckResult]: Stem: 50729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50549#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50265#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50266#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51442#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51443#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50401#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50402#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50858#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50691#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50692#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50468#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50469#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50867#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51044#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51198#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51235#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50481#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50482#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51655#L1258-2 assume !(0 == ~T1_E~0); 50774#L1263-1 assume !(0 == ~T2_E~0); 50775#L1268-1 assume !(0 == ~T3_E~0); 51078#L1273-1 assume !(0 == ~T4_E~0); 51637#L1278-1 assume !(0 == ~T5_E~0); 51498#L1283-1 assume !(0 == ~T6_E~0); 51499#L1288-1 assume !(0 == ~T7_E~0); 51735#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51723#L1298-1 assume !(0 == ~T9_E~0); 51649#L1303-1 assume !(0 == ~T10_E~0); 50294#L1308-1 assume !(0 == ~T11_E~0); 50236#L1313-1 assume !(0 == ~T12_E~0); 50237#L1318-1 assume !(0 == ~T13_E~0); 50245#L1323-1 assume !(0 == ~E_1~0); 50246#L1328-1 assume !(0 == ~E_2~0); 50411#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51370#L1338-1 assume !(0 == ~E_4~0); 51371#L1343-1 assume !(0 == ~E_5~0); 51472#L1348-1 assume !(0 == ~E_6~0); 51758#L1353-1 assume !(0 == ~E_7~0); 51097#L1358-1 assume !(0 == ~E_8~0); 51098#L1363-1 assume !(0 == ~E_9~0); 51388#L1368-1 assume !(0 == ~E_10~0); 50073#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50074#L1378-1 assume !(0 == ~E_12~0); 50362#L1383-1 assume !(0 == ~E_13~0); 50363#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51104#L607 assume 1 == ~m_pc~0; 51105#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50431#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51470#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51024#L1560 assume !(0 != activate_threads_~tmp~1#1); 51025#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50256#L626 assume !(1 == ~t1_pc~0); 50257#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50525#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50526#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50695#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50156#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50157#L645 assume 1 == ~t2_pc~0; 50273#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50230#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50910#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50911#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51000#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51001#L664 assume 1 == ~t3_pc~0; 51757#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49997#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49998#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50656#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50657#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51665#L683 assume !(1 == ~t4_pc~0); 51220#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51172#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51173#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51207#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51331#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50954#L702 assume 1 == ~t5_pc~0; 50955#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50877#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51326#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51625#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51566#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50045#L721 assume !(1 == ~t6_pc~0); 50019#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50020#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50183#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50665#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50666#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51267#L740 assume 1 == ~t7_pc~0; 50094#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49907#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49908#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49897#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49898#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50602#L759 assume !(1 == ~t8_pc~0); 50603#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50631#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51324#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51325#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51456#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51734#L778 assume 1 == ~t9_pc~0; 51621#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50072#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50012#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49941#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49942#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50270#L797 assume !(1 == ~t10_pc~0); 50271#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50388#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51522#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50772#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50773#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51062#L816 assume 1 == ~t11_pc~0; 49977#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49978#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50735#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50672#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50673#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51197#L835 assume 1 == ~t12_pc~0; 51075#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50141#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50163#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50304#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50829#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50830#L854 assume !(1 == ~t13_pc~0); 50470#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50471#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50521#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50181#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50182#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51561#L1401 assume !(1 == ~M_E~0); 50660#L1401-2 assume !(1 == ~T1_E~0); 50661#L1406-1 assume !(1 == ~T2_E~0); 51256#L1411-1 assume !(1 == ~T3_E~0); 51257#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50923#L1421-1 assume !(1 == ~T5_E~0); 50466#L1426-1 assume !(1 == ~T6_E~0); 50467#L1431-1 assume !(1 == ~T7_E~0); 50015#L1436-1 assume !(1 == ~T8_E~0); 50016#L1441-1 assume !(1 == ~T9_E~0); 50765#L1446-1 assume !(1 == ~T10_E~0); 50766#L1451-1 assume !(1 == ~T11_E~0); 51469#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51123#L1461-1 assume !(1 == ~T13_E~0); 50684#L1466-1 assume !(1 == ~E_1~0); 50685#L1471-1 assume !(1 == ~E_2~0); 51454#L1476-1 assume !(1 == ~E_3~0); 51455#L1481-1 assume !(1 == ~E_4~0); 51603#L1486-1 assume !(1 == ~E_5~0); 50309#L1491-1 assume !(1 == ~E_6~0); 49949#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49950#L1501-1 assume !(1 == ~E_8~0); 50761#L1506-1 assume !(1 == ~E_9~0); 50762#L1511-1 assume !(1 == ~E_10~0); 50718#L1516-1 assume !(1 == ~E_11~0); 49893#L1521-1 assume !(1 == ~E_12~0); 49894#L1526-1 assume !(1 == ~E_13~0); 49948#L1531-1 assume { :end_inline_reset_delta_events } true; 50491#L1892-2 [2021-11-20 07:20:40,804 INFO L793 eck$LassoCheckResult]: Loop: 50491#L1892-2 assume !false; 51514#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51712#L1233 assume !false; 51695#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51027#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51007#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51165#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49991#L1046 assume !(0 != eval_~tmp~0#1); 49993#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50027#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51199#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51756#L1258-5 assume !(0 == ~T1_E~0); 50169#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50170#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51748#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51754#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51755#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50393#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50394#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51511#L1298-3 assume !(0 == ~T9_E~0); 51512#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51671#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51510#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51011#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50171#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50172#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51595#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50314#L1338-3 assume !(0 == ~E_4~0); 50315#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51427#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51601#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51602#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50969#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50527#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50528#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51284#L1378-3 assume !(0 == ~E_12~0); 51285#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51466#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51467#L607-42 assume 1 == ~m_pc~0; 51082#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50808#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50809#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50541#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50542#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51066#L626-42 assume 1 == ~t1_pc~0; 50628#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50629#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50930#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50931#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50205#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50206#L645-42 assume 1 == ~t2_pc~0; 51664#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51406#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51571#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50412#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49919#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49920#L664-42 assume 1 == ~t3_pc~0; 50724#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50448#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51698#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51233#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51234#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51399#L683-42 assume 1 == ~t4_pc~0; 51764#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51110#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51240#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51660#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51661#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51508#L702-42 assume 1 == ~t5_pc~0; 50996#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50618#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50916#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51587#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 49933#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49934#L721-42 assume 1 == ~t6_pc~0; 50088#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50109#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50573#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51740#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50745#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50589#L740-42 assume !(1 == ~t7_pc~0); 50325#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50326#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50870#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50725#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50726#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50999#L759-42 assume 1 == ~t8_pc~0; 50848#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50780#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50781#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50856#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50857#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50953#L778-42 assume 1 == ~t9_pc~0; 50792#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50794#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51202#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51106#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51107#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51167#L797-42 assume !(1 == ~t10_pc~0); 50336#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 50335#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51336#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51645#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51205#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51206#L816-42 assume 1 == ~t11_pc~0; 49883#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49884#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50426#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50427#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50506#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50507#L835-42 assume !(1 == ~t12_pc~0); 50800#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50801#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50479#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50480#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51564#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51348#L854-42 assume 1 == ~t13_pc~0; 51349#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50423#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50035#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50036#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50682#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50683#L1401-3 assume !(1 == ~M_E~0); 51461#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50269#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50136#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50137#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50736#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50737#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50312#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50313#L1436-3 assume !(1 == ~T8_E~0); 49899#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49900#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51489#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50820#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50473#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50474#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51751#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50413#L1476-3 assume !(1 == ~E_3~0); 50414#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50814#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50441#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50442#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50853#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50854#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51281#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51270#L1516-3 assume !(1 == ~E_11~0); 51271#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50971#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50972#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51366#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50248#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51141#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50782#L1911 assume !(0 == start_simulation_~tmp~3#1); 50783#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51305#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50373#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51243#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50077#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50078#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50307#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50308#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50491#L1892-2 [2021-11-20 07:20:40,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2021-11-20 07:20:40,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518847410] [2021-11-20 07:20:40,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,838 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518847410] [2021-11-20 07:20:40,839 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518847410] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,839 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:20:40,839 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647366060] [2021-11-20 07:20:40,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,840 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:40,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:40,840 INFO L85 PathProgramCache]: Analyzing trace with hash -118340366, now seen corresponding path program 1 times [2021-11-20 07:20:40,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:40,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007525243] [2021-11-20 07:20:40,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:40,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:40,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:40,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:40,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:40,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007525243] [2021-11-20 07:20:40,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007525243] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:40,882 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:40,882 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:40,882 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812726566] [2021-11-20 07:20:40,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:40,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:40,883 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:40,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:20:40,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:20:40,884 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:41,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:41,014 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2021-11-20 07:20:41,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:20:41,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2021-11-20 07:20:41,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-11-20 07:20:41,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-11-20 07:20:41,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2021-11-20 07:20:41,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2021-11-20 07:20:41,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2021-11-20 07:20:41,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:41,057 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-20 07:20:41,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2021-11-20 07:20:41,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2021-11-20 07:20:41,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:41,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-11-20 07:20:41,130 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-20 07:20:41,163 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-20 07:20:41,163 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 07:20:41,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2021-11-20 07:20:41,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-11-20 07:20:41,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:41,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:41,181 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:41,181 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:41,181 INFO L791 eck$LassoCheckResult]: Stem: 56208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56027#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55741#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55742#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56940#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56941#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55878#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55879#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56337#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56170#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56171#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55946#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55947#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56348#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56531#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56683#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56722#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55957#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55958#L1258 assume !(0 == ~M_E~0); 57173#L1258-2 assume !(0 == ~T1_E~0); 56254#L1263-1 assume !(0 == ~T2_E~0); 56255#L1268-1 assume !(0 == ~T3_E~0); 56565#L1273-1 assume !(0 == ~T4_E~0); 57152#L1278-1 assume !(0 == ~T5_E~0); 57000#L1283-1 assume !(0 == ~T6_E~0); 57001#L1288-1 assume !(0 == ~T7_E~0); 57267#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57165#L1303-1 assume !(0 == ~T10_E~0); 55770#L1308-1 assume !(0 == ~T11_E~0); 55712#L1313-1 assume !(0 == ~T12_E~0); 55713#L1318-1 assume !(0 == ~T13_E~0); 55719#L1323-1 assume !(0 == ~E_1~0); 55720#L1328-1 assume !(0 == ~E_2~0); 55889#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56863#L1338-1 assume !(0 == ~E_4~0); 56864#L1343-1 assume !(0 == ~E_5~0); 56972#L1348-1 assume !(0 == ~E_6~0); 57295#L1353-1 assume !(0 == ~E_7~0); 56584#L1358-1 assume !(0 == ~E_8~0); 56585#L1363-1 assume !(0 == ~E_9~0); 56882#L1368-1 assume !(0 == ~E_10~0); 55549#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55550#L1378-1 assume !(0 == ~E_12~0); 55837#L1383-1 assume !(0 == ~E_13~0); 55838#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56590#L607 assume !(1 == ~m_pc~0); 55908#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55909#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56970#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55732#L626 assume !(1 == ~t1_pc~0); 55733#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56003#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56004#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56174#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55632#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55633#L645 assume 1 == ~t2_pc~0; 55749#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55706#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56486#L664 assume 1 == ~t3_pc~0; 57293#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55473#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55474#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56135#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56136#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57183#L683 assume !(1 == ~t4_pc~0); 56707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56693#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56822#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56817#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57137#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57072#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55521#L721 assume !(1 == ~t6_pc~0); 55495#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55496#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55659#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56144#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56145#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56755#L740 assume 1 == ~t7_pc~0; 55570#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55383#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55384#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55373#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55374#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56079#L759 assume !(1 == ~t8_pc~0); 56080#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56110#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56815#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56816#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56955#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57266#L778 assume 1 == ~t9_pc~0; 57134#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55548#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55488#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55417#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55418#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55745#L797 assume !(1 == ~t10_pc~0); 55746#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55865#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57027#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56252#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56253#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56549#L816 assume 1 == ~t11_pc~0; 55453#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55454#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56212#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56151#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56152#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56682#L835 assume 1 == ~t12_pc~0; 56562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55617#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55639#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55780#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56310#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56311#L854 assume !(1 == ~t13_pc~0); 55948#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55949#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55999#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55657#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55658#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57067#L1401 assume !(1 == ~M_E~0); 56139#L1401-2 assume !(1 == ~T1_E~0); 56140#L1406-1 assume !(1 == ~T2_E~0); 56744#L1411-1 assume !(1 == ~T3_E~0); 56745#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55944#L1426-1 assume !(1 == ~T6_E~0); 55945#L1431-1 assume !(1 == ~T7_E~0); 55491#L1436-1 assume !(1 == ~T8_E~0); 55492#L1441-1 assume !(1 == ~T9_E~0); 56243#L1446-1 assume !(1 == ~T10_E~0); 56244#L1451-1 assume !(1 == ~T11_E~0); 56969#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56609#L1461-1 assume !(1 == ~T13_E~0); 56163#L1466-1 assume !(1 == ~E_1~0); 56164#L1471-1 assume !(1 == ~E_2~0); 56953#L1476-1 assume !(1 == ~E_3~0); 56954#L1481-1 assume !(1 == ~E_4~0); 57115#L1486-1 assume !(1 == ~E_5~0); 55785#L1491-1 assume !(1 == ~E_6~0); 55425#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55426#L1501-1 assume !(1 == ~E_8~0); 56241#L1506-1 assume !(1 == ~E_9~0); 56242#L1511-1 assume !(1 == ~E_10~0); 56197#L1516-1 assume !(1 == ~E_11~0); 55369#L1521-1 assume !(1 == ~E_12~0); 55370#L1526-1 assume !(1 == ~E_13~0); 55424#L1531-1 assume { :end_inline_reset_delta_events } true; 55969#L1892-2 [2021-11-20 07:20:41,182 INFO L793 eck$LassoCheckResult]: Loop: 55969#L1892-2 assume !false; 57386#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57384#L1233 assume !false; 57218#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55467#L1046 assume !(0 != eval_~tmp~0#1); 55469#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58593#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58592#L1258-3 assume !(0 == ~M_E~0); 57333#L1258-5 assume !(0 == ~T1_E~0); 55645#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55646#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57281#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57288#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57289#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55870#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55871#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57013#L1298-3 assume !(0 == ~T9_E~0); 57014#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57190#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57012#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55647#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55648#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57106#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55790#L1338-3 assume !(0 == ~E_4~0); 55791#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56923#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57112#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57113#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56450#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 56005#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56006#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56775#L1378-3 assume !(0 == ~E_12~0); 56776#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 56966#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56967#L607-42 assume !(1 == ~m_pc~0); 56568#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58412#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58411#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58410#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58409#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58408#L626-42 assume 1 == ~t1_pc~0; 58406#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58405#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58404#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58403#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58402#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58401#L645-42 assume 1 == ~t2_pc~0; 58400#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58397#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58396#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58395#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58394#L664-42 assume 1 == ~t3_pc~0; 58392#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58391#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58390#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58389#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58388#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58387#L683-42 assume !(1 == ~t4_pc~0); 58385#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58384#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58383#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58382#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58381#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58380#L702-42 assume 1 == ~t5_pc~0; 58378#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58377#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58376#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58375#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 58374#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58373#L721-42 assume 1 == ~t6_pc~0; 58371#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58370#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58369#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58368#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58367#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58366#L740-42 assume 1 == ~t7_pc~0; 58364#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58363#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58362#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58361#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58360#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58359#L759-42 assume 1 == ~t8_pc~0; 58357#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58356#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58355#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58354#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58353#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58352#L778-42 assume 1 == ~t9_pc~0; 56272#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56274#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58350#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58348#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58345#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58343#L797-42 assume 1 == ~t10_pc~0; 58340#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56827#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56828#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57161#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57331#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58327#L816-42 assume !(1 == ~t11_pc~0); 58323#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58321#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58320#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58319#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58318#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58317#L835-42 assume 1 == ~t12_pc~0; 58315#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58314#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58313#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58312#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58311#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58310#L854-42 assume !(1 == ~t13_pc~0); 58308#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58307#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58306#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58305#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58304#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57326#L1401-3 assume !(1 == ~M_E~0); 57327#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58805#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58096#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58095#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58093#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58090#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58088#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58086#L1436-3 assume !(1 == ~T8_E~0); 58084#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58082#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58080#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58077#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58075#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58073#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58070#L1476-3 assume !(1 == ~E_3~0); 58069#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58068#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58067#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58066#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58065#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58064#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58063#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58062#L1516-3 assume !(1 == ~E_11~0); 58061#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58060#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58059#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57867#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57332#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56262#L1911 assume !(0 == start_simulation_~tmp~3#1); 56263#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57473#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57458#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57455#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57453#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57451#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57449#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57447#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55969#L1892-2 [2021-11-20 07:20:41,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:41,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2021-11-20 07:20:41,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:41,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241580484] [2021-11-20 07:20:41,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:41,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:41,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:41,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:41,223 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:41,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241580484] [2021-11-20 07:20:41,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241580484] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:41,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:41,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:41,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863667951] [2021-11-20 07:20:41,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:41,224 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:41,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:41,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1909928847, now seen corresponding path program 1 times [2021-11-20 07:20:41,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:41,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485420353] [2021-11-20 07:20:41,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:41,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:41,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:41,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:41,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:41,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485420353] [2021-11-20 07:20:41,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485420353] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:41,270 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:41,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:41,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707235275] [2021-11-20 07:20:41,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:41,271 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:41,271 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:41,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:20:41,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:20:41,272 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:41,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:41,431 INFO L93 Difference]: Finished difference Result 6963 states and 10201 transitions. [2021-11-20 07:20:41,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:20:41,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6963 states and 10201 transitions. [2021-11-20 07:20:41,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2021-11-20 07:20:41,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6963 states to 6963 states and 10201 transitions. [2021-11-20 07:20:41,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6963 [2021-11-20 07:20:41,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6963 [2021-11-20 07:20:41,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6963 states and 10201 transitions. [2021-11-20 07:20:41,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:41,504 INFO L681 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-20 07:20:41,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6963 states and 10201 transitions. [2021-11-20 07:20:41,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6963 to 6963. [2021-11-20 07:20:41,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6963 states, 6963 states have (on average 1.465029441332759) internal successors, (10201), 6962 states have internal predecessors, (10201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:41,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6963 states to 6963 states and 10201 transitions. [2021-11-20 07:20:41,632 INFO L704 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-20 07:20:41,632 INFO L587 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-20 07:20:41,633 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-20 07:20:41,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6963 states and 10201 transitions. [2021-11-20 07:20:41,654 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2021-11-20 07:20:41,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:41,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:41,658 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:41,658 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:41,659 INFO L791 eck$LassoCheckResult]: Stem: 66741#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 66557#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66270#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66271#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67504#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67505#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66409#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66410#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66874#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66703#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66704#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66476#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66477#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66885#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67072#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67228#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67268#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66489#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66490#L1258 assume !(0 == ~M_E~0); 67756#L1258-2 assume !(0 == ~T1_E~0); 66788#L1263-1 assume !(0 == ~T2_E~0); 66789#L1268-1 assume !(0 == ~T3_E~0); 67106#L1273-1 assume !(0 == ~T4_E~0); 67733#L1278-1 assume !(0 == ~T5_E~0); 67563#L1283-1 assume !(0 == ~T6_E~0); 67564#L1288-1 assume !(0 == ~T7_E~0); 67873#L1293-1 assume !(0 == ~T8_E~0); 67856#L1298-1 assume !(0 == ~T9_E~0); 67749#L1303-1 assume !(0 == ~T10_E~0); 66299#L1308-1 assume !(0 == ~T11_E~0); 66241#L1313-1 assume !(0 == ~T12_E~0); 66242#L1318-1 assume !(0 == ~T13_E~0); 66248#L1323-1 assume !(0 == ~E_1~0); 66249#L1328-1 assume !(0 == ~E_2~0); 66419#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67418#L1338-1 assume !(0 == ~E_4~0); 67419#L1343-1 assume !(0 == ~E_5~0); 67535#L1348-1 assume !(0 == ~E_6~0); 67914#L1353-1 assume !(0 == ~E_7~0); 67125#L1358-1 assume !(0 == ~E_8~0); 67126#L1363-1 assume !(0 == ~E_9~0); 67442#L1368-1 assume !(0 == ~E_10~0); 66078#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66079#L1378-1 assume !(0 == ~E_12~0); 66367#L1383-1 assume !(0 == ~E_13~0); 66368#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67132#L607 assume !(1 == ~m_pc~0); 66438#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66439#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67533#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67051#L1560 assume !(0 != activate_threads_~tmp~1#1); 67052#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66261#L626 assume !(1 == ~t1_pc~0); 66262#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66533#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66534#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66707#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66161#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66162#L645 assume 1 == ~t2_pc~0; 66278#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66235#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66931#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66932#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67027#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67028#L664 assume 1 == ~t3_pc~0; 67911#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66001#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66002#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66666#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66667#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67770#L683 assume !(1 == ~t4_pc~0); 67251#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67201#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67202#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67238#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67378#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66974#L702 assume 1 == ~t5_pc~0; 66975#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66896#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67371#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67717#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67643#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66050#L721 assume !(1 == ~t6_pc~0); 66024#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66025#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66188#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66676#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66677#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67302#L740 assume 1 == ~t7_pc~0; 66099#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65911#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65912#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65901#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65902#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66609#L759 assume !(1 == ~t8_pc~0); 66610#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66641#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67369#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67370#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67518#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67872#L778 assume 1 == ~t9_pc~0; 67713#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66077#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66016#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65945#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65946#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66275#L797 assume !(1 == ~t10_pc~0); 66276#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66396#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67590#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66786#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66787#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67090#L816 assume 1 == ~t11_pc~0; 65981#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65982#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66747#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66683#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66684#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67227#L835 assume 1 == ~t12_pc~0; 67103#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66146#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66168#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66309#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66845#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66846#L854 assume !(1 == ~t13_pc~0); 66478#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66479#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66529#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66186#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66187#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67638#L1401 assume !(1 == ~M_E~0); 66670#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66671#L1406-1 assume !(1 == ~T2_E~0); 67291#L1411-1 assume !(1 == ~T3_E~0); 67292#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66945#L1421-1 assume !(1 == ~T5_E~0); 66946#L1426-1 assume !(1 == ~T6_E~0); 72104#L1431-1 assume !(1 == ~T7_E~0); 72101#L1436-1 assume !(1 == ~T8_E~0); 66020#L1441-1 assume !(1 == ~T9_E~0); 72098#L1446-1 assume !(1 == ~T10_E~0); 72096#L1451-1 assume !(1 == ~T11_E~0); 72094#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 72092#L1461-1 assume !(1 == ~T13_E~0); 66696#L1466-1 assume !(1 == ~E_1~0); 66697#L1471-1 assume !(1 == ~E_2~0); 67516#L1476-1 assume !(1 == ~E_3~0); 67517#L1481-1 assume !(1 == ~E_4~0); 67693#L1486-1 assume !(1 == ~E_5~0); 67885#L1491-1 assume !(1 == ~E_6~0); 70829#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 70826#L1501-1 assume !(1 == ~E_8~0); 70824#L1506-1 assume !(1 == ~E_9~0); 70822#L1511-1 assume !(1 == ~E_10~0); 70820#L1516-1 assume !(1 == ~E_11~0); 70818#L1521-1 assume !(1 == ~E_12~0); 70814#L1526-1 assume !(1 == ~E_13~0); 70812#L1531-1 assume { :end_inline_reset_delta_events } true; 70809#L1892-2 [2021-11-20 07:20:41,659 INFO L793 eck$LassoCheckResult]: Loop: 70809#L1892-2 assume !false; 68045#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68043#L1233 assume !false; 67811#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67812#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67933#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67934#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 70630#L1046 assume !(0 != eval_~tmp~0#1); 70614#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70613#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70612#L1258-3 assume !(0 == ~M_E~0); 70611#L1258-5 assume !(0 == ~T1_E~0); 70610#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70609#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70608#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70607#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70606#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70605#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70604#L1293-3 assume !(0 == ~T8_E~0); 70603#L1298-3 assume !(0 == ~T9_E~0); 70602#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70601#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 70600#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 70599#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70598#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70597#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70596#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70595#L1338-3 assume !(0 == ~E_4~0); 70594#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70593#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70592#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70591#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70590#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 70589#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70588#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70587#L1378-3 assume !(0 == ~E_12~0); 70586#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 70585#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70584#L607-42 assume !(1 == ~m_pc~0); 70582#L607-44 is_master_triggered_~__retres1~0#1 := 0; 70581#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70580#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70579#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70578#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70577#L626-42 assume !(1 == ~t1_pc~0); 70576#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 70574#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70573#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70572#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70571#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70570#L645-42 assume 1 == ~t2_pc~0; 70569#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70567#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70566#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70565#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70564#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70563#L664-42 assume 1 == ~t3_pc~0; 70561#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70560#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70559#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70558#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70557#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70556#L683-42 assume 1 == ~t4_pc~0; 70555#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70553#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70552#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70551#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70550#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70549#L702-42 assume 1 == ~t5_pc~0; 70547#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70546#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70545#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70544#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 70543#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70542#L721-42 assume !(1 == ~t6_pc~0); 70541#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 70539#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70538#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70537#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66757#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66599#L740-42 assume 1 == ~t7_pc~0; 66600#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66336#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70343#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70342#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70341#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70340#L759-42 assume 1 == ~t8_pc~0; 66865#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66794#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66795#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66877#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66878#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66979#L778-42 assume !(1 == ~t9_pc~0); 66807#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 66808#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67235#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67137#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67138#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67195#L797-42 assume 1 == ~t10_pc~0; 66341#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66342#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67383#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67743#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 67236#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67237#L816-42 assume !(1 == ~t11_pc~0); 65889#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 65888#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66434#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66435#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66514#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66515#L835-42 assume 1 == ~t12_pc~0; 66930#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66815#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66487#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66488#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 67642#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67396#L854-42 assume 1 == ~t13_pc~0; 67397#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 66431#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66041#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66042#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66694#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66695#L1401-3 assume !(1 == ~M_E~0); 67955#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70157#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70155#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70153#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70151#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70149#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70147#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70143#L1436-3 assume !(1 == ~T8_E~0); 70142#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70141#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70140#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70139#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70138#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70137#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70136#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70135#L1476-3 assume !(1 == ~E_3~0); 70134#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70133#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70132#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70131#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70130#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70129#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70128#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70113#L1516-3 assume !(1 == ~E_11~0); 70111#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 70109#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 70108#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70096#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 70093#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67170#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 66796#L1911 assume !(0 == start_simulation_~tmp~3#1); 66797#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 71015#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 71001#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 71000#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 70999#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70998#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70997#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 70811#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 70809#L1892-2 [2021-11-20 07:20:41,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:41,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1174343799, now seen corresponding path program 1 times [2021-11-20 07:20:41,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:41,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842969163] [2021-11-20 07:20:41,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:41,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:41,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:41,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:41,743 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:41,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842969163] [2021-11-20 07:20:41,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842969163] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:41,743 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:41,743 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:41,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040346977] [2021-11-20 07:20:41,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:41,744 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:41,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:41,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1496006700, now seen corresponding path program 1 times [2021-11-20 07:20:41,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:41,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082765143] [2021-11-20 07:20:41,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:41,746 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:41,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:41,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:41,793 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:41,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082765143] [2021-11-20 07:20:41,794 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082765143] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:41,794 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:41,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:41,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374463695] [2021-11-20 07:20:41,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:41,795 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:41,795 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:41,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:20:41,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:20:41,796 INFO L87 Difference]: Start difference. First operand 6963 states and 10201 transitions. cyclomatic complexity: 3240 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:42,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:42,048 INFO L93 Difference]: Finished difference Result 13361 states and 19570 transitions. [2021-11-20 07:20:42,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:20:42,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13361 states and 19570 transitions. [2021-11-20 07:20:42,116 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2021-11-20 07:20:42,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13361 states to 13361 states and 19570 transitions. [2021-11-20 07:20:42,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13361 [2021-11-20 07:20:42,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13361 [2021-11-20 07:20:42,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13361 states and 19570 transitions. [2021-11-20 07:20:42,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:42,203 INFO L681 BuchiCegarLoop]: Abstraction has 13361 states and 19570 transitions. [2021-11-20 07:20:42,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13361 states and 19570 transitions. [2021-11-20 07:20:42,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13361 to 13357. [2021-11-20 07:20:42,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13357 states, 13357 states have (on average 1.4648498914426893) internal successors, (19566), 13356 states have internal predecessors, (19566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:42,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13357 states to 13357 states and 19566 transitions. [2021-11-20 07:20:42,452 INFO L704 BuchiCegarLoop]: Abstraction has 13357 states and 19566 transitions. [2021-11-20 07:20:42,452 INFO L587 BuchiCegarLoop]: Abstraction has 13357 states and 19566 transitions. [2021-11-20 07:20:42,452 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-20 07:20:42,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13357 states and 19566 transitions. [2021-11-20 07:20:42,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2021-11-20 07:20:42,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:42,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:42,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:42,496 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:42,497 INFO L791 eck$LassoCheckResult]: Stem: 87086#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86897#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86606#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86607#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87893#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87894#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86743#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86744#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87220#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87047#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87048#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86814#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86815#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87231#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87431#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87595#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87635#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86825#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86826#L1258 assume !(0 == ~M_E~0); 88168#L1258-2 assume !(0 == ~T1_E~0); 87134#L1263-1 assume !(0 == ~T2_E~0); 87135#L1268-1 assume !(0 == ~T3_E~0); 87469#L1273-1 assume !(0 == ~T4_E~0); 88144#L1278-1 assume !(0 == ~T5_E~0); 87967#L1283-1 assume !(0 == ~T6_E~0); 87968#L1288-1 assume !(0 == ~T7_E~0); 88285#L1293-1 assume !(0 == ~T8_E~0); 88265#L1298-1 assume !(0 == ~T9_E~0); 88159#L1303-1 assume !(0 == ~T10_E~0); 86635#L1308-1 assume !(0 == ~T11_E~0); 86577#L1313-1 assume !(0 == ~T12_E~0); 86578#L1318-1 assume !(0 == ~T13_E~0); 86584#L1323-1 assume !(0 == ~E_1~0); 86585#L1328-1 assume !(0 == ~E_2~0); 86753#L1333-1 assume !(0 == ~E_3~0); 87793#L1338-1 assume !(0 == ~E_4~0); 87794#L1343-1 assume !(0 == ~E_5~0); 87934#L1348-1 assume !(0 == ~E_6~0); 88328#L1353-1 assume !(0 == ~E_7~0); 87490#L1358-1 assume !(0 == ~E_8~0); 87491#L1363-1 assume !(0 == ~E_9~0); 87822#L1368-1 assume !(0 == ~E_10~0); 86414#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86415#L1378-1 assume !(0 == ~E_12~0); 86702#L1383-1 assume !(0 == ~E_13~0); 86703#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87496#L607 assume !(1 == ~m_pc~0); 86773#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86774#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87932#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87404#L1560 assume !(0 != activate_threads_~tmp~1#1); 87405#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86597#L626 assume !(1 == ~t1_pc~0); 86598#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86873#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86874#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87051#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86497#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86498#L645 assume 1 == ~t2_pc~0; 86614#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86571#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87274#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87275#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87379#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87380#L664 assume 1 == ~t3_pc~0; 88322#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86336#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86337#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87010#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87011#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88180#L683 assume !(1 == ~t4_pc~0); 87619#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87567#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87568#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87605#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87749#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87324#L702 assume 1 == ~t5_pc~0; 87325#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87240#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87744#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88122#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88046#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86386#L721 assume !(1 == ~t6_pc~0); 86359#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86360#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86524#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87021#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87022#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87674#L740 assume 1 == ~t7_pc~0; 86435#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86245#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86246#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86235#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86236#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86954#L759 assume !(1 == ~t8_pc~0); 86955#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86985#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87742#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87743#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87907#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88284#L778 assume 1 == ~t9_pc~0; 88119#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86413#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86351#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86279#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86280#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86610#L797 assume !(1 == ~t10_pc~0); 86611#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86730#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87998#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87132#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87133#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87451#L816 assume 1 == ~t11_pc~0; 86316#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86317#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87091#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87028#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87029#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87594#L835 assume 1 == ~t12_pc~0; 87466#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86482#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86504#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86645#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87192#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87193#L854 assume !(1 == ~t13_pc~0); 86816#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86817#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86869#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86522#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86523#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88041#L1401 assume !(1 == ~M_E~0); 87014#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87015#L1406-1 assume !(1 == ~T2_E~0); 95827#L1411-1 assume !(1 == ~T3_E~0); 95826#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95825#L1421-1 assume !(1 == ~T5_E~0); 95824#L1426-1 assume !(1 == ~T6_E~0); 95823#L1431-1 assume !(1 == ~T7_E~0); 95822#L1436-1 assume !(1 == ~T8_E~0); 95821#L1441-1 assume !(1 == ~T9_E~0); 87122#L1446-1 assume !(1 == ~T10_E~0); 87123#L1451-1 assume !(1 == ~T11_E~0); 87931#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87515#L1461-1 assume !(1 == ~T13_E~0); 87040#L1466-1 assume !(1 == ~E_1~0); 87041#L1471-1 assume !(1 == ~E_2~0); 87905#L1476-1 assume !(1 == ~E_3~0); 87906#L1481-1 assume !(1 == ~E_4~0); 95720#L1486-1 assume !(1 == ~E_5~0); 95719#L1491-1 assume !(1 == ~E_6~0); 95718#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 95717#L1501-1 assume !(1 == ~E_8~0); 95716#L1506-1 assume !(1 == ~E_9~0); 95715#L1511-1 assume !(1 == ~E_10~0); 95714#L1516-1 assume !(1 == ~E_11~0); 95713#L1521-1 assume !(1 == ~E_12~0); 95712#L1526-1 assume !(1 == ~E_13~0); 95711#L1531-1 assume { :end_inline_reset_delta_events } true; 95710#L1892-2 [2021-11-20 07:20:42,497 INFO L793 eck$LassoCheckResult]: Loop: 95710#L1892-2 assume !false; 95695#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95693#L1233 assume !false; 95645#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 95603#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 95598#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 95582#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95563#L1046 assume !(0 != eval_~tmp~0#1); 95558#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95557#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95555#L1258-3 assume !(0 == ~M_E~0); 95520#L1258-5 assume !(0 == ~T1_E~0); 95501#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95492#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95465#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95450#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 95448#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95446#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95443#L1293-3 assume !(0 == ~T8_E~0); 95441#L1298-3 assume !(0 == ~T9_E~0); 95439#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 95437#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 95435#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 95433#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 95431#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95429#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95427#L1333-3 assume !(0 == ~E_3~0); 95425#L1338-3 assume !(0 == ~E_4~0); 95423#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95421#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 95419#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 95417#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 95415#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 95413#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 95411#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 95409#L1378-3 assume !(0 == ~E_12~0); 95407#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 95405#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95403#L607-42 assume !(1 == ~m_pc~0); 95400#L607-44 is_master_triggered_~__retres1~0#1 := 0; 95398#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95396#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95394#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95392#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95390#L626-42 assume !(1 == ~t1_pc~0); 95387#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 95384#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95382#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95379#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95377#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95375#L645-42 assume 1 == ~t2_pc~0; 95373#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95370#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95368#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95366#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95363#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95361#L664-42 assume !(1 == ~t3_pc~0); 95359#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 95356#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95354#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95352#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95349#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95347#L683-42 assume 1 == ~t4_pc~0; 95345#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95342#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95340#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95296#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 95293#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95290#L702-42 assume 1 == ~t5_pc~0; 95285#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95216#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95214#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95212#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 95210#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95208#L721-42 assume 1 == ~t6_pc~0; 95205#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95202#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95200#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95198#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95196#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95194#L740-42 assume 1 == ~t7_pc~0; 95191#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95188#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95186#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95184#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 95183#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95182#L759-42 assume !(1 == ~t8_pc~0); 95181#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 95178#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87412#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87413#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 95172#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95171#L778-42 assume !(1 == ~t9_pc~0); 95169#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 95168#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95167#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95166#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 95165#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95164#L797-42 assume !(1 == ~t10_pc~0); 95163#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 95161#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95160#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95159#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 95158#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95157#L816-42 assume !(1 == ~t11_pc~0); 95155#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 95154#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95153#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95152#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 95151#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 95149#L835-42 assume 1 == ~t12_pc~0; 95145#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95143#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95141#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95139#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 95137#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 95135#L854-42 assume !(1 == ~t13_pc~0); 95131#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 95129#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95127#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95125#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 95123#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95121#L1401-3 assume !(1 == ~M_E~0); 92974#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87917#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 95116#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95114#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95112#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95110#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95107#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 95105#L1436-3 assume !(1 == ~T8_E~0); 93294#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 95102#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 95100#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 95098#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 95095#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 95093#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95091#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95089#L1476-3 assume !(1 == ~E_3~0); 86757#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 95086#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95083#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 95081#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 95079#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 95077#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 95075#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 95073#L1516-3 assume !(1 == ~E_11~0); 95070#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 95068#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 95066#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 95037#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88408#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87534#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 87142#L1911 assume !(0 == start_simulation_~tmp~3#1); 87143#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87721#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86715#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87644#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 86418#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86419#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86648#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 86649#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 95710#L1892-2 [2021-11-20 07:20:42,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:42,498 INFO L85 PathProgramCache]: Analyzing trace with hash 2121381685, now seen corresponding path program 1 times [2021-11-20 07:20:42,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:42,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510765304] [2021-11-20 07:20:42,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:42,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:42,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:42,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:42,536 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:42,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510765304] [2021-11-20 07:20:42,536 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510765304] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:42,537 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:42,537 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:42,537 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453545505] [2021-11-20 07:20:42,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:42,538 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:42,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:42,538 INFO L85 PathProgramCache]: Analyzing trace with hash 509055303, now seen corresponding path program 1 times [2021-11-20 07:20:42,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:42,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213869461] [2021-11-20 07:20:42,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:42,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:42,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:42,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:42,582 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:42,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213869461] [2021-11-20 07:20:42,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213869461] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:42,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:42,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:42,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654139892] [2021-11-20 07:20:42,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:42,584 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:42,584 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:42,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:20:42,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:20:42,585 INFO L87 Difference]: Start difference. First operand 13357 states and 19566 transitions. cyclomatic complexity: 6213 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:42,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:42,907 INFO L93 Difference]: Finished difference Result 25713 states and 37651 transitions. [2021-11-20 07:20:42,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:20:42,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25713 states and 37651 transitions. [2021-11-20 07:20:43,019 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2021-11-20 07:20:43,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25713 states to 25713 states and 37651 transitions. [2021-11-20 07:20:43,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25713 [2021-11-20 07:20:43,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25713 [2021-11-20 07:20:43,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25713 states and 37651 transitions. [2021-11-20 07:20:43,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:43,168 INFO L681 BuchiCegarLoop]: Abstraction has 25713 states and 37651 transitions. [2021-11-20 07:20:43,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25713 states and 37651 transitions. [2021-11-20 07:20:43,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25713 to 25705. [2021-11-20 07:20:43,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25705 states, 25705 states have (on average 1.4644232639564287) internal successors, (37643), 25704 states have internal predecessors, (37643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:43,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25705 states to 25705 states and 37643 transitions. [2021-11-20 07:20:43,706 INFO L704 BuchiCegarLoop]: Abstraction has 25705 states and 37643 transitions. [2021-11-20 07:20:43,706 INFO L587 BuchiCegarLoop]: Abstraction has 25705 states and 37643 transitions. [2021-11-20 07:20:43,706 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-20 07:20:43,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25705 states and 37643 transitions. [2021-11-20 07:20:43,783 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2021-11-20 07:20:43,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:43,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:43,786 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:43,786 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:43,786 INFO L791 eck$LassoCheckResult]: Stem: 126164#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126165#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 125971#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125684#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125685#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126932#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126933#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125822#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125823#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126294#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126121#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126122#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125889#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125890#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126305#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126497#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126660#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126698#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125900#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125901#L1258 assume !(0 == ~M_E~0); 127201#L1258-2 assume !(0 == ~T1_E~0); 126209#L1263-1 assume !(0 == ~T2_E~0); 126210#L1268-1 assume !(0 == ~T3_E~0); 126531#L1273-1 assume !(0 == ~T4_E~0); 127174#L1278-1 assume !(0 == ~T5_E~0); 127004#L1283-1 assume !(0 == ~T6_E~0); 127005#L1288-1 assume !(0 == ~T7_E~0); 127311#L1293-1 assume !(0 == ~T8_E~0); 127296#L1298-1 assume !(0 == ~T9_E~0); 127190#L1303-1 assume !(0 == ~T10_E~0); 125713#L1308-1 assume !(0 == ~T11_E~0); 125655#L1313-1 assume !(0 == ~T12_E~0); 125656#L1318-1 assume !(0 == ~T13_E~0); 125662#L1323-1 assume !(0 == ~E_1~0); 125663#L1328-1 assume !(0 == ~E_2~0); 125832#L1333-1 assume !(0 == ~E_3~0); 126849#L1338-1 assume !(0 == ~E_4~0); 126850#L1343-1 assume !(0 == ~E_5~0); 126974#L1348-1 assume !(0 == ~E_6~0); 127349#L1353-1 assume !(0 == ~E_7~0); 126552#L1358-1 assume !(0 == ~E_8~0); 126553#L1363-1 assume !(0 == ~E_9~0); 126870#L1368-1 assume !(0 == ~E_10~0); 125492#L1373-1 assume !(0 == ~E_11~0); 125493#L1378-1 assume !(0 == ~E_12~0); 125780#L1383-1 assume !(0 == ~E_13~0); 125781#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126558#L607 assume !(1 == ~m_pc~0); 125851#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125852#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126972#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126472#L1560 assume !(0 != activate_threads_~tmp~1#1); 126473#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125675#L626 assume !(1 == ~t1_pc~0); 125676#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125947#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125948#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126125#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125575#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125576#L645 assume 1 == ~t2_pc~0; 125692#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125649#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126346#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126347#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126447#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126448#L664 assume 1 == ~t3_pc~0; 127345#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125416#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125417#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126085#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126086#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127211#L683 assume !(1 == ~t4_pc~0); 126683#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126633#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126634#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126669#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126805#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126392#L702 assume 1 == ~t5_pc~0; 126393#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126314#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126800#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127154#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127080#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125464#L721 assume !(1 == ~t6_pc~0); 125438#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125439#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125602#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126095#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126096#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126736#L740 assume 1 == ~t7_pc~0; 125513#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125325#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125326#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125315#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125316#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126030#L759 assume !(1 == ~t8_pc~0); 126031#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126060#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126798#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126799#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126947#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127310#L778 assume 1 == ~t9_pc~0; 127151#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125491#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125431#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125359#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125360#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125688#L797 assume !(1 == ~t10_pc~0); 125689#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125809#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127032#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126207#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126208#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126515#L816 assume 1 == ~t11_pc~0; 125396#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125397#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126168#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126102#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126103#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126659#L835 assume 1 == ~t12_pc~0; 126528#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125560#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125582#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125724#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126267#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126268#L854 assume !(1 == ~t13_pc~0); 125891#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125892#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125943#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125600#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125601#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127076#L1401 assume !(1 == ~M_E~0); 126089#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126090#L1406-1 assume !(1 == ~T2_E~0); 136415#L1411-1 assume !(1 == ~T3_E~0); 136413#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 136411#L1421-1 assume !(1 == ~T5_E~0); 136409#L1426-1 assume !(1 == ~T6_E~0); 136407#L1431-1 assume !(1 == ~T7_E~0); 125434#L1436-1 assume !(1 == ~T8_E~0); 125435#L1441-1 assume !(1 == ~T9_E~0); 136417#L1446-1 assume !(1 == ~T10_E~0); 136416#L1451-1 assume !(1 == ~T11_E~0); 126971#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126578#L1461-1 assume !(1 == ~T13_E~0); 126114#L1466-1 assume !(1 == ~E_1~0); 126115#L1471-1 assume !(1 == ~E_2~0); 129259#L1476-1 assume !(1 == ~E_3~0); 129200#L1481-1 assume !(1 == ~E_4~0); 129145#L1486-1 assume !(1 == ~E_5~0); 129096#L1491-1 assume !(1 == ~E_6~0); 129034#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 129032#L1501-1 assume !(1 == ~E_8~0); 128987#L1506-1 assume !(1 == ~E_9~0); 128985#L1511-1 assume !(1 == ~E_10~0); 128954#L1516-1 assume !(1 == ~E_11~0); 128928#L1521-1 assume !(1 == ~E_12~0); 128906#L1526-1 assume !(1 == ~E_13~0); 128892#L1531-1 assume { :end_inline_reset_delta_events } true; 128880#L1892-2 [2021-11-20 07:20:43,787 INFO L793 eck$LassoCheckResult]: Loop: 128880#L1892-2 assume !false; 128874#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128873#L1233 assume !false; 128872#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128857#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128842#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128840#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 128837#L1046 assume !(0 != eval_~tmp~0#1); 128834#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128832#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128830#L1258-3 assume !(0 == ~M_E~0); 128826#L1258-5 assume !(0 == ~T1_E~0); 128827#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 141526#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 141524#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 141522#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 141520#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 141517#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 141515#L1293-3 assume !(0 == ~T8_E~0); 141513#L1298-3 assume !(0 == ~T9_E~0); 141511#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 141509#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 141507#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 141504#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 141502#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 141500#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 141498#L1333-3 assume !(0 == ~E_3~0); 141496#L1338-3 assume !(0 == ~E_4~0); 141494#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 141491#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141489#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 141487#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 141485#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 141483#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 141482#L1373-3 assume !(0 == ~E_11~0); 141481#L1378-3 assume !(0 == ~E_12~0); 141480#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 141479#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141478#L607-42 assume !(1 == ~m_pc~0); 141476#L607-44 is_master_triggered_~__retres1~0#1 := 0; 141475#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141474#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 141471#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 141469#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141467#L626-42 assume 1 == ~t1_pc~0; 141464#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 141462#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141460#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 141458#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 141455#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141453#L645-42 assume !(1 == ~t2_pc~0); 141450#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 141448#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141447#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 141446#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 141445#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141444#L664-42 assume 1 == ~t3_pc~0; 141442#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 141441#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141440#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 141439#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 141438#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141437#L683-42 assume !(1 == ~t4_pc~0); 141435#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 141434#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141433#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 141432#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 141431#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141430#L702-42 assume 1 == ~t5_pc~0; 141428#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 141427#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141426#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 141425#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 141424#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 141423#L721-42 assume !(1 == ~t6_pc~0); 141422#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 141418#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 141416#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141414#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 141412#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141410#L740-42 assume !(1 == ~t7_pc~0); 141408#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 141405#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 141402#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 141400#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 141398#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 141396#L759-42 assume !(1 == ~t8_pc~0); 141394#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 141391#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 138664#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138661#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 138659#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138657#L778-42 assume !(1 == ~t9_pc~0); 138654#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 138652#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 138650#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138647#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 138645#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138643#L797-42 assume !(1 == ~t10_pc~0); 138640#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 138637#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138634#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138632#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138630#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138628#L816-42 assume 1 == ~t11_pc~0; 138626#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 138623#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 138620#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138618#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 138616#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138614#L835-42 assume 1 == ~t12_pc~0; 138611#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 138609#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138606#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138604#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138602#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 138600#L854-42 assume 1 == ~t13_pc~0; 138598#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 138595#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138592#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138590#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 138588#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138561#L1401-3 assume !(1 == ~M_E~0); 138559#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128513#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 138555#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138553#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138551#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 138549#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 138547#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 138545#L1436-3 assume !(1 == ~T8_E~0); 130040#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 138541#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 138539#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138537#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 138535#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 138533#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 138530#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 138528#L1476-3 assume !(1 == ~E_3~0); 129988#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 138525#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 138523#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 138521#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 138520#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 138519#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 138518#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 138517#L1516-3 assume !(1 == ~E_11~0); 128465#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 138516#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 138515#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 136817#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129296#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129233#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 129167#L1911 assume !(0 == start_simulation_~tmp~3#1); 129121#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129079#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129020#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128974#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 128947#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128923#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128905#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 128891#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 128880#L1892-2 [2021-11-20 07:20:43,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:43,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1788738547, now seen corresponding path program 1 times [2021-11-20 07:20:43,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:43,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111282813] [2021-11-20 07:20:43,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:43,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:43,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:43,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:43,831 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:43,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111282813] [2021-11-20 07:20:43,831 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111282813] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:43,831 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:43,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:43,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252238293] [2021-11-20 07:20:43,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:43,832 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:43,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:43,833 INFO L85 PathProgramCache]: Analyzing trace with hash 2146802629, now seen corresponding path program 1 times [2021-11-20 07:20:43,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:43,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685493958] [2021-11-20 07:20:43,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:43,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:43,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:43,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:43,989 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:43,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685493958] [2021-11-20 07:20:43,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685493958] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:43,990 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:43,990 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:43,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438901225] [2021-11-20 07:20:43,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:43,990 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:43,990 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:43,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:20:43,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:20:43,991 INFO L87 Difference]: Start difference. First operand 25705 states and 37643 transitions. cyclomatic complexity: 11946 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:44,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:44,682 INFO L93 Difference]: Finished difference Result 74991 states and 108894 transitions. [2021-11-20 07:20:44,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:20:44,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74991 states and 108894 transitions. [2021-11-20 07:20:45,017 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2021-11-20 07:20:45,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74991 states to 74991 states and 108894 transitions. [2021-11-20 07:20:45,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74991 [2021-11-20 07:20:45,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74991 [2021-11-20 07:20:45,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74991 states and 108894 transitions. [2021-11-20 07:20:45,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:45,581 INFO L681 BuchiCegarLoop]: Abstraction has 74991 states and 108894 transitions. [2021-11-20 07:20:45,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74991 states and 108894 transitions. [2021-11-20 07:20:46,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74991 to 72679. [2021-11-20 07:20:46,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72679 states, 72679 states have (on average 1.454147690529589) internal successors, (105686), 72678 states have internal predecessors, (105686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:47,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72679 states to 72679 states and 105686 transitions. [2021-11-20 07:20:47,061 INFO L704 BuchiCegarLoop]: Abstraction has 72679 states and 105686 transitions. [2021-11-20 07:20:47,061 INFO L587 BuchiCegarLoop]: Abstraction has 72679 states and 105686 transitions. [2021-11-20 07:20:47,061 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-20 07:20:47,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72679 states and 105686 transitions. [2021-11-20 07:20:47,345 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2021-11-20 07:20:47,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:47,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:47,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:47,347 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:47,348 INFO L791 eck$LassoCheckResult]: Stem: 226857#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 226676#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 226389#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 226390#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227599#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227600#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226526#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226527#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226985#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226819#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226820#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226595#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226596#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 226996#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227179#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227336#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227373#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226606#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226607#L1258 assume !(0 == ~M_E~0); 227839#L1258-2 assume !(0 == ~T1_E~0); 226902#L1263-1 assume !(0 == ~T2_E~0); 226903#L1268-1 assume !(0 == ~T3_E~0); 227213#L1273-1 assume !(0 == ~T4_E~0); 227819#L1278-1 assume !(0 == ~T5_E~0); 227667#L1283-1 assume !(0 == ~T6_E~0); 227668#L1288-1 assume !(0 == ~T7_E~0); 227946#L1293-1 assume !(0 == ~T8_E~0); 227929#L1298-1 assume !(0 == ~T9_E~0); 227832#L1303-1 assume !(0 == ~T10_E~0); 226417#L1308-1 assume !(0 == ~T11_E~0); 226360#L1313-1 assume !(0 == ~T12_E~0); 226361#L1318-1 assume !(0 == ~T13_E~0); 226367#L1323-1 assume !(0 == ~E_1~0); 226368#L1328-1 assume !(0 == ~E_2~0); 226536#L1333-1 assume !(0 == ~E_3~0); 227518#L1338-1 assume !(0 == ~E_4~0); 227519#L1343-1 assume !(0 == ~E_5~0); 227638#L1348-1 assume !(0 == ~E_6~0); 227985#L1353-1 assume !(0 == ~E_7~0); 227231#L1358-1 assume !(0 == ~E_8~0); 227232#L1363-1 assume !(0 == ~E_9~0); 227539#L1368-1 assume !(0 == ~E_10~0); 226197#L1373-1 assume !(0 == ~E_11~0); 226198#L1378-1 assume !(0 == ~E_12~0); 226485#L1383-1 assume !(0 == ~E_13~0); 226486#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227237#L607 assume !(1 == ~m_pc~0); 226555#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226556#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227636#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227158#L1560 assume !(0 != activate_threads_~tmp~1#1); 227159#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226380#L626 assume !(1 == ~t1_pc~0); 226381#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226652#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226653#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 226823#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226280#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226281#L645 assume !(1 == ~t2_pc~0); 226353#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226354#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227038#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 227039#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227134#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227135#L664 assume 1 == ~t3_pc~0; 227979#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226121#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226122#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226784#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226785#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227854#L683 assume !(1 == ~t4_pc~0); 227358#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227308#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227309#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227345#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227476#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227082#L702 assume 1 == ~t5_pc~0; 227083#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 227005#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227471#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227804#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227739#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226169#L721 assume !(1 == ~t6_pc~0); 226143#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226144#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226307#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226794#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226795#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227408#L740 assume 1 == ~t7_pc~0; 226218#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226031#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226032#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226021#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226022#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226729#L759 assume !(1 == ~t8_pc~0); 226730#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226759#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227469#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227470#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227613#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227945#L778 assume 1 == ~t9_pc~0; 227802#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226196#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226136#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226065#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226066#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226393#L797 assume !(1 == ~t10_pc~0); 226394#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226513#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227694#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226900#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226901#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227197#L816 assume 1 == ~t11_pc~0; 226101#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226102#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 226861#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226801#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226802#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227335#L835 assume 1 == ~t12_pc~0; 227210#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226265#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226287#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226428#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226957#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226958#L854 assume !(1 == ~t13_pc~0); 226597#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226598#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226648#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226305#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226306#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227734#L1401 assume !(1 == ~M_E~0); 226788#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226789#L1406-1 assume !(1 == ~T2_E~0); 227742#L1411-1 assume !(1 == ~T3_E~0); 227972#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227973#L1421-1 assume !(1 == ~T5_E~0); 226593#L1426-1 assume !(1 == ~T6_E~0); 226594#L1431-1 assume !(1 == ~T7_E~0); 226139#L1436-1 assume !(1 == ~T8_E~0); 226140#L1441-1 assume !(1 == ~T9_E~0); 226891#L1446-1 assume !(1 == ~T10_E~0); 226892#L1451-1 assume !(1 == ~T11_E~0); 260042#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 260040#L1461-1 assume !(1 == ~T13_E~0); 226813#L1466-1 assume !(1 == ~E_1~0); 226814#L1471-1 assume !(1 == ~E_2~0); 227611#L1476-1 assume !(1 == ~E_3~0); 227612#L1481-1 assume !(1 == ~E_4~0); 227784#L1486-1 assume !(1 == ~E_5~0); 226433#L1491-1 assume !(1 == ~E_6~0); 226073#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 226074#L1501-1 assume !(1 == ~E_8~0); 226889#L1506-1 assume !(1 == ~E_9~0); 226890#L1511-1 assume !(1 == ~E_10~0); 226846#L1516-1 assume !(1 == ~E_11~0); 226017#L1521-1 assume !(1 == ~E_12~0); 226018#L1526-1 assume !(1 == ~E_13~0); 226072#L1531-1 assume { :end_inline_reset_delta_events } true; 226618#L1892-2 [2021-11-20 07:20:47,348 INFO L793 eck$LassoCheckResult]: Loop: 226618#L1892-2 assume !false; 284351#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 284349#L1233 assume !false; 284348#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 284286#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 284284#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 284282#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 284279#L1046 assume !(0 != eval_~tmp~0#1); 284276#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 284274#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 283914#L1258-3 assume !(0 == ~M_E~0); 283886#L1258-5 assume !(0 == ~T1_E~0); 283877#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 283869#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 283862#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 283757#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 283738#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 283732#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 283726#L1293-3 assume !(0 == ~T8_E~0); 283719#L1298-3 assume !(0 == ~T9_E~0); 283713#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 283706#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 283699#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 283692#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 283685#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 283676#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 283669#L1333-3 assume !(0 == ~E_3~0); 283661#L1338-3 assume !(0 == ~E_4~0); 283653#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 283645#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 283638#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 283630#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 283623#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 283615#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 283607#L1373-3 assume !(0 == ~E_11~0); 283599#L1378-3 assume !(0 == ~E_12~0); 283593#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 283587#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 283581#L607-42 assume !(1 == ~m_pc~0); 283573#L607-44 is_master_triggered_~__retres1~0#1 := 0; 283565#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 283558#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 283551#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 283542#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282633#L626-42 assume 1 == ~t1_pc~0; 282628#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282627#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282626#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 282625#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282624#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282623#L645-42 assume !(1 == ~t2_pc~0); 282622#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 282621#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 282620#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 282619#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 282618#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282617#L664-42 assume 1 == ~t3_pc~0; 282614#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 282612#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282610#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 282608#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 282606#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282604#L683-42 assume !(1 == ~t4_pc~0); 282445#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 282443#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 282441#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282439#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282437#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282435#L702-42 assume 1 == ~t5_pc~0; 282429#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282427#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282425#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 282423#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 282421#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282419#L721-42 assume 1 == ~t6_pc~0; 282416#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 282414#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282412#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 282410#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 282408#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 282406#L740-42 assume 1 == ~t7_pc~0; 282402#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 282400#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 282398#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 282396#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 282394#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 282392#L759-42 assume 1 == ~t8_pc~0; 282388#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 282386#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 282384#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 282382#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 282380#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 282378#L778-42 assume !(1 == ~t9_pc~0); 282374#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 282372#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282370#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 282368#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 282366#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 282364#L797-42 assume 1 == ~t10_pc~0; 282360#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 282358#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 282356#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 282354#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 282352#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 282350#L816-42 assume !(1 == ~t11_pc~0); 282346#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 282344#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 282342#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 282340#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 282338#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 282336#L835-42 assume 1 == ~t12_pc~0; 282332#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 282330#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 282328#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 282326#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 282324#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 282322#L854-42 assume !(1 == ~t13_pc~0); 282318#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 282316#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 282314#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 282312#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 282310#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282308#L1401-3 assume !(1 == ~M_E~0); 277049#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 253564#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278653#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 278651#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 278649#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 278647#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 278646#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 277893#L1436-3 assume !(1 == ~T8_E~0); 277889#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 277887#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277885#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 277883#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 277881#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 277879#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 277877#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 277875#L1476-3 assume !(1 == ~E_3~0); 271314#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 277873#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 277871#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 277869#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 277867#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 277865#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 277863#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 277859#L1516-3 assume !(1 == ~E_11~0); 277858#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 277857#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 277856#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 277844#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 277841#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 277840#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 277838#L1911 assume !(0 == start_simulation_~tmp~3#1); 277839#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 285587#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 285573#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 285572#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 285571#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 285570#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 285569#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 285567#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 226618#L1892-2 [2021-11-20 07:20:47,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:47,349 INFO L85 PathProgramCache]: Analyzing trace with hash 785681682, now seen corresponding path program 1 times [2021-11-20 07:20:47,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:47,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401772245] [2021-11-20 07:20:47,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:47,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:47,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:47,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:47,388 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:47,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401772245] [2021-11-20 07:20:47,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1401772245] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:47,389 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:47,389 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:47,389 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348128375] [2021-11-20 07:20:47,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:47,390 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:47,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:47,390 INFO L85 PathProgramCache]: Analyzing trace with hash -304251705, now seen corresponding path program 1 times [2021-11-20 07:20:47,390 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:47,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843594723] [2021-11-20 07:20:47,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:47,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:47,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:47,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:47,427 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:47,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843594723] [2021-11-20 07:20:47,427 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843594723] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:47,427 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:47,428 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:20:47,428 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369206039] [2021-11-20 07:20:47,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:47,428 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:47,428 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:47,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:20:47,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:20:47,429 INFO L87 Difference]: Start difference. First operand 72679 states and 105686 transitions. cyclomatic complexity: 33023 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:48,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:48,768 INFO L93 Difference]: Finished difference Result 210030 states and 303419 transitions. [2021-11-20 07:20:48,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:20:48,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210030 states and 303419 transitions. [2021-11-20 07:20:49,749 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2021-11-20 07:20:50,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210030 states to 210030 states and 303419 transitions. [2021-11-20 07:20:50,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210030 [2021-11-20 07:20:50,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210030 [2021-11-20 07:20:50,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210030 states and 303419 transitions. [2021-11-20 07:20:50,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:20:50,725 INFO L681 BuchiCegarLoop]: Abstraction has 210030 states and 303419 transitions. [2021-11-20 07:20:50,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210030 states and 303419 transitions. [2021-11-20 07:20:52,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210030 to 202814. [2021-11-20 07:20:53,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202814 states, 202814 states have (on average 1.446897157000996) internal successors, (293451), 202813 states have internal predecessors, (293451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:54,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202814 states to 202814 states and 293451 transitions. [2021-11-20 07:20:54,015 INFO L704 BuchiCegarLoop]: Abstraction has 202814 states and 293451 transitions. [2021-11-20 07:20:54,015 INFO L587 BuchiCegarLoop]: Abstraction has 202814 states and 293451 transitions. [2021-11-20 07:20:54,015 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-20 07:20:54,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202814 states and 293451 transitions. [2021-11-20 07:20:54,463 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2021-11-20 07:20:54,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:20:54,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:20:54,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:54,466 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:20:54,466 INFO L791 eck$LassoCheckResult]: Stem: 509579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 509580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509393#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509107#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509108#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510350#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510351#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509242#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509243#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509710#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509539#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509540#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509309#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509310#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509721#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509905#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510067#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510107#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509322#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509323#L1258 assume !(0 == ~M_E~0); 510604#L1258-2 assume !(0 == ~T1_E~0); 509625#L1263-1 assume !(0 == ~T2_E~0); 509626#L1268-1 assume !(0 == ~T3_E~0); 509939#L1273-1 assume !(0 == ~T4_E~0); 510585#L1278-1 assume !(0 == ~T5_E~0); 510415#L1283-1 assume !(0 == ~T6_E~0); 510416#L1288-1 assume !(0 == ~T7_E~0); 510723#L1293-1 assume !(0 == ~T8_E~0); 510703#L1298-1 assume !(0 == ~T9_E~0); 510598#L1303-1 assume !(0 == ~T10_E~0); 509135#L1308-1 assume !(0 == ~T11_E~0); 509078#L1313-1 assume !(0 == ~T12_E~0); 509079#L1318-1 assume !(0 == ~T13_E~0); 509085#L1323-1 assume !(0 == ~E_1~0); 509086#L1328-1 assume !(0 == ~E_2~0); 509252#L1333-1 assume !(0 == ~E_3~0); 510258#L1338-1 assume !(0 == ~E_4~0); 510259#L1343-1 assume !(0 == ~E_5~0); 510385#L1348-1 assume !(0 == ~E_6~0); 510767#L1353-1 assume !(0 == ~E_7~0); 509959#L1358-1 assume !(0 == ~E_8~0); 509960#L1363-1 assume !(0 == ~E_9~0); 510285#L1368-1 assume !(0 == ~E_10~0); 508915#L1373-1 assume !(0 == ~E_11~0); 508916#L1378-1 assume !(0 == ~E_12~0); 509201#L1383-1 assume !(0 == ~E_13~0); 509202#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509966#L607 assume !(1 == ~m_pc~0); 509271#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509272#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 510383#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509884#L1560 assume !(0 != activate_threads_~tmp~1#1); 509885#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509098#L626 assume !(1 == ~t1_pc~0); 509099#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509369#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509370#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 509543#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 508998#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508999#L645 assume !(1 == ~t2_pc~0); 509071#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509072#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509763#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509764#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509860#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509861#L664 assume !(1 == ~t3_pc~0); 510313#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508839#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508840#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509503#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509504#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510619#L683 assume !(1 == ~t4_pc~0); 510092#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510039#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 510040#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 510077#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510215#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509807#L702 assume 1 == ~t5_pc~0; 509808#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509730#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510210#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510567#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510494#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508887#L721 assume !(1 == ~t6_pc~0); 508861#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508862#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509025#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509513#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509514#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510142#L740 assume 1 == ~t7_pc~0; 508936#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508750#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508751#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508740#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508741#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509445#L759 assume !(1 == ~t8_pc~0); 509446#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509476#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510208#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510209#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510364#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510722#L778 assume 1 == ~t9_pc~0; 510565#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508914#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 508854#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508783#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508784#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509111#L797 assume !(1 == ~t10_pc~0); 509112#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509229#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510440#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509623#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509624#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509923#L816 assume 1 == ~t11_pc~0; 508819#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508820#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509583#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509521#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509522#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510066#L835 assume 1 == ~t12_pc~0; 509936#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508983#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 509005#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 509145#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509680#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509681#L854 assume !(1 == ~t13_pc~0); 509311#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509312#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509365#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 509023#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 509024#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510485#L1401 assume !(1 == ~M_E~0); 509507#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 509508#L1406-1 assume !(1 == ~T2_E~0); 510497#L1411-1 assume !(1 == ~T3_E~0); 510756#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 510757#L1421-1 assume !(1 == ~T5_E~0); 509307#L1426-1 assume !(1 == ~T6_E~0); 509308#L1431-1 assume !(1 == ~T7_E~0); 508857#L1436-1 assume !(1 == ~T8_E~0); 508858#L1441-1 assume !(1 == ~T9_E~0); 509986#L1446-1 assume !(1 == ~T10_E~0); 510808#L1451-1 assume !(1 == ~T11_E~0); 510809#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 509984#L1461-1 assume !(1 == ~T13_E~0); 509985#L1466-1 assume !(1 == ~E_1~0); 510806#L1471-1 assume !(1 == ~E_2~0); 510807#L1476-1 assume !(1 == ~E_3~0); 590564#L1481-1 assume !(1 == ~E_4~0); 590562#L1486-1 assume !(1 == ~E_5~0); 590560#L1491-1 assume !(1 == ~E_6~0); 590558#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 590543#L1501-1 assume !(1 == ~E_8~0); 590542#L1506-1 assume !(1 == ~E_9~0); 590540#L1511-1 assume !(1 == ~E_10~0); 590538#L1516-1 assume !(1 == ~E_11~0); 590535#L1521-1 assume !(1 == ~E_12~0); 590534#L1526-1 assume !(1 == ~E_13~0); 590533#L1531-1 assume { :end_inline_reset_delta_events } true; 590520#L1892-2 [2021-11-20 07:20:54,467 INFO L793 eck$LassoCheckResult]: Loop: 590520#L1892-2 assume !false; 590508#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 590500#L1233 assume !false; 590501#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 590405#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 590406#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 699976#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 699974#L1046 assume !(0 != eval_~tmp~0#1); 650432#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 650428#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 650423#L1258-3 assume !(0 == ~M_E~0); 650419#L1258-5 assume !(0 == ~T1_E~0); 650413#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 650409#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 650405#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 650402#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 650398#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 650395#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 650391#L1293-3 assume !(0 == ~T8_E~0); 650386#L1298-3 assume !(0 == ~T9_E~0); 650380#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 650375#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 650369#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 650364#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 650359#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 650353#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 650346#L1333-3 assume !(0 == ~E_3~0); 650341#L1338-3 assume !(0 == ~E_4~0); 650335#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 650330#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 650325#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 650320#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 650314#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 650309#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 650303#L1373-3 assume !(0 == ~E_11~0); 650298#L1378-3 assume !(0 == ~E_12~0); 650293#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 650290#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650286#L607-42 assume !(1 == ~m_pc~0); 650282#L607-44 is_master_triggered_~__retres1~0#1 := 0; 650277#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650273#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 650269#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 650265#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 650260#L626-42 assume 1 == ~t1_pc~0; 650255#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 650249#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 650245#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 650241#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 650237#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 650232#L645-42 assume !(1 == ~t2_pc~0); 650226#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 650209#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650206#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 650203#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 650197#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 650180#L664-42 assume !(1 == ~t3_pc~0); 650138#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 650135#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 650106#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 650103#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 650100#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 650097#L683-42 assume !(1 == ~t4_pc~0); 650091#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 650085#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 650080#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 650075#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 650070#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 650065#L702-42 assume 1 == ~t5_pc~0; 650059#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 650051#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650052#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 701382#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 701379#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 701377#L721-42 assume 1 == ~t6_pc~0; 701372#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 701370#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 649990#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 649984#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 649977#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 649978#L740-42 assume 1 == ~t7_pc~0; 701358#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 701357#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 701356#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 701355#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 701352#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 701350#L759-42 assume !(1 == ~t8_pc~0); 701346#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 701343#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 649915#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 649910#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 649903#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 649904#L778-42 assume !(1 == ~t9_pc~0); 701328#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 701326#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 649873#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 649868#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 649862#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 649855#L797-42 assume 1 == ~t10_pc~0; 649849#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 649843#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 649837#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 649831#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 649824#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 649817#L816-42 assume !(1 == ~t11_pc~0); 649811#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 649806#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 649800#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 649795#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 649789#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 649783#L835-42 assume !(1 == ~t12_pc~0); 649777#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 649769#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 649762#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 649757#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 649751#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 649745#L854-42 assume 1 == ~t13_pc~0; 649739#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 649730#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 649723#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 649717#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 649709#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 649703#L1401-3 assume !(1 == ~M_E~0); 599949#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 591986#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 649684#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 649678#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 649671#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 649665#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 649659#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 649652#L1436-3 assume !(1 == ~T8_E~0); 606387#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 649640#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 649633#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 649627#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 649622#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 649613#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 598495#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 595475#L1476-3 assume !(1 == ~E_3~0); 595472#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 595470#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 595468#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 595466#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 595464#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 595462#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 595461#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 594474#L1516-3 assume !(1 == ~E_11~0); 594472#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 594470#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 594468#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 594315#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 594303#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 594293#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 594285#L1911 assume !(0 == start_simulation_~tmp~3#1); 590767#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 590595#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 590579#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 590577#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 590575#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 590573#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 590571#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 590532#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 590520#L1892-2 [2021-11-20 07:20:54,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:54,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1058677105, now seen corresponding path program 1 times [2021-11-20 07:20:54,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:54,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534046571] [2021-11-20 07:20:54,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:54,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:54,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:54,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:54,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:54,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534046571] [2021-11-20 07:20:54,513 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534046571] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:54,513 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:54,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:20:54,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478045658] [2021-11-20 07:20:54,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:54,514 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:20:54,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:20:54,514 INFO L85 PathProgramCache]: Analyzing trace with hash 702625157, now seen corresponding path program 1 times [2021-11-20 07:20:54,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:20:54,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113726083] [2021-11-20 07:20:54,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:20:54,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:20:54,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:20:54,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:20:54,555 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:20:54,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113726083] [2021-11-20 07:20:54,556 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113726083] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:20:54,556 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:20:54,556 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:20:54,556 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310913974] [2021-11-20 07:20:54,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:20:54,557 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:20:54,557 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:20:54,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 07:20:54,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 07:20:54,558 INFO L87 Difference]: Start difference. First operand 202814 states and 293451 transitions. cyclomatic complexity: 90669 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:20:57,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:20:57,368 INFO L93 Difference]: Finished difference Result 547729 states and 795262 transitions. [2021-11-20 07:20:57,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-20 07:20:57,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547729 states and 795262 transitions. [2021-11-20 07:21:00,753 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2021-11-20 07:21:01,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547729 states to 547729 states and 795262 transitions. [2021-11-20 07:21:01,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547729 [2021-11-20 07:21:02,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547729 [2021-11-20 07:21:02,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547729 states and 795262 transitions. [2021-11-20 07:21:02,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:21:02,954 INFO L681 BuchiCegarLoop]: Abstraction has 547729 states and 795262 transitions. [2021-11-20 07:21:03,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547729 states and 795262 transitions. [2021-11-20 07:21:05,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547729 to 207977. [2021-11-20 07:21:06,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207977 states, 207977 states have (on average 1.4358029974468332) internal successors, (298614), 207976 states have internal predecessors, (298614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:21:06,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207977 states to 207977 states and 298614 transitions. [2021-11-20 07:21:06,561 INFO L704 BuchiCegarLoop]: Abstraction has 207977 states and 298614 transitions. [2021-11-20 07:21:06,561 INFO L587 BuchiCegarLoop]: Abstraction has 207977 states and 298614 transitions. [2021-11-20 07:21:06,561 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-20 07:21:06,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207977 states and 298614 transitions. [2021-11-20 07:21:07,112 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2021-11-20 07:21:07,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:21:07,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:21:07,117 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:21:07,117 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:21:07,118 INFO L791 eck$LassoCheckResult]: Stem: 1260138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1260139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1259953#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1259665#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1259666#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260932#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260933#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259802#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259803#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260276#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260099#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260100#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259869#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259870#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260283#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260472#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260635#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260676#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259884#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259885#L1258 assume !(0 == ~M_E~0); 1261187#L1258-2 assume !(0 == ~T1_E~0); 1260185#L1263-1 assume !(0 == ~T2_E~0); 1260186#L1268-1 assume !(0 == ~T3_E~0); 1260507#L1273-1 assume !(0 == ~T4_E~0); 1261163#L1278-1 assume !(0 == ~T5_E~0); 1260989#L1283-1 assume !(0 == ~T6_E~0); 1260990#L1288-1 assume !(0 == ~T7_E~0); 1261312#L1293-1 assume !(0 == ~T8_E~0); 1261292#L1298-1 assume !(0 == ~T9_E~0); 1261180#L1303-1 assume !(0 == ~T10_E~0); 1259693#L1308-1 assume !(0 == ~T11_E~0); 1259636#L1313-1 assume !(0 == ~T12_E~0); 1259637#L1318-1 assume !(0 == ~T13_E~0); 1259645#L1323-1 assume !(0 == ~E_1~0); 1259646#L1328-1 assume !(0 == ~E_2~0); 1259812#L1333-1 assume !(0 == ~E_3~0); 1260838#L1338-1 assume !(0 == ~E_4~0); 1260839#L1343-1 assume !(0 == ~E_5~0); 1260962#L1348-1 assume !(0 == ~E_6~0); 1261351#L1353-1 assume !(0 == ~E_7~0); 1260526#L1358-1 assume !(0 == ~E_8~0); 1260527#L1363-1 assume !(0 == ~E_9~0); 1260865#L1368-1 assume !(0 == ~E_10~0); 1259473#L1373-1 assume !(0 == ~E_11~0); 1259474#L1378-1 assume !(0 == ~E_12~0); 1259762#L1383-1 assume !(0 == ~E_13~0); 1259763#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260532#L607 assume !(1 == ~m_pc~0); 1259831#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259832#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260960#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260451#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260452#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259656#L626 assume !(1 == ~t1_pc~0); 1259657#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259931#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259932#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260105#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259559#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259560#L645 assume !(1 == ~t2_pc~0); 1259629#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259630#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1260326#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1260327#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260425#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260426#L664 assume !(1 == ~t3_pc~0); 1260892#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259401#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259402#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260062#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260063#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261203#L683 assume !(1 == ~t4_pc~0); 1260661#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260609#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260610#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261364#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260789#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260372#L702 assume 1 == ~t5_pc~0; 1260373#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260293#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260784#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261144#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261067#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259445#L721 assume !(1 == ~t6_pc~0); 1259419#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259420#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259583#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1260072#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260073#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260712#L740 assume 1 == ~t7_pc~0; 1259494#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259308#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259309#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259298#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259299#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1260006#L759 assume !(1 == ~t8_pc~0); 1260007#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260035#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260782#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260783#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260945#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261310#L778 assume 1 == ~t9_pc~0; 1261142#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259472#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259412#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259341#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259342#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259670#L797 assume !(1 == ~t10_pc~0); 1259671#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259789#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1261015#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260183#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260184#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260490#L816 assume 1 == ~t11_pc~0; 1259377#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259378#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260144#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260079#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260080#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260634#L835 assume 1 == ~t12_pc~0; 1260503#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259541#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259563#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259704#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260244#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260245#L854 assume !(1 == ~t13_pc~0); 1259871#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259872#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259927#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259581#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259582#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261058#L1401 assume !(1 == ~M_E~0); 1260066#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1260067#L1406-1 assume !(1 == ~T2_E~0); 1261069#L1411-1 assume !(1 == ~T3_E~0); 1261339#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1261340#L1421-1 assume !(1 == ~T5_E~0); 1259867#L1426-1 assume !(1 == ~T6_E~0); 1259868#L1431-1 assume !(1 == ~T7_E~0); 1259415#L1436-1 assume !(1 == ~T8_E~0); 1259416#L1441-1 assume !(1 == ~T9_E~0); 1260176#L1446-1 assume !(1 == ~T10_E~0); 1260177#L1451-1 assume !(1 == ~T11_E~0); 1260959#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1260552#L1461-1 assume !(1 == ~T13_E~0); 1260093#L1466-1 assume !(1 == ~E_1~0); 1260094#L1471-1 assume !(1 == ~E_2~0); 1260943#L1476-1 assume !(1 == ~E_3~0); 1260944#L1481-1 assume !(1 == ~E_4~0); 1417361#L1486-1 assume !(1 == ~E_5~0); 1417359#L1491-1 assume !(1 == ~E_6~0); 1417356#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1417354#L1501-1 assume !(1 == ~E_8~0); 1417352#L1506-1 assume !(1 == ~E_9~0); 1417350#L1511-1 assume !(1 == ~E_10~0); 1417348#L1516-1 assume !(1 == ~E_11~0); 1417345#L1521-1 assume !(1 == ~E_12~0); 1417342#L1526-1 assume !(1 == ~E_13~0); 1417340#L1531-1 assume { :end_inline_reset_delta_events } true; 1417337#L1892-2 [2021-11-20 07:21:07,118 INFO L793 eck$LassoCheckResult]: Loop: 1417337#L1892-2 assume !false; 1412360#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1412358#L1233 assume !false; 1412356#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1412328#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1412326#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1412324#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1412319#L1046 assume !(0 != eval_~tmp~0#1); 1259427#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1259428#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1260636#L1258-3 assume !(0 == ~M_E~0); 1261347#L1258-5 assume !(0 == ~T1_E~0); 1259573#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1259574#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1261335#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1261345#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1261346#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1259792#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1259793#L1293-3 assume !(0 == ~T8_E~0); 1261002#L1298-3 assume !(0 == ~T9_E~0); 1261003#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1261212#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1261001#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1260437#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1259569#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1259570#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1261106#L1333-3 assume !(0 == ~E_3~0); 1259714#L1338-3 assume !(0 == ~E_4~0); 1259715#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1260913#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1261116#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1261117#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1260385#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1259929#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1259930#L1373-3 assume !(0 == ~E_11~0); 1260735#L1378-3 assume !(0 == ~E_12~0); 1260736#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1260956#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260957#L607-42 assume !(1 == ~m_pc~0); 1260765#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1260223#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260224#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1259945#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1259946#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1260491#L626-42 assume !(1 == ~t1_pc~0); 1260031#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1260030#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1260348#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260349#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1259605#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259606#L645-42 assume !(1 == ~t2_pc~0); 1260887#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1260888#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1261075#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1259813#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1259320#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1259321#L664-42 assume !(1 == ~t3_pc~0); 1259847#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1259848#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1261249#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260674#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1260675#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1260879#L683-42 assume !(1 == ~t4_pc~0); 1260535#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1260536#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1261384#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261194#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1261195#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260996#L702-42 assume !(1 == ~t5_pc~0); 1260021#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1260022#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260330#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261098#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1259335#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259336#L721-42 assume !(1 == ~t6_pc~0); 1259490#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1259509#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259977#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1261323#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1260154#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1259995#L740-42 assume !(1 == ~t7_pc~0); 1259728#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1259729#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1260286#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1260134#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1260135#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1260422#L759-42 assume 1 == ~t8_pc~0; 1260263#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1260191#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260192#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260274#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1260275#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1260371#L778-42 assume !(1 == ~t9_pc~0); 1260206#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1260207#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1260641#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1260537#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1260538#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1260602#L797-42 assume 1 == ~t10_pc~0; 1259734#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1259735#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260797#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1261175#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1260642#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260643#L816-42 assume !(1 == ~t11_pc~0); 1259286#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1259285#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1259827#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1259828#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1259910#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1259911#L835-42 assume 1 == ~t12_pc~0; 1260325#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1260219#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259882#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259883#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1261065#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260812#L854-42 assume !(1 == ~t13_pc~0); 1259823#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1259824#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259436#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259437#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1260091#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1260092#L1401-3 assume !(1 == ~M_E~0); 1261404#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1369451#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1463302#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1463300#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1463298#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1463296#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1463294#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1463292#L1436-3 assume !(1 == ~T8_E~0); 1455110#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1463288#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1463286#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1463284#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1463282#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1463281#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1463277#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1463275#L1476-3 assume !(1 == ~E_3~0); 1460695#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1463273#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1463272#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1463271#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1463253#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1463246#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1463176#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1396639#L1516-3 assume !(1 == ~E_11~0); 1396638#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1396637#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1396636#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1396621#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1396618#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1396617#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1396615#L1911 assume !(0 == start_simulation_~tmp~3#1); 1396616#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1425603#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1425575#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1425573#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1425571#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1425569#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1425567#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1417339#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1417337#L1892-2 [2021-11-20 07:21:07,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:21:07,119 INFO L85 PathProgramCache]: Analyzing trace with hash -820453841, now seen corresponding path program 1 times [2021-11-20 07:21:07,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:21:07,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311275679] [2021-11-20 07:21:07,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:21:07,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:21:07,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:21:07,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:21:07,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:21:07,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311275679] [2021-11-20 07:21:07,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311275679] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:21:07,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:21:07,166 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:21:07,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969185481] [2021-11-20 07:21:07,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:21:07,166 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:21:07,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:21:07,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1868413088, now seen corresponding path program 1 times [2021-11-20 07:21:07,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:21:07,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006257048] [2021-11-20 07:21:07,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:21:07,168 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:21:07,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:21:07,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:21:07,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:21:07,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006257048] [2021-11-20 07:21:07,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006257048] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:21:07,212 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:21:07,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:21:07,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802344007] [2021-11-20 07:21:07,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:21:07,213 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:21:07,213 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:21:07,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:21:07,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:21:07,214 INFO L87 Difference]: Start difference. First operand 207977 states and 298614 transitions. cyclomatic complexity: 90669 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:21:09,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:21:09,288 INFO L93 Difference]: Finished difference Result 399424 states and 571773 transitions. [2021-11-20 07:21:09,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:21:09,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399424 states and 571773 transitions. [2021-11-20 07:21:11,709 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2021-11-20 07:21:13,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399424 states to 399424 states and 571773 transitions. [2021-11-20 07:21:13,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399424 [2021-11-20 07:21:13,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399424 [2021-11-20 07:21:13,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399424 states and 571773 transitions. [2021-11-20 07:21:13,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:21:13,414 INFO L681 BuchiCegarLoop]: Abstraction has 399424 states and 571773 transitions. [2021-11-20 07:21:13,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399424 states and 571773 transitions.