./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c2bb9f0c15e3c3296f863c26b4377b27546cf1c417a60e9663a6ff48eb617ef8 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 06:11:28,977 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 06:11:28,980 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 06:11:29,015 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 06:11:29,016 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 06:11:29,018 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 06:11:29,020 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 06:11:29,023 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 06:11:29,026 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 06:11:29,027 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 06:11:29,029 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 06:11:29,031 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 06:11:29,031 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 06:11:29,033 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 06:11:29,035 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 06:11:29,037 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 06:11:29,038 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 06:11:29,040 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 06:11:29,042 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 06:11:29,045 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 06:11:29,048 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 06:11:29,050 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 06:11:29,051 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 06:11:29,053 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 06:11:29,057 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 06:11:29,058 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 06:11:29,058 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 06:11:29,060 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 06:11:29,061 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 06:11:29,062 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 06:11:29,063 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 06:11:29,064 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 06:11:29,065 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 06:11:29,067 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 06:11:29,068 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 06:11:29,068 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 06:11:29,069 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 06:11:29,070 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 06:11:29,070 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 06:11:29,071 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 06:11:29,072 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 06:11:29,073 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 06:11:29,102 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 06:11:29,109 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 06:11:29,110 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 06:11:29,111 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 06:11:29,112 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 06:11:29,113 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 06:11:29,114 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 06:11:29,114 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 06:11:29,114 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 06:11:29,115 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 06:11:29,116 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 06:11:29,117 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 06:11:29,117 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 06:11:29,117 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 06:11:29,118 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 06:11:29,118 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 06:11:29,118 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 06:11:29,119 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 06:11:29,119 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 06:11:29,119 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 06:11:29,120 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 06:11:29,120 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 06:11:29,120 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 06:11:29,121 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 06:11:29,121 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 06:11:29,121 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 06:11:29,123 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 06:11:29,124 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 06:11:29,124 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 06:11:29,125 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 06:11:29,125 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 06:11:29,125 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 06:11:29,127 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 06:11:29,127 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c2bb9f0c15e3c3296f863c26b4377b27546cf1c417a60e9663a6ff48eb617ef8 [2021-11-20 06:11:29,470 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 06:11:29,508 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 06:11:29,510 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 06:11:29,512 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 06:11:29,513 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 06:11:29,515 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i [2021-11-20 06:11:29,607 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/data/08e23b381/997dc5886d4c4d228625c7838cfe26e9/FLAG609304d5a [2021-11-20 06:11:30,348 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 06:11:30,349 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i [2021-11-20 06:11:30,366 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/data/08e23b381/997dc5886d4c4d228625c7838cfe26e9/FLAG609304d5a [2021-11-20 06:11:30,521 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/data/08e23b381/997dc5886d4c4d228625c7838cfe26e9 [2021-11-20 06:11:30,524 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 06:11:30,526 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 06:11:30,528 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 06:11:30,528 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 06:11:30,555 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 06:11:30,556 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:11:30" (1/1) ... [2021-11-20 06:11:30,557 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1648263e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:30, skipping insertion in model container [2021-11-20 06:11:30,557 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:11:30" (1/1) ... [2021-11-20 06:11:30,564 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 06:11:30,649 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 06:11:31,247 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[33021,33034] [2021-11-20 06:11:31,441 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[44124,44137] [2021-11-20 06:11:31,445 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[44245,44258] [2021-11-20 06:11:31,454 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 06:11:31,479 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 06:11:31,539 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[33021,33034] [2021-11-20 06:11:31,619 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[44124,44137] [2021-11-20 06:11:31,620 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i[44245,44258] [2021-11-20 06:11:31,623 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 06:11:31,685 INFO L208 MainTranslator]: Completed translation [2021-11-20 06:11:31,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31 WrapperNode [2021-11-20 06:11:31,686 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 06:11:31,687 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 06:11:31,687 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 06:11:31,687 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 06:11:31,696 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,745 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,838 INFO L137 Inliner]: procedures = 176, calls = 277, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 996 [2021-11-20 06:11:31,839 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 06:11:31,839 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 06:11:31,840 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 06:11:31,840 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 06:11:31,852 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,853 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,890 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,891 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,982 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,994 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:31,999 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:32,009 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 06:11:32,010 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 06:11:32,010 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 06:11:32,011 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 06:11:32,012 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (1/1) ... [2021-11-20 06:11:32,020 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 06:11:32,033 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:11:32,047 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 06:11:32,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 06:11:32,100 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-20 06:11:32,100 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-20 06:11:32,100 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2021-11-20 06:11:32,100 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2021-11-20 06:11:32,101 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-11-20 06:11:32,101 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 06:11:32,101 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2021-11-20 06:11:32,101 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-20 06:11:32,101 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2021-11-20 06:11:32,102 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2021-11-20 06:11:32,102 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-20 06:11:32,102 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 06:11:32,102 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 06:11:32,102 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 06:11:32,330 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 06:11:32,332 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 06:11:32,337 WARN L815 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2021-11-20 06:11:33,726 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 06:11:33,739 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 06:11:33,739 INFO L301 CfgBuilder]: Removed 63 assume(true) statements. [2021-11-20 06:11:33,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:11:33 BoogieIcfgContainer [2021-11-20 06:11:33,742 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 06:11:33,745 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 06:11:33,746 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 06:11:33,750 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 06:11:33,751 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:11:33,751 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 06:11:30" (1/3) ... [2021-11-20 06:11:33,753 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e0e7671 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 06:11:33, skipping insertion in model container [2021-11-20 06:11:33,753 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:11:33,754 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:11:31" (2/3) ... [2021-11-20 06:11:33,755 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e0e7671 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 06:11:33, skipping insertion in model container [2021-11-20 06:11:33,755 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:11:33,755 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:11:33" (3/3) ... [2021-11-20 06:11:33,757 INFO L388 chiAutomizerObserver]: Analyzing ICFG uthash_SFH_test7-1.i [2021-11-20 06:11:33,814 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 06:11:33,814 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 06:11:33,814 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 06:11:33,814 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 06:11:33,814 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 06:11:33,814 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 06:11:33,814 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 06:11:33,814 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 06:11:33,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-20 06:11:33,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 171 [2021-11-20 06:11:33,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:11:33,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:11:33,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-20 06:11:33,886 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2021-11-20 06:11:33,886 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 06:11:33,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-20 06:11:33,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 171 [2021-11-20 06:11:33,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:11:33,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:11:33,904 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-20 06:11:33,904 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2021-11-20 06:11:33,912 INFO L791 eck$LassoCheckResult]: Stem: 167#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 65#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 140#L715-4true [2021-11-20 06:11:33,912 INFO L793 eck$LassoCheckResult]: Loop: 140#L715-4true call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 117#L715-1true assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 38#L717true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 143#L717-2true call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 128#L722-124true assume !true; 80#L715-3true call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 140#L715-4true [2021-11-20 06:11:33,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:33,919 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2021-11-20 06:11:33,929 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:33,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191666388] [2021-11-20 06:11:33,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:33,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:34,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:34,051 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:11:34,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:34,124 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:11:34,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:34,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1336134572, now seen corresponding path program 1 times [2021-11-20 06:11:34,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:34,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653987475] [2021-11-20 06:11:34,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:34,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:34,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:11:34,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:11:34,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:11:34,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653987475] [2021-11-20 06:11:34,250 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653987475] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:11:34,251 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:11:34,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 06:11:34,251 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776119197] [2021-11-20 06:11:34,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:11:34,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:11:34,258 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:11:34,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-20 06:11:34,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-20 06:11:34,298 INFO L87 Difference]: Start difference. First operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:11:34,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:11:34,322 INFO L93 Difference]: Finished difference Result 182 states and 237 transitions. [2021-11-20 06:11:34,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-20 06:11:34,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182 states and 237 transitions. [2021-11-20 06:11:34,336 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 169 [2021-11-20 06:11:34,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182 states to 176 states and 231 transitions. [2021-11-20 06:11:34,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176 [2021-11-20 06:11:34,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176 [2021-11-20 06:11:34,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176 states and 231 transitions. [2021-11-20 06:11:34,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:11:34,351 INFO L681 BuchiCegarLoop]: Abstraction has 176 states and 231 transitions. [2021-11-20 06:11:34,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states and 231 transitions. [2021-11-20 06:11:34,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2021-11-20 06:11:34,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 172 states have (on average 1.308139534883721) internal successors, (225), 171 states have internal predecessors, (225), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-20 06:11:34,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 231 transitions. [2021-11-20 06:11:34,395 INFO L704 BuchiCegarLoop]: Abstraction has 176 states and 231 transitions. [2021-11-20 06:11:34,395 INFO L587 BuchiCegarLoop]: Abstraction has 176 states and 231 transitions. [2021-11-20 06:11:34,395 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 06:11:34,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 231 transitions. [2021-11-20 06:11:34,399 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 169 [2021-11-20 06:11:34,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:11:34,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:11:34,401 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-20 06:11:34,401 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:11:34,401 INFO L791 eck$LassoCheckResult]: Stem: 548#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 481#L715-4 [2021-11-20 06:11:34,403 INFO L793 eck$LassoCheckResult]: Loop: 481#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 528#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 443#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 444#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 536#L722-124 havoc main_~_ha_hashv~0#1; 537#L722-49 goto; 476#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 424#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 425#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 486#L722-10 assume main_#t~switch22#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 501#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 458#L722-13 assume main_#t~switch22#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 459#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 494#L722-16 assume main_#t~switch22#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 521#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 418#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 419#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 527#L722-22 assume !main_#t~switch22#1; 522#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 523#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 460#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 461#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 534#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 535#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 484#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 427#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 428#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 515#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 376#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 377#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 505#L722-42 havoc main_#t~switch22#1; 506#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768); 530#L722-44 goto; 403#L722-46 goto; 404#L722-48 goto; 546#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 545#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 519#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 520#L722-66 goto; 488#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 477#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1);havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 478#L722-70 goto; 541#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 407#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 408#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 497#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 373#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 375#L722-117 goto; 469#L722-119 goto; 491#L722-121 goto; 388#L722-123 goto; 389#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 481#L715-4 [2021-11-20 06:11:34,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:34,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2021-11-20 06:11:34,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:34,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688118540] [2021-11-20 06:11:34,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:34,405 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:34,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:34,426 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:11:34,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:34,453 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:11:34,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:34,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1570577107, now seen corresponding path program 1 times [2021-11-20 06:11:34,454 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:34,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536452788] [2021-11-20 06:11:34,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:34,455 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:34,472 ERROR L247 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2021-11-20 06:11:34,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [26504238] [2021-11-20 06:11:34,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:34,473 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:11:34,474 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:11:34,475 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:11:34,491 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-11-20 06:11:34,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:11:34,705 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-20 06:11:34,711 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:11:34,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:11:34,909 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-20 06:11:34,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:11:34,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536452788] [2021-11-20 06:11:34,913 WARN L312 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2021-11-20 06:11:34,914 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [26504238] [2021-11-20 06:11:34,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [26504238] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:11:34,916 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:11:34,916 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:11:34,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168535516] [2021-11-20 06:11:34,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:11:34,917 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:11:34,918 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:11:34,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:11:34,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:11:34,919 INFO L87 Difference]: Start difference. First operand 176 states and 231 transitions. cyclomatic complexity: 58 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:11:35,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:11:35,060 INFO L93 Difference]: Finished difference Result 197 states and 252 transitions. [2021-11-20 06:11:35,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:11:35,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 197 states and 252 transitions. [2021-11-20 06:11:35,067 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 190 [2021-11-20 06:11:35,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 197 states to 197 states and 252 transitions. [2021-11-20 06:11:35,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2021-11-20 06:11:35,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2021-11-20 06:11:35,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 252 transitions. [2021-11-20 06:11:35,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:11:35,086 INFO L681 BuchiCegarLoop]: Abstraction has 197 states and 252 transitions. [2021-11-20 06:11:35,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 252 transitions. [2021-11-20 06:11:35,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 196. [2021-11-20 06:11:35,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 192 states have (on average 1.2760416666666667) internal successors, (245), 191 states have internal predecessors, (245), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-20 06:11:35,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 251 transitions. [2021-11-20 06:11:35,106 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 251 transitions. [2021-11-20 06:11:35,106 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 251 transitions. [2021-11-20 06:11:35,106 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 06:11:35,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 251 transitions. [2021-11-20 06:11:35,108 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 189 [2021-11-20 06:11:35,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:11:35,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:11:35,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-20 06:11:35,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:11:35,113 INFO L791 eck$LassoCheckResult]: Stem: 1084#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1013#L715-4 [2021-11-20 06:11:35,115 INFO L793 eck$LassoCheckResult]: Loop: 1013#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1064#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 975#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 976#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1072#L722-124 havoc main_~_ha_hashv~0#1; 1073#L722-49 goto; 1006#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 954#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 955#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1019#L722-10 assume !main_#t~switch22#1; 1063#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1086#L722-13 assume main_#t~switch22#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 985#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1027#L722-16 assume main_#t~switch22#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 1056#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 945#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 946#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1061#L722-22 assume main_#t~switch22#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 1057#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1058#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 986#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 987#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 1069#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1070#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 1085#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 957#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 958#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1049#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1050#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1055#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1040#L722-42 havoc main_#t~switch22#1; 1041#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768); 1068#L722-44 goto; 935#L722-46 goto; 936#L722-48 goto; 1082#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1081#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1053#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1054#L722-66 goto; 1023#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1009#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1);havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1010#L722-70 goto; 1077#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 939#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 940#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1030#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 905#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 907#L722-117 goto; 1003#L722-119 goto; 1024#L722-121 goto; 924#L722-123 goto; 925#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1013#L715-4 [2021-11-20 06:11:35,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:35,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2021-11-20 06:11:35,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:35,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807231513] [2021-11-20 06:11:35,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,118 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:35,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:35,162 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:11:35,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:35,203 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:11:35,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:35,206 INFO L85 PathProgramCache]: Analyzing trace with hash -1623964883, now seen corresponding path program 1 times [2021-11-20 06:11:35,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:35,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700044592] [2021-11-20 06:11:35,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:35,253 ERROR L247 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2021-11-20 06:11:35,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1677923130] [2021-11-20 06:11:35,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,255 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:11:35,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:11:35,264 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:11:35,287 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-11-20 06:11:35,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:11:35,449 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-20 06:11:35,456 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:11:35,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:11:35,602 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-20 06:11:35,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:11:35,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700044592] [2021-11-20 06:11:35,603 WARN L312 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2021-11-20 06:11:35,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1677923130] [2021-11-20 06:11:35,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1677923130] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:11:35,604 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:11:35,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:11:35,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953928532] [2021-11-20 06:11:35,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:11:35,606 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:11:35,606 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:11:35,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 06:11:35,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-11-20 06:11:35,607 INFO L87 Difference]: Start difference. First operand 196 states and 251 transitions. cyclomatic complexity: 58 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:11:35,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:11:35,738 INFO L93 Difference]: Finished difference Result 271 states and 347 transitions. [2021-11-20 06:11:35,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 06:11:35,740 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 347 transitions. [2021-11-20 06:11:35,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 256 [2021-11-20 06:11:35,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 347 transitions. [2021-11-20 06:11:35,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 271 [2021-11-20 06:11:35,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 271 [2021-11-20 06:11:35,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 347 transitions. [2021-11-20 06:11:35,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:11:35,749 INFO L681 BuchiCegarLoop]: Abstraction has 271 states and 347 transitions. [2021-11-20 06:11:35,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 347 transitions. [2021-11-20 06:11:35,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 182. [2021-11-20 06:11:35,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 178 states have (on average 1.2584269662921348) internal successors, (224), 177 states have internal predecessors, (224), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-20 06:11:35,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 230 transitions. [2021-11-20 06:11:35,776 INFO L704 BuchiCegarLoop]: Abstraction has 182 states and 230 transitions. [2021-11-20 06:11:35,776 INFO L587 BuchiCegarLoop]: Abstraction has 182 states and 230 transitions. [2021-11-20 06:11:35,776 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 06:11:35,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 230 transitions. [2021-11-20 06:11:35,781 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 175 [2021-11-20 06:11:35,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:11:35,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:11:35,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-20 06:11:35,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:11:35,785 INFO L791 eck$LassoCheckResult]: Stem: 1710#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1641#L715-4 [2021-11-20 06:11:35,785 INFO L793 eck$LassoCheckResult]: Loop: 1641#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1688#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1603#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1604#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1696#L722-124 havoc main_~_ha_hashv~0#1; 1697#L722-49 goto; 1634#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1582#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1583#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1646#L722-10 assume !main_#t~switch22#1; 1661#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1612#L722-13 assume !main_#t~switch22#1; 1613#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1654#L722-16 assume !main_#t~switch22#1; 1681#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 1573#L722-19 assume !main_#t~switch22#1; 1574#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1686#L722-22 assume !main_#t~switch22#1; 1682#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1683#L722-25 assume !main_#t~switch22#1; 1614#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 1615#L722-28 assume !main_#t~switch22#1; 1693#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1694#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 1644#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 1585#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 1586#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1676#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1536#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1537#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1667#L722-42 havoc main_#t~switch22#1; 1668#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32);main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8);main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768); 1692#L722-44 goto; 1563#L722-46 goto; 1564#L722-48 goto; 1708#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1707#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1679#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1680#L722-66 goto; 1650#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1637#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1);havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1638#L722-70 goto; 1703#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1567#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 1568#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1657#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 1533#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 1535#L722-117 goto; 1631#L722-119 goto; 1651#L722-121 goto; 1552#L722-123 goto; 1553#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1641#L715-4 [2021-11-20 06:11:35,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:35,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2021-11-20 06:11:35,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:35,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484701577] [2021-11-20 06:11:35,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:35,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:35,809 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:11:35,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:35,849 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:11:35,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:11:35,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1694021305, now seen corresponding path program 1 times [2021-11-20 06:11:35,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:11:35,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591476512] [2021-11-20 06:11:35,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:11:35,874 ERROR L247 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2021-11-20 06:11:35,878 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [290239728] [2021-11-20 06:11:35,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:11:35,879 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:11:35,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:11:35,909 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:11:35,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-11-20 06:11:53,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:11:53,381 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:13:45,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:13:46,481 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:13:46,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:13:46,483 INFO L85 PathProgramCache]: Analyzing trace with hash -40931685, now seen corresponding path program 1 times [2021-11-20 06:13:46,483 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:13:46,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069392769] [2021-11-20 06:13:46,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:13:46,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:13:46,505 ERROR L247 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2021-11-20 06:13:46,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1257715732] [2021-11-20 06:13:46,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:13:46,506 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:13:46,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:13:46,509 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:13:46,530 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0c3b86ee-4a2b-411c-880d-3379175e0b63/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-11-20 06:13:46,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:13:46,774 INFO L263 TraceCheckSpWp]: Trace formula consists of 310 conjuncts, 5 conjunts are in the unsatisfiable core [2021-11-20 06:13:46,781 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:13:47,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:13:47,107 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-20 06:13:47,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:13:47,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069392769] [2021-11-20 06:13:47,108 WARN L312 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2021-11-20 06:13:47,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1257715732] [2021-11-20 06:13:47,108 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1257715732] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:13:47,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:13:47,109 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:13:47,109 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716494282] [2021-11-20 06:13:47,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton