./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aef121e0 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-aef121e [2021-11-22 15:27:10,946 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-22 15:27:10,950 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-22 15:27:11,021 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-22 15:27:11,022 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-22 15:27:11,028 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-22 15:27:11,031 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-22 15:27:11,036 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-22 15:27:11,039 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-22 15:27:11,046 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-22 15:27:11,048 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-22 15:27:11,050 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-22 15:27:11,051 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-22 15:27:11,054 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-22 15:27:11,056 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-22 15:27:11,066 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-22 15:27:11,069 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-22 15:27:11,070 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-22 15:27:11,073 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-22 15:27:11,086 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-22 15:27:11,089 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-22 15:27:11,090 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-22 15:27:11,095 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-22 15:27:11,097 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-22 15:27:11,109 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-22 15:27:11,110 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-22 15:27:11,110 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-22 15:27:11,113 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-22 15:27:11,114 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-22 15:27:11,116 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-22 15:27:11,117 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-22 15:27:11,118 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-22 15:27:11,121 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-22 15:27:11,122 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-22 15:27:11,124 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-22 15:27:11,124 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-22 15:27:11,125 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-22 15:27:11,125 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-22 15:27:11,126 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-22 15:27:11,127 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-22 15:27:11,128 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-22 15:27:11,129 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-22 15:27:11,182 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-22 15:27:11,183 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-22 15:27:11,183 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-22 15:27:11,184 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-22 15:27:11,185 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-22 15:27:11,186 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-22 15:27:11,186 INFO L138 SettingsManager]: * Use SBE=true [2021-11-22 15:27:11,186 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-22 15:27:11,186 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-22 15:27:11,187 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-22 15:27:11,188 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-22 15:27:11,189 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-22 15:27:11,189 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-22 15:27:11,189 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-22 15:27:11,190 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-22 15:27:11,190 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-22 15:27:11,190 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-22 15:27:11,190 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-22 15:27:11,191 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-22 15:27:11,191 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-22 15:27:11,191 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-22 15:27:11,191 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-22 15:27:11,192 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-22 15:27:11,192 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-22 15:27:11,192 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-22 15:27:11,192 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-22 15:27:11,195 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-22 15:27:11,195 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-22 15:27:11,196 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-22 15:27:11,196 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-22 15:27:11,196 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-22 15:27:11,197 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-22 15:27:11,198 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-22 15:27:11,198 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2021-11-22 15:27:11,520 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-22 15:27:11,550 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-22 15:27:11,554 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-22 15:27:11,555 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-22 15:27:11,556 INFO L275 PluginConnector]: CDTParser initialized [2021-11-22 15:27:11,558 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-22 15:27:11,659 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/data/0bd6e3816/fa8f22519ec0464cb2f6b898e2bb15d3/FLAG2324f43be [2021-11-22 15:27:12,418 INFO L306 CDTParser]: Found 1 translation units. [2021-11-22 15:27:12,419 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-22 15:27:12,436 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/data/0bd6e3816/fa8f22519ec0464cb2f6b898e2bb15d3/FLAG2324f43be [2021-11-22 15:27:12,659 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/data/0bd6e3816/fa8f22519ec0464cb2f6b898e2bb15d3 [2021-11-22 15:27:12,664 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-22 15:27:12,668 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-22 15:27:12,673 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-22 15:27:12,674 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-22 15:27:12,678 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-22 15:27:12,679 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 03:27:12" (1/1) ... [2021-11-22 15:27:12,682 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@20e5ef7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:12, skipping insertion in model container [2021-11-22 15:27:12,683 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 03:27:12" (1/1) ... [2021-11-22 15:27:12,692 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-22 15:27:12,780 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-22 15:27:13,041 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-22 15:27:13,216 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-22 15:27:13,233 INFO L203 MainTranslator]: Completed pre-run [2021-11-22 15:27:13,247 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-22 15:27:13,316 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-22 15:27:13,342 INFO L208 MainTranslator]: Completed translation [2021-11-22 15:27:13,342 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13 WrapperNode [2021-11-22 15:27:13,343 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-22 15:27:13,345 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-22 15:27:13,345 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-22 15:27:13,346 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-22 15:27:13,355 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,389 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,520 INFO L137 Inliner]: procedures = 50, calls = 63, calls flagged for inlining = 58, calls inlined = 224, statements flattened = 3437 [2021-11-22 15:27:13,521 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-22 15:27:13,522 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-22 15:27:13,522 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-22 15:27:13,522 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-22 15:27:13,532 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,532 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,545 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,546 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,609 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,657 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,662 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,676 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-22 15:27:13,677 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-22 15:27:13,677 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-22 15:27:13,678 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-22 15:27:13,679 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (1/1) ... [2021-11-22 15:27:13,687 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-22 15:27:13,698 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/z3 [2021-11-22 15:27:13,728 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-22 15:27:13,745 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4bda2f8-45c1-4968-bcab-0429813f24b6/bin/uautomizer-w2VwFs6gM0/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-22 15:27:13,785 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-22 15:27:13,785 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-22 15:27:13,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-22 15:27:13,786 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-22 15:27:13,986 INFO L236 CfgBuilder]: Building ICFG [2021-11-22 15:27:13,988 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-22 15:27:16,328 INFO L277 CfgBuilder]: Performing block encoding [2021-11-22 15:27:16,355 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-22 15:27:16,356 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-11-22 15:27:16,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 03:27:16 BoogieIcfgContainer [2021-11-22 15:27:16,360 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-22 15:27:16,362 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-22 15:27:16,362 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-22 15:27:16,365 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-22 15:27:16,366 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 15:27:16,366 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.11 03:27:12" (1/3) ... [2021-11-22 15:27:16,368 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b838c8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 03:27:16, skipping insertion in model container [2021-11-22 15:27:16,368 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 15:27:16,368 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 03:27:13" (2/3) ... [2021-11-22 15:27:16,369 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b838c8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 03:27:16, skipping insertion in model container [2021-11-22 15:27:16,369 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 15:27:16,369 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 03:27:16" (3/3) ... [2021-11-22 15:27:16,371 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2021-11-22 15:27:16,420 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-22 15:27:16,421 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-22 15:27:16,421 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-22 15:27:16,421 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-22 15:27:16,421 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-22 15:27:16,421 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-22 15:27:16,422 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-22 15:27:16,422 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-22 15:27:16,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:16,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-11-22 15:27:16,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:16,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:16,588 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:16,589 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:16,589 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-22 15:27:16,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:16,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-11-22 15:27:16,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:16,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:16,623 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:16,623 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:16,634 INFO L791 eck$LassoCheckResult]: Stem: 715#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1355#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 725#L1607true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1298#L754true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 511#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 527#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 366#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 204#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 44#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 646#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 612#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 655#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1335#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 262#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1145#L1090true assume !(0 == ~M_E~0); 288#L1090-2true assume !(0 == ~T1_E~0); 1306#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L1100-1true assume !(0 == ~T3_E~0); 811#L1105-1true assume !(0 == ~T4_E~0); 157#L1110-1true assume !(0 == ~T5_E~0); 386#L1115-1true assume !(0 == ~T6_E~0); 595#L1120-1true assume !(0 == ~T7_E~0); 1343#L1125-1true assume !(0 == ~T8_E~0); 1336#L1130-1true assume !(0 == ~T9_E~0); 809#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 265#L1140-1true assume !(0 == ~T11_E~0); 739#L1145-1true assume !(0 == ~E_1~0); 781#L1150-1true assume !(0 == ~E_2~0); 374#L1155-1true assume !(0 == ~E_3~0); 1315#L1160-1true assume !(0 == ~E_4~0); 430#L1165-1true assume !(0 == ~E_5~0); 1070#L1170-1true assume !(0 == ~E_6~0); 1255#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 480#L1180-1true assume !(0 == ~E_8~0); 895#L1185-1true assume !(0 == ~E_9~0); 263#L1190-1true assume !(0 == ~E_10~0); 490#L1195-1true assume !(0 == ~E_11~0); 1013#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381#L525true assume !(1 == ~m_pc~0); 62#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1009#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 492#L537true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 874#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 254#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 531#L544true assume 1 == ~t1_pc~0; 412#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 736#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#L556true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 574#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1004#L563true assume !(1 == ~t2_pc~0); 726#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 73#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#L575true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 634#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 737#L582true assume 1 == ~t3_pc~0; 141#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1214#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1427#L594true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1082#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1378#L601true assume !(1 == ~t4_pc~0); 829#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 387#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 791#L613true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 748#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1387#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1186#L620true assume 1 == ~t5_pc~0; 87#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 652#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 592#L632true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1460#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1244#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1348#L639true assume !(1 == ~t6_pc~0); 593#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 325#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1086#L651true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1239#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 391#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 940#L658true assume 1 == ~t7_pc~0; 594#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1262#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 621#L670true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 687#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 259#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 394#L677true assume 1 == ~t8_pc~0; 864#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1034#L689true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 302#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 865#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 972#L696true assume !(1 == ~t9_pc~0); 582#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 662#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 755#L708true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 598#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 789#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1123#L715true assume 1 == ~t10_pc~0; 797#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 677#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 576#L727true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 766#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 475#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145#L734true assume !(1 == ~t11_pc~0); 432#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 496#L746true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 653#L1438-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L1213true assume !(1 == ~M_E~0); 473#L1213-2true assume !(1 == ~T1_E~0); 958#L1218-1true assume !(1 == ~T2_E~0); 33#L1223-1true assume !(1 == ~T3_E~0); 458#L1228-1true assume !(1 == ~T4_E~0); 1245#L1233-1true assume !(1 == ~T5_E~0); 1440#L1238-1true assume !(1 == ~T6_E~0); 747#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1393#L1248-1true assume !(1 == ~T8_E~0); 795#L1253-1true assume !(1 == ~T9_E~0); 1087#L1258-1true assume !(1 == ~T10_E~0); 773#L1263-1true assume !(1 == ~T11_E~0); 1129#L1268-1true assume !(1 == ~E_1~0); 611#L1273-1true assume !(1 == ~E_2~0); 1225#L1278-1true assume !(1 == ~E_3~0); 324#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1276#L1288-1true assume !(1 == ~E_5~0); 916#L1293-1true assume !(1 == ~E_6~0); 870#L1298-1true assume !(1 == ~E_7~0); 637#L1303-1true assume !(1 == ~E_8~0); 331#L1308-1true assume !(1 == ~E_9~0); 268#L1313-1true assume !(1 == ~E_10~0); 1361#L1318-1true assume !(1 == ~E_11~0); 274#L1323-1true assume { :end_inline_reset_delta_events } true; 1135#L1644-2true [2021-11-22 15:27:16,638 INFO L793 eck$LassoCheckResult]: Loop: 1135#L1644-2true assume !false; 685#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 765#L1065true assume !true; 867#L1080true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 762#L754-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 946#L1090-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 975#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1237#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 201#L1110-3true assume !(0 == ~T5_E~0); 1075#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 367#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 744#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1115#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1273#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 318#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 49#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 498#L1150-3true assume !(0 == ~E_2~0); 109#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1421#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 308#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1480#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 567#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 256#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 124#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1278#L1190-3true assume !(0 == ~E_10~0); 1095#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1478#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447#L525-36true assume !(1 == ~m_pc~0); 1132#L525-38true is_master_triggered_~__retres1~0#1 := 0; 174#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1351#L537-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 339#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 566#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L544-36true assume 1 == ~t1_pc~0; 792#L545-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 667#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221#L556-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1257#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906#L563-36true assume 1 == ~t2_pc~0; 167#L564-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752#L575-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1254#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363#L582-36true assume 1 == ~t3_pc~0; 361#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 510#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366#L594-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444#L601-36true assume 1 == ~t4_pc~0; 378#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1456#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1265#L613-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1035#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1177#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 891#L620-36true assume !(1 == ~t5_pc~0); 1453#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 729#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 953#L632-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393#L1390-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70#L639-36true assume 1 == ~t6_pc~0; 717#L640-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1005#L651-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 212#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 597#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1176#L658-36true assume !(1 == ~t7_pc~0); 75#L658-38true is_transmit7_triggered_~__retres1~7#1 := 0; 1006#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1046#L670-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64#L1406-36true assume !(0 != activate_threads_~tmp___6~0#1); 712#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 927#L677-36true assume !(1 == ~t8_pc~0); 534#L677-38true is_transmit8_triggered_~__retres1~8#1 := 0; 635#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1187#L689-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1174#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 555#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1092#L696-36true assume 1 == ~t9_pc~0; 471#L697-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 827#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98#L708-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1007#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 568#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1251#L715-36true assume !(1 == ~t10_pc~0); 543#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 16#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127#L727-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1052#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 206#L734-36true assume 1 == ~t11_pc~0; 799#L735-12true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 216#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460#L746-12true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 616#L1438-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1098#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 372#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 710#L1218-3true assume !(1 == ~T2_E~0); 233#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 753#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 345#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1263#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 508#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1033#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1400#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1042#L1258-3true assume !(1 == ~T10_E~0); 222#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 989#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1012#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1454#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1015#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1285#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 338#L1298-3true assume !(1 == ~E_7~0); 1136#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 683#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 336#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1037#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 223#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1428#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 440#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 836#L892-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1429#L1663true assume !(0 == start_simulation_~tmp~3#1); 1329#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 596#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 703#L892-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 80#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 261#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1299#L1626true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1164#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1135#L1644-2true [2021-11-22 15:27:16,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:16,646 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2021-11-22 15:27:16,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:16,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973566719] [2021-11-22 15:27:16,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:16,659 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:16,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:16,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:16,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:16,916 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973566719] [2021-11-22 15:27:16,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973566719] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:16,920 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:16,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:16,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979600576] [2021-11-22 15:27:16,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:16,929 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:16,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:16,930 INFO L85 PathProgramCache]: Analyzing trace with hash 862291405, now seen corresponding path program 1 times [2021-11-22 15:27:16,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:16,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322669725] [2021-11-22 15:27:16,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:16,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:16,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:16,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:16,991 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:16,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322669725] [2021-11-22 15:27:16,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322669725] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:16,992 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:16,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:16,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524605756] [2021-11-22 15:27:16,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:16,994 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:16,995 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:17,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-22 15:27:17,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-22 15:27:17,053 INFO L87 Difference]: Start difference. First operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:17,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:17,257 INFO L93 Difference]: Finished difference Result 1482 states and 2199 transitions. [2021-11-22 15:27:17,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-22 15:27:17,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2199 transitions. [2021-11-22 15:27:17,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:17,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1476 states and 2193 transitions. [2021-11-22 15:27:17,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:17,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:17,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2193 transitions. [2021-11-22 15:27:17,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:17,377 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-22 15:27:17,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2193 transitions. [2021-11-22 15:27:17,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:17,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4857723577235773) internal successors, (2193), 1475 states have internal predecessors, (2193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:17,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2193 transitions. [2021-11-22 15:27:17,488 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-22 15:27:17,488 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-22 15:27:17,488 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-22 15:27:17,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2193 transitions. [2021-11-22 15:27:17,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:17,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:17,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:17,505 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:17,506 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:17,507 INFO L791 eck$LassoCheckResult]: Stem: 4096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4106#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4107#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3872#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3873#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3654#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3377#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3012#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3013#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3990#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3991#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4029#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3477#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3478#L1090 assume !(0 == ~M_E~0); 3523#L1090-2 assume !(0 == ~T1_E~0); 3524#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4167#L1100-1 assume !(0 == ~T3_E~0); 4168#L1105-1 assume !(0 == ~T4_E~0); 3296#L1110-1 assume !(0 == ~T5_E~0); 3297#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 3969#L1125-1 assume !(0 == ~T8_E~0); 4438#L1130-1 assume !(0 == ~T9_E~0); 4187#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3482#L1140-1 assume !(0 == ~T11_E~0); 3483#L1145-1 assume !(0 == ~E_1~0); 4121#L1150-1 assume !(0 == ~E_2~0); 3667#L1155-1 assume !(0 == ~E_3~0); 3668#L1160-1 assume !(0 == ~E_4~0); 3750#L1165-1 assume !(0 == ~E_5~0); 3751#L1170-1 assume !(0 == ~E_6~0); 4359#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3828#L1180-1 assume !(0 == ~E_8~0); 3829#L1185-1 assume !(0 == ~E_9~0); 3479#L1190-1 assume !(0 == ~E_10~0); 3480#L1195-1 assume !(0 == ~E_11~0); 3842#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3100#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3101#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3846#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3847#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3466#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3467#L544 assume 1 == ~t1_pc~0; 3727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4119#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3317#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3318#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3940#L563 assume !(1 == ~t2_pc~0); 4108#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3121#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3122#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3553#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3554#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4013#L582 assume 1 == ~t3_pc~0; 3261#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3262#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4410#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4368#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3195#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3196#L601 assume !(1 == ~t4_pc~0); 4136#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3694#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4130#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4131#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4402#L620 assume 1 == ~t5_pc~0; 3154#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3155#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3965#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3966#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4417#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4418#L639 assume !(1 == ~t6_pc~0); 3967#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3590#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3591#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4371#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3701#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3702#L658 assume 1 == ~t7_pc~0; 3968#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3895#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4000#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4001#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3473#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3474#L677 assume 1 == ~t8_pc~0; 3706#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3276#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3277#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3547#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3548#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4226#L696 assume !(1 == ~t9_pc~0); 3953#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3954#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4044#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3973#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3974#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4171#L715 assume 1 == ~t10_pc~0; 4175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3943#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3944#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3820#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3270#L734 assume !(1 == ~t11_pc~0); 3271#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3754#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3833#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3002#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3003#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4028#L1213 assume !(1 == ~M_E~0); 3818#L1213-2 assume !(1 == ~T1_E~0); 3819#L1218-1 assume !(1 == ~T2_E~0); 3037#L1223-1 assume !(1 == ~T3_E~0); 3038#L1228-1 assume !(1 == ~T4_E~0); 3797#L1233-1 assume !(1 == ~T5_E~0); 4419#L1238-1 assume !(1 == ~T6_E~0); 4128#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4129#L1248-1 assume !(1 == ~T8_E~0); 4173#L1253-1 assume !(1 == ~T9_E~0); 4174#L1258-1 assume !(1 == ~T10_E~0); 4152#L1263-1 assume !(1 == ~T11_E~0); 4153#L1268-1 assume !(1 == ~E_1~0); 3988#L1273-1 assume !(1 == ~E_2~0); 3989#L1278-1 assume !(1 == ~E_3~0); 3588#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3589#L1288-1 assume !(1 == ~E_5~0); 4266#L1293-1 assume !(1 == ~E_6~0); 4230#L1298-1 assume !(1 == ~E_7~0); 4016#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3488#L1313-1 assume !(1 == ~E_10~0); 3489#L1318-1 assume !(1 == ~E_11~0); 3501#L1323-1 assume { :end_inline_reset_delta_events } true; 3502#L1644-2 [2021-11-22 15:27:17,508 INFO L793 eck$LassoCheckResult]: Loop: 3502#L1644-2 assume !false; 4069#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4070#L1065 assume !false; 4145#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4415#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3119#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4331#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4143#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4144#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4283#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4335#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4298#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4299#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3372#L1110-3 assume !(0 == ~T5_E~0); 3373#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3655#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3656#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4126#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4380#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3580#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3075#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3076#L1150-3 assume !(0 == ~E_2~0); 3198#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3199#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3559#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3560#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3932#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3469#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3230#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3231#L1190-3 assume !(0 == ~E_10~0); 4374#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4375#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3782#L525-36 assume !(1 == ~m_pc~0); 3783#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3520#L544-36 assume 1 == ~t1_pc~0; 3521#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4047#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3412#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3413#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4356#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4259#L563-36 assume 1 == ~t2_pc~0; 3315#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3071#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3072#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4134#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3795#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3796#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3871#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4038#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3832#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3776#L601-36 assume 1 == ~t4_pc~0; 3675#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3676#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4423#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4341#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4342#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4247#L620-36 assume 1 == ~t5_pc~0; 3715#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3716#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4109#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3703#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3337#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3115#L639-36 assume 1 == ~t6_pc~0; 3116#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3152#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3153#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3393#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3394#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3972#L658-36 assume 1 == ~t7_pc~0; 3232#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3127#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4326#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3102#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3103#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4093#L677-36 assume !(1 == ~t8_pc~0); 3897#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3898#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4014#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4398#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3921#L696-36 assume 1 == ~t9_pc~0; 3814#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3816#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3175#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3176#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3933#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3934#L715-36 assume !(1 == ~t10_pc~0); 3904#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3001#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2976#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2977#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3381#L734-36 assume 1 == ~t11_pc~0; 3382#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3081#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3403#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2994#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2995#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3994#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3661#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3662#L1218-3 assume !(1 == ~T2_E~0); 3432#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3622#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3623#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3867#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3868#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4339#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344#L1258-3 assume !(1 == ~T10_E~0); 3414#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3415#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4310#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4328#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4330#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3746#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3747#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume !(1 == ~E_7~0); 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4068#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3416#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3417#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3356#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3767#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4206#L1663 assume !(0 == start_simulation_~tmp~3#1); 3249#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3970#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3193#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3889#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3137#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3138#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3476#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4395#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3502#L1644-2 [2021-11-22 15:27:17,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:17,510 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2021-11-22 15:27:17,510 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:17,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825430100] [2021-11-22 15:27:17,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:17,511 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:17,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:17,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:17,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:17,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825430100] [2021-11-22 15:27:17,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825430100] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:17,632 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:17,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:17,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487510575] [2021-11-22 15:27:17,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:17,633 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:17,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:17,634 INFO L85 PathProgramCache]: Analyzing trace with hash -852141939, now seen corresponding path program 1 times [2021-11-22 15:27:17,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:17,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68932686] [2021-11-22 15:27:17,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:17,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:17,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:17,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:17,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:17,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68932686] [2021-11-22 15:27:17,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68932686] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:17,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:17,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:17,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036619162] [2021-11-22 15:27:17,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:17,871 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:17,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:17,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:17,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:17,873 INFO L87 Difference]: Start difference. First operand 1476 states and 2193 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:17,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:17,944 INFO L93 Difference]: Finished difference Result 1476 states and 2192 transitions. [2021-11-22 15:27:17,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:17,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2192 transitions. [2021-11-22 15:27:17,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:17,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-11-22 15:27:17,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:17,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:17,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2192 transitions. [2021-11-22 15:27:17,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:17,983 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-22 15:27:17,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2192 transitions. [2021-11-22 15:27:18,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:18,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4850948509485096) internal successors, (2192), 1475 states have internal predecessors, (2192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-11-22 15:27:18,022 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-22 15:27:18,022 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-22 15:27:18,022 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-22 15:27:18,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2192 transitions. [2021-11-22 15:27:18,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:18,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:18,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:18,061 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,068 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,070 INFO L791 eck$LassoCheckResult]: Stem: 7055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 7056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7063#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7064#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6831#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6832#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6701#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6613#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6336#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5971#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5972#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6020#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6021#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6949#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6950#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6988#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6436#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6437#L1090 assume !(0 == ~M_E~0); 6479#L1090-2 assume !(0 == ~T1_E~0); 6480#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7125#L1100-1 assume !(0 == ~T3_E~0); 7126#L1105-1 assume !(0 == ~T4_E~0); 6254#L1110-1 assume !(0 == ~T5_E~0); 6255#L1115-1 assume !(0 == ~T6_E~0); 6651#L1120-1 assume !(0 == ~T7_E~0); 6928#L1125-1 assume !(0 == ~T8_E~0); 7397#L1130-1 assume !(0 == ~T9_E~0); 7146#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6441#L1140-1 assume !(0 == ~T11_E~0); 6442#L1145-1 assume !(0 == ~E_1~0); 7080#L1150-1 assume !(0 == ~E_2~0); 6626#L1155-1 assume !(0 == ~E_3~0); 6627#L1160-1 assume !(0 == ~E_4~0); 6709#L1165-1 assume !(0 == ~E_5~0); 6710#L1170-1 assume !(0 == ~E_6~0); 7318#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6787#L1180-1 assume !(0 == ~E_8~0); 6788#L1185-1 assume !(0 == ~E_9~0); 6438#L1190-1 assume !(0 == ~E_10~0); 6439#L1195-1 assume !(0 == ~E_11~0); 6801#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6641#L525 assume !(1 == ~m_pc~0); 6059#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6060#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6805#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6806#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6425#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6426#L544 assume 1 == ~t1_pc~0; 6686#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6650#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7078#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6276#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6277#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6899#L563 assume !(1 == ~t2_pc~0); 7065#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6080#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6081#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6509#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6510#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6972#L582 assume 1 == ~t3_pc~0; 6218#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6219#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7369#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7327#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6154#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6155#L601 assume !(1 == ~t4_pc~0); 7095#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6652#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6653#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7089#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7090#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7361#L620 assume 1 == ~t5_pc~0; 6109#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6924#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6925#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7376#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L639 assume !(1 == ~t6_pc~0); 6926#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6549#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6550#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7330#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6660#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6661#L658 assume 1 == ~t7_pc~0; 6927#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6852#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6959#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6960#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6432#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L677 assume 1 == ~t8_pc~0; 6663#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6235#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6236#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6506#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6507#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7185#L696 assume !(1 == ~t9_pc~0); 6910#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6911#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7000#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6932#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6933#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7130#L715 assume 1 == ~t10_pc~0; 7134#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7017#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6902#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6903#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6779#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6227#L734 assume !(1 == ~t11_pc~0); 6228#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6713#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6792#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5959#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5960#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6987#L1213 assume !(1 == ~M_E~0); 6776#L1213-2 assume !(1 == ~T1_E~0); 6777#L1218-1 assume !(1 == ~T2_E~0); 5996#L1223-1 assume !(1 == ~T3_E~0); 5997#L1228-1 assume !(1 == ~T4_E~0); 6756#L1233-1 assume !(1 == ~T5_E~0); 7378#L1238-1 assume !(1 == ~T6_E~0); 7087#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7088#L1248-1 assume !(1 == ~T8_E~0); 7132#L1253-1 assume !(1 == ~T9_E~0); 7133#L1258-1 assume !(1 == ~T10_E~0); 7111#L1263-1 assume !(1 == ~T11_E~0); 7112#L1268-1 assume !(1 == ~E_1~0); 6947#L1273-1 assume !(1 == ~E_2~0); 6948#L1278-1 assume !(1 == ~E_3~0); 6547#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1288-1 assume !(1 == ~E_5~0); 7225#L1293-1 assume !(1 == ~E_6~0); 7189#L1298-1 assume !(1 == ~E_7~0); 6975#L1303-1 assume !(1 == ~E_8~0); 6558#L1308-1 assume !(1 == ~E_9~0); 6447#L1313-1 assume !(1 == ~E_10~0); 6448#L1318-1 assume !(1 == ~E_11~0); 6457#L1323-1 assume { :end_inline_reset_delta_events } true; 6458#L1644-2 [2021-11-22 15:27:18,071 INFO L793 eck$LassoCheckResult]: Loop: 6458#L1644-2 assume !false; 7028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7029#L1065 assume !false; 7104#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7374#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6078#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7290#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6563#L906 assume !(0 != eval_~tmp~0#1); 6565#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7101#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7102#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7242#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7294#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7257#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7258#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6331#L1110-3 assume !(0 == ~T5_E~0); 6332#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6614#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6615#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7085#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7339#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6537#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6032#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6033#L1150-3 assume !(0 == ~E_2~0); 6156#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6157#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6518#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6519#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6891#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6428#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6187#L1190-3 assume !(0 == ~E_10~0); 7333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6741#L525-36 assume !(1 == ~m_pc~0); 6742#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6288#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6573#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6574#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6482#L544-36 assume 1 == ~t1_pc~0; 6483#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7006#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6371#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6372#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7315#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7218#L563-36 assume 1 == ~t2_pc~0; 6274#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6030#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6031#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7093#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6754#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6755#L582-36 assume 1 == ~t3_pc~0; 6605#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6606#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6997#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6791#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6735#L601-36 assume 1 == ~t4_pc~0; 6634#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6635#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7382#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7300#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7301#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7206#L620-36 assume 1 == ~t5_pc~0; 6676#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6677#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7068#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6662#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L639-36 assume 1 == ~t6_pc~0; 6075#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6114#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6115#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6354#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6355#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6931#L658-36 assume 1 == ~t7_pc~0; 6193#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6086#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7285#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6061#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 6062#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7052#L677-36 assume !(1 == ~t8_pc~0); 6856#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6857#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6973#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7357#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6879#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6880#L696-36 assume 1 == ~t9_pc~0; 6773#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6775#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6134#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6135#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6892#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6893#L715-36 assume 1 == ~t10_pc~0; 7026#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5961#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5962#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5935#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5936#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6340#L734-36 assume 1 == ~t11_pc~0; 6341#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6040#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6362#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5953#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5954#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6622#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6623#L1218-3 assume !(1 == ~T2_E~0); 6391#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6392#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6581#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6582#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6826#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6827#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7299#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7304#L1258-3 assume !(1 == ~T10_E~0); 6373#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6374#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7269#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7287#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7289#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6705#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6706#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1298-3 assume !(1 == ~E_7~0); 6572#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7027#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6568#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6569#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6375#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6376#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6315#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6726#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 7165#L1663 assume !(0 == start_simulation_~tmp~3#1); 6208#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6929#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6152#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6850#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6096#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6097#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6435#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7354#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6458#L1644-2 [2021-11-22 15:27:18,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,072 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2021-11-22 15:27:18,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140246613] [2021-11-22 15:27:18,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140246613] [2021-11-22 15:27:18,151 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140246613] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,151 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,151 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,152 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480258896] [2021-11-22 15:27:18,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,152 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:18,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,153 INFO L85 PathProgramCache]: Analyzing trace with hash 2047437327, now seen corresponding path program 1 times [2021-11-22 15:27:18,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351432299] [2021-11-22 15:27:18,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,233 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,233 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351432299] [2021-11-22 15:27:18,233 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351432299] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,233 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,233 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,234 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799303274] [2021-11-22 15:27:18,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,235 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:18,235 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:18,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:18,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:18,236 INFO L87 Difference]: Start difference. First operand 1476 states and 2192 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:18,279 INFO L93 Difference]: Finished difference Result 1476 states and 2191 transitions. [2021-11-22 15:27:18,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:18,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2191 transitions. [2021-11-22 15:27:18,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:18,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-11-22 15:27:18,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:18,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:18,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2191 transitions. [2021-11-22 15:27:18,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:18,316 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-22 15:27:18,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2191 transitions. [2021-11-22 15:27:18,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:18,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4844173441734418) internal successors, (2191), 1475 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-11-22 15:27:18,356 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-22 15:27:18,356 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-22 15:27:18,356 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-22 15:27:18,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2191 transitions. [2021-11-22 15:27:18,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:18,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:18,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:18,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,371 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,371 INFO L791 eck$LassoCheckResult]: Stem: 10014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 10015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10024#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10025#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9790#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9791#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9660#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9572#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9295#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8930#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8931#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8979#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8980#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9908#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9909#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9947#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9395#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9396#L1090 assume !(0 == ~M_E~0); 9438#L1090-2 assume !(0 == ~T1_E~0); 9439#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10085#L1100-1 assume !(0 == ~T3_E~0); 10086#L1105-1 assume !(0 == ~T4_E~0); 9214#L1110-1 assume !(0 == ~T5_E~0); 9215#L1115-1 assume !(0 == ~T6_E~0); 9610#L1120-1 assume !(0 == ~T7_E~0); 9887#L1125-1 assume !(0 == ~T8_E~0); 10356#L1130-1 assume !(0 == ~T9_E~0); 10105#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9400#L1140-1 assume !(0 == ~T11_E~0); 9401#L1145-1 assume !(0 == ~E_1~0); 10039#L1150-1 assume !(0 == ~E_2~0); 9585#L1155-1 assume !(0 == ~E_3~0); 9586#L1160-1 assume !(0 == ~E_4~0); 9668#L1165-1 assume !(0 == ~E_5~0); 9669#L1170-1 assume !(0 == ~E_6~0); 10277#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9746#L1180-1 assume !(0 == ~E_8~0); 9747#L1185-1 assume !(0 == ~E_9~0); 9397#L1190-1 assume !(0 == ~E_10~0); 9398#L1195-1 assume !(0 == ~E_11~0); 9760#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9607#L525 assume !(1 == ~m_pc~0); 9018#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9019#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9764#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9765#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9384#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9385#L544 assume 1 == ~t1_pc~0; 9645#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10037#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9858#L563 assume !(1 == ~t2_pc~0); 10026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9039#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9040#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9931#L582 assume 1 == ~t3_pc~0; 9179#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9180#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10328#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10286#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9113#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9114#L601 assume !(1 == ~t4_pc~0); 10054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9611#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9612#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10048#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10320#L620 assume 1 == ~t5_pc~0; 9070#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9071#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9883#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9884#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10335#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10336#L639 assume !(1 == ~t6_pc~0); 9885#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9508#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9509#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10289#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9619#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9620#L658 assume 1 == ~t7_pc~0; 9886#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9918#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9919#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9391#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9392#L677 assume 1 == ~t8_pc~0; 9624#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9194#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9195#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9465#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9466#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10144#L696 assume !(1 == ~t9_pc~0); 9871#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9872#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9959#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9891#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9892#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10089#L715 assume 1 == ~t10_pc~0; 10093#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9976#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9861#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9862#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9738#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9188#L734 assume !(1 == ~t11_pc~0); 9189#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9672#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9751#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8920#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8921#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9946#L1213 assume !(1 == ~M_E~0); 9736#L1213-2 assume !(1 == ~T1_E~0); 9737#L1218-1 assume !(1 == ~T2_E~0); 8955#L1223-1 assume !(1 == ~T3_E~0); 8956#L1228-1 assume !(1 == ~T4_E~0); 9715#L1233-1 assume !(1 == ~T5_E~0); 10337#L1238-1 assume !(1 == ~T6_E~0); 10046#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10047#L1248-1 assume !(1 == ~T8_E~0); 10091#L1253-1 assume !(1 == ~T9_E~0); 10092#L1258-1 assume !(1 == ~T10_E~0); 10070#L1263-1 assume !(1 == ~T11_E~0); 10071#L1268-1 assume !(1 == ~E_1~0); 9906#L1273-1 assume !(1 == ~E_2~0); 9907#L1278-1 assume !(1 == ~E_3~0); 9506#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9507#L1288-1 assume !(1 == ~E_5~0); 10184#L1293-1 assume !(1 == ~E_6~0); 10148#L1298-1 assume !(1 == ~E_7~0); 9934#L1303-1 assume !(1 == ~E_8~0); 9517#L1308-1 assume !(1 == ~E_9~0); 9406#L1313-1 assume !(1 == ~E_10~0); 9407#L1318-1 assume !(1 == ~E_11~0); 9419#L1323-1 assume { :end_inline_reset_delta_events } true; 9420#L1644-2 [2021-11-22 15:27:18,372 INFO L793 eck$LassoCheckResult]: Loop: 9420#L1644-2 assume !false; 9987#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9988#L1065 assume !false; 10063#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10333#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9037#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10249#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9522#L906 assume !(0 != eval_~tmp~0#1); 9524#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10062#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10201#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10253#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10216#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10217#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9290#L1110-3 assume !(0 == ~T5_E~0); 9291#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9573#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9574#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10044#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10298#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9498#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8993#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8994#L1150-3 assume !(0 == ~E_2~0); 9116#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9117#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9477#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9850#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9146#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9147#L1190-3 assume !(0 == ~E_10~0); 10292#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10293#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9700#L525-36 assume !(1 == ~m_pc~0); 9701#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9251#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9252#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9533#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9534#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544-36 assume 1 == ~t1_pc~0; 9442#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9965#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9336#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9337#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10275#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10177#L563-36 assume 1 == ~t2_pc~0; 9233#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8989#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8990#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10052#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9713#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9714#L582-36 assume 1 == ~t3_pc~0; 9564#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9789#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9956#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9750#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9691#L601-36 assume 1 == ~t4_pc~0; 9593#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9594#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10341#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10259#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10163#L620-36 assume 1 == ~t5_pc~0; 9633#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9255#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9033#L639-36 assume 1 == ~t6_pc~0; 9034#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9068#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9069#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9311#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9312#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9890#L658-36 assume !(1 == ~t7_pc~0); 9044#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9045#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10244#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9020#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 9021#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10011#L677-36 assume !(1 == ~t8_pc~0); 9815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9932#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10316#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9838#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9839#L696-36 assume 1 == ~t9_pc~0; 9732#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9734#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9090#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9091#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9851#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9852#L715-36 assume 1 == ~t10_pc~0; 9985#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8918#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8919#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8894#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8895#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9299#L734-36 assume 1 == ~t11_pc~0; 9300#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9321#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8912#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8913#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9912#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9579#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9580#L1218-3 assume !(1 == ~T2_E~0); 9350#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9540#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9541#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9785#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9786#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10257#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10262#L1258-3 assume !(1 == ~T10_E~0); 9330#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9331#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10228#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10246#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10248#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9530#L1298-3 assume !(1 == ~E_7~0); 9531#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9986#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9527#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9528#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9332#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9333#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9274#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9685#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 10124#L1663 assume !(0 == start_simulation_~tmp~3#1); 9162#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9888#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9111#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9807#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9052#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9394#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10313#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9420#L1644-2 [2021-11-22 15:27:18,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,375 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2021-11-22 15:27:18,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260456503] [2021-11-22 15:27:18,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,460 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260456503] [2021-11-22 15:27:18,461 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260456503] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,462 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,462 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,465 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184314862] [2021-11-22 15:27:18,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,466 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:18,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,468 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 1 times [2021-11-22 15:27:18,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581274021] [2021-11-22 15:27:18,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,592 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581274021] [2021-11-22 15:27:18,593 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581274021] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,593 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599109660] [2021-11-22 15:27:18,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,595 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:18,595 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:18,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:18,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:18,598 INFO L87 Difference]: Start difference. First operand 1476 states and 2191 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:18,647 INFO L93 Difference]: Finished difference Result 1476 states and 2190 transitions. [2021-11-22 15:27:18,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:18,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2190 transitions. [2021-11-22 15:27:18,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:18,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-11-22 15:27:18,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:18,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:18,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2190 transitions. [2021-11-22 15:27:18,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:18,687 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-22 15:27:18,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2190 transitions. [2021-11-22 15:27:18,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:18,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.483739837398374) internal successors, (2190), 1475 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-11-22 15:27:18,735 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-22 15:27:18,735 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-22 15:27:18,735 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-22 15:27:18,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2190 transitions. [2021-11-22 15:27:18,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:18,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:18,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:18,751 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,751 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:18,752 INFO L791 eck$LassoCheckResult]: Stem: 12973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 12981#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12982#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12750#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12619#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12531#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12254#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11889#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11890#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11938#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11939#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12867#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12868#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12906#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12354#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12355#L1090 assume !(0 == ~M_E~0); 12397#L1090-2 assume !(0 == ~T1_E~0); 12398#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13043#L1100-1 assume !(0 == ~T3_E~0); 13044#L1105-1 assume !(0 == ~T4_E~0); 12172#L1110-1 assume !(0 == ~T5_E~0); 12173#L1115-1 assume !(0 == ~T6_E~0); 12569#L1120-1 assume !(0 == ~T7_E~0); 12846#L1125-1 assume !(0 == ~T8_E~0); 13315#L1130-1 assume !(0 == ~T9_E~0); 13064#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12359#L1140-1 assume !(0 == ~T11_E~0); 12360#L1145-1 assume !(0 == ~E_1~0); 12998#L1150-1 assume !(0 == ~E_2~0); 12544#L1155-1 assume !(0 == ~E_3~0); 12545#L1160-1 assume !(0 == ~E_4~0); 12627#L1165-1 assume !(0 == ~E_5~0); 12628#L1170-1 assume !(0 == ~E_6~0); 13236#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12705#L1180-1 assume !(0 == ~E_8~0); 12706#L1185-1 assume !(0 == ~E_9~0); 12356#L1190-1 assume !(0 == ~E_10~0); 12357#L1195-1 assume !(0 == ~E_11~0); 12719#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12559#L525 assume !(1 == ~m_pc~0); 11977#L525-2 is_master_triggered_~__retres1~0#1 := 0; 11978#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12723#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12724#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12343#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12344#L544 assume 1 == ~t1_pc~0; 12604#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12568#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12996#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12194#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12195#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12817#L563 assume !(1 == ~t2_pc~0); 12983#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11998#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11999#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12427#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12428#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12890#L582 assume 1 == ~t3_pc~0; 12136#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12137#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13287#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13245#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12072#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12073#L601 assume !(1 == ~t4_pc~0); 13013#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12570#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12571#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13007#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13008#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13279#L620 assume 1 == ~t5_pc~0; 12027#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12028#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12842#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12843#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13294#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13295#L639 assume !(1 == ~t6_pc~0); 12844#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12468#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13248#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12578#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12579#L658 assume 1 == ~t7_pc~0; 12845#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12770#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12877#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12878#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12350#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12351#L677 assume 1 == ~t8_pc~0; 12581#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12153#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12154#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12424#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12425#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13103#L696 assume !(1 == ~t9_pc~0); 12828#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12829#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12918#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12850#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12851#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13048#L715 assume 1 == ~t10_pc~0; 13052#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12935#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12820#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12821#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12697#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12145#L734 assume !(1 == ~t11_pc~0); 12146#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12631#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12710#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11877#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11878#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12905#L1213 assume !(1 == ~M_E~0); 12694#L1213-2 assume !(1 == ~T1_E~0); 12695#L1218-1 assume !(1 == ~T2_E~0); 11914#L1223-1 assume !(1 == ~T3_E~0); 11915#L1228-1 assume !(1 == ~T4_E~0); 12674#L1233-1 assume !(1 == ~T5_E~0); 13296#L1238-1 assume !(1 == ~T6_E~0); 13005#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13006#L1248-1 assume !(1 == ~T8_E~0); 13050#L1253-1 assume !(1 == ~T9_E~0); 13051#L1258-1 assume !(1 == ~T10_E~0); 13029#L1263-1 assume !(1 == ~T11_E~0); 13030#L1268-1 assume !(1 == ~E_1~0); 12865#L1273-1 assume !(1 == ~E_2~0); 12866#L1278-1 assume !(1 == ~E_3~0); 12465#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1288-1 assume !(1 == ~E_5~0); 13143#L1293-1 assume !(1 == ~E_6~0); 13107#L1298-1 assume !(1 == ~E_7~0); 12893#L1303-1 assume !(1 == ~E_8~0); 12476#L1308-1 assume !(1 == ~E_9~0); 12365#L1313-1 assume !(1 == ~E_10~0); 12366#L1318-1 assume !(1 == ~E_11~0); 12375#L1323-1 assume { :end_inline_reset_delta_events } true; 12376#L1644-2 [2021-11-22 15:27:18,753 INFO L793 eck$LassoCheckResult]: Loop: 12376#L1644-2 assume !false; 12946#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12947#L1065 assume !false; 13022#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13292#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 11996#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13208#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12481#L906 assume !(0 != eval_~tmp~0#1); 12483#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13019#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13020#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13160#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13212#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13175#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13176#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12249#L1110-3 assume !(0 == ~T5_E~0); 12250#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12532#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12533#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13257#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12455#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11950#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11951#L1150-3 assume !(0 == ~E_2~0); 12074#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12075#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12436#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12437#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12346#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12104#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12105#L1190-3 assume !(0 == ~E_10~0); 13251#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13252#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12659#L525-36 assume !(1 == ~m_pc~0); 12660#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12205#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12206#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12491#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12492#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L544-36 assume 1 == ~t1_pc~0; 12401#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12924#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12289#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12290#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13233#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13136#L563-36 assume 1 == ~t2_pc~0; 12192#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11948#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11949#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13011#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12672#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12673#L582-36 assume 1 == ~t3_pc~0; 12523#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12524#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12748#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12915#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12709#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12653#L601-36 assume 1 == ~t4_pc~0; 12552#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12553#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13300#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13218#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13219#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13124#L620-36 assume 1 == ~t5_pc~0; 12594#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12595#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12986#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12580#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12214#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11992#L639-36 assume 1 == ~t6_pc~0; 11993#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12032#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12033#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12272#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12273#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12849#L658-36 assume !(1 == ~t7_pc~0); 12003#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12004#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13203#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11979#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 11980#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L677-36 assume !(1 == ~t8_pc~0); 12774#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12775#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12891#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13275#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12797#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12798#L696-36 assume 1 == ~t9_pc~0; 12691#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12693#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12052#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12053#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12811#L715-36 assume 1 == ~t10_pc~0; 12944#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11879#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11880#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11853#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11854#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12258#L734-36 assume 1 == ~t11_pc~0; 12259#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11958#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12280#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11871#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11872#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12871#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12540#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1218-3 assume !(1 == ~T2_E~0); 12309#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12310#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12499#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12744#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12745#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13217#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13222#L1258-3 assume !(1 == ~T10_E~0); 12291#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12292#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13187#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13205#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13207#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12623#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12624#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12489#L1298-3 assume !(1 == ~E_7~0); 12490#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12945#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12486#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12487#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12293#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12294#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12233#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12644#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 13083#L1663 assume !(0 == start_simulation_~tmp~3#1); 12126#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12847#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12070#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12768#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12014#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12015#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12353#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13272#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12376#L1644-2 [2021-11-22 15:27:18,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,754 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2021-11-22 15:27:18,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356109510] [2021-11-22 15:27:18,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,755 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356109510] [2021-11-22 15:27:18,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356109510] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,820 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514519906] [2021-11-22 15:27:18,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,821 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:18,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:18,822 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 2 times [2021-11-22 15:27:18,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:18,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158431767] [2021-11-22 15:27:18,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:18,823 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:18,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:18,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:18,901 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:18,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158431767] [2021-11-22 15:27:18,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158431767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:18,905 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:18,905 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:18,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117163422] [2021-11-22 15:27:18,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:18,907 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:18,907 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:18,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:18,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:18,908 INFO L87 Difference]: Start difference. First operand 1476 states and 2190 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:18,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:18,968 INFO L93 Difference]: Finished difference Result 1476 states and 2189 transitions. [2021-11-22 15:27:18,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:18,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2189 transitions. [2021-11-22 15:27:18,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-11-22 15:27:19,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:19,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:19,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2189 transitions. [2021-11-22 15:27:19,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:19,008 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-22 15:27:19,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2189 transitions. [2021-11-22 15:27:19,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:19,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4830623306233062) internal successors, (2189), 1475 states have internal predecessors, (2189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-11-22 15:27:19,052 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-22 15:27:19,052 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-22 15:27:19,052 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-22 15:27:19,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2189 transitions. [2021-11-22 15:27:19,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:19,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:19,066 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,067 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,067 INFO L791 eck$LassoCheckResult]: Stem: 15932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 15942#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15943#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15708#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15709#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15578#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15490#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15213#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14848#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14849#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14897#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14898#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15826#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15827#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15865#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15313#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15314#L1090 assume !(0 == ~M_E~0); 15356#L1090-2 assume !(0 == ~T1_E~0); 15357#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16003#L1100-1 assume !(0 == ~T3_E~0); 16004#L1105-1 assume !(0 == ~T4_E~0); 15132#L1110-1 assume !(0 == ~T5_E~0); 15133#L1115-1 assume !(0 == ~T6_E~0); 15528#L1120-1 assume !(0 == ~T7_E~0); 15805#L1125-1 assume !(0 == ~T8_E~0); 16274#L1130-1 assume !(0 == ~T9_E~0); 16023#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15318#L1140-1 assume !(0 == ~T11_E~0); 15319#L1145-1 assume !(0 == ~E_1~0); 15957#L1150-1 assume !(0 == ~E_2~0); 15503#L1155-1 assume !(0 == ~E_3~0); 15504#L1160-1 assume !(0 == ~E_4~0); 15586#L1165-1 assume !(0 == ~E_5~0); 15587#L1170-1 assume !(0 == ~E_6~0); 16195#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15664#L1180-1 assume !(0 == ~E_8~0); 15665#L1185-1 assume !(0 == ~E_9~0); 15315#L1190-1 assume !(0 == ~E_10~0); 15316#L1195-1 assume !(0 == ~E_11~0); 15678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15525#L525 assume !(1 == ~m_pc~0); 14936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 14937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15682#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15683#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15302#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15303#L544 assume 1 == ~t1_pc~0; 15563#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15527#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15955#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15153#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15154#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15776#L563 assume !(1 == ~t2_pc~0); 15944#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14957#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14958#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15386#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15387#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15849#L582 assume 1 == ~t3_pc~0; 15097#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15098#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16246#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16204#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15031#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15032#L601 assume !(1 == ~t4_pc~0); 15972#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15529#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15530#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15966#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 15967#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16238#L620 assume 1 == ~t5_pc~0; 14988#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14989#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15801#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15802#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16253#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16254#L639 assume !(1 == ~t6_pc~0); 15803#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15426#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15427#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16207#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15537#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15538#L658 assume 1 == ~t7_pc~0; 15804#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15836#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15837#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15309#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15310#L677 assume 1 == ~t8_pc~0; 15540#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15112#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15113#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15383#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15384#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16062#L696 assume !(1 == ~t9_pc~0); 15789#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15790#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15877#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15809#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15810#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16007#L715 assume 1 == ~t10_pc~0; 16011#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15894#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15779#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15780#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15106#L734 assume !(1 == ~t11_pc~0); 15107#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15590#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15669#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14838#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14839#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15864#L1213 assume !(1 == ~M_E~0); 15654#L1213-2 assume !(1 == ~T1_E~0); 15655#L1218-1 assume !(1 == ~T2_E~0); 14873#L1223-1 assume !(1 == ~T3_E~0); 14874#L1228-1 assume !(1 == ~T4_E~0); 15633#L1233-1 assume !(1 == ~T5_E~0); 16255#L1238-1 assume !(1 == ~T6_E~0); 15964#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15965#L1248-1 assume !(1 == ~T8_E~0); 16009#L1253-1 assume !(1 == ~T9_E~0); 16010#L1258-1 assume !(1 == ~T10_E~0); 15988#L1263-1 assume !(1 == ~T11_E~0); 15989#L1268-1 assume !(1 == ~E_1~0); 15824#L1273-1 assume !(1 == ~E_2~0); 15825#L1278-1 assume !(1 == ~E_3~0); 15424#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15425#L1288-1 assume !(1 == ~E_5~0); 16102#L1293-1 assume !(1 == ~E_6~0); 16066#L1298-1 assume !(1 == ~E_7~0); 15852#L1303-1 assume !(1 == ~E_8~0); 15435#L1308-1 assume !(1 == ~E_9~0); 15324#L1313-1 assume !(1 == ~E_10~0); 15325#L1318-1 assume !(1 == ~E_11~0); 15337#L1323-1 assume { :end_inline_reset_delta_events } true; 15338#L1644-2 [2021-11-22 15:27:19,068 INFO L793 eck$LassoCheckResult]: Loop: 15338#L1644-2 assume !false; 15905#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15906#L1065 assume !false; 15981#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16251#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 14955#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16167#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15440#L906 assume !(0 != eval_~tmp~0#1); 15442#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15978#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15979#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16119#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16171#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16134#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16135#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15208#L1110-3 assume !(0 == ~T5_E~0); 15209#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15491#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15492#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15962#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16216#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15414#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14911#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1150-3 assume !(0 == ~E_2~0); 15034#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15035#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15395#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15396#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15768#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15305#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15064#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15065#L1190-3 assume !(0 == ~E_10~0); 16210#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16211#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15618#L525-36 assume !(1 == ~m_pc~0); 15619#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15169#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15170#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15451#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15452#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15359#L544-36 assume 1 == ~t1_pc~0; 15360#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15883#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15254#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16193#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16095#L563-36 assume !(1 == ~t2_pc~0); 15152#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 14907#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14908#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15970#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15631#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15632#L582-36 assume 1 == ~t3_pc~0; 15482#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15483#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15707#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15874#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15668#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15612#L601-36 assume 1 == ~t4_pc~0; 15511#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15512#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16259#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16177#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16178#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16083#L620-36 assume 1 == ~t5_pc~0; 15554#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15555#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15947#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15539#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15173#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14948#L639-36 assume 1 == ~t6_pc~0; 14949#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14986#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14987#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15808#L658-36 assume 1 == ~t7_pc~0; 15068#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14960#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16162#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14938#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 14939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15929#L677-36 assume !(1 == ~t8_pc~0); 15732#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15733#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15850#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16234#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15756#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15757#L696-36 assume 1 == ~t9_pc~0; 15650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15652#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15008#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15009#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15769#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15770#L715-36 assume !(1 == ~t10_pc~0); 15740#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14836#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14837#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15217#L734-36 assume 1 == ~t11_pc~0; 15218#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14917#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15239#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14830#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14831#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15830#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15497#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15498#L1218-3 assume !(1 == ~T2_E~0); 15268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15458#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15459#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15703#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15704#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16175#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16180#L1258-3 assume !(1 == ~T10_E~0); 15248#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15249#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16146#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16164#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16166#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15582#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15583#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15447#L1298-3 assume !(1 == ~E_7~0); 15448#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15904#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15445#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15446#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15250#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15251#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15192#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15603#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 16042#L1663 assume !(0 == start_simulation_~tmp~3#1); 15078#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15806#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15029#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15725#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14970#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15312#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16231#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15338#L1644-2 [2021-11-22 15:27:19,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,091 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2021-11-22 15:27:19,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500536645] [2021-11-22 15:27:19,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,092 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,136 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500536645] [2021-11-22 15:27:19,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500536645] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,137 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723215401] [2021-11-22 15:27:19,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:19,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,143 INFO L85 PathProgramCache]: Analyzing trace with hash -459098803, now seen corresponding path program 1 times [2021-11-22 15:27:19,143 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522119620] [2021-11-22 15:27:19,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,149 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,216 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,216 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522119620] [2021-11-22 15:27:19,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522119620] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,221 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,221 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,221 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918434779] [2021-11-22 15:27:19,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,223 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:19,223 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:19,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:19,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:19,225 INFO L87 Difference]: Start difference. First operand 1476 states and 2189 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:19,272 INFO L93 Difference]: Finished difference Result 1476 states and 2188 transitions. [2021-11-22 15:27:19,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:19,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2188 transitions. [2021-11-22 15:27:19,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-11-22 15:27:19,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:19,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:19,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2188 transitions. [2021-11-22 15:27:19,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:19,310 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-22 15:27:19,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2188 transitions. [2021-11-22 15:27:19,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:19,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4823848238482384) internal successors, (2188), 1475 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-11-22 15:27:19,355 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-22 15:27:19,355 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-22 15:27:19,355 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-22 15:27:19,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2188 transitions. [2021-11-22 15:27:19,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:19,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:19,367 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,367 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,368 INFO L791 eck$LassoCheckResult]: Stem: 18891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 18901#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18902#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18667#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18668#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18537#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18449#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18172#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17807#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17808#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17856#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17857#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18787#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18788#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18831#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18272#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18273#L1090 assume !(0 == ~M_E~0); 18319#L1090-2 assume !(0 == ~T1_E~0); 18320#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18962#L1100-1 assume !(0 == ~T3_E~0); 18963#L1105-1 assume !(0 == ~T4_E~0); 18091#L1110-1 assume !(0 == ~T5_E~0); 18092#L1115-1 assume !(0 == ~T6_E~0); 18490#L1120-1 assume !(0 == ~T7_E~0); 18764#L1125-1 assume !(0 == ~T8_E~0); 19233#L1130-1 assume !(0 == ~T9_E~0); 18982#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18279#L1140-1 assume !(0 == ~T11_E~0); 18280#L1145-1 assume !(0 == ~E_1~0); 18916#L1150-1 assume !(0 == ~E_2~0); 18462#L1155-1 assume !(0 == ~E_3~0); 18463#L1160-1 assume !(0 == ~E_4~0); 18545#L1165-1 assume !(0 == ~E_5~0); 18546#L1170-1 assume !(0 == ~E_6~0); 19154#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18623#L1180-1 assume !(0 == ~E_8~0); 18624#L1185-1 assume !(0 == ~E_9~0); 18274#L1190-1 assume !(0 == ~E_10~0); 18275#L1195-1 assume !(0 == ~E_11~0); 18637#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18484#L525 assume !(1 == ~m_pc~0); 17895#L525-2 is_master_triggered_~__retres1~0#1 := 0; 17896#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18641#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18642#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18262#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18263#L544 assume 1 == ~t1_pc~0; 18522#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18486#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18914#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18112#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18113#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18735#L563 assume !(1 == ~t2_pc~0); 18903#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17916#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17917#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18348#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18349#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18808#L582 assume 1 == ~t3_pc~0; 18056#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18057#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19205#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19164#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 17990#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17991#L601 assume !(1 == ~t4_pc~0); 18931#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18491#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18492#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18925#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 18926#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19197#L620 assume 1 == ~t5_pc~0; 17949#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17950#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18761#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18762#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19212#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19213#L639 assume !(1 == ~t6_pc~0); 18763#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18385#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18386#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19166#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18496#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18497#L658 assume 1 == ~t7_pc~0; 18760#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18688#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18795#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18796#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18268#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18269#L677 assume 1 == ~t8_pc~0; 18499#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18071#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18072#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18342#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18343#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19021#L696 assume !(1 == ~t9_pc~0); 18746#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18747#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18836#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18768#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18769#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18966#L715 assume 1 == ~t10_pc~0; 18970#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18853#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18738#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18739#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18615#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18063#L734 assume !(1 == ~t11_pc~0); 18064#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18549#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18628#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17795#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17796#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18823#L1213 assume !(1 == ~M_E~0); 18612#L1213-2 assume !(1 == ~T1_E~0); 18613#L1218-1 assume !(1 == ~T2_E~0); 17832#L1223-1 assume !(1 == ~T3_E~0); 17833#L1228-1 assume !(1 == ~T4_E~0); 18592#L1233-1 assume !(1 == ~T5_E~0); 19214#L1238-1 assume !(1 == ~T6_E~0); 18923#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18924#L1248-1 assume !(1 == ~T8_E~0); 18968#L1253-1 assume !(1 == ~T9_E~0); 18969#L1258-1 assume !(1 == ~T10_E~0); 18947#L1263-1 assume !(1 == ~T11_E~0); 18948#L1268-1 assume !(1 == ~E_1~0); 18783#L1273-1 assume !(1 == ~E_2~0); 18784#L1278-1 assume !(1 == ~E_3~0); 18383#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18384#L1288-1 assume !(1 == ~E_5~0); 19061#L1293-1 assume !(1 == ~E_6~0); 19025#L1298-1 assume !(1 == ~E_7~0); 18811#L1303-1 assume !(1 == ~E_8~0); 18394#L1308-1 assume !(1 == ~E_9~0); 18283#L1313-1 assume !(1 == ~E_10~0); 18284#L1318-1 assume !(1 == ~E_11~0); 18293#L1323-1 assume { :end_inline_reset_delta_events } true; 18294#L1644-2 [2021-11-22 15:27:19,369 INFO L793 eck$LassoCheckResult]: Loop: 18294#L1644-2 assume !false; 18864#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18865#L1065 assume !false; 18940#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19210#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17914#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19126#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18399#L906 assume !(0 != eval_~tmp~0#1); 18401#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18937#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18938#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19078#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19130#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19093#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19094#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18167#L1110-3 assume !(0 == ~T5_E~0); 18168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18450#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18451#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18921#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19175#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18373#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17868#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17869#L1150-3 assume !(0 == ~E_2~0); 17992#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17993#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18354#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18355#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18727#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18264#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18022#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18023#L1190-3 assume !(0 == ~E_10~0); 19169#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19170#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18577#L525-36 assume !(1 == ~m_pc~0); 18578#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18123#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18124#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18409#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18410#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18316#L544-36 assume 1 == ~t1_pc~0; 18317#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18842#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18207#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18208#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19151#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19054#L563-36 assume 1 == ~t2_pc~0; 18110#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17866#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17867#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18929#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18590#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18591#L582-36 assume 1 == ~t3_pc~0; 18441#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18442#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18833#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18627#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18571#L601-36 assume 1 == ~t4_pc~0; 18470#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18471#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19218#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19136#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19137#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19042#L620-36 assume 1 == ~t5_pc~0; 18512#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18513#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18904#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18498#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18132#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17910#L639-36 assume 1 == ~t6_pc~0; 17911#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17947#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17948#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18190#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18191#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18767#L658-36 assume !(1 == ~t7_pc~0); 17921#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 17922#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19121#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17897#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 17898#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18888#L677-36 assume !(1 == ~t8_pc~0); 18692#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18693#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18809#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19193#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18715#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L696-36 assume 1 == ~t9_pc~0; 18609#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18611#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17970#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17971#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18728#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18729#L715-36 assume !(1 == ~t10_pc~0); 18699#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17797#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17798#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17771#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17772#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18176#L734-36 assume 1 == ~t11_pc~0; 18177#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17876#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18198#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17789#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17790#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18789#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18458#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18459#L1218-3 assume !(1 == ~T2_E~0); 18227#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18228#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18417#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18418#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18662#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18663#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19135#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19140#L1258-3 assume !(1 == ~T10_E~0); 18209#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18210#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19105#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19123#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19125#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18541#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18407#L1298-3 assume !(1 == ~E_7~0); 18408#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18863#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18404#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18405#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18211#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18212#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18151#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18562#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19001#L1663 assume !(0 == start_simulation_~tmp~3#1); 18044#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18765#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17988#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18686#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 17932#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17933#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18271#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19190#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18294#L1644-2 [2021-11-22 15:27:19,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,370 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2021-11-22 15:27:19,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271017412] [2021-11-22 15:27:19,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,371 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,413 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271017412] [2021-11-22 15:27:19,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271017412] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,414 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,415 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773307622] [2021-11-22 15:27:19,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,416 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:19,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1992669811, now seen corresponding path program 1 times [2021-11-22 15:27:19,417 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778004432] [2021-11-22 15:27:19,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,418 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778004432] [2021-11-22 15:27:19,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778004432] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633788391] [2021-11-22 15:27:19,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,484 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:19,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:19,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:19,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:19,486 INFO L87 Difference]: Start difference. First operand 1476 states and 2188 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:19,534 INFO L93 Difference]: Finished difference Result 1476 states and 2187 transitions. [2021-11-22 15:27:19,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:19,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2187 transitions. [2021-11-22 15:27:19,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-11-22 15:27:19,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:19,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:19,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2187 transitions. [2021-11-22 15:27:19,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:19,571 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-22 15:27:19,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2187 transitions. [2021-11-22 15:27:19,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:19,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4817073170731707) internal successors, (2187), 1475 states have internal predecessors, (2187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-11-22 15:27:19,617 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-22 15:27:19,618 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-22 15:27:19,618 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-22 15:27:19,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2187 transitions. [2021-11-22 15:27:19,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:19,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:19,630 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,630 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,631 INFO L791 eck$LassoCheckResult]: Stem: 21850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 21858#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21859#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21626#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21627#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21496#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21408#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21131#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20766#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20767#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20815#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20816#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21744#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21745#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21783#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21231#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21232#L1090 assume !(0 == ~M_E~0); 21274#L1090-2 assume !(0 == ~T1_E~0); 21275#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21920#L1100-1 assume !(0 == ~T3_E~0); 21921#L1105-1 assume !(0 == ~T4_E~0); 21049#L1110-1 assume !(0 == ~T5_E~0); 21050#L1115-1 assume !(0 == ~T6_E~0); 21446#L1120-1 assume !(0 == ~T7_E~0); 21723#L1125-1 assume !(0 == ~T8_E~0); 22192#L1130-1 assume !(0 == ~T9_E~0); 21941#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21236#L1140-1 assume !(0 == ~T11_E~0); 21237#L1145-1 assume !(0 == ~E_1~0); 21875#L1150-1 assume !(0 == ~E_2~0); 21421#L1155-1 assume !(0 == ~E_3~0); 21422#L1160-1 assume !(0 == ~E_4~0); 21504#L1165-1 assume !(0 == ~E_5~0); 21505#L1170-1 assume !(0 == ~E_6~0); 22113#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21582#L1180-1 assume !(0 == ~E_8~0); 21583#L1185-1 assume !(0 == ~E_9~0); 21233#L1190-1 assume !(0 == ~E_10~0); 21234#L1195-1 assume !(0 == ~E_11~0); 21596#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21438#L525 assume !(1 == ~m_pc~0); 20854#L525-2 is_master_triggered_~__retres1~0#1 := 0; 20855#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21600#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21601#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21220#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21221#L544 assume 1 == ~t1_pc~0; 21481#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21445#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21873#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21071#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21072#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21694#L563 assume !(1 == ~t2_pc~0); 21860#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20875#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20876#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21304#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21767#L582 assume 1 == ~t3_pc~0; 21013#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21014#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22164#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22122#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 20949#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20950#L601 assume !(1 == ~t4_pc~0); 21890#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21447#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21448#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21884#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 21885#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22156#L620 assume 1 == ~t5_pc~0; 20904#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20905#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21719#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21720#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22171#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22172#L639 assume !(1 == ~t6_pc~0); 21721#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21344#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21345#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22125#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21455#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21456#L658 assume 1 == ~t7_pc~0; 21722#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21647#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21754#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21755#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21227#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21228#L677 assume 1 == ~t8_pc~0; 21458#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21030#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21031#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21301#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21302#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21980#L696 assume !(1 == ~t9_pc~0); 21705#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21706#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21795#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21728#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21925#L715 assume 1 == ~t10_pc~0; 21929#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21812#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21697#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21574#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21022#L734 assume !(1 == ~t11_pc~0); 21023#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21508#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21587#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20756#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20757#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21782#L1213 assume !(1 == ~M_E~0); 21571#L1213-2 assume !(1 == ~T1_E~0); 21572#L1218-1 assume !(1 == ~T2_E~0); 20791#L1223-1 assume !(1 == ~T3_E~0); 20792#L1228-1 assume !(1 == ~T4_E~0); 21551#L1233-1 assume !(1 == ~T5_E~0); 22173#L1238-1 assume !(1 == ~T6_E~0); 21882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21883#L1248-1 assume !(1 == ~T8_E~0); 21927#L1253-1 assume !(1 == ~T9_E~0); 21928#L1258-1 assume !(1 == ~T10_E~0); 21906#L1263-1 assume !(1 == ~T11_E~0); 21907#L1268-1 assume !(1 == ~E_1~0); 21742#L1273-1 assume !(1 == ~E_2~0); 21743#L1278-1 assume !(1 == ~E_3~0); 21342#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21343#L1288-1 assume !(1 == ~E_5~0); 22020#L1293-1 assume !(1 == ~E_6~0); 21984#L1298-1 assume !(1 == ~E_7~0); 21770#L1303-1 assume !(1 == ~E_8~0); 21353#L1308-1 assume !(1 == ~E_9~0); 21242#L1313-1 assume !(1 == ~E_10~0); 21243#L1318-1 assume !(1 == ~E_11~0); 21252#L1323-1 assume { :end_inline_reset_delta_events } true; 21253#L1644-2 [2021-11-22 15:27:19,632 INFO L793 eck$LassoCheckResult]: Loop: 21253#L1644-2 assume !false; 21823#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21824#L1065 assume !false; 21899#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22169#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20873#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22085#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21358#L906 assume !(0 != eval_~tmp~0#1); 21360#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21896#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21897#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22037#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22089#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22052#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22053#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21126#L1110-3 assume !(0 == ~T5_E~0); 21127#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21409#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21410#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21880#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22134#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21332#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20827#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20828#L1150-3 assume !(0 == ~E_2~0); 20952#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20953#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21313#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21314#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21686#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21223#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20981#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20982#L1190-3 assume !(0 == ~E_10~0); 22128#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22129#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21536#L525-36 assume !(1 == ~m_pc~0); 21537#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21082#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21083#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21368#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21369#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21277#L544-36 assume 1 == ~t1_pc~0; 21278#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21801#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21172#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21173#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22111#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22013#L563-36 assume 1 == ~t2_pc~0; 21069#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20825#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20826#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21888#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21549#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21550#L582-36 assume 1 == ~t3_pc~0; 21400#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21401#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21625#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21792#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21586#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21530#L601-36 assume 1 == ~t4_pc~0; 21429#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21430#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22177#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22096#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22001#L620-36 assume 1 == ~t5_pc~0; 21472#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21473#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21865#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21457#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21091#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20869#L639-36 assume 1 == ~t6_pc~0; 20870#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20909#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20910#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21149#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21150#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21726#L658-36 assume !(1 == ~t7_pc~0); 20880#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22080#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20856#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 20857#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21847#L677-36 assume !(1 == ~t8_pc~0); 21651#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21652#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21768#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22152#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21674#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21675#L696-36 assume 1 == ~t9_pc~0; 21568#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21570#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20926#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20927#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21687#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21688#L715-36 assume !(1 == ~t10_pc~0); 21658#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 20754#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20755#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20730#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20731#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21132#L734-36 assume !(1 == ~t11_pc~0); 20834#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20835#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21157#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20748#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20749#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21748#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21415#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21416#L1218-3 assume !(1 == ~T2_E~0); 21186#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21187#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21376#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21377#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21621#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21622#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22093#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22098#L1258-3 assume !(1 == ~T10_E~0); 21166#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21167#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22064#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22082#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22083#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21500#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21501#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21365#L1298-3 assume !(1 == ~E_7~0); 21366#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21822#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21363#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21364#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21168#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21169#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21110#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21521#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21960#L1663 assume !(0 == start_simulation_~tmp~3#1); 20996#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21724#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20947#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21643#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20888#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20889#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21230#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22149#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21253#L1644-2 [2021-11-22 15:27:19,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2021-11-22 15:27:19,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301287275] [2021-11-22 15:27:19,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,634 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,676 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301287275] [2021-11-22 15:27:19,676 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301287275] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,678 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,678 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,679 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590366688] [2021-11-22 15:27:19,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,679 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:19,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,680 INFO L85 PathProgramCache]: Analyzing trace with hash 146783084, now seen corresponding path program 1 times [2021-11-22 15:27:19,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876543252] [2021-11-22 15:27:19,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,694 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,739 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876543252] [2021-11-22 15:27:19,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876543252] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,739 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637688045] [2021-11-22 15:27:19,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,741 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:19,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:19,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:19,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:19,742 INFO L87 Difference]: Start difference. First operand 1476 states and 2187 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:19,786 INFO L93 Difference]: Finished difference Result 1476 states and 2186 transitions. [2021-11-22 15:27:19,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:19,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2186 transitions. [2021-11-22 15:27:19,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-11-22 15:27:19,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:19,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:19,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2186 transitions. [2021-11-22 15:27:19,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:19,854 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-22 15:27:19,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2186 transitions. [2021-11-22 15:27:19,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:19,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.481029810298103) internal successors, (2186), 1475 states have internal predecessors, (2186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:19,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-11-22 15:27:19,899 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-22 15:27:19,899 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-22 15:27:19,899 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-22 15:27:19,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2186 transitions. [2021-11-22 15:27:19,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:19,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:19,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:19,912 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,912 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:19,913 INFO L791 eck$LassoCheckResult]: Stem: 24809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 24819#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24820#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24585#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24586#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24455#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24367#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24090#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23725#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23726#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23774#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23775#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24705#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24706#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24749#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24190#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24191#L1090 assume !(0 == ~M_E~0); 24237#L1090-2 assume !(0 == ~T1_E~0); 24238#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24880#L1100-1 assume !(0 == ~T3_E~0); 24881#L1105-1 assume !(0 == ~T4_E~0); 24009#L1110-1 assume !(0 == ~T5_E~0); 24010#L1115-1 assume !(0 == ~T6_E~0); 24408#L1120-1 assume !(0 == ~T7_E~0); 24682#L1125-1 assume !(0 == ~T8_E~0); 25151#L1130-1 assume !(0 == ~T9_E~0); 24900#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24197#L1140-1 assume !(0 == ~T11_E~0); 24198#L1145-1 assume !(0 == ~E_1~0); 24834#L1150-1 assume !(0 == ~E_2~0); 24380#L1155-1 assume !(0 == ~E_3~0); 24381#L1160-1 assume !(0 == ~E_4~0); 24463#L1165-1 assume !(0 == ~E_5~0); 24464#L1170-1 assume !(0 == ~E_6~0); 25072#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24541#L1180-1 assume !(0 == ~E_8~0); 24542#L1185-1 assume !(0 == ~E_9~0); 24192#L1190-1 assume !(0 == ~E_10~0); 24193#L1195-1 assume !(0 == ~E_11~0); 24555#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24402#L525 assume !(1 == ~m_pc~0); 23813#L525-2 is_master_triggered_~__retres1~0#1 := 0; 23814#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24559#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24560#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24179#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24180#L544 assume 1 == ~t1_pc~0; 24440#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24404#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24832#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24030#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24031#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24653#L563 assume !(1 == ~t2_pc~0); 24821#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23834#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23835#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24266#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24267#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24726#L582 assume 1 == ~t3_pc~0; 23974#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23975#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25123#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25081#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 23908#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23909#L601 assume !(1 == ~t4_pc~0); 24849#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24410#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24843#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 24844#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25115#L620 assume 1 == ~t5_pc~0; 23867#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23868#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24678#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24679#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25130#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25131#L639 assume !(1 == ~t6_pc~0); 24680#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24303#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24304#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25084#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24414#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24415#L658 assume 1 == ~t7_pc~0; 24681#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24713#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24714#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24186#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24187#L677 assume 1 == ~t8_pc~0; 24419#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23992#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23993#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24260#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24261#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24939#L696 assume !(1 == ~t9_pc~0); 24667#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24668#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24757#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24688#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24689#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24884#L715 assume 1 == ~t10_pc~0; 24888#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24771#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24656#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24657#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24533#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23983#L734 assume !(1 == ~t11_pc~0); 23984#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24467#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24546#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23715#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23716#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24741#L1213 assume !(1 == ~M_E~0); 24531#L1213-2 assume !(1 == ~T1_E~0); 24532#L1218-1 assume !(1 == ~T2_E~0); 23750#L1223-1 assume !(1 == ~T3_E~0); 23751#L1228-1 assume !(1 == ~T4_E~0); 24510#L1233-1 assume !(1 == ~T5_E~0); 25132#L1238-1 assume !(1 == ~T6_E~0); 24841#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1248-1 assume !(1 == ~T8_E~0); 24886#L1253-1 assume !(1 == ~T9_E~0); 24887#L1258-1 assume !(1 == ~T10_E~0); 24865#L1263-1 assume !(1 == ~T11_E~0); 24866#L1268-1 assume !(1 == ~E_1~0); 24701#L1273-1 assume !(1 == ~E_2~0); 24702#L1278-1 assume !(1 == ~E_3~0); 24301#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24302#L1288-1 assume !(1 == ~E_5~0); 24979#L1293-1 assume !(1 == ~E_6~0); 24943#L1298-1 assume !(1 == ~E_7~0); 24729#L1303-1 assume !(1 == ~E_8~0); 24312#L1308-1 assume !(1 == ~E_9~0); 24201#L1313-1 assume !(1 == ~E_10~0); 24202#L1318-1 assume !(1 == ~E_11~0); 24214#L1323-1 assume { :end_inline_reset_delta_events } true; 24215#L1644-2 [2021-11-22 15:27:19,914 INFO L793 eck$LassoCheckResult]: Loop: 24215#L1644-2 assume !false; 24782#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24783#L1065 assume !false; 24858#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25128#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23832#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25044#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24317#L906 assume !(0 != eval_~tmp~0#1); 24319#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24856#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24857#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24996#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25011#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25012#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24085#L1110-3 assume !(0 == ~T5_E~0); 24086#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24368#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24369#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24839#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25093#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24291#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23786#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23787#L1150-3 assume !(0 == ~E_2~0); 23910#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23911#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24272#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24273#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24645#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24182#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23940#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23941#L1190-3 assume !(0 == ~E_10~0); 25087#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25088#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24492#L525-36 assume !(1 == ~m_pc~0); 24493#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24041#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24042#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24327#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24328#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24234#L544-36 assume 1 == ~t1_pc~0; 24235#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24760#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24125#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24126#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25069#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24972#L563-36 assume 1 == ~t2_pc~0; 24028#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23784#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23785#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24847#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24508#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24509#L582-36 assume 1 == ~t3_pc~0; 24359#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24360#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24584#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24751#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24545#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24489#L601-36 assume 1 == ~t4_pc~0; 24388#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24389#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25136#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25054#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25055#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24960#L620-36 assume 1 == ~t5_pc~0; 24428#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24429#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24822#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24416#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24050#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23828#L639-36 assume 1 == ~t6_pc~0; 23829#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23865#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23866#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24106#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24107#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24685#L658-36 assume 1 == ~t7_pc~0; 23947#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23840#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25039#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23815#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 23816#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24806#L677-36 assume !(1 == ~t8_pc~0); 24610#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 24611#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24727#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25111#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24633#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24634#L696-36 assume !(1 == ~t9_pc~0); 24528#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24529#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23888#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23889#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24646#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L715-36 assume !(1 == ~t10_pc~0); 24617#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23713#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23714#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23689#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23690#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24094#L734-36 assume !(1 == ~t11_pc~0); 23793#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 23794#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24116#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23707#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23708#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24707#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24374#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24375#L1218-3 assume !(1 == ~T2_E~0); 24145#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24146#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24335#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24336#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24580#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24581#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25052#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25057#L1258-3 assume !(1 == ~T10_E~0); 24127#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24128#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25023#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25041#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25043#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24459#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24460#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24325#L1298-3 assume !(1 == ~E_7~0); 24326#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24781#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24322#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24323#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24129#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24130#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24069#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24480#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24919#L1663 assume !(0 == start_simulation_~tmp~3#1); 23962#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24683#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23906#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24602#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23850#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23851#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24189#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25108#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24215#L1644-2 [2021-11-22 15:27:19,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2021-11-22 15:27:19,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747292758] [2021-11-22 15:27:19,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747292758] [2021-11-22 15:27:19,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747292758] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,951 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641297519] [2021-11-22 15:27:19,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,952 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:19,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:19,953 INFO L85 PathProgramCache]: Analyzing trace with hash 1427558892, now seen corresponding path program 1 times [2021-11-22 15:27:19,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:19,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296643117] [2021-11-22 15:27:19,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:19,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:19,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:19,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:19,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:19,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296643117] [2021-11-22 15:27:19,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296643117] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:19,997 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:19,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:19,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599684177] [2021-11-22 15:27:19,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:19,998 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:19,998 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:19,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:19,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:19,999 INFO L87 Difference]: Start difference. First operand 1476 states and 2186 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:20,037 INFO L93 Difference]: Finished difference Result 1476 states and 2185 transitions. [2021-11-22 15:27:20,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:20,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2185 transitions. [2021-11-22 15:27:20,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-11-22 15:27:20,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:20,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:20,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2185 transitions. [2021-11-22 15:27:20,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:20,066 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-22 15:27:20,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2185 transitions. [2021-11-22 15:27:20,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:20,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4803523035230353) internal successors, (2185), 1475 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-11-22 15:27:20,104 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-22 15:27:20,104 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-22 15:27:20,104 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-22 15:27:20,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2185 transitions. [2021-11-22 15:27:20,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:20,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:20,116 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,116 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,117 INFO L791 eck$LassoCheckResult]: Stem: 27768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 27776#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27777#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27544#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27545#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27414#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27326#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27049#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26684#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26685#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26733#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26734#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27662#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27663#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27701#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27149#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27150#L1090 assume !(0 == ~M_E~0); 27192#L1090-2 assume !(0 == ~T1_E~0); 27193#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27838#L1100-1 assume !(0 == ~T3_E~0); 27839#L1105-1 assume !(0 == ~T4_E~0); 26967#L1110-1 assume !(0 == ~T5_E~0); 26968#L1115-1 assume !(0 == ~T6_E~0); 27364#L1120-1 assume !(0 == ~T7_E~0); 27641#L1125-1 assume !(0 == ~T8_E~0); 28110#L1130-1 assume !(0 == ~T9_E~0); 27859#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27154#L1140-1 assume !(0 == ~T11_E~0); 27155#L1145-1 assume !(0 == ~E_1~0); 27793#L1150-1 assume !(0 == ~E_2~0); 27339#L1155-1 assume !(0 == ~E_3~0); 27340#L1160-1 assume !(0 == ~E_4~0); 27422#L1165-1 assume !(0 == ~E_5~0); 27423#L1170-1 assume !(0 == ~E_6~0); 28031#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27500#L1180-1 assume !(0 == ~E_8~0); 27501#L1185-1 assume !(0 == ~E_9~0); 27151#L1190-1 assume !(0 == ~E_10~0); 27152#L1195-1 assume !(0 == ~E_11~0); 27514#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27354#L525 assume !(1 == ~m_pc~0); 26772#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26773#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27518#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27519#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27138#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27139#L544 assume 1 == ~t1_pc~0; 27399#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27363#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27791#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26989#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 26990#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27612#L563 assume !(1 == ~t2_pc~0); 27778#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26793#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26794#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27222#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27223#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27685#L582 assume 1 == ~t3_pc~0; 26931#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26932#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28082#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28040#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 26867#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26868#L601 assume !(1 == ~t4_pc~0); 27808#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27365#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27366#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27802#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 27803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28074#L620 assume 1 == ~t5_pc~0; 26822#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26823#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27637#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27638#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28089#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28090#L639 assume !(1 == ~t6_pc~0); 27639#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27262#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27263#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28043#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27373#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27374#L658 assume 1 == ~t7_pc~0; 27640#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27565#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27672#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27673#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27145#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27146#L677 assume 1 == ~t8_pc~0; 27376#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26948#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26949#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27219#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27220#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27898#L696 assume !(1 == ~t9_pc~0); 27623#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27624#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27713#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27645#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27646#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27843#L715 assume 1 == ~t10_pc~0; 27847#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27730#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27615#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27616#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27492#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26940#L734 assume !(1 == ~t11_pc~0); 26941#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27426#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27505#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26672#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26673#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27700#L1213 assume !(1 == ~M_E~0); 27489#L1213-2 assume !(1 == ~T1_E~0); 27490#L1218-1 assume !(1 == ~T2_E~0); 26709#L1223-1 assume !(1 == ~T3_E~0); 26710#L1228-1 assume !(1 == ~T4_E~0); 27469#L1233-1 assume !(1 == ~T5_E~0); 28091#L1238-1 assume !(1 == ~T6_E~0); 27800#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27801#L1248-1 assume !(1 == ~T8_E~0); 27845#L1253-1 assume !(1 == ~T9_E~0); 27846#L1258-1 assume !(1 == ~T10_E~0); 27824#L1263-1 assume !(1 == ~T11_E~0); 27825#L1268-1 assume !(1 == ~E_1~0); 27660#L1273-1 assume !(1 == ~E_2~0); 27661#L1278-1 assume !(1 == ~E_3~0); 27260#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27261#L1288-1 assume !(1 == ~E_5~0); 27938#L1293-1 assume !(1 == ~E_6~0); 27902#L1298-1 assume !(1 == ~E_7~0); 27688#L1303-1 assume !(1 == ~E_8~0); 27271#L1308-1 assume !(1 == ~E_9~0); 27160#L1313-1 assume !(1 == ~E_10~0); 27161#L1318-1 assume !(1 == ~E_11~0); 27170#L1323-1 assume { :end_inline_reset_delta_events } true; 27171#L1644-2 [2021-11-22 15:27:20,117 INFO L793 eck$LassoCheckResult]: Loop: 27171#L1644-2 assume !false; 27741#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27742#L1065 assume !false; 27817#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28087#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26791#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28003#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27276#L906 assume !(0 != eval_~tmp~0#1); 27278#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27814#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27815#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27955#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28007#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27970#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27971#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27044#L1110-3 assume !(0 == ~T5_E~0); 27045#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27327#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27328#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27798#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28052#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27250#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26745#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26746#L1150-3 assume !(0 == ~E_2~0); 26869#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26870#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27231#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27232#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27604#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27141#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26899#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26900#L1190-3 assume !(0 == ~E_10~0); 28046#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28047#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27454#L525-36 assume 1 == ~m_pc~0; 27456#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27000#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27001#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27287#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27195#L544-36 assume 1 == ~t1_pc~0; 27196#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27719#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27084#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27085#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28028#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27931#L563-36 assume 1 == ~t2_pc~0; 26987#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26743#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26744#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27806#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27467#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27468#L582-36 assume 1 == ~t3_pc~0; 27318#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27319#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27543#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27710#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27504#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27448#L601-36 assume 1 == ~t4_pc~0; 27347#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27348#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28095#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28013#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28014#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27919#L620-36 assume 1 == ~t5_pc~0; 27389#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27390#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27781#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27375#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27009#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26787#L639-36 assume 1 == ~t6_pc~0; 26788#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26827#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26828#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27067#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27068#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27644#L658-36 assume 1 == ~t7_pc~0; 26906#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26799#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27998#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26774#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 26775#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27765#L677-36 assume !(1 == ~t8_pc~0); 27569#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27570#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27686#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28070#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27592#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27593#L696-36 assume 1 == ~t9_pc~0; 27486#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27488#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26847#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26848#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27605#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27606#L715-36 assume !(1 == ~t10_pc~0); 27576#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 26674#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26675#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26648#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26649#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27053#L734-36 assume !(1 == ~t11_pc~0); 26752#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26753#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27075#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26666#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26667#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27666#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27335#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27336#L1218-3 assume !(1 == ~T2_E~0); 27104#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27105#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27294#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27295#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27539#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27540#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28012#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28017#L1258-3 assume !(1 == ~T10_E~0); 27086#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27087#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27982#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28000#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28002#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27418#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27419#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27284#L1298-3 assume !(1 == ~E_7~0); 27285#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27740#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27281#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27282#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27088#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27089#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27028#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27439#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27878#L1663 assume !(0 == start_simulation_~tmp~3#1); 26914#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26865#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27563#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26809#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26810#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27148#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28067#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27171#L1644-2 [2021-11-22 15:27:20,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,119 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2021-11-22 15:27:20,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086976260] [2021-11-22 15:27:20,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086976260] [2021-11-22 15:27:20,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086976260] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894587952] [2021-11-22 15:27:20,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:20,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1771516014, now seen corresponding path program 1 times [2021-11-22 15:27:20,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94545876] [2021-11-22 15:27:20,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94545876] [2021-11-22 15:27:20,209 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94545876] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,209 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,210 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398081313] [2021-11-22 15:27:20,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,211 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:20,211 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:20,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:20,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:20,212 INFO L87 Difference]: Start difference. First operand 1476 states and 2185 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:20,260 INFO L93 Difference]: Finished difference Result 1476 states and 2184 transitions. [2021-11-22 15:27:20,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:20,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2184 transitions. [2021-11-22 15:27:20,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-11-22 15:27:20,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:20,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:20,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2184 transitions. [2021-11-22 15:27:20,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:20,298 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-22 15:27:20,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2184 transitions. [2021-11-22 15:27:20,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:20,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4796747967479675) internal successors, (2184), 1475 states have internal predecessors, (2184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-11-22 15:27:20,343 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-22 15:27:20,343 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-22 15:27:20,343 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-22 15:27:20,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2184 transitions. [2021-11-22 15:27:20,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:20,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:20,355 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,355 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,356 INFO L791 eck$LassoCheckResult]: Stem: 30727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 30737#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30738#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30503#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30504#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30373#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30285#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30008#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29643#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29644#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29692#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29693#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30621#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30622#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30660#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30108#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30109#L1090 assume !(0 == ~M_E~0); 30154#L1090-2 assume !(0 == ~T1_E~0); 30155#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30798#L1100-1 assume !(0 == ~T3_E~0); 30799#L1105-1 assume !(0 == ~T4_E~0); 29927#L1110-1 assume !(0 == ~T5_E~0); 29928#L1115-1 assume !(0 == ~T6_E~0); 30323#L1120-1 assume !(0 == ~T7_E~0); 30600#L1125-1 assume !(0 == ~T8_E~0); 31069#L1130-1 assume !(0 == ~T9_E~0); 30818#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30113#L1140-1 assume !(0 == ~T11_E~0); 30114#L1145-1 assume !(0 == ~E_1~0); 30752#L1150-1 assume !(0 == ~E_2~0); 30298#L1155-1 assume !(0 == ~E_3~0); 30299#L1160-1 assume !(0 == ~E_4~0); 30381#L1165-1 assume !(0 == ~E_5~0); 30382#L1170-1 assume !(0 == ~E_6~0); 30990#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30459#L1180-1 assume !(0 == ~E_8~0); 30460#L1185-1 assume !(0 == ~E_9~0); 30110#L1190-1 assume !(0 == ~E_10~0); 30111#L1195-1 assume !(0 == ~E_11~0); 30473#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30320#L525 assume !(1 == ~m_pc~0); 29731#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29732#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30477#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30478#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30097#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30098#L544 assume 1 == ~t1_pc~0; 30358#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30322#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30750#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29948#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 29949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30571#L563 assume !(1 == ~t2_pc~0); 30739#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29752#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29753#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30184#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30185#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30644#L582 assume 1 == ~t3_pc~0; 29892#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29893#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31041#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30999#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 29826#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29827#L601 assume !(1 == ~t4_pc~0); 30767#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30324#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30325#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30761#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 30762#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31033#L620 assume 1 == ~t5_pc~0; 29785#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29786#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30596#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30597#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31048#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31049#L639 assume !(1 == ~t6_pc~0); 30598#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30221#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30222#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31002#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30332#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30333#L658 assume 1 == ~t7_pc~0; 30599#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30526#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30631#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30632#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30104#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30105#L677 assume 1 == ~t8_pc~0; 30337#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29907#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29908#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30178#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30179#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30857#L696 assume !(1 == ~t9_pc~0); 30584#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30585#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30675#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30604#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30605#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30802#L715 assume 1 == ~t10_pc~0; 30806#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30689#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30574#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30575#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30451#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29901#L734 assume !(1 == ~t11_pc~0); 29902#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30385#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30464#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29633#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29634#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30659#L1213 assume !(1 == ~M_E~0); 30449#L1213-2 assume !(1 == ~T1_E~0); 30450#L1218-1 assume !(1 == ~T2_E~0); 29668#L1223-1 assume !(1 == ~T3_E~0); 29669#L1228-1 assume !(1 == ~T4_E~0); 30428#L1233-1 assume !(1 == ~T5_E~0); 31050#L1238-1 assume !(1 == ~T6_E~0); 30759#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30760#L1248-1 assume !(1 == ~T8_E~0); 30804#L1253-1 assume !(1 == ~T9_E~0); 30805#L1258-1 assume !(1 == ~T10_E~0); 30783#L1263-1 assume !(1 == ~T11_E~0); 30784#L1268-1 assume !(1 == ~E_1~0); 30619#L1273-1 assume !(1 == ~E_2~0); 30620#L1278-1 assume !(1 == ~E_3~0); 30219#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30220#L1288-1 assume !(1 == ~E_5~0); 30897#L1293-1 assume !(1 == ~E_6~0); 30861#L1298-1 assume !(1 == ~E_7~0); 30647#L1303-1 assume !(1 == ~E_8~0); 30230#L1308-1 assume !(1 == ~E_9~0); 30119#L1313-1 assume !(1 == ~E_10~0); 30120#L1318-1 assume !(1 == ~E_11~0); 30132#L1323-1 assume { :end_inline_reset_delta_events } true; 30133#L1644-2 [2021-11-22 15:27:20,357 INFO L793 eck$LassoCheckResult]: Loop: 30133#L1644-2 assume !false; 30700#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30701#L1065 assume !false; 30776#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31046#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29750#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30962#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30235#L906 assume !(0 != eval_~tmp~0#1); 30237#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30774#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30775#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30966#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30929#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30930#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30003#L1110-3 assume !(0 == ~T5_E~0); 30004#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30286#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30287#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30757#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31011#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30211#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29706#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29707#L1150-3 assume !(0 == ~E_2~0); 29829#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29830#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30190#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30191#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30563#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30100#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29861#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29862#L1190-3 assume !(0 == ~E_10~0); 31005#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31006#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30413#L525-36 assume !(1 == ~m_pc~0); 30414#L525-38 is_master_triggered_~__retres1~0#1 := 0; 29964#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29965#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30245#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30246#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30151#L544-36 assume 1 == ~t1_pc~0; 30152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30678#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30044#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30987#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30890#L563-36 assume 1 == ~t2_pc~0; 29946#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29702#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29703#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30765#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30426#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30427#L582-36 assume 1 == ~t3_pc~0; 30277#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30278#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30502#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30669#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30463#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30407#L601-36 assume 1 == ~t4_pc~0; 30306#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30307#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31054#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30972#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30973#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30878#L620-36 assume 1 == ~t5_pc~0; 30346#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30347#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30740#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30334#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29746#L639-36 assume 1 == ~t6_pc~0; 29747#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29783#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29784#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30024#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30603#L658-36 assume 1 == ~t7_pc~0; 29863#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29758#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30957#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29733#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 29734#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30724#L677-36 assume !(1 == ~t8_pc~0); 30528#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 30529#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30645#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31029#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30551#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30552#L696-36 assume 1 == ~t9_pc~0; 30445#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30447#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29806#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29807#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30564#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30565#L715-36 assume !(1 == ~t10_pc~0); 30535#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29631#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29632#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29607#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29608#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30012#L734-36 assume 1 == ~t11_pc~0; 30013#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29712#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30034#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29625#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29626#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30625#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30292#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30293#L1218-3 assume !(1 == ~T2_E~0); 30063#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30064#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30253#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30254#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30498#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30499#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30970#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30975#L1258-3 assume !(1 == ~T10_E~0); 30045#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30046#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30941#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30959#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30961#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30377#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30378#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30243#L1298-3 assume !(1 == ~E_7~0); 30244#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30699#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30240#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30241#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30047#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30048#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29987#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30398#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30837#L1663 assume !(0 == start_simulation_~tmp~3#1); 29880#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30601#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29824#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30520#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29768#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29769#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30107#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 31026#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30133#L1644-2 [2021-11-22 15:27:20,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2021-11-22 15:27:20,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135933880] [2021-11-22 15:27:20,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135933880] [2021-11-22 15:27:20,429 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135933880] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,429 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,429 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411681384] [2021-11-22 15:27:20,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:20,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,431 INFO L85 PathProgramCache]: Analyzing trace with hash -814695250, now seen corresponding path program 1 times [2021-11-22 15:27:20,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015734515] [2021-11-22 15:27:20,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,484 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,484 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015734515] [2021-11-22 15:27:20,484 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015734515] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,484 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,484 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,485 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823194672] [2021-11-22 15:27:20,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,485 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:20,486 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:20,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:20,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:20,487 INFO L87 Difference]: Start difference. First operand 1476 states and 2184 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:20,524 INFO L93 Difference]: Finished difference Result 1476 states and 2183 transitions. [2021-11-22 15:27:20,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:20,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2183 transitions. [2021-11-22 15:27:20,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-11-22 15:27:20,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:20,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:20,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2183 transitions. [2021-11-22 15:27:20,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:20,551 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-22 15:27:20,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2183 transitions. [2021-11-22 15:27:20,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:20,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4789972899728998) internal successors, (2183), 1475 states have internal predecessors, (2183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-11-22 15:27:20,588 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-22 15:27:20,589 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-22 15:27:20,589 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-22 15:27:20,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2183 transitions. [2021-11-22 15:27:20,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:20,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:20,600 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,600 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,600 INFO L791 eck$LassoCheckResult]: Stem: 33686#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33694#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33695#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33462#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33463#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33332#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33244#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32967#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32602#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32603#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32651#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32652#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33580#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33581#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33619#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33067#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33068#L1090 assume !(0 == ~M_E~0); 33110#L1090-2 assume !(0 == ~T1_E~0); 33111#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33756#L1100-1 assume !(0 == ~T3_E~0); 33757#L1105-1 assume !(0 == ~T4_E~0); 32885#L1110-1 assume !(0 == ~T5_E~0); 32886#L1115-1 assume !(0 == ~T6_E~0); 33282#L1120-1 assume !(0 == ~T7_E~0); 33559#L1125-1 assume !(0 == ~T8_E~0); 34028#L1130-1 assume !(0 == ~T9_E~0); 33777#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33072#L1140-1 assume !(0 == ~T11_E~0); 33073#L1145-1 assume !(0 == ~E_1~0); 33711#L1150-1 assume !(0 == ~E_2~0); 33257#L1155-1 assume !(0 == ~E_3~0); 33258#L1160-1 assume !(0 == ~E_4~0); 33340#L1165-1 assume !(0 == ~E_5~0); 33341#L1170-1 assume !(0 == ~E_6~0); 33949#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33418#L1180-1 assume !(0 == ~E_8~0); 33419#L1185-1 assume !(0 == ~E_9~0); 33069#L1190-1 assume !(0 == ~E_10~0); 33070#L1195-1 assume !(0 == ~E_11~0); 33432#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33272#L525 assume !(1 == ~m_pc~0); 32690#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32691#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33436#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33437#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33056#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33057#L544 assume 1 == ~t1_pc~0; 33317#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33281#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33709#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32907#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 32908#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33530#L563 assume !(1 == ~t2_pc~0); 33696#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32711#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32712#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33140#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33141#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L582 assume 1 == ~t3_pc~0; 32849#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32850#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34000#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 32785#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32786#L601 assume !(1 == ~t4_pc~0); 33726#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33283#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33720#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 33721#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33992#L620 assume 1 == ~t5_pc~0; 32740#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32741#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33555#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33556#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34007#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34008#L639 assume !(1 == ~t6_pc~0); 33557#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33180#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33181#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33961#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33292#L658 assume 1 == ~t7_pc~0; 33558#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33483#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33590#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33591#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33063#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33064#L677 assume 1 == ~t8_pc~0; 33294#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32866#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32867#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33137#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33138#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33816#L696 assume !(1 == ~t9_pc~0); 33541#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33542#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33631#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33563#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33564#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33761#L715 assume 1 == ~t10_pc~0; 33765#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33648#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33533#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33534#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33410#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32858#L734 assume !(1 == ~t11_pc~0); 32859#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33344#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33423#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32590#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32591#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33618#L1213 assume !(1 == ~M_E~0); 33407#L1213-2 assume !(1 == ~T1_E~0); 33408#L1218-1 assume !(1 == ~T2_E~0); 32627#L1223-1 assume !(1 == ~T3_E~0); 32628#L1228-1 assume !(1 == ~T4_E~0); 33387#L1233-1 assume !(1 == ~T5_E~0); 34009#L1238-1 assume !(1 == ~T6_E~0); 33718#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-1 assume !(1 == ~T8_E~0); 33763#L1253-1 assume !(1 == ~T9_E~0); 33764#L1258-1 assume !(1 == ~T10_E~0); 33742#L1263-1 assume !(1 == ~T11_E~0); 33743#L1268-1 assume !(1 == ~E_1~0); 33578#L1273-1 assume !(1 == ~E_2~0); 33579#L1278-1 assume !(1 == ~E_3~0); 33178#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33179#L1288-1 assume !(1 == ~E_5~0); 33856#L1293-1 assume !(1 == ~E_6~0); 33820#L1298-1 assume !(1 == ~E_7~0); 33606#L1303-1 assume !(1 == ~E_8~0); 33189#L1308-1 assume !(1 == ~E_9~0); 33078#L1313-1 assume !(1 == ~E_10~0); 33079#L1318-1 assume !(1 == ~E_11~0); 33088#L1323-1 assume { :end_inline_reset_delta_events } true; 33089#L1644-2 [2021-11-22 15:27:20,601 INFO L793 eck$LassoCheckResult]: Loop: 33089#L1644-2 assume !false; 33659#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33660#L1065 assume !false; 33735#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34005#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32709#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33921#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33194#L906 assume !(0 != eval_~tmp~0#1); 33196#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33732#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33733#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33873#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33925#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33888#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33889#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32962#L1110-3 assume !(0 == ~T5_E~0); 32963#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33245#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33246#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33716#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33970#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33168#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32663#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32664#L1150-3 assume !(0 == ~E_2~0); 32787#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32788#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33149#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33150#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33522#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33059#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32817#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32818#L1190-3 assume !(0 == ~E_10~0); 33964#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33965#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33372#L525-36 assume !(1 == ~m_pc~0); 33373#L525-38 is_master_triggered_~__retres1~0#1 := 0; 32918#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32919#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33204#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33205#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33113#L544-36 assume 1 == ~t1_pc~0; 33114#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33637#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33002#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33003#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33946#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33849#L563-36 assume 1 == ~t2_pc~0; 32905#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32661#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32662#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33724#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33385#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33386#L582-36 assume 1 == ~t3_pc~0; 33236#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33237#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33461#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33628#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33422#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33366#L601-36 assume 1 == ~t4_pc~0; 33265#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33266#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34013#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33931#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33932#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33837#L620-36 assume 1 == ~t5_pc~0; 33307#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33308#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33699#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33293#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32927#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32705#L639-36 assume 1 == ~t6_pc~0; 32706#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32745#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32746#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32985#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32986#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33562#L658-36 assume 1 == ~t7_pc~0; 32824#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32717#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32692#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 32693#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33683#L677-36 assume 1 == ~t8_pc~0; 33861#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33488#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33604#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33988#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33510#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33511#L696-36 assume 1 == ~t9_pc~0; 33404#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33406#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32765#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32766#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33523#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33524#L715-36 assume !(1 == ~t10_pc~0); 33494#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 32592#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32593#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32566#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32567#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32971#L734-36 assume 1 == ~t11_pc~0; 32972#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32993#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32584#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32585#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33584#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33253#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33254#L1218-3 assume !(1 == ~T2_E~0); 33022#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33023#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33212#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33213#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33457#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33458#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33930#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33935#L1258-3 assume !(1 == ~T10_E~0); 33004#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33005#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33900#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33918#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33920#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33336#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33337#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33202#L1298-3 assume !(1 == ~E_7~0); 33203#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33658#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33199#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33200#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33006#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33007#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32946#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33357#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33796#L1663 assume !(0 == start_simulation_~tmp~3#1); 32839#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33560#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32783#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33481#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32727#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32728#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33066#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33985#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33089#L1644-2 [2021-11-22 15:27:20,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,602 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2021-11-22 15:27:20,602 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094566393] [2021-11-22 15:27:20,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,603 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094566393] [2021-11-22 15:27:20,657 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094566393] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,659 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:20,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535655001] [2021-11-22 15:27:20,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:20,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1091788943, now seen corresponding path program 1 times [2021-11-22 15:27:20,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032798681] [2021-11-22 15:27:20,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032798681] [2021-11-22 15:27:20,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032798681] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,718 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,719 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998469973] [2021-11-22 15:27:20,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:20,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:20,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:20,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:20,721 INFO L87 Difference]: Start difference. First operand 1476 states and 2183 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:20,773 INFO L93 Difference]: Finished difference Result 1476 states and 2178 transitions. [2021-11-22 15:27:20,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:20,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2178 transitions. [2021-11-22 15:27:20,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2178 transitions. [2021-11-22 15:27:20,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-22 15:27:20,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-22 15:27:20,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2178 transitions. [2021-11-22 15:27:20,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:20,806 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-22 15:27:20,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2178 transitions. [2021-11-22 15:27:20,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-22 15:27:20,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.475609756097561) internal successors, (2178), 1475 states have internal predecessors, (2178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:20,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2178 transitions. [2021-11-22 15:27:20,849 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-22 15:27:20,849 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-22 15:27:20,849 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-22 15:27:20,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2178 transitions. [2021-11-22 15:27:20,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-22 15:27:20,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:20,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:20,860 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:20,861 INFO L791 eck$LassoCheckResult]: Stem: 36645#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36655#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36656#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36421#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36422#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36291#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36203#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35926#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35561#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35562#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35610#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35611#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36539#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36540#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36578#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36026#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36027#L1090 assume !(0 == ~M_E~0); 36069#L1090-2 assume !(0 == ~T1_E~0); 36070#L1095-1 assume !(0 == ~T2_E~0); 36716#L1100-1 assume !(0 == ~T3_E~0); 36717#L1105-1 assume !(0 == ~T4_E~0); 35845#L1110-1 assume !(0 == ~T5_E~0); 35846#L1115-1 assume !(0 == ~T6_E~0); 36241#L1120-1 assume !(0 == ~T7_E~0); 36518#L1125-1 assume !(0 == ~T8_E~0); 36987#L1130-1 assume !(0 == ~T9_E~0); 36736#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36031#L1140-1 assume !(0 == ~T11_E~0); 36032#L1145-1 assume !(0 == ~E_1~0); 36670#L1150-1 assume !(0 == ~E_2~0); 36216#L1155-1 assume !(0 == ~E_3~0); 36217#L1160-1 assume !(0 == ~E_4~0); 36299#L1165-1 assume !(0 == ~E_5~0); 36300#L1170-1 assume !(0 == ~E_6~0); 36908#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36377#L1180-1 assume !(0 == ~E_8~0); 36378#L1185-1 assume !(0 == ~E_9~0); 36028#L1190-1 assume !(0 == ~E_10~0); 36029#L1195-1 assume !(0 == ~E_11~0); 36391#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36238#L525 assume !(1 == ~m_pc~0); 35649#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35650#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36395#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36396#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36015#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36016#L544 assume 1 == ~t1_pc~0; 36276#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36240#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36668#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35866#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 35867#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36489#L563 assume !(1 == ~t2_pc~0); 36657#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35670#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35671#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36099#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36100#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36562#L582 assume 1 == ~t3_pc~0; 35810#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35811#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36959#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36917#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 35744#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35745#L601 assume !(1 == ~t4_pc~0); 36685#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36242#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36243#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36679#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36680#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36951#L620 assume 1 == ~t5_pc~0; 35701#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35702#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36514#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36515#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 36966#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36967#L639 assume !(1 == ~t6_pc~0); 36516#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36139#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36140#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36920#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36250#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36251#L658 assume 1 == ~t7_pc~0; 36517#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36444#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36549#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36022#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36023#L677 assume 1 == ~t8_pc~0; 36255#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35825#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35826#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36096#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36097#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36775#L696 assume !(1 == ~t9_pc~0); 36502#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36503#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36590#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36522#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36523#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36720#L715 assume 1 == ~t10_pc~0; 36724#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36607#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36492#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36493#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36369#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35819#L734 assume !(1 == ~t11_pc~0); 35820#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36303#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36382#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35551#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35552#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36577#L1213 assume !(1 == ~M_E~0); 36367#L1213-2 assume !(1 == ~T1_E~0); 36368#L1218-1 assume !(1 == ~T2_E~0); 35586#L1223-1 assume !(1 == ~T3_E~0); 35587#L1228-1 assume !(1 == ~T4_E~0); 36346#L1233-1 assume !(1 == ~T5_E~0); 36968#L1238-1 assume !(1 == ~T6_E~0); 36677#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36678#L1248-1 assume !(1 == ~T8_E~0); 36722#L1253-1 assume !(1 == ~T9_E~0); 36723#L1258-1 assume !(1 == ~T10_E~0); 36701#L1263-1 assume !(1 == ~T11_E~0); 36702#L1268-1 assume !(1 == ~E_1~0); 36537#L1273-1 assume !(1 == ~E_2~0); 36538#L1278-1 assume !(1 == ~E_3~0); 36137#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36138#L1288-1 assume !(1 == ~E_5~0); 36815#L1293-1 assume !(1 == ~E_6~0); 36779#L1298-1 assume !(1 == ~E_7~0); 36565#L1303-1 assume !(1 == ~E_8~0); 36148#L1308-1 assume !(1 == ~E_9~0); 36037#L1313-1 assume !(1 == ~E_10~0); 36038#L1318-1 assume !(1 == ~E_11~0); 36050#L1323-1 assume { :end_inline_reset_delta_events } true; 36051#L1644-2 [2021-11-22 15:27:20,862 INFO L793 eck$LassoCheckResult]: Loop: 36051#L1644-2 assume !false; 36618#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36619#L1065 assume !false; 36694#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36964#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35668#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36880#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36153#L906 assume !(0 != eval_~tmp~0#1); 36155#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36692#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36693#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36832#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36884#L1095-3 assume !(0 == ~T2_E~0); 36847#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36848#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35921#L1110-3 assume !(0 == ~T5_E~0); 35922#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36204#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36205#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36675#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36929#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36129#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35624#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35625#L1150-3 assume !(0 == ~E_2~0); 35747#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35748#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36108#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36109#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36481#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36018#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35777#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35778#L1190-3 assume !(0 == ~E_10~0); 36923#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36924#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36331#L525-36 assume !(1 == ~m_pc~0); 36332#L525-38 is_master_triggered_~__retres1~0#1 := 0; 35882#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35883#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36164#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36165#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36072#L544-36 assume 1 == ~t1_pc~0; 36073#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36596#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35967#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35968#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36906#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36808#L563-36 assume 1 == ~t2_pc~0; 35864#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35620#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35621#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36683#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36344#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36345#L582-36 assume 1 == ~t3_pc~0; 36195#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36196#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36420#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36587#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36381#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36322#L601-36 assume 1 == ~t4_pc~0; 36224#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36225#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36972#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36890#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36891#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36794#L620-36 assume 1 == ~t5_pc~0; 36264#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36265#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36658#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36252#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35886#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35664#L639-36 assume 1 == ~t6_pc~0; 35665#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35699#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35700#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35942#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35943#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36521#L658-36 assume 1 == ~t7_pc~0; 35781#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35676#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36875#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35651#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 35652#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36642#L677-36 assume 1 == ~t8_pc~0; 36820#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36447#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36563#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36469#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36470#L696-36 assume 1 == ~t9_pc~0; 36363#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36365#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35721#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35722#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36482#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36483#L715-36 assume !(1 == ~t10_pc~0); 36453#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35549#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35550#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35525#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35526#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35930#L734-36 assume 1 == ~t11_pc~0; 35931#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35630#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35952#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35543#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35544#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36543#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36210#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36211#L1218-3 assume !(1 == ~T2_E~0); 35981#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35982#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36171#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36172#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36416#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36417#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36888#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36893#L1258-3 assume !(1 == ~T10_E~0); 35961#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35962#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36859#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36877#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36879#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36295#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36296#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36161#L1298-3 assume !(1 == ~E_7~0); 36162#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36617#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36158#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36159#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35963#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35964#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35905#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36316#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36755#L1663 assume !(0 == start_simulation_~tmp~3#1); 35793#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36519#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35742#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36438#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35683#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35684#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36025#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36944#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36051#L1644-2 [2021-11-22 15:27:20,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,863 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2021-11-22 15:27:20,863 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199622799] [2021-11-22 15:27:20,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,864 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199622799] [2021-11-22 15:27:20,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199622799] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,913 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,914 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945717257] [2021-11-22 15:27:20,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:20,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:20,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1766949069, now seen corresponding path program 1 times [2021-11-22 15:27:20,916 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:20,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932275584] [2021-11-22 15:27:20,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:20,917 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:20,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:20,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:20,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:20,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932275584] [2021-11-22 15:27:20,968 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932275584] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:20,968 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:20,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:20,968 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410264633] [2021-11-22 15:27:20,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:20,969 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:20,970 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:20,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:27:20,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:27:20,971 INFO L87 Difference]: Start difference. First operand 1476 states and 2178 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:21,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:21,197 INFO L93 Difference]: Finished difference Result 2825 states and 4162 transitions. [2021-11-22 15:27:21,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 15:27:21,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2825 states and 4162 transitions. [2021-11-22 15:27:21,224 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2021-11-22 15:27:21,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2825 states to 2825 states and 4162 transitions. [2021-11-22 15:27:21,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2825 [2021-11-22 15:27:21,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2825 [2021-11-22 15:27:21,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2825 states and 4162 transitions. [2021-11-22 15:27:21,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:21,269 INFO L681 BuchiCegarLoop]: Abstraction has 2825 states and 4162 transitions. [2021-11-22 15:27:21,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2825 states and 4162 transitions. [2021-11-22 15:27:21,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2825 to 2825. [2021-11-22 15:27:21,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2825 states, 2825 states have (on average 1.473274336283186) internal successors, (4162), 2824 states have internal predecessors, (4162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:21,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2825 states to 2825 states and 4162 transitions. [2021-11-22 15:27:21,378 INFO L704 BuchiCegarLoop]: Abstraction has 2825 states and 4162 transitions. [2021-11-22 15:27:21,378 INFO L587 BuchiCegarLoop]: Abstraction has 2825 states and 4162 transitions. [2021-11-22 15:27:21,378 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-22 15:27:21,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2825 states and 4162 transitions. [2021-11-22 15:27:21,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2021-11-22 15:27:21,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:21,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:21,397 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:21,397 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:21,398 INFO L791 eck$LassoCheckResult]: Stem: 40976#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40977#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40984#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40985#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40740#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 40741#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40608#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40516#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40237#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39872#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39873#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39921#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39922#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40864#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40865#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40904#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40338#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40339#L1090 assume !(0 == ~M_E~0); 40381#L1090-2 assume !(0 == ~T1_E~0); 40382#L1095-1 assume !(0 == ~T2_E~0); 41047#L1100-1 assume !(0 == ~T3_E~0); 41048#L1105-1 assume !(0 == ~T4_E~0); 40155#L1110-1 assume !(0 == ~T5_E~0); 40156#L1115-1 assume !(0 == ~T6_E~0); 40555#L1120-1 assume !(0 == ~T7_E~0); 40842#L1125-1 assume !(0 == ~T8_E~0); 41344#L1130-1 assume !(0 == ~T9_E~0); 41072#L1135-1 assume !(0 == ~T10_E~0); 40343#L1140-1 assume !(0 == ~T11_E~0); 40344#L1145-1 assume !(0 == ~E_1~0); 41001#L1150-1 assume !(0 == ~E_2~0); 40530#L1155-1 assume !(0 == ~E_3~0); 40531#L1160-1 assume !(0 == ~E_4~0); 40616#L1165-1 assume !(0 == ~E_5~0); 40617#L1170-1 assume !(0 == ~E_6~0); 41252#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 40696#L1180-1 assume !(0 == ~E_8~0); 40697#L1185-1 assume !(0 == ~E_9~0); 40340#L1190-1 assume !(0 == ~E_10~0); 40341#L1195-1 assume !(0 == ~E_11~0); 40710#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40545#L525 assume !(1 == ~m_pc~0); 39960#L525-2 is_master_triggered_~__retres1~0#1 := 0; 39961#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40714#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40715#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40326#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40327#L544 assume 1 == ~t1_pc~0; 40593#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40554#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40999#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40177#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40178#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40813#L563 assume !(1 == ~t2_pc~0); 40986#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39981#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39982#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40411#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40412#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40887#L582 assume 1 == ~t3_pc~0; 40119#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40120#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41305#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41261#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40055#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40056#L601 assume !(1 == ~t4_pc~0); 41016#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40556#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40557#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41010#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 41011#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41297#L620 assume 1 == ~t5_pc~0; 40010#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40011#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40838#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40839#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41313#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41314#L639 assume !(1 == ~t6_pc~0); 40840#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40452#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40453#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41264#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40564#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40565#L658 assume 1 == ~t7_pc~0; 40841#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40763#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40874#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40875#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40333#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40334#L677 assume 1 == ~t8_pc~0; 40567#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40136#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40137#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40408#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40409#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41113#L696 assume !(1 == ~t9_pc~0); 40824#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 40825#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40916#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40846#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40847#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41052#L715 assume 1 == ~t10_pc~0; 41058#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40934#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40816#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40817#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40688#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40128#L734 assume !(1 == ~t11_pc~0); 40129#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40620#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40701#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39860#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 39861#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40903#L1213 assume !(1 == ~M_E~0); 40684#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40685#L1218-1 assume !(1 == ~T2_E~0); 39897#L1223-1 assume !(1 == ~T3_E~0); 39898#L1228-1 assume !(1 == ~T4_E~0); 40664#L1233-1 assume !(1 == ~T5_E~0); 41315#L1238-1 assume !(1 == ~T6_E~0); 41008#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41009#L1248-1 assume !(1 == ~T8_E~0); 41056#L1253-1 assume !(1 == ~T9_E~0); 41057#L1258-1 assume !(1 == ~T10_E~0); 41033#L1263-1 assume !(1 == ~T11_E~0); 41034#L1268-1 assume !(1 == ~E_1~0); 40862#L1273-1 assume !(1 == ~E_2~0); 40863#L1278-1 assume !(1 == ~E_3~0); 40450#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40451#L1288-1 assume !(1 == ~E_5~0); 41153#L1293-1 assume !(1 == ~E_6~0); 41117#L1298-1 assume !(1 == ~E_7~0); 40890#L1303-1 assume !(1 == ~E_8~0); 40891#L1308-1 assume !(1 == ~E_9~0); 41396#L1313-1 assume !(1 == ~E_10~0); 41395#L1318-1 assume !(1 == ~E_11~0); 41394#L1323-1 assume { :end_inline_reset_delta_events } true; 41392#L1644-2 [2021-11-22 15:27:21,398 INFO L793 eck$LassoCheckResult]: Loop: 41392#L1644-2 assume !false; 41391#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41387#L1065 assume !false; 41386#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41335#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39979#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41220#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40466#L906 assume !(0 != eval_~tmp~0#1); 40468#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41022#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41023#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41170#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41367#L1095-3 assume !(0 == ~T2_E~0); 41768#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41767#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41766#L1110-3 assume !(0 == ~T5_E~0); 41765#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41764#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41763#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41762#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41761#L1135-3 assume !(0 == ~T10_E~0); 41760#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41759#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41758#L1150-3 assume !(0 == ~E_2~0); 41757#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41756#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41755#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41754#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41753#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41752#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41751#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41750#L1190-3 assume !(0 == ~E_10~0); 41749#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41748#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41747#L525-36 assume 1 == ~m_pc~0; 41745#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41744#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41743#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41742#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41741#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41740#L544-36 assume 1 == ~t1_pc~0; 41053#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40923#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40272#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40273#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41249#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41146#L563-36 assume !(1 == ~t2_pc~0); 40176#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 39931#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39932#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41014#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40662#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40663#L582-36 assume 1 == ~t3_pc~0; 40508#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40509#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40739#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40913#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40700#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40643#L601-36 assume 1 == ~t4_pc~0; 40538#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40539#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41322#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41231#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41232#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41134#L620-36 assume 1 == ~t5_pc~0; 40582#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40583#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40989#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40566#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40197#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39975#L639-36 assume 1 == ~t6_pc~0; 39976#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40015#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40016#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40255#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40256#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40845#L658-36 assume !(1 == ~t7_pc~0); 39986#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 39987#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41215#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39962#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 39963#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40973#L677-36 assume 1 == ~t8_pc~0; 41158#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40768#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40888#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41293#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40790#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40791#L696-36 assume 1 == ~t9_pc~0; 40681#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40683#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40035#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40036#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40805#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40806#L715-36 assume 1 == ~t10_pc~0; 41317#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41678#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41677#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41676#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41675#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41674#L734-36 assume !(1 == ~t11_pc~0); 41672#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 41671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41670#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41669#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41668#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41667#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41666#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40526#L1218-3 assume !(1 == ~T2_E~0); 41665#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41664#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41663#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41662#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41661#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41660#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41659#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41658#L1258-3 assume !(1 == ~T10_E~0); 41236#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41657#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41656#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41655#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41654#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41653#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41652#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41651#L1298-3 assume !(1 == ~E_7~0); 41650#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41649#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41648#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41647#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41646#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41645#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40633#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40634#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 41358#L1663 assume !(0 == start_simulation_~tmp~3#1); 40109#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40843#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40053#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40969#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 39997#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39998#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41397#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41393#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 41392#L1644-2 [2021-11-22 15:27:21,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:21,399 INFO L85 PathProgramCache]: Analyzing trace with hash 1537128352, now seen corresponding path program 1 times [2021-11-22 15:27:21,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:21,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562801964] [2021-11-22 15:27:21,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:21,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:21,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:21,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:21,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:21,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562801964] [2021-11-22 15:27:21,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562801964] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:21,468 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:21,469 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:21,469 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144664441] [2021-11-22 15:27:21,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:21,470 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:21,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:21,470 INFO L85 PathProgramCache]: Analyzing trace with hash 47538602, now seen corresponding path program 1 times [2021-11-22 15:27:21,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:21,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923689056] [2021-11-22 15:27:21,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:21,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:21,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:21,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:21,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:21,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923689056] [2021-11-22 15:27:21,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923689056] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:21,528 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:21,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:21,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852822944] [2021-11-22 15:27:21,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:21,530 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:21,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:21,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:21,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:21,531 INFO L87 Difference]: Start difference. First operand 2825 states and 4162 transitions. cyclomatic complexity: 1339 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:21,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:21,631 INFO L93 Difference]: Finished difference Result 2825 states and 4128 transitions. [2021-11-22 15:27:21,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:21,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2825 states and 4128 transitions. [2021-11-22 15:27:21,652 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2021-11-22 15:27:21,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2825 states to 2825 states and 4128 transitions. [2021-11-22 15:27:21,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2825 [2021-11-22 15:27:21,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2825 [2021-11-22 15:27:21,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2825 states and 4128 transitions. [2021-11-22 15:27:21,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:21,679 INFO L681 BuchiCegarLoop]: Abstraction has 2825 states and 4128 transitions. [2021-11-22 15:27:21,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2825 states and 4128 transitions. [2021-11-22 15:27:21,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2825 to 2825. [2021-11-22 15:27:21,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2825 states, 2825 states have (on average 1.4612389380530972) internal successors, (4128), 2824 states have internal predecessors, (4128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:21,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2825 states to 2825 states and 4128 transitions. [2021-11-22 15:27:21,764 INFO L704 BuchiCegarLoop]: Abstraction has 2825 states and 4128 transitions. [2021-11-22 15:27:21,764 INFO L587 BuchiCegarLoop]: Abstraction has 2825 states and 4128 transitions. [2021-11-22 15:27:21,764 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-22 15:27:21,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2825 states and 4128 transitions. [2021-11-22 15:27:21,779 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2021-11-22 15:27:21,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:21,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:21,782 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:21,782 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:21,783 INFO L791 eck$LassoCheckResult]: Stem: 46623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 46624#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 46633#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46634#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46392#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 46393#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46262#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46173#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45895#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45529#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45530#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45578#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45579#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46513#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46514#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46553#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45996#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45997#L1090 assume !(0 == ~M_E~0); 46039#L1090-2 assume !(0 == ~T1_E~0); 46040#L1095-1 assume !(0 == ~T2_E~0); 46697#L1100-1 assume !(0 == ~T3_E~0); 46698#L1105-1 assume !(0 == ~T4_E~0); 45812#L1110-1 assume !(0 == ~T5_E~0); 45813#L1115-1 assume !(0 == ~T6_E~0); 46211#L1120-1 assume !(0 == ~T7_E~0); 46491#L1125-1 assume !(0 == ~T8_E~0); 46993#L1130-1 assume !(0 == ~T9_E~0); 46719#L1135-1 assume !(0 == ~T10_E~0); 46001#L1140-1 assume !(0 == ~T11_E~0); 46002#L1145-1 assume !(0 == ~E_1~0); 46650#L1150-1 assume !(0 == ~E_2~0); 46186#L1155-1 assume !(0 == ~E_3~0); 46187#L1160-1 assume !(0 == ~E_4~0); 46270#L1165-1 assume !(0 == ~E_5~0); 46271#L1170-1 assume !(0 == ~E_6~0); 46900#L1175-1 assume !(0 == ~E_7~0); 46348#L1180-1 assume !(0 == ~E_8~0); 46349#L1185-1 assume !(0 == ~E_9~0); 45998#L1190-1 assume !(0 == ~E_10~0); 45999#L1195-1 assume !(0 == ~E_11~0); 46362#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46203#L525 assume !(1 == ~m_pc~0); 45617#L525-2 is_master_triggered_~__retres1~0#1 := 0; 45618#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46366#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46367#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45984#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45985#L544 assume 1 == ~t1_pc~0; 46247#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46210#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46648#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45834#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 45835#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46462#L563 assume !(1 == ~t2_pc~0); 46635#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45638#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45639#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46069#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 46070#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46536#L582 assume 1 == ~t3_pc~0; 45776#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45777#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46956#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46909#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 45712#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45713#L601 assume !(1 == ~t4_pc~0); 46665#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46212#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46213#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46659#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 46660#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46947#L620 assume 1 == ~t5_pc~0; 45667#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45668#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46487#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46488#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 46965#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46966#L639 assume !(1 == ~t6_pc~0); 46489#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46109#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46110#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46912#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 46220#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46221#L658 assume !(1 == ~t7_pc~0); 46412#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 46413#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46523#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46524#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 45991#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45992#L677 assume 1 == ~t8_pc~0; 46224#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45793#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45794#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46066#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 46067#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46759#L696 assume !(1 == ~t9_pc~0); 46473#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 46474#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46565#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46495#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46496#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46702#L715 assume 1 == ~t10_pc~0; 46706#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46582#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46465#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46466#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 46340#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45785#L734 assume !(1 == ~t11_pc~0); 45786#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 46274#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46353#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45519#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 45520#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46552#L1213 assume !(1 == ~M_E~0); 46336#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46337#L1218-1 assume !(1 == ~T2_E~0); 45554#L1223-1 assume !(1 == ~T3_E~0); 45555#L1228-1 assume !(1 == ~T4_E~0); 46316#L1233-1 assume !(1 == ~T5_E~0); 46967#L1238-1 assume !(1 == ~T6_E~0); 46657#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46658#L1248-1 assume !(1 == ~T8_E~0); 46704#L1253-1 assume !(1 == ~T9_E~0); 46705#L1258-1 assume !(1 == ~T10_E~0); 46683#L1263-1 assume !(1 == ~T11_E~0); 46684#L1268-1 assume !(1 == ~E_1~0); 46511#L1273-1 assume !(1 == ~E_2~0); 46512#L1278-1 assume !(1 == ~E_3~0); 46107#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46108#L1288-1 assume !(1 == ~E_5~0); 46799#L1293-1 assume !(1 == ~E_6~0); 46763#L1298-1 assume !(1 == ~E_7~0); 46539#L1303-1 assume !(1 == ~E_8~0); 46540#L1308-1 assume !(1 == ~E_9~0); 47043#L1313-1 assume !(1 == ~E_10~0); 47042#L1318-1 assume !(1 == ~E_11~0); 47041#L1323-1 assume { :end_inline_reset_delta_events } true; 47039#L1644-2 [2021-11-22 15:27:21,783 INFO L793 eck$LassoCheckResult]: Loop: 47039#L1644-2 assume !false; 47038#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47035#L1065 assume !false; 47034#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46987#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 45636#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46869#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46123#L906 assume !(0 != eval_~tmp~0#1); 46125#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46672#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46673#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46818#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47000#L1095-3 assume !(0 == ~T2_E~0); 46834#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46835#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45890#L1110-3 assume !(0 == ~T5_E~0); 45891#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46174#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46175#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46655#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46923#L1135-3 assume !(0 == ~T10_E~0); 46097#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45590#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45591#L1150-3 assume !(0 == ~E_2~0); 45715#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45716#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46078#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46079#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46453#L1175-3 assume !(0 == ~E_7~0); 45987#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45744#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45745#L1190-3 assume !(0 == ~E_10~0); 46915#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46916#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46301#L525-36 assume !(1 == ~m_pc~0); 46302#L525-38 is_master_triggered_~__retres1~0#1 := 0; 45845#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45846#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46133#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46134#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46042#L544-36 assume 1 == ~t1_pc~0; 46043#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46571#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45936#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45937#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46898#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46792#L563-36 assume 1 == ~t2_pc~0; 45832#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45588#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45589#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46663#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46314#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46315#L582-36 assume 1 == ~t3_pc~0; 46165#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46166#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46391#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46562#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46352#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46295#L601-36 assume 1 == ~t4_pc~0; 46194#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46195#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46975#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46881#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46882#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46780#L620-36 assume !(1 == ~t5_pc~0); 46240#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 46239#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46640#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47409#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45854#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45855#L639-36 assume 1 == ~t6_pc~0; 46626#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45672#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45673#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45913#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45914#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46494#L658-36 assume !(1 == ~t7_pc~0); 45643#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 45644#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46864#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45619#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 45620#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46620#L677-36 assume !(1 == ~t8_pc~0); 46417#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 46418#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46537#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46943#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46440#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46441#L696-36 assume 1 == ~t9_pc~0; 46333#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46335#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45689#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45690#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46454#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46455#L715-36 assume !(1 == ~t10_pc~0); 46424#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 45517#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45518#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45493#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45494#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45896#L734-36 assume 1 == ~t11_pc~0; 45897#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45595#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45921#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45511#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45512#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46517#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46180#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46181#L1218-3 assume !(1 == ~T2_E~0); 45950#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45951#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46141#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46142#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46387#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46388#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46879#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46884#L1258-3 assume !(1 == ~T10_E~0); 45930#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45931#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46846#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46866#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46867#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46266#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46267#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46130#L1298-3 assume !(1 == ~E_7~0); 46131#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46592#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46128#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46129#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45932#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 45933#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 45874#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46287#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 46739#L1663 assume !(0 == start_simulation_~tmp~3#1); 45759#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46492#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 45710#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46409#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 45651#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45652#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47044#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 47040#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 47039#L1644-2 [2021-11-22 15:27:21,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:21,785 INFO L85 PathProgramCache]: Analyzing trace with hash -226779075, now seen corresponding path program 1 times [2021-11-22 15:27:21,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:21,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212052269] [2021-11-22 15:27:21,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:21,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:21,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:21,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:21,847 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:21,847 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212052269] [2021-11-22 15:27:21,847 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212052269] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:21,847 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:21,847 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:21,848 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186852199] [2021-11-22 15:27:21,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:21,848 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:21,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:21,849 INFO L85 PathProgramCache]: Analyzing trace with hash 1651782310, now seen corresponding path program 1 times [2021-11-22 15:27:21,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:21,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247162645] [2021-11-22 15:27:21,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:21,850 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:21,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:21,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:21,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:21,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247162645] [2021-11-22 15:27:21,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247162645] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:21,901 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:21,902 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:21,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34303516] [2021-11-22 15:27:21,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:21,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:21,903 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:21,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-22 15:27:21,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-22 15:27:21,904 INFO L87 Difference]: Start difference. First operand 2825 states and 4128 transitions. cyclomatic complexity: 1305 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:22,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:22,466 INFO L93 Difference]: Finished difference Result 8150 states and 11855 transitions. [2021-11-22 15:27:22,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-22 15:27:22,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8150 states and 11855 transitions. [2021-11-22 15:27:22,526 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7728 [2021-11-22 15:27:22,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8150 states to 8150 states and 11855 transitions. [2021-11-22 15:27:22,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8150 [2021-11-22 15:27:22,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8150 [2021-11-22 15:27:22,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8150 states and 11855 transitions. [2021-11-22 15:27:22,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:22,601 INFO L681 BuchiCegarLoop]: Abstraction has 8150 states and 11855 transitions. [2021-11-22 15:27:22,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8150 states and 11855 transitions. [2021-11-22 15:27:22,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8150 to 2906. [2021-11-22 15:27:22,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2906 states, 2906 states have (on average 1.4483826565726083) internal successors, (4209), 2905 states have internal predecessors, (4209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:22,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2906 states to 2906 states and 4209 transitions. [2021-11-22 15:27:22,712 INFO L704 BuchiCegarLoop]: Abstraction has 2906 states and 4209 transitions. [2021-11-22 15:27:22,713 INFO L587 BuchiCegarLoop]: Abstraction has 2906 states and 4209 transitions. [2021-11-22 15:27:22,713 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-22 15:27:22,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2906 states and 4209 transitions. [2021-11-22 15:27:22,731 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2732 [2021-11-22 15:27:22,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:22,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:22,734 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:22,735 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:22,735 INFO L791 eck$LassoCheckResult]: Stem: 57653#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 57654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 57663#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57664#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57403#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 57404#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57262#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57172#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56887#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56519#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56520#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56568#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56569#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 57534#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 57535#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57579#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56991#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56992#L1090 assume !(0 == ~M_E~0); 57038#L1090-2 assume !(0 == ~T1_E~0); 57039#L1095-1 assume !(0 == ~T2_E~0); 57729#L1100-1 assume !(0 == ~T3_E~0); 57730#L1105-1 assume !(0 == ~T4_E~0); 56805#L1110-1 assume !(0 == ~T5_E~0); 56806#L1115-1 assume !(0 == ~T6_E~0); 57213#L1120-1 assume !(0 == ~T7_E~0); 57510#L1125-1 assume !(0 == ~T8_E~0); 58107#L1130-1 assume !(0 == ~T9_E~0); 57749#L1135-1 assume !(0 == ~T10_E~0); 56998#L1140-1 assume !(0 == ~T11_E~0); 56999#L1145-1 assume !(0 == ~E_1~0); 57679#L1150-1 assume !(0 == ~E_2~0); 57185#L1155-1 assume !(0 == ~E_3~0); 57186#L1160-1 assume !(0 == ~E_4~0); 57272#L1165-1 assume !(0 == ~E_5~0); 57273#L1170-1 assume !(0 == ~E_6~0); 57968#L1175-1 assume !(0 == ~E_7~0); 57355#L1180-1 assume !(0 == ~E_8~0); 57356#L1185-1 assume !(0 == ~E_9~0); 56993#L1190-1 assume !(0 == ~E_10~0); 56994#L1195-1 assume !(0 == ~E_11~0); 57369#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57207#L525 assume !(1 == ~m_pc~0); 56608#L525-2 is_master_triggered_~__retres1~0#1 := 0; 56609#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57923#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57805#L1350 assume !(0 != activate_threads_~tmp~1#1); 56981#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56982#L544 assume 1 == ~t1_pc~0; 57245#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57209#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57676#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56826#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 56827#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57478#L563 assume !(1 == ~t2_pc~0); 57665#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56630#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56631#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57067#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 57068#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57555#L582 assume 1 == ~t3_pc~0; 56770#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56771#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58045#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57978#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 56704#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56705#L601 assume !(1 == ~t4_pc~0); 57695#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 57214#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57215#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57689#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 57690#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58033#L620 assume 1 == ~t5_pc~0; 56663#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56664#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57506#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57507#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 58066#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58067#L639 assume !(1 == ~t6_pc~0); 57508#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 57105#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57106#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57980#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 57219#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57220#L658 assume !(1 == ~t7_pc~0); 57427#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 57428#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57542#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57543#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 56987#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56988#L677 assume 1 == ~t8_pc~0; 57224#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56788#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56789#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57061#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 57062#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57793#L696 assume !(1 == ~t9_pc~0); 57494#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 57495#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57587#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57516#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57517#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57733#L715 assume 1 == ~t10_pc~0; 57737#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 57604#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57481#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57482#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 57345#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56779#L734 assume !(1 == ~t11_pc~0); 56780#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 57279#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57360#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56509#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 56510#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57571#L1213 assume !(1 == ~M_E~0); 57342#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57343#L1218-1 assume !(1 == ~T2_E~0); 58650#L1223-1 assume !(1 == ~T3_E~0); 58649#L1228-1 assume !(1 == ~T4_E~0); 58648#L1233-1 assume !(1 == ~T5_E~0); 58647#L1238-1 assume !(1 == ~T6_E~0); 58646#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58645#L1248-1 assume !(1 == ~T8_E~0); 57735#L1253-1 assume !(1 == ~T9_E~0); 57736#L1258-1 assume !(1 == ~T10_E~0); 57713#L1263-1 assume !(1 == ~T11_E~0); 57714#L1268-1 assume !(1 == ~E_1~0); 57530#L1273-1 assume !(1 == ~E_2~0); 57531#L1278-1 assume !(1 == ~E_3~0); 57103#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 57104#L1288-1 assume !(1 == ~E_5~0); 57842#L1293-1 assume !(1 == ~E_6~0); 57843#L1298-1 assume !(1 == ~E_7~0); 57558#L1303-1 assume !(1 == ~E_8~0); 57559#L1308-1 assume !(1 == ~E_9~0); 58253#L1313-1 assume !(1 == ~E_10~0); 58116#L1318-1 assume !(1 == ~E_11~0); 57015#L1323-1 assume { :end_inline_reset_delta_events } true; 57016#L1644-2 [2021-11-22 15:27:22,736 INFO L793 eck$LassoCheckResult]: Loop: 57016#L1644-2 assume !false; 57618#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57619#L1065 assume !false; 58063#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 58064#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56628#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 57983#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57984#L906 assume !(0 != eval_~tmp~0#1); 57795#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57796#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57865#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57866#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58181#L1095-3 assume !(0 == ~T2_E~0); 59386#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59385#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59384#L1110-3 assume !(0 == ~T5_E~0); 59383#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59382#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59381#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59380#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 59379#L1135-3 assume !(0 == ~T10_E~0); 59378#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59377#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59376#L1150-3 assume !(0 == ~E_2~0); 59375#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59374#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59373#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59372#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59371#L1175-3 assume !(0 == ~E_7~0); 59370#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59369#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59368#L1190-3 assume !(0 == ~E_10~0); 59367#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59366#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57304#L525-36 assume !(1 == ~m_pc~0); 57305#L525-38 is_master_triggered_~__retres1~0#1 := 0; 56837#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56838#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57130#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 57131#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57035#L544-36 assume 1 == ~t1_pc~0; 57036#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57591#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56922#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56923#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57964#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57834#L563-36 assume 1 == ~t2_pc~0; 56824#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56578#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56579#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57693#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57318#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57319#L582-36 assume 1 == ~t3_pc~0; 57164#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57165#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57402#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57581#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57359#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57298#L601-36 assume 1 == ~t4_pc~0; 57193#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57194#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58072#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57942#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57943#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57821#L620-36 assume 1 == ~t5_pc~0; 57235#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57236#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57666#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57221#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56846#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56623#L639-36 assume 1 == ~t6_pc~0; 56624#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56661#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56662#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56903#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56904#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57513#L658-36 assume !(1 == ~t7_pc~0); 56635#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 56636#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57919#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56610#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 56611#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57650#L677-36 assume !(1 == ~t8_pc~0); 57430#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 57431#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57556#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58029#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57456#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57457#L696-36 assume 1 == ~t9_pc~0; 57338#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57340#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56684#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56685#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57471#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57472#L715-36 assume 1 == ~t10_pc~0; 57614#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56507#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56508#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56483#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56484#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56891#L734-36 assume !(1 == ~t11_pc~0); 56587#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 56588#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56913#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56501#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56502#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57536#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57181#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57182#L1218-3 assume !(1 == ~T2_E~0); 56944#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56945#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57138#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57139#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57398#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57399#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57940#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57947#L1258-3 assume !(1 == ~T10_E~0); 56924#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56925#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57898#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57924#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57926#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57268#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57269#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57128#L1298-3 assume !(1 == ~E_7~0); 57129#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57615#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57125#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57126#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56926#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 56927#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56866#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 58312#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 58133#L1663 assume !(0 == start_simulation_~tmp~3#1); 56758#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 58104#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 58210#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 58209#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 58208#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58207#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58206#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 58023#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 57016#L1644-2 [2021-11-22 15:27:22,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:22,737 INFO L85 PathProgramCache]: Analyzing trace with hash -255279365, now seen corresponding path program 1 times [2021-11-22 15:27:22,737 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:22,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556795595] [2021-11-22 15:27:22,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:22,738 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:22,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:22,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:22,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:22,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556795595] [2021-11-22 15:27:22,786 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556795595] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:22,786 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:22,786 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:22,786 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797214133] [2021-11-22 15:27:22,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:22,787 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:22,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:22,788 INFO L85 PathProgramCache]: Analyzing trace with hash 729879877, now seen corresponding path program 1 times [2021-11-22 15:27:22,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:22,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094596005] [2021-11-22 15:27:22,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:22,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:22,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:22,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:22,843 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:22,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094596005] [2021-11-22 15:27:22,844 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094596005] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:22,844 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:22,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:22,845 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888587616] [2021-11-22 15:27:22,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:22,845 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:22,846 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:22,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:27:22,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:27:22,847 INFO L87 Difference]: Start difference. First operand 2906 states and 4209 transitions. cyclomatic complexity: 1305 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:23,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:23,275 INFO L93 Difference]: Finished difference Result 8011 states and 11469 transitions. [2021-11-22 15:27:23,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 15:27:23,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8011 states and 11469 transitions. [2021-11-22 15:27:23,329 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7656 [2021-11-22 15:27:23,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8011 states to 8011 states and 11469 transitions. [2021-11-22 15:27:23,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8011 [2021-11-22 15:27:23,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8011 [2021-11-22 15:27:23,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8011 states and 11469 transitions. [2021-11-22 15:27:23,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:23,427 INFO L681 BuchiCegarLoop]: Abstraction has 8011 states and 11469 transitions. [2021-11-22 15:27:23,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8011 states and 11469 transitions. [2021-11-22 15:27:23,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8011 to 7679. [2021-11-22 15:27:23,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7679 states, 7679 states have (on average 1.4344315666102356) internal successors, (11015), 7678 states have internal predecessors, (11015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:23,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7679 states to 7679 states and 11015 transitions. [2021-11-22 15:27:23,608 INFO L704 BuchiCegarLoop]: Abstraction has 7679 states and 11015 transitions. [2021-11-22 15:27:23,608 INFO L587 BuchiCegarLoop]: Abstraction has 7679 states and 11015 transitions. [2021-11-22 15:27:23,608 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-22 15:27:23,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7679 states and 11015 transitions. [2021-11-22 15:27:23,649 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7500 [2021-11-22 15:27:23,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:23,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:23,652 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:23,653 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:23,653 INFO L791 eck$LassoCheckResult]: Stem: 68553#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 68554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 68561#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68562#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68317#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 68318#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68184#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68091#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67813#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67448#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67449#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67497#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67498#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68441#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68442#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68481#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67915#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67916#L1090 assume !(0 == ~M_E~0); 67960#L1090-2 assume !(0 == ~T1_E~0); 67961#L1095-1 assume !(0 == ~T2_E~0); 68626#L1100-1 assume !(0 == ~T3_E~0); 68627#L1105-1 assume !(0 == ~T4_E~0); 67731#L1110-1 assume !(0 == ~T5_E~0); 67732#L1115-1 assume !(0 == ~T6_E~0); 68134#L1120-1 assume !(0 == ~T7_E~0); 68418#L1125-1 assume !(0 == ~T8_E~0); 68962#L1130-1 assume !(0 == ~T9_E~0); 68649#L1135-1 assume !(0 == ~T10_E~0); 67920#L1140-1 assume !(0 == ~T11_E~0); 67921#L1145-1 assume !(0 == ~E_1~0); 68578#L1150-1 assume !(0 == ~E_2~0); 68105#L1155-1 assume !(0 == ~E_3~0); 68106#L1160-1 assume !(0 == ~E_4~0); 68192#L1165-1 assume !(0 == ~E_5~0); 68193#L1170-1 assume !(0 == ~E_6~0); 68839#L1175-1 assume !(0 == ~E_7~0); 68271#L1180-1 assume !(0 == ~E_8~0); 68272#L1185-1 assume !(0 == ~E_9~0); 67917#L1190-1 assume !(0 == ~E_10~0); 67918#L1195-1 assume !(0 == ~E_11~0); 68286#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68124#L525 assume !(1 == ~m_pc~0); 67536#L525-2 is_master_triggered_~__retres1~0#1 := 0; 67537#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68290#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68291#L1350 assume !(0 != activate_threads_~tmp~1#1); 67905#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67906#L544 assume !(1 == ~t1_pc~0); 68130#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68131#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68576#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67752#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 67753#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68389#L563 assume !(1 == ~t2_pc~0); 68563#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67557#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67558#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67988#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 67989#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68465#L582 assume 1 == ~t3_pc~0; 67697#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67698#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68915#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68850#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 67631#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67632#L601 assume !(1 == ~t4_pc~0); 68594#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68135#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68136#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68588#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 68589#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68905#L620 assume 1 == ~t5_pc~0; 67588#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67589#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68414#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68415#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 68931#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68932#L639 assume !(1 == ~t6_pc~0); 68416#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68026#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68027#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68852#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 68140#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68141#L658 assume !(1 == ~t7_pc~0); 68338#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68339#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68452#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68453#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 67911#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67912#L677 assume 1 == ~t8_pc~0; 68144#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67712#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67713#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67985#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 67986#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68690#L696 assume !(1 == ~t9_pc~0); 68401#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 68402#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68492#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68422#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68423#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68630#L715 assume 1 == ~t10_pc~0; 68637#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68510#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68392#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68393#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 68262#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67706#L734 assume !(1 == ~t11_pc~0); 67707#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 68199#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68276#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67438#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 67439#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68480#L1213 assume !(1 == ~M_E~0); 68259#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68260#L1218-1 assume !(1 == ~T2_E~0); 67473#L1223-1 assume !(1 == ~T3_E~0); 67474#L1228-1 assume !(1 == ~T4_E~0); 68238#L1233-1 assume !(1 == ~T5_E~0); 68933#L1238-1 assume !(1 == ~T6_E~0); 68586#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68587#L1248-1 assume !(1 == ~T8_E~0); 68635#L1253-1 assume !(1 == ~T9_E~0); 68636#L1258-1 assume !(1 == ~T10_E~0); 68610#L1263-1 assume !(1 == ~T11_E~0); 68611#L1268-1 assume !(1 == ~E_1~0); 68439#L1273-1 assume !(1 == ~E_2~0); 68440#L1278-1 assume !(1 == ~E_3~0); 68024#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 68025#L1288-1 assume !(1 == ~E_5~0); 68736#L1293-1 assume !(1 == ~E_6~0); 68695#L1298-1 assume !(1 == ~E_7~0); 68468#L1303-1 assume !(1 == ~E_8~0); 68036#L1308-1 assume !(1 == ~E_9~0); 67928#L1313-1 assume !(1 == ~E_10~0); 67929#L1318-1 assume !(1 == ~E_11~0); 67936#L1323-1 assume { :end_inline_reset_delta_events } true; 67937#L1644-2 [2021-11-22 15:27:23,654 INFO L793 eck$LassoCheckResult]: Loop: 67937#L1644-2 assume !false; 72094#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 72087#L1065 assume !false; 72088#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 68953#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 67555#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 68804#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68853#L906 assume !(0 != eval_~tmp~0#1); 72379#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74282#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74280#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 74278#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 74276#L1095-3 assume !(0 == ~T2_E~0); 74273#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74271#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74262#L1110-3 assume !(0 == ~T5_E~0); 74259#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74257#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74255#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74253#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 74251#L1135-3 assume !(0 == ~T10_E~0); 74249#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74246#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 74244#L1150-3 assume !(0 == ~E_2~0); 74242#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74240#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74238#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74236#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74233#L1175-3 assume !(0 == ~E_7~0); 74231#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 74229#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 74227#L1190-3 assume !(0 == ~E_10~0); 74225#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 74223#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74220#L525-36 assume !(1 == ~m_pc~0); 74218#L525-38 is_master_triggered_~__retres1~0#1 := 0; 74216#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74214#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74212#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 74209#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74207#L544-36 assume !(1 == ~t1_pc~0); 74205#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 74203#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74201#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74199#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74197#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74189#L563-36 assume !(1 == ~t2_pc~0); 74185#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 74181#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74179#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74177#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74175#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74173#L582-36 assume 1 == ~t3_pc~0; 74169#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 74167#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74166#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74165#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74164#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74163#L601-36 assume !(1 == ~t4_pc~0); 74161#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 74160#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74159#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74158#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74157#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74156#L620-36 assume !(1 == ~t5_pc~0); 74155#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 74153#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74152#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74151#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74150#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74149#L639-36 assume !(1 == ~t6_pc~0); 74147#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 74146#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74145#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74144#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74143#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74142#L658-36 assume !(1 == ~t7_pc~0); 74140#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 74139#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74138#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74137#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 74136#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74135#L677-36 assume !(1 == ~t8_pc~0); 74133#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 74131#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74130#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74129#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74128#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74127#L696-36 assume !(1 == ~t9_pc~0); 74125#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 74124#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74123#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74122#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74121#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74120#L715-36 assume 1 == ~t10_pc~0; 74115#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74113#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74111#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74109#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74106#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74104#L734-36 assume !(1 == ~t11_pc~0); 74101#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 74100#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74098#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74096#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 74094#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74093#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 74092#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73370#L1218-3 assume !(1 == ~T2_E~0); 73859#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73858#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73815#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73814#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73755#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73754#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 73753#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 73752#L1258-3 assume !(1 == ~T10_E~0); 73360#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73751#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73749#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73747#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73745#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73743#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73741#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73739#L1298-3 assume !(1 == ~E_7~0); 73737#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 73735#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 72315#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 72314#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 72313#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 72199#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 72185#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 72176#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 72161#L1663 assume !(0 == start_simulation_~tmp~3#1); 72158#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 72132#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 72125#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 72121#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 72117#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72113#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 72108#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 72105#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 67937#L1644-2 [2021-11-22 15:27:23,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:23,656 INFO L85 PathProgramCache]: Analyzing trace with hash -292726054, now seen corresponding path program 1 times [2021-11-22 15:27:23,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:23,656 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928226193] [2021-11-22 15:27:23,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:23,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:23,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:23,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:23,703 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:23,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928226193] [2021-11-22 15:27:23,703 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928226193] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:23,704 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:23,704 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:23,704 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651329183] [2021-11-22 15:27:23,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:23,705 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:23,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:23,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1400797631, now seen corresponding path program 1 times [2021-11-22 15:27:23,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:23,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360116804] [2021-11-22 15:27:23,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:23,706 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:23,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:23,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:23,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:23,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360116804] [2021-11-22 15:27:23,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360116804] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:23,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:23,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:23,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811998252] [2021-11-22 15:27:23,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:23,756 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:23,756 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:23,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:27:23,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:27:23,757 INFO L87 Difference]: Start difference. First operand 7679 states and 11015 transitions. cyclomatic complexity: 3340 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:24,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:24,284 INFO L93 Difference]: Finished difference Result 21694 states and 30852 transitions. [2021-11-22 15:27:24,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 15:27:24,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21694 states and 30852 transitions. [2021-11-22 15:27:24,397 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21118 [2021-11-22 15:27:24,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21694 states to 21694 states and 30852 transitions. [2021-11-22 15:27:24,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21694 [2021-11-22 15:27:24,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21694 [2021-11-22 15:27:24,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21694 states and 30852 transitions. [2021-11-22 15:27:24,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:24,532 INFO L681 BuchiCegarLoop]: Abstraction has 21694 states and 30852 transitions. [2021-11-22 15:27:24,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21694 states and 30852 transitions. [2021-11-22 15:27:24,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21694 to 20932. [2021-11-22 15:27:24,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20932 states, 20932 states have (on average 1.4246130326772406) internal successors, (29820), 20931 states have internal predecessors, (29820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:25,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20932 states to 20932 states and 29820 transitions. [2021-11-22 15:27:25,080 INFO L704 BuchiCegarLoop]: Abstraction has 20932 states and 29820 transitions. [2021-11-22 15:27:25,080 INFO L587 BuchiCegarLoop]: Abstraction has 20932 states and 29820 transitions. [2021-11-22 15:27:25,080 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-22 15:27:25,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20932 states and 29820 transitions. [2021-11-22 15:27:25,165 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20734 [2021-11-22 15:27:25,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:25,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:25,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:25,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:25,169 INFO L791 eck$LassoCheckResult]: Stem: 97958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 97959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 97966#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97967#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97713#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 97714#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97575#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97481#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97195#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96833#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96834#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96882#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96883#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97842#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97843#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97884#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97304#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97305#L1090 assume !(0 == ~M_E~0); 97347#L1090-2 assume !(0 == ~T1_E~0); 97348#L1095-1 assume !(0 == ~T2_E~0); 98038#L1100-1 assume !(0 == ~T3_E~0); 98039#L1105-1 assume !(0 == ~T4_E~0); 97112#L1110-1 assume !(0 == ~T5_E~0); 97113#L1115-1 assume !(0 == ~T6_E~0); 97522#L1120-1 assume !(0 == ~T7_E~0); 97817#L1125-1 assume !(0 == ~T8_E~0); 98428#L1130-1 assume !(0 == ~T9_E~0); 98063#L1135-1 assume !(0 == ~T10_E~0); 97309#L1140-1 assume !(0 == ~T11_E~0); 97310#L1145-1 assume !(0 == ~E_1~0); 97984#L1150-1 assume !(0 == ~E_2~0); 97496#L1155-1 assume !(0 == ~E_3~0); 97497#L1160-1 assume !(0 == ~E_4~0); 97584#L1165-1 assume !(0 == ~E_5~0); 97585#L1170-1 assume !(0 == ~E_6~0); 98286#L1175-1 assume !(0 == ~E_7~0); 97667#L1180-1 assume !(0 == ~E_8~0); 97668#L1185-1 assume !(0 == ~E_9~0); 97306#L1190-1 assume !(0 == ~E_10~0); 97307#L1195-1 assume !(0 == ~E_11~0); 97681#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97512#L525 assume !(1 == ~m_pc~0); 96920#L525-2 is_master_triggered_~__retres1~0#1 := 0; 96921#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97685#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97686#L1350 assume !(0 != activate_threads_~tmp~1#1); 97292#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97293#L544 assume !(1 == ~t1_pc~0); 97520#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97521#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97981#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 97134#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 97135#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97788#L563 assume !(1 == ~t2_pc~0); 97968#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96941#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96942#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97377#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 97378#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97867#L582 assume !(1 == ~t3_pc~0); 97982#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98368#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98369#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 98296#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 97015#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97016#L601 assume !(1 == ~t4_pc~0); 98004#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97523#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97524#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97998#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 97999#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98359#L620 assume 1 == ~t5_pc~0; 96970#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 96971#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97813#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97814#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 98388#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98389#L639 assume !(1 == ~t6_pc~0); 97815#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 97415#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97416#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98301#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 97530#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97531#L658 assume !(1 == ~t7_pc~0); 97734#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 97735#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97853#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97854#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 97299#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97300#L677 assume 1 == ~t8_pc~0; 97534#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 97093#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97094#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97374#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 97375#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 98111#L696 assume !(1 == ~t9_pc~0); 97799#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 97800#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97895#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97821#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 97822#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98043#L715 assume 1 == ~t10_pc~0; 98050#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 97913#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97791#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97792#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 97658#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97085#L734 assume !(1 == ~t11_pc~0); 97086#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 97588#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97672#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96821#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 96822#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97883#L1213 assume !(1 == ~M_E~0); 97654#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97655#L1218-1 assume !(1 == ~T2_E~0); 96858#L1223-1 assume !(1 == ~T3_E~0); 96859#L1228-1 assume !(1 == ~T4_E~0); 98390#L1233-1 assume !(1 == ~T5_E~0); 98391#L1238-1 assume !(1 == ~T6_E~0); 97996#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 97997#L1248-1 assume !(1 == ~T8_E~0); 98048#L1253-1 assume !(1 == ~T9_E~0); 98049#L1258-1 assume !(1 == ~T10_E~0); 98022#L1263-1 assume !(1 == ~T11_E~0); 98023#L1268-1 assume !(1 == ~E_1~0); 97840#L1273-1 assume !(1 == ~E_2~0); 97841#L1278-1 assume !(1 == ~E_3~0); 97413#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 97414#L1288-1 assume !(1 == ~E_5~0); 98164#L1293-1 assume !(1 == ~E_6~0); 98165#L1298-1 assume !(1 == ~E_7~0); 97870#L1303-1 assume !(1 == ~E_8~0); 97871#L1308-1 assume !(1 == ~E_9~0); 97315#L1313-1 assume !(1 == ~E_10~0); 97316#L1318-1 assume !(1 == ~E_11~0); 97325#L1323-1 assume { :end_inline_reset_delta_events } true; 97326#L1644-2 [2021-11-22 15:27:25,170 INFO L793 eck$LassoCheckResult]: Loop: 97326#L1644-2 assume !false; 97925#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97926#L1065 assume !false; 98014#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98418#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 96939#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98249#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 97430#L906 assume !(0 != eval_~tmp~0#1); 97432#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117205#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117204#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117203#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117202#L1095-3 assume !(0 == ~T2_E~0); 117201#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117200#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117199#L1110-3 assume !(0 == ~T5_E~0); 117198#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117197#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117196#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117195#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117194#L1135-3 assume !(0 == ~T10_E~0); 117193#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117192#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117191#L1150-3 assume !(0 == ~E_2~0); 117190#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117189#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117188#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117187#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117186#L1175-3 assume !(0 == ~E_7~0); 117185#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117184#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117183#L1190-3 assume !(0 == ~E_10~0); 117182#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117181#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117180#L525-36 assume !(1 == ~m_pc~0); 117179#L525-38 is_master_triggered_~__retres1~0#1 := 0; 117178#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117177#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117176#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 117175#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117174#L544-36 assume !(1 == ~t1_pc~0); 117173#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 117172#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117171#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117170#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117169#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117168#L563-36 assume 1 == ~t2_pc~0; 117167#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 117165#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117164#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117163#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117162#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117161#L582-36 assume !(1 == ~t3_pc~0); 117160#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 117159#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117158#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117157#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117156#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117155#L601-36 assume !(1 == ~t4_pc~0); 117153#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 117152#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117151#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117150#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117149#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117148#L620-36 assume !(1 == ~t5_pc~0); 117147#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 117145#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117144#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117143#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117142#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117141#L639-36 assume !(1 == ~t6_pc~0); 117139#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 117138#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117137#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117136#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117135#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117134#L658-36 assume !(1 == ~t7_pc~0); 117132#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 117131#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117130#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117129#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 117128#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117127#L677-36 assume 1 == ~t8_pc~0; 117125#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117124#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117123#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117122#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117121#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117120#L696-36 assume 1 == ~t9_pc~0; 117119#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117117#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117116#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117115#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117114#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117113#L715-36 assume 1 == ~t10_pc~0; 117111#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 117110#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117109#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117108#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117107#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117106#L734-36 assume 1 == ~t11_pc~0; 117105#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117103#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117102#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117101#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117100#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117099#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 117098#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 115694#L1218-3 assume !(1 == ~T2_E~0); 117097#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117096#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117095#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 115688#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 115687#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 114826#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 114824#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 114823#L1258-3 assume !(1 == ~T10_E~0); 98268#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 114818#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 114817#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 114816#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 114815#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 114814#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 114813#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 114812#L1298-3 assume !(1 == ~E_7~0); 98330#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97923#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97435#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97436#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 97236#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97237#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97173#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97601#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 98087#L1663 assume !(0 == start_simulation_~tmp~3#1); 97069#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97818#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97013#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 115394#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 115392#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97302#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97303#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 98414#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 97326#L1644-2 [2021-11-22 15:27:25,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:25,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1569878727, now seen corresponding path program 1 times [2021-11-22 15:27:25,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:25,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793445101] [2021-11-22 15:27:25,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:25,171 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:25,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:25,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:25,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:25,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793445101] [2021-11-22 15:27:25,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793445101] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:25,225 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:25,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:25,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332795896] [2021-11-22 15:27:25,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:25,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:25,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:25,227 INFO L85 PathProgramCache]: Analyzing trace with hash 671984546, now seen corresponding path program 1 times [2021-11-22 15:27:25,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:25,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553300924] [2021-11-22 15:27:25,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:25,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:25,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:25,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:25,273 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:25,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553300924] [2021-11-22 15:27:25,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553300924] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:25,274 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:25,274 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:25,274 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553091147] [2021-11-22 15:27:25,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:25,275 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:25,275 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:25,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:25,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:25,277 INFO L87 Difference]: Start difference. First operand 20932 states and 29820 transitions. cyclomatic complexity: 8896 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:25,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:25,717 INFO L93 Difference]: Finished difference Result 39957 states and 56708 transitions. [2021-11-22 15:27:25,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:25,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39957 states and 56708 transitions. [2021-11-22 15:27:25,946 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39694 [2021-11-22 15:27:26,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39957 states to 39957 states and 56708 transitions. [2021-11-22 15:27:26,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39957 [2021-11-22 15:27:26,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39957 [2021-11-22 15:27:26,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39957 states and 56708 transitions. [2021-11-22 15:27:26,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:26,345 INFO L681 BuchiCegarLoop]: Abstraction has 39957 states and 56708 transitions. [2021-11-22 15:27:26,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39957 states and 56708 transitions. [2021-11-22 15:27:27,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39957 to 39921. [2021-11-22 15:27:27,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39921 states, 39921 states have (on average 1.41960371734175) internal successors, (56672), 39920 states have internal predecessors, (56672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:27,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39921 states to 39921 states and 56672 transitions. [2021-11-22 15:27:27,719 INFO L704 BuchiCegarLoop]: Abstraction has 39921 states and 56672 transitions. [2021-11-22 15:27:27,719 INFO L587 BuchiCegarLoop]: Abstraction has 39921 states and 56672 transitions. [2021-11-22 15:27:27,719 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-22 15:27:27,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39921 states and 56672 transitions. [2021-11-22 15:27:28,028 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39658 [2021-11-22 15:27:28,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:28,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:28,031 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:28,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:28,072 INFO L791 eck$LassoCheckResult]: Stem: 158875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 158876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 158887#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 158888#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158615#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 158616#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158479#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158387#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158100#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157731#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157732#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157780#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157781#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 158752#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 158753#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 158801#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 158206#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158207#L1090 assume !(0 == ~M_E~0); 158256#L1090-2 assume !(0 == ~T1_E~0); 158257#L1095-1 assume !(0 == ~T2_E~0); 158955#L1100-1 assume !(0 == ~T3_E~0); 158956#L1105-1 assume !(0 == ~T4_E~0); 158013#L1110-1 assume !(0 == ~T5_E~0); 158014#L1115-1 assume !(0 == ~T6_E~0); 158429#L1120-1 assume !(0 == ~T7_E~0); 158723#L1125-1 assume !(0 == ~T8_E~0); 159367#L1130-1 assume !(0 == ~T9_E~0); 158978#L1135-1 assume !(0 == ~T10_E~0); 158211#L1140-1 assume !(0 == ~T11_E~0); 158212#L1145-1 assume !(0 == ~E_1~0); 158905#L1150-1 assume !(0 == ~E_2~0); 158401#L1155-1 assume !(0 == ~E_3~0); 158402#L1160-1 assume !(0 == ~E_4~0); 158488#L1165-1 assume !(0 == ~E_5~0); 158489#L1170-1 assume !(0 == ~E_6~0); 159198#L1175-1 assume !(0 == ~E_7~0); 158568#L1180-1 assume !(0 == ~E_8~0); 158569#L1185-1 assume !(0 == ~E_9~0); 158208#L1190-1 assume !(0 == ~E_10~0); 158209#L1195-1 assume !(0 == ~E_11~0); 158582#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158424#L525 assume !(1 == ~m_pc~0); 157818#L525-2 is_master_triggered_~__retres1~0#1 := 0; 157819#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158586#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158587#L1350 assume !(0 != activate_threads_~tmp~1#1); 158196#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158197#L544 assume !(1 == ~t1_pc~0); 158425#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 158426#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 158901#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158035#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 158036#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158691#L563 assume !(1 == ~t2_pc~0); 158889#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157842#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157843#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 158285#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 158286#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158775#L582 assume !(1 == ~t3_pc~0); 158902#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159293#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159294#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159209#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 157915#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157916#L601 assume !(1 == ~t4_pc~0); 158922#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 158430#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158431#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 158915#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 158916#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159281#L620 assume !(1 == ~t5_pc~0); 158744#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158745#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158719#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 158720#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 159315#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159316#L639 assume !(1 == ~t6_pc~0); 158721#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 158320#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158321#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 159213#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 158435#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158436#L658 assume !(1 == ~t7_pc~0); 158639#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 158640#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 158761#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158762#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 158202#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 158203#L677 assume 1 == ~t8_pc~0; 158441#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 157999#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 158000#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 158279#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 158280#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 159024#L696 assume !(1 == ~t9_pc~0); 158707#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 158708#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158806#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158729#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 158730#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 158959#L715 assume 1 == ~t10_pc~0; 158965#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 158824#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 158694#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 158695#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 158559#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157987#L734 assume !(1 == ~t11_pc~0); 157988#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 158495#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 158573#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 157721#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 157722#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158792#L1213 assume !(1 == ~M_E~0); 158556#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 158557#L1218-1 assume !(1 == ~T2_E~0); 185015#L1223-1 assume !(1 == ~T3_E~0); 185014#L1228-1 assume !(1 == ~T4_E~0); 185013#L1233-1 assume !(1 == ~T5_E~0); 185012#L1238-1 assume !(1 == ~T6_E~0); 185011#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 185010#L1248-1 assume !(1 == ~T8_E~0); 185009#L1253-1 assume !(1 == ~T9_E~0); 185008#L1258-1 assume !(1 == ~T10_E~0); 159214#L1263-1 assume !(1 == ~T11_E~0); 185007#L1268-1 assume !(1 == ~E_1~0); 185004#L1273-1 assume !(1 == ~E_2~0); 185002#L1278-1 assume !(1 == ~E_3~0); 185000#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 184998#L1288-1 assume !(1 == ~E_5~0); 184996#L1293-1 assume !(1 == ~E_6~0); 184994#L1298-1 assume !(1 == ~E_7~0); 184991#L1303-1 assume !(1 == ~E_8~0); 184989#L1308-1 assume !(1 == ~E_9~0); 158219#L1313-1 assume !(1 == ~E_10~0); 158220#L1318-1 assume !(1 == ~E_11~0); 184414#L1323-1 assume { :end_inline_reset_delta_events } true; 184415#L1644-2 [2021-11-22 15:27:28,073 INFO L793 eck$LassoCheckResult]: Loop: 184415#L1644-2 assume !false; 188250#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188244#L1065 assume !false; 188243#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 184395#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 184383#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 184381#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 184377#L906 assume !(0 != eval_~tmp~0#1); 184379#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 190354#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 190352#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 190350#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 190348#L1095-3 assume !(0 == ~T2_E~0); 190346#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 190344#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190342#L1110-3 assume !(0 == ~T5_E~0); 190340#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190338#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 190335#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 190333#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 190331#L1135-3 assume !(0 == ~T10_E~0); 190329#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 190327#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 190325#L1150-3 assume !(0 == ~E_2~0); 190323#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 190321#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 190319#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 190317#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 190315#L1175-3 assume !(0 == ~E_7~0); 190313#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 190310#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 190308#L1190-3 assume !(0 == ~E_10~0); 190306#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 190304#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190302#L525-36 assume !(1 == ~m_pc~0); 190300#L525-38 is_master_triggered_~__retres1~0#1 := 0; 190298#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190296#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 190294#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 190292#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190290#L544-36 assume !(1 == ~t1_pc~0); 190288#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 190285#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190283#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190281#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 190279#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190277#L563-36 assume 1 == ~t2_pc~0; 190274#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 190271#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190269#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190267#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 190265#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190263#L582-36 assume !(1 == ~t3_pc~0); 190261#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 190258#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190256#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190254#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 190252#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190250#L601-36 assume !(1 == ~t4_pc~0); 190247#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 190244#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 190242#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 190240#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 190238#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190236#L620-36 assume !(1 == ~t5_pc~0); 190234#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 190231#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190229#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 190227#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 190225#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190223#L639-36 assume !(1 == ~t6_pc~0); 190220#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 190217#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190215#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 190213#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 190211#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 190209#L658-36 assume !(1 == ~t7_pc~0); 190206#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 190205#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190204#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 190203#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 190202#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 190201#L677-36 assume 1 == ~t8_pc~0; 190199#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 190197#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 190195#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 190193#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 190191#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 190189#L696-36 assume !(1 == ~t9_pc~0); 190186#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 190184#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 190182#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 190180#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 190178#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 190176#L715-36 assume !(1 == ~t10_pc~0); 190174#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 190171#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 190168#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 190166#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 190164#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 190162#L734-36 assume !(1 == ~t11_pc~0); 190092#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 190090#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 190088#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 190086#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 190084#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190082#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 190080#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 190076#L1218-3 assume !(1 == ~T2_E~0); 190074#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 190072#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 190070#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 190067#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 190065#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 190063#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 190061#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 190057#L1258-3 assume !(1 == ~T10_E~0); 190054#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 190052#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 190050#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 190048#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 190046#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 190044#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 190041#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 190039#L1298-3 assume !(1 == ~E_7~0); 190037#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 190035#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 190033#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 190032#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 190031#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 188674#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 188662#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 188661#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 188656#L1663 assume !(0 == start_simulation_~tmp~3#1); 188653#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 188270#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 188264#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 188262#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 188260#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 188258#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188256#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 188254#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 184415#L1644-2 [2021-11-22 15:27:28,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:28,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1547114008, now seen corresponding path program 1 times [2021-11-22 15:27:28,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:28,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696730905] [2021-11-22 15:27:28,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:28,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:28,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:28,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:28,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:28,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696730905] [2021-11-22 15:27:28,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696730905] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:28,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:28,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:28,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793047582] [2021-11-22 15:27:28,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:28,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:28,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:28,125 INFO L85 PathProgramCache]: Analyzing trace with hash 52106111, now seen corresponding path program 1 times [2021-11-22 15:27:28,125 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:28,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720358104] [2021-11-22 15:27:28,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:28,125 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:28,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:28,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:28,197 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:28,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720358104] [2021-11-22 15:27:28,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720358104] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:28,198 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:28,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:28,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493847012] [2021-11-22 15:27:28,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:28,199 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:28,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:28,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:28,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:28,200 INFO L87 Difference]: Start difference. First operand 39921 states and 56672 transitions. cyclomatic complexity: 16767 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:28,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:28,944 INFO L93 Difference]: Finished difference Result 76234 states and 107851 transitions. [2021-11-22 15:27:28,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:28,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76234 states and 107851 transitions. [2021-11-22 15:27:29,491 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75804 [2021-11-22 15:27:29,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76234 states to 76234 states and 107851 transitions. [2021-11-22 15:27:29,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76234 [2021-11-22 15:27:30,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76234 [2021-11-22 15:27:30,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76234 states and 107851 transitions. [2021-11-22 15:27:30,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:30,160 INFO L681 BuchiCegarLoop]: Abstraction has 76234 states and 107851 transitions. [2021-11-22 15:27:30,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76234 states and 107851 transitions. [2021-11-22 15:27:31,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76234 to 76162. [2021-11-22 15:27:31,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76162 states, 76162 states have (on average 1.415128279194349) internal successors, (107779), 76161 states have internal predecessors, (107779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:32,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76162 states to 76162 states and 107779 transitions. [2021-11-22 15:27:32,250 INFO L704 BuchiCegarLoop]: Abstraction has 76162 states and 107779 transitions. [2021-11-22 15:27:32,250 INFO L587 BuchiCegarLoop]: Abstraction has 76162 states and 107779 transitions. [2021-11-22 15:27:32,250 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-22 15:27:32,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76162 states and 107779 transitions. [2021-11-22 15:27:32,519 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75732 [2021-11-22 15:27:32,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:32,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:32,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:32,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:32,523 INFO L791 eck$LassoCheckResult]: Stem: 275018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 275019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 275027#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 275028#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274766#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 274767#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274631#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 274540#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 274255#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273895#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273896#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 273944#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 273945#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 274898#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 274899#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 274942#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 274360#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274361#L1090 assume !(0 == ~M_E~0); 274407#L1090-2 assume !(0 == ~T1_E~0); 274408#L1095-1 assume !(0 == ~T2_E~0); 275102#L1100-1 assume !(0 == ~T3_E~0); 275103#L1105-1 assume !(0 == ~T4_E~0); 274171#L1110-1 assume !(0 == ~T5_E~0); 274172#L1115-1 assume !(0 == ~T6_E~0); 274578#L1120-1 assume !(0 == ~T7_E~0); 274872#L1125-1 assume !(0 == ~T8_E~0); 275503#L1130-1 assume !(0 == ~T9_E~0); 275128#L1135-1 assume !(0 == ~T10_E~0); 274366#L1140-1 assume !(0 == ~T11_E~0); 274367#L1145-1 assume !(0 == ~E_1~0); 275047#L1150-1 assume !(0 == ~E_2~0); 274554#L1155-1 assume !(0 == ~E_3~0); 274555#L1160-1 assume !(0 == ~E_4~0); 274640#L1165-1 assume !(0 == ~E_5~0); 274641#L1170-1 assume !(0 == ~E_6~0); 275345#L1175-1 assume !(0 == ~E_7~0); 274722#L1180-1 assume !(0 == ~E_8~0); 274723#L1185-1 assume !(0 == ~E_9~0); 274362#L1190-1 assume !(0 == ~E_10~0); 274363#L1195-1 assume !(0 == ~E_11~0); 274736#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274568#L525 assume !(1 == ~m_pc~0); 273982#L525-2 is_master_triggered_~__retres1~0#1 := 0; 273983#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274739#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 274740#L1350 assume !(0 != activate_threads_~tmp~1#1); 274349#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274350#L544 assume !(1 == ~t1_pc~0); 274576#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 274577#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275043#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 274193#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 274194#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274843#L563 assume !(1 == ~t2_pc~0); 275029#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274003#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274004#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274435#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 274436#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 274926#L582 assume !(1 == ~t3_pc~0); 275044#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 275443#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275444#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275358#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 274074#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274075#L601 assume !(1 == ~t4_pc~0); 275067#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 274579#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274580#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 275061#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 275062#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 275427#L620 assume !(1 == ~t5_pc~0); 274888#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 274889#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274868#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 274869#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 275460#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 275461#L639 assume !(1 == ~t6_pc~0); 274870#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 274475#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274476#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 275362#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 274586#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 274587#L658 assume !(1 == ~t7_pc~0); 274788#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 274789#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274910#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 274911#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 274356#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 274357#L677 assume !(1 == ~t8_pc~0); 274381#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 274152#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 274153#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 274431#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 274432#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 275173#L696 assume !(1 == ~t9_pc~0); 274854#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 274855#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 274954#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 274876#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 274877#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 275108#L715 assume 1 == ~t10_pc~0; 275115#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 274973#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 274846#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 274847#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 274713#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 274144#L734 assume !(1 == ~t11_pc~0); 274145#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 274644#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 274727#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 273883#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 273884#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274941#L1213 assume !(1 == ~M_E~0); 274709#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 274710#L1218-1 assume !(1 == ~T2_E~0); 314202#L1223-1 assume !(1 == ~T3_E~0); 314201#L1228-1 assume !(1 == ~T4_E~0); 314200#L1233-1 assume !(1 == ~T5_E~0); 314199#L1238-1 assume !(1 == ~T6_E~0); 314198#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 314197#L1248-1 assume !(1 == ~T8_E~0); 314196#L1253-1 assume !(1 == ~T9_E~0); 314195#L1258-1 assume !(1 == ~T10_E~0); 275363#L1263-1 assume !(1 == ~T11_E~0); 314194#L1268-1 assume !(1 == ~E_1~0); 314193#L1273-1 assume !(1 == ~E_2~0); 314192#L1278-1 assume !(1 == ~E_3~0); 314191#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 314190#L1288-1 assume !(1 == ~E_5~0); 314189#L1293-1 assume !(1 == ~E_6~0); 314185#L1298-1 assume !(1 == ~E_7~0); 314181#L1303-1 assume !(1 == ~E_8~0); 314176#L1308-1 assume !(1 == ~E_9~0); 314171#L1313-1 assume !(1 == ~E_10~0); 314167#L1318-1 assume !(1 == ~E_11~0); 314162#L1323-1 assume { :end_inline_reset_delta_events } true; 314156#L1644-2 [2021-11-22 15:27:32,524 INFO L793 eck$LassoCheckResult]: Loop: 314156#L1644-2 assume !false; 314155#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 314150#L1065 assume !false; 314148#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 314138#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 314127#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 314125#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 314122#L906 assume !(0 != eval_~tmp~0#1); 314123#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 315184#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 315182#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 315180#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 315178#L1095-3 assume !(0 == ~T2_E~0); 315176#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 315174#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 315172#L1110-3 assume !(0 == ~T5_E~0); 315170#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 315168#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 315166#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 315163#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 315161#L1135-3 assume !(0 == ~T10_E~0); 315159#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 315157#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 315155#L1150-3 assume !(0 == ~E_2~0); 315153#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 315151#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 315149#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 315147#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 315145#L1175-3 assume !(0 == ~E_7~0); 315143#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 315141#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 315138#L1190-3 assume !(0 == ~E_10~0); 315136#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 315134#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315132#L525-36 assume !(1 == ~m_pc~0); 315130#L525-38 is_master_triggered_~__retres1~0#1 := 0; 315127#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315125#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 315123#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 315121#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315119#L544-36 assume !(1 == ~t1_pc~0); 315117#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 315115#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315113#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315111#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315109#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315107#L563-36 assume !(1 == ~t2_pc~0); 315104#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 315102#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315099#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 315097#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 315095#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315093#L582-36 assume !(1 == ~t3_pc~0); 315091#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 315089#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315086#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 315084#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 315082#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 315080#L601-36 assume !(1 == ~t4_pc~0); 315077#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 315075#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 315072#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 315070#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 315068#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 315066#L620-36 assume !(1 == ~t5_pc~0); 315064#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 315063#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315062#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 315061#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 315060#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 315059#L639-36 assume !(1 == ~t6_pc~0); 315057#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 315056#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 315055#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 315054#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 315053#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315052#L658-36 assume !(1 == ~t7_pc~0); 315050#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 315049#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 315048#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 315047#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 315046#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 315045#L677-36 assume !(1 == ~t8_pc~0); 315043#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 315041#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 315039#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 315037#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 315035#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 315033#L696-36 assume !(1 == ~t9_pc~0); 315030#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 315029#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 315028#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 315027#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 315026#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 315025#L715-36 assume 1 == ~t10_pc~0; 315022#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 315020#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 315018#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 315016#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 315014#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 315012#L734-36 assume !(1 == ~t11_pc~0); 315009#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 315007#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 315005#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 315003#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 315001#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314999#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 314997#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 314633#L1218-3 assume !(1 == ~T2_E~0); 314993#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 314991#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314989#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314987#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314985#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 314983#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 314981#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 314610#L1258-3 assume !(1 == ~T10_E~0); 314608#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 314606#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314604#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314600#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314598#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 314596#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314594#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 314592#L1298-3 assume !(1 == ~E_7~0); 314590#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 314588#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 314586#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 314584#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 314582#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 314580#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 314567#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 314565#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 314563#L1663 assume !(0 == start_simulation_~tmp~3#1); 314561#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 314553#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 314548#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 314544#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 314542#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 314540#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 314539#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 314161#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 314156#L1644-2 [2021-11-22 15:27:32,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:32,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1315018569, now seen corresponding path program 1 times [2021-11-22 15:27:32,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:32,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463247504] [2021-11-22 15:27:32,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:32,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:32,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:32,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:32,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:32,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463247504] [2021-11-22 15:27:32,580 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463247504] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:32,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:32,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:32,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977118164] [2021-11-22 15:27:32,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:32,584 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:32,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:32,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1363350942, now seen corresponding path program 1 times [2021-11-22 15:27:32,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:32,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107710271] [2021-11-22 15:27:32,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:32,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:32,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:32,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:32,636 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:32,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107710271] [2021-11-22 15:27:32,637 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107710271] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:32,637 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:32,637 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:32,637 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410850183] [2021-11-22 15:27:32,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:32,638 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:32,638 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:32,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-22 15:27:32,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-22 15:27:32,639 INFO L87 Difference]: Start difference. First operand 76162 states and 107779 transitions. cyclomatic complexity: 31649 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:34,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:34,094 INFO L93 Difference]: Finished difference Result 176779 states and 252552 transitions. [2021-11-22 15:27:34,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-22 15:27:34,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176779 states and 252552 transitions. [2021-11-22 15:27:35,738 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 175720 [2021-11-22 15:27:36,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176779 states to 176779 states and 252552 transitions. [2021-11-22 15:27:36,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176779 [2021-11-22 15:27:36,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176779 [2021-11-22 15:27:36,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176779 states and 252552 transitions. [2021-11-22 15:27:37,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:37,229 INFO L681 BuchiCegarLoop]: Abstraction has 176779 states and 252552 transitions. [2021-11-22 15:27:37,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176779 states and 252552 transitions. [2021-11-22 15:27:38,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176779 to 78349. [2021-11-22 15:27:39,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78349 states, 78349 states have (on average 1.4035405684820483) internal successors, (109966), 78348 states have internal predecessors, (109966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:39,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78349 states to 78349 states and 109966 transitions. [2021-11-22 15:27:39,795 INFO L704 BuchiCegarLoop]: Abstraction has 78349 states and 109966 transitions. [2021-11-22 15:27:39,795 INFO L587 BuchiCegarLoop]: Abstraction has 78349 states and 109966 transitions. [2021-11-22 15:27:39,795 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-22 15:27:39,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78349 states and 109966 transitions. [2021-11-22 15:27:40,022 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77916 [2021-11-22 15:27:40,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:40,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:40,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:40,026 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:40,026 INFO L791 eck$LassoCheckResult]: Stem: 527979#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 527980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 527989#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 527990#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 527726#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 527727#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 527589#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 527500#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 527212#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 526851#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 526852#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 526901#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 526902#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 527855#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 527856#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 527899#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 527318#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527319#L1090 assume !(0 == ~M_E~0); 527365#L1090-2 assume !(0 == ~T1_E~0); 527366#L1095-1 assume !(0 == ~T2_E~0); 528063#L1100-1 assume !(0 == ~T3_E~0); 528064#L1105-1 assume !(0 == ~T4_E~0); 527128#L1110-1 assume !(0 == ~T5_E~0); 527129#L1115-1 assume !(0 == ~T6_E~0); 527540#L1120-1 assume !(0 == ~T7_E~0); 527829#L1125-1 assume !(0 == ~T8_E~0); 528501#L1130-1 assume !(0 == ~T9_E~0); 528092#L1135-1 assume !(0 == ~T10_E~0); 527324#L1140-1 assume !(0 == ~T11_E~0); 527325#L1145-1 assume !(0 == ~E_1~0); 528007#L1150-1 assume !(0 == ~E_2~0); 527514#L1155-1 assume !(0 == ~E_3~0); 527515#L1160-1 assume !(0 == ~E_4~0); 527597#L1165-1 assume !(0 == ~E_5~0); 527598#L1170-1 assume !(0 == ~E_6~0); 528327#L1175-1 assume !(0 == ~E_7~0); 527678#L1180-1 assume !(0 == ~E_8~0); 527679#L1185-1 assume !(0 == ~E_9~0); 527320#L1190-1 assume !(0 == ~E_10~0); 527321#L1195-1 assume !(0 == ~E_11~0); 527694#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 527530#L525 assume !(1 == ~m_pc~0); 526939#L525-2 is_master_triggered_~__retres1~0#1 := 0; 526940#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527697#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 527698#L1350 assume !(0 != activate_threads_~tmp~1#1); 527307#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527308#L544 assume !(1 == ~t1_pc~0); 527538#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 527539#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 528004#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527149#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 527150#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 527800#L563 assume !(1 == ~t2_pc~0); 527991#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 526960#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 526961#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527394#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 527395#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 527880#L582 assume !(1 == ~t3_pc~0); 528005#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 528430#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 528431#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 528338#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 527031#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527032#L601 assume !(1 == ~t4_pc~0); 528028#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 527541#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527542#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 528022#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 528023#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 528416#L620 assume !(1 == ~t5_pc~0); 527845#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 527846#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527826#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 527827#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 528455#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528456#L639 assume !(1 == ~t6_pc~0); 527825#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 527432#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527433#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 528344#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 527548#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 527549#L658 assume !(1 == ~t7_pc~0); 527746#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 527747#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 527865#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 527866#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 527314#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 527315#L677 assume !(1 == ~t8_pc~0); 527341#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 527109#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 527110#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 527391#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 527392#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 528143#L696 assume !(1 == ~t9_pc~0); 527811#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 527812#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 527911#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 527833#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 527834#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 528070#L715 assume 1 == ~t10_pc~0; 528077#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 527930#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 527803#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 527804#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 527669#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 527101#L734 assume !(1 == ~t11_pc~0); 527102#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 527601#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 527683#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 526839#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 526840#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527898#L1213 assume !(1 == ~M_E~0); 527665#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 527666#L1218-1 assume !(1 == ~T2_E~0); 528235#L1223-1 assume !(1 == ~T3_E~0); 527644#L1228-1 assume !(1 == ~T4_E~0); 527645#L1233-1 assume !(1 == ~T5_E~0); 528457#L1238-1 assume !(1 == ~T6_E~0); 528542#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 566624#L1248-1 assume !(1 == ~T8_E~0); 566622#L1253-1 assume !(1 == ~T9_E~0); 528345#L1258-1 assume !(1 == ~T10_E~0); 528048#L1263-1 assume !(1 == ~T11_E~0); 528049#L1268-1 assume !(1 == ~E_1~0); 527853#L1273-1 assume !(1 == ~E_2~0); 527854#L1278-1 assume !(1 == ~E_3~0); 528444#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 528472#L1288-1 assume !(1 == ~E_5~0); 528473#L1293-1 assume !(1 == ~E_6~0); 528149#L1298-1 assume !(1 == ~E_7~0); 528150#L1303-1 assume !(1 == ~E_8~0); 527441#L1308-1 assume !(1 == ~E_9~0); 527442#L1313-1 assume !(1 == ~E_10~0); 566270#L1318-1 assume !(1 == ~E_11~0); 566265#L1323-1 assume { :end_inline_reset_delta_events } true; 566259#L1644-2 [2021-11-22 15:27:40,027 INFO L793 eck$LassoCheckResult]: Loop: 566259#L1644-2 assume !false; 566258#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 566253#L1065 assume !false; 566252#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 566247#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 566237#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 566236#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 566234#L906 assume !(0 != eval_~tmp~0#1); 566235#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 570293#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 570291#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 568207#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 568205#L1095-3 assume !(0 == ~T2_E~0); 568203#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 568200#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 568198#L1110-3 assume !(0 == ~T5_E~0); 568196#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 568194#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 568192#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 568190#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 568187#L1135-3 assume !(0 == ~T10_E~0); 568185#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 568183#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 568181#L1150-3 assume !(0 == ~E_2~0); 568179#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 568178#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 568177#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 568176#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 568175#L1175-3 assume !(0 == ~E_7~0); 568174#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 568170#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 568168#L1190-3 assume !(0 == ~E_10~0); 568166#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 567449#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567448#L525-36 assume !(1 == ~m_pc~0); 567447#L525-38 is_master_triggered_~__retres1~0#1 := 0; 567446#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567445#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567444#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 567443#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567442#L544-36 assume !(1 == ~t1_pc~0); 567441#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 567440#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567439#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567438#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 567437#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567436#L563-36 assume !(1 == ~t2_pc~0); 567434#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 567433#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567432#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567431#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567430#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567429#L582-36 assume !(1 == ~t3_pc~0); 567428#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 567427#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567426#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567425#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567424#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567423#L601-36 assume !(1 == ~t4_pc~0); 567421#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 567420#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567419#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567418#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567417#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567416#L620-36 assume !(1 == ~t5_pc~0); 567415#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 567414#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567413#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 567412#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567411#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567410#L639-36 assume !(1 == ~t6_pc~0); 567408#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 567407#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567406#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 567405#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 567404#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567403#L658-36 assume !(1 == ~t7_pc~0); 567401#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 567400#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567399#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 567398#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 567397#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 567396#L677-36 assume !(1 == ~t8_pc~0); 567395#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 567394#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 567393#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 567392#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 567391#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 567390#L696-36 assume 1 == ~t9_pc~0; 567388#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 567386#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 567384#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 567382#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 567377#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 567374#L715-36 assume 1 == ~t10_pc~0; 567371#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 567369#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 567367#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 567365#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 567363#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 567360#L734-36 assume !(1 == ~t11_pc~0); 567357#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 567355#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 567353#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 567351#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 567349#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567347#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 567345#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567341#L1218-3 assume !(1 == ~T2_E~0); 567337#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567335#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 567333#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567331#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 567329#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 567327#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 567325#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 567249#L1258-3 assume !(1 == ~T10_E~0); 567247#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 567245#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 567243#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 567241#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 567239#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 567237#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 567231#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 567229#L1298-3 assume !(1 == ~E_7~0); 567227#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 567226#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 567225#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 567224#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 566981#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 566900#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 566887#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 566885#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 566883#L1663 assume !(0 == start_simulation_~tmp~3#1); 566869#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 566453#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 566447#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 566445#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 566441#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 566439#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 566437#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 566264#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 566259#L1644-2 [2021-11-22 15:27:40,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:40,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1950589429, now seen corresponding path program 1 times [2021-11-22 15:27:40,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:40,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127414372] [2021-11-22 15:27:40,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:40,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:40,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:40,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:40,078 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:40,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127414372] [2021-11-22 15:27:40,078 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127414372] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:40,078 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:40,079 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:27:40,079 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667471703] [2021-11-22 15:27:40,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:40,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:40,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:40,080 INFO L85 PathProgramCache]: Analyzing trace with hash 1260549695, now seen corresponding path program 1 times [2021-11-22 15:27:40,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:40,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936382786] [2021-11-22 15:27:40,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:40,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:40,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:40,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:40,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:40,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936382786] [2021-11-22 15:27:40,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936382786] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:40,129 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:40,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:40,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39636316] [2021-11-22 15:27:40,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:40,130 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:40,130 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:40,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:27:40,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:27:40,131 INFO L87 Difference]: Start difference. First operand 78349 states and 109966 transitions. cyclomatic complexity: 31649 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:41,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:41,999 INFO L93 Difference]: Finished difference Result 220284 states and 307363 transitions. [2021-11-22 15:27:41,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 15:27:42,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220284 states and 307363 transitions. [2021-11-22 15:27:42,899 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 216156 [2021-11-22 15:27:44,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220284 states to 220284 states and 307363 transitions. [2021-11-22 15:27:44,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 220284 [2021-11-22 15:27:44,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 220284 [2021-11-22 15:27:44,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 220284 states and 307363 transitions. [2021-11-22 15:27:44,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:44,485 INFO L681 BuchiCegarLoop]: Abstraction has 220284 states and 307363 transitions. [2021-11-22 15:27:44,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220284 states and 307363 transitions. [2021-11-22 15:27:47,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220284 to 215956. [2021-11-22 15:27:47,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 215956 states, 215956 states have (on average 1.3974837466891403) internal successors, (301795), 215955 states have internal predecessors, (301795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:48,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215956 states to 215956 states and 301795 transitions. [2021-11-22 15:27:48,256 INFO L704 BuchiCegarLoop]: Abstraction has 215956 states and 301795 transitions. [2021-11-22 15:27:48,256 INFO L587 BuchiCegarLoop]: Abstraction has 215956 states and 301795 transitions. [2021-11-22 15:27:48,256 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-22 15:27:48,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215956 states and 301795 transitions. [2021-11-22 15:27:49,687 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 215076 [2021-11-22 15:27:49,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:49,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:49,718 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:49,718 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:49,718 INFO L791 eck$LassoCheckResult]: Stem: 826646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 826647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 826654#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 826655#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 826380#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 826381#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 826242#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 826151#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 825859#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 825496#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 825497#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 825546#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 825547#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 826517#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 826518#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 826566#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 825963#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 825964#L1090 assume !(0 == ~M_E~0); 826010#L1090-2 assume !(0 == ~T1_E~0); 826011#L1095-1 assume !(0 == ~T2_E~0); 826723#L1100-1 assume !(0 == ~T3_E~0); 826724#L1105-1 assume !(0 == ~T4_E~0); 825773#L1110-1 assume !(0 == ~T5_E~0); 825774#L1115-1 assume !(0 == ~T6_E~0); 826193#L1120-1 assume !(0 == ~T7_E~0); 826489#L1125-1 assume !(0 == ~T8_E~0); 827147#L1130-1 assume !(0 == ~T9_E~0); 826745#L1135-1 assume !(0 == ~T10_E~0); 825969#L1140-1 assume !(0 == ~T11_E~0); 825970#L1145-1 assume !(0 == ~E_1~0); 826671#L1150-1 assume !(0 == ~E_2~0); 826167#L1155-1 assume !(0 == ~E_3~0); 826168#L1160-1 assume !(0 == ~E_4~0); 826250#L1165-1 assume !(0 == ~E_5~0); 826251#L1170-1 assume !(0 == ~E_6~0); 826977#L1175-1 assume !(0 == ~E_7~0); 826334#L1180-1 assume !(0 == ~E_8~0); 826335#L1185-1 assume !(0 == ~E_9~0); 825965#L1190-1 assume !(0 == ~E_10~0); 825966#L1195-1 assume !(0 == ~E_11~0); 826348#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 826183#L525 assume !(1 == ~m_pc~0); 825584#L525-2 is_master_triggered_~__retres1~0#1 := 0; 825585#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 826351#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 826352#L1350 assume !(0 != activate_threads_~tmp~1#1); 825952#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 825953#L544 assume !(1 == ~t1_pc~0); 826191#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 826192#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 826668#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 825796#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 825797#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 826457#L563 assume !(1 == ~t2_pc~0); 826656#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 825605#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 825606#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 826040#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 826041#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 826544#L582 assume !(1 == ~t3_pc~0); 826669#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 827080#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 827081#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 826989#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 825676#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 825677#L601 assume !(1 == ~t4_pc~0); 826689#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 826194#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 826195#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 826683#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 826684#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827068#L620 assume !(1 == ~t5_pc~0); 826507#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 826508#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 826486#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 826487#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 827102#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 827103#L639 assume !(1 == ~t6_pc~0); 826488#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 826081#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 826082#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 826995#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 826201#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 826202#L658 assume !(1 == ~t7_pc~0); 826402#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 826403#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 826528#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 826529#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 825959#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 825960#L677 assume !(1 == ~t8_pc~0); 825984#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 825754#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 825755#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 826036#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 826037#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 826795#L696 assume !(1 == ~t9_pc~0); 826468#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 826469#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 826579#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 826493#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 826494#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 826728#L715 assume !(1 == ~t10_pc~0); 827023#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 826597#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 826460#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 826461#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 826325#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 825746#L734 assume !(1 == ~t11_pc~0); 825747#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 826254#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 826339#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 825484#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 825485#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 826565#L1213 assume !(1 == ~M_E~0); 826321#L1213-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 826322#L1218-1 assume !(1 == ~T2_E~0); 826890#L1223-1 assume !(1 == ~T3_E~0); 826296#L1228-1 assume !(1 == ~T4_E~0); 826297#L1233-1 assume !(1 == ~T5_E~0); 827193#L1238-1 assume !(1 == ~T6_E~0); 827194#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 827169#L1248-1 assume !(1 == ~T8_E~0); 827170#L1253-1 assume !(1 == ~T9_E~0); 826996#L1258-1 assume !(1 == ~T10_E~0); 826997#L1263-1 assume !(1 == ~T11_E~0); 827026#L1268-1 assume !(1 == ~E_1~0); 827027#L1273-1 assume !(1 == ~E_2~0); 827092#L1278-1 assume !(1 == ~E_3~0); 827093#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 827120#L1288-1 assume !(1 == ~E_5~0); 827121#L1293-1 assume !(1 == ~E_6~0); 826800#L1298-1 assume !(1 == ~E_7~0); 826801#L1303-1 assume !(1 == ~E_8~0); 826090#L1308-1 assume !(1 == ~E_9~0); 826091#L1313-1 assume !(1 == ~E_10~0); 827153#L1318-1 assume !(1 == ~E_11~0); 827154#L1323-1 assume { :end_inline_reset_delta_events } true; 995587#L1644-2 [2021-11-22 15:27:49,719 INFO L793 eck$LassoCheckResult]: Loop: 995587#L1644-2 assume !false; 995585#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 995578#L1065 assume !false; 995576#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 995566#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 995555#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 995554#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 995552#L906 assume !(0 != eval_~tmp~0#1); 995553#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 999059#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999057#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 999055#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 999052#L1095-3 assume !(0 == ~T2_E~0); 999050#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 999047#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 999044#L1110-3 assume !(0 == ~T5_E~0); 999041#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 999038#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 999035#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 999032#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 999029#L1135-3 assume !(0 == ~T10_E~0); 999026#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 999023#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 999020#L1150-3 assume !(0 == ~E_2~0); 999017#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 999014#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 999010#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 999004#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 998999#L1175-3 assume !(0 == ~E_7~0); 998994#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 998988#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 998982#L1190-3 assume !(0 == ~E_10~0); 998976#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 998969#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 998963#L525-36 assume !(1 == ~m_pc~0); 998957#L525-38 is_master_triggered_~__retres1~0#1 := 0; 998951#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998947#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 998943#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 998939#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 998932#L544-36 assume !(1 == ~t1_pc~0); 998927#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 998922#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 998914#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 998907#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 998900#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 998894#L563-36 assume 1 == ~t2_pc~0; 998888#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 998881#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 998874#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 998868#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 998862#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 998855#L582-36 assume !(1 == ~t3_pc~0); 998848#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 998842#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 998835#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 998829#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 998822#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 998816#L601-36 assume 1 == ~t4_pc~0; 998810#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 998725#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 998531#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 998526#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 998521#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 998514#L620-36 assume !(1 == ~t5_pc~0); 998508#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 998501#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 998493#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998486#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 998480#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 998479#L639-36 assume 1 == ~t6_pc~0; 998451#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 998447#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998445#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 998443#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 995767#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 995764#L658-36 assume !(1 == ~t7_pc~0); 995761#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 995759#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 995757#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 995755#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 995752#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 995750#L677-36 assume !(1 == ~t8_pc~0); 995748#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 995746#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 995744#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 995742#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 995740#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 995738#L696-36 assume !(1 == ~t9_pc~0); 995736#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 998518#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 998440#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 995720#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 995717#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 995715#L715-36 assume !(1 == ~t10_pc~0); 995713#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 995711#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 995709#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 995707#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 995705#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 995703#L734-36 assume 1 == ~t11_pc~0; 995700#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 995697#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 995695#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 995693#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 995691#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 995689#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 995686#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 995682#L1218-3 assume !(1 == ~T2_E~0); 995680#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 995678#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 995676#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 995674#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 995672#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 995670#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 995668#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 995664#L1258-3 assume !(1 == ~T10_E~0); 995662#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 995660#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 995658#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 995654#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 995652#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 995650#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 995648#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 995646#L1298-3 assume !(1 == ~E_7~0); 995644#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 995642#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 995640#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 995638#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 995636#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 995634#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 995621#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 995619#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 995617#L1663 assume !(0 == start_simulation_~tmp~3#1); 995615#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 995604#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 995599#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 995598#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 995596#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 995594#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 995592#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 995589#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 995587#L1644-2 [2021-11-22 15:27:49,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:49,720 INFO L85 PathProgramCache]: Analyzing trace with hash 185772820, now seen corresponding path program 1 times [2021-11-22 15:27:49,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:49,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81946175] [2021-11-22 15:27:49,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:49,722 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:49,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:49,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:49,860 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:49,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81946175] [2021-11-22 15:27:49,860 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81946175] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:49,860 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:49,861 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:49,861 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108263379] [2021-11-22 15:27:49,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:49,861 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:49,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:49,862 INFO L85 PathProgramCache]: Analyzing trace with hash 760377663, now seen corresponding path program 1 times [2021-11-22 15:27:49,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:49,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266389791] [2021-11-22 15:27:49,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:49,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:49,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:49,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:49,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:49,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266389791] [2021-11-22 15:27:49,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266389791] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:49,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:49,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:49,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804032854] [2021-11-22 15:27:49,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:49,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:49,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:49,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:49,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:49,923 INFO L87 Difference]: Start difference. First operand 215956 states and 301795 transitions. cyclomatic complexity: 85903 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:50,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:50,658 INFO L93 Difference]: Finished difference Result 215947 states and 301237 transitions. [2021-11-22 15:27:50,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:50,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215947 states and 301237 transitions. [2021-11-22 15:27:52,540 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 215076 [2021-11-22 15:27:53,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215947 states to 215947 states and 301237 transitions. [2021-11-22 15:27:53,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215947 [2021-11-22 15:27:53,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215947 [2021-11-22 15:27:53,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215947 states and 301237 transitions. [2021-11-22 15:27:53,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:53,327 INFO L681 BuchiCegarLoop]: Abstraction has 215947 states and 301237 transitions. [2021-11-22 15:27:53,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215947 states and 301237 transitions. [2021-11-22 15:27:55,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215947 to 108040. [2021-11-22 15:27:55,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.3949555720103666) internal successors, (150711), 108039 states have internal predecessors, (150711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:55,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 150711 transitions. [2021-11-22 15:27:55,821 INFO L704 BuchiCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2021-11-22 15:27:55,821 INFO L587 BuchiCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2021-11-22 15:27:55,821 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-22 15:27:55,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 150711 transitions. [2021-11-22 15:27:56,177 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2021-11-22 15:27:56,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:27:56,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:27:56,180 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:56,180 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:27:56,181 INFO L791 eck$LassoCheckResult]: Stem: 1258556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1258557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1258566#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258567#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1258292#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1258293#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1258155#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1258059#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1257769#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1257408#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1257409#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1257458#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1257459#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1258432#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1258433#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1258482#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1257878#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1257879#L1090 assume !(0 == ~M_E~0); 1257927#L1090-2 assume !(0 == ~T1_E~0); 1257928#L1095-1 assume !(0 == ~T2_E~0); 1258639#L1100-1 assume !(0 == ~T3_E~0); 1258640#L1105-1 assume !(0 == ~T4_E~0); 1257688#L1110-1 assume !(0 == ~T5_E~0); 1257689#L1115-1 assume !(0 == ~T6_E~0); 1258103#L1120-1 assume !(0 == ~T7_E~0); 1258403#L1125-1 assume !(0 == ~T8_E~0); 1259076#L1130-1 assume !(0 == ~T9_E~0); 1258661#L1135-1 assume !(0 == ~T10_E~0); 1257886#L1140-1 assume !(0 == ~T11_E~0); 1257887#L1145-1 assume !(0 == ~E_1~0); 1258582#L1150-1 assume !(0 == ~E_2~0); 1258075#L1155-1 assume !(0 == ~E_3~0); 1258076#L1160-1 assume !(0 == ~E_4~0); 1258165#L1165-1 assume !(0 == ~E_5~0); 1258166#L1170-1 assume !(0 == ~E_6~0); 1258894#L1175-1 assume !(0 == ~E_7~0); 1258246#L1180-1 assume !(0 == ~E_8~0); 1258247#L1185-1 assume !(0 == ~E_9~0); 1257880#L1190-1 assume !(0 == ~E_10~0); 1257881#L1195-1 assume !(0 == ~E_11~0); 1258260#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1258098#L525 assume !(1 == ~m_pc~0); 1257496#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1257497#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1258264#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1258265#L1350 assume !(0 != activate_threads_~tmp~1#1); 1257867#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1257868#L544 assume !(1 == ~t1_pc~0); 1258099#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1258100#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1258579#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1257708#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1257709#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1258370#L563 assume !(1 == ~t2_pc~0); 1258568#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1257517#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1257518#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1257955#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1257956#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1258457#L582 assume !(1 == ~t3_pc~0); 1258580#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1258996#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1258997#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1258908#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1257588#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1257589#L601 assume !(1 == ~t4_pc~0); 1258604#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1258104#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1258105#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1258596#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1258597#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1258986#L620 assume !(1 == ~t5_pc~0); 1258423#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1258424#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1258400#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1258401#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1259018#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259019#L639 assume !(1 == ~t6_pc~0); 1258399#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1257992#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1257993#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1258910#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1258109#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1258110#L658 assume !(1 == ~t7_pc~0); 1258315#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1258316#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258441#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1258442#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1257874#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1257875#L677 assume !(1 == ~t8_pc~0); 1257901#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1257673#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1257674#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1257949#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1257950#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1258716#L696 assume !(1 == ~t9_pc~0); 1258386#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1258387#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1258490#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1258412#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1258413#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1258644#L715 assume !(1 == ~t10_pc~0); 1258935#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1258507#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1258373#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1258374#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1258237#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1257661#L734 assume !(1 == ~t11_pc~0); 1257662#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1258172#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1258251#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1257398#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1257399#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1258475#L1213 assume !(1 == ~M_E~0); 1258235#L1213-2 assume !(1 == ~T1_E~0); 1258236#L1218-1 assume !(1 == ~T2_E~0); 1257433#L1223-1 assume !(1 == ~T3_E~0); 1257434#L1228-1 assume !(1 == ~T4_E~0); 1258211#L1233-1 assume !(1 == ~T5_E~0); 1259020#L1238-1 assume !(1 == ~T6_E~0); 1258594#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1258595#L1248-1 assume !(1 == ~T8_E~0); 1258648#L1253-1 assume !(1 == ~T9_E~0); 1258649#L1258-1 assume !(1 == ~T10_E~0); 1258622#L1263-1 assume !(1 == ~T11_E~0); 1258623#L1268-1 assume !(1 == ~E_1~0); 1258428#L1273-1 assume !(1 == ~E_2~0); 1258429#L1278-1 assume !(1 == ~E_3~0); 1257990#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1257991#L1288-1 assume !(1 == ~E_5~0); 1258769#L1293-1 assume !(1 == ~E_6~0); 1258725#L1298-1 assume !(1 == ~E_7~0); 1258460#L1303-1 assume !(1 == ~E_8~0); 1258001#L1308-1 assume !(1 == ~E_9~0); 1257892#L1313-1 assume !(1 == ~E_10~0); 1257893#L1318-1 assume !(1 == ~E_11~0); 1257902#L1323-1 assume { :end_inline_reset_delta_events } true; 1257903#L1644-2 [2021-11-22 15:27:56,182 INFO L793 eck$LassoCheckResult]: Loop: 1257903#L1644-2 assume !false; 1310658#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1310653#L1065 assume !false; 1310652#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1310649#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1310639#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1310638#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1310636#L906 assume !(0 != eval_~tmp~0#1); 1310637#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1310952#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1310951#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1310950#L1090-5 assume !(0 == ~T1_E~0); 1310949#L1095-3 assume !(0 == ~T2_E~0); 1310948#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1310947#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1310946#L1110-3 assume !(0 == ~T5_E~0); 1310945#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1310944#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1310943#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1310942#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1310941#L1135-3 assume !(0 == ~T10_E~0); 1310940#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1310938#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1310937#L1150-3 assume !(0 == ~E_2~0); 1310936#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1310934#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1310933#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1310932#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1310931#L1175-3 assume !(0 == ~E_7~0); 1310930#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1310929#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1310928#L1190-3 assume !(0 == ~E_10~0); 1310927#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1310926#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1310925#L525-36 assume !(1 == ~m_pc~0); 1310924#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1310923#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1310922#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1310920#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1310918#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1310916#L544-36 assume !(1 == ~t1_pc~0); 1310914#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1310912#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1310910#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1310908#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1310906#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1310904#L563-36 assume !(1 == ~t2_pc~0); 1310901#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1310899#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1310897#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1310895#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1310892#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1310890#L582-36 assume !(1 == ~t3_pc~0); 1310888#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1310886#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1310884#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1310882#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1310880#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1310878#L601-36 assume 1 == ~t4_pc~0; 1310876#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1310873#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1310871#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1310869#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1310866#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1310864#L620-36 assume !(1 == ~t5_pc~0); 1310862#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1310860#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1310858#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1310856#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1310854#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1310852#L639-36 assume !(1 == ~t6_pc~0); 1310849#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1310847#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1310845#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1310843#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1310840#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1310838#L658-36 assume !(1 == ~t7_pc~0); 1310835#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1310833#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1310831#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1310828#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1310826#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1310824#L677-36 assume !(1 == ~t8_pc~0); 1310822#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1310820#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1310818#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1310816#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1310814#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1310812#L696-36 assume !(1 == ~t9_pc~0); 1310808#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1310806#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1310804#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1310800#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1310797#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1310795#L715-36 assume !(1 == ~t10_pc~0); 1310793#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1310790#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1310788#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1310786#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1310784#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1310782#L734-36 assume 1 == ~t11_pc~0; 1310780#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1310777#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1310775#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1310773#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1310770#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1310768#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1310766#L1213-5 assume !(1 == ~T1_E~0); 1310764#L1218-3 assume !(1 == ~T2_E~0); 1310762#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1310760#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1310758#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1310756#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1310754#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1310752#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1310750#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1310748#L1258-3 assume !(1 == ~T10_E~0); 1310746#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1310744#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1310742#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1310740#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1310738#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1310736#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1310734#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1310732#L1298-3 assume !(1 == ~E_7~0); 1310730#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1310728#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1310726#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1310724#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1310722#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1310720#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1310707#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1310705#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1310703#L1663 assume !(0 == start_simulation_~tmp~3#1); 1310701#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1310693#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1310684#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1310680#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1310675#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1310670#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1310666#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1310661#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1257903#L1644-2 [2021-11-22 15:27:56,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:56,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2021-11-22 15:27:56,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:56,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623904458] [2021-11-22 15:27:56,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:56,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:56,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:56,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:56,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:56,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623904458] [2021-11-22 15:27:56,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623904458] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:56,828 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:56,828 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 15:27:56,828 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127877189] [2021-11-22 15:27:56,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:56,829 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:27:56,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:27:56,830 INFO L85 PathProgramCache]: Analyzing trace with hash -758319487, now seen corresponding path program 1 times [2021-11-22 15:27:56,830 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:27:56,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604756352] [2021-11-22 15:27:56,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:27:56,830 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:27:56,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:27:56,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:27:56,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:27:56,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604756352] [2021-11-22 15:27:56,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604756352] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:27:56,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:27:56,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:27:56,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690889403] [2021-11-22 15:27:56,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:27:56,866 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:27:56,866 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:27:56,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 15:27:56,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 15:27:56,867 INFO L87 Difference]: Start difference. First operand 108040 states and 150711 transitions. cyclomatic complexity: 42703 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:27:57,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:27:57,306 INFO L93 Difference]: Finished difference Result 108040 states and 150385 transitions. [2021-11-22 15:27:57,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 15:27:57,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108040 states and 150385 transitions. [2021-11-22 15:27:57,774 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2021-11-22 15:27:58,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108040 states to 108040 states and 150385 transitions. [2021-11-22 15:27:58,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108040 [2021-11-22 15:27:58,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108040 [2021-11-22 15:27:58,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108040 states and 150385 transitions. [2021-11-22 15:27:58,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:27:58,182 INFO L681 BuchiCegarLoop]: Abstraction has 108040 states and 150385 transitions. [2021-11-22 15:27:58,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108040 states and 150385 transitions. [2021-11-22 15:27:59,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108040 to 108040. [2021-11-22 15:27:59,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.39193817104776) internal successors, (150385), 108039 states have internal predecessors, (150385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:28:00,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 150385 transitions. [2021-11-22 15:28:00,092 INFO L704 BuchiCegarLoop]: Abstraction has 108040 states and 150385 transitions. [2021-11-22 15:28:00,092 INFO L587 BuchiCegarLoop]: Abstraction has 108040 states and 150385 transitions. [2021-11-22 15:28:00,092 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-22 15:28:00,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 150385 transitions. [2021-11-22 15:28:00,409 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2021-11-22 15:28:00,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:28:00,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:28:00,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:28:00,413 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:28:00,413 INFO L791 eck$LassoCheckResult]: Stem: 1474635#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1474636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1474644#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1474645#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1474372#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1474373#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1474239#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1474148#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1473858#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1473497#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1473498#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1473546#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1473547#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1474511#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1474512#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1474557#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1473967#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1473968#L1090 assume !(0 == ~M_E~0); 1474012#L1090-2 assume !(0 == ~T1_E~0); 1474013#L1095-1 assume !(0 == ~T2_E~0); 1474717#L1100-1 assume !(0 == ~T3_E~0); 1474718#L1105-1 assume !(0 == ~T4_E~0); 1473774#L1110-1 assume !(0 == ~T5_E~0); 1473775#L1115-1 assume !(0 == ~T6_E~0); 1474188#L1120-1 assume !(0 == ~T7_E~0); 1474485#L1125-1 assume !(0 == ~T8_E~0); 1475135#L1130-1 assume !(0 == ~T9_E~0); 1474744#L1135-1 assume !(0 == ~T10_E~0); 1473972#L1140-1 assume !(0 == ~T11_E~0); 1473973#L1145-1 assume !(0 == ~E_1~0); 1474662#L1150-1 assume !(0 == ~E_2~0); 1474162#L1155-1 assume !(0 == ~E_3~0); 1474163#L1160-1 assume !(0 == ~E_4~0); 1474247#L1165-1 assume !(0 == ~E_5~0); 1474248#L1170-1 assume !(0 == ~E_6~0); 1474974#L1175-1 assume !(0 == ~E_7~0); 1474327#L1180-1 assume !(0 == ~E_8~0); 1474328#L1185-1 assume !(0 == ~E_9~0); 1473969#L1190-1 assume !(0 == ~E_10~0); 1473970#L1195-1 assume !(0 == ~E_11~0); 1474341#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1474178#L525 assume !(1 == ~m_pc~0); 1473584#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1473585#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1474344#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1474345#L1350 assume !(0 != activate_threads_~tmp~1#1); 1473955#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1473956#L544 assume !(1 == ~t1_pc~0); 1474186#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1474187#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1474659#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1473796#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1473797#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1474453#L563 assume !(1 == ~t2_pc~0); 1474646#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1473606#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1473607#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1474041#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1474042#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474536#L582 assume !(1 == ~t3_pc~0); 1474660#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1475072#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1475073#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1474985#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1473677#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1473678#L601 assume !(1 == ~t4_pc~0); 1474680#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1474189#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1474190#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1474674#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1474675#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1475054#L620 assume !(1 == ~t5_pc~0); 1474501#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1474502#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1474481#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1474482#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1475091#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1475092#L639 assume !(1 == ~t6_pc~0); 1474483#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1474079#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1474080#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1474991#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1474196#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1474197#L658 assume !(1 == ~t7_pc~0); 1474396#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1474397#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1474522#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1474523#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1473963#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1473964#L677 assume !(1 == ~t8_pc~0); 1473987#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1473755#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1473756#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1474038#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1474039#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1474799#L696 assume !(1 == ~t9_pc~0); 1474464#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1474465#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1474568#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1474489#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1474490#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1474723#L715 assume !(1 == ~t10_pc~0); 1475014#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1474587#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1474456#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1474457#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1474318#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1473747#L734 assume !(1 == ~t11_pc~0); 1473748#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1474251#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1474332#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1473485#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1473486#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1474556#L1213 assume !(1 == ~M_E~0); 1474314#L1213-2 assume !(1 == ~T1_E~0); 1474315#L1218-1 assume !(1 == ~T2_E~0); 1473522#L1223-1 assume !(1 == ~T3_E~0); 1473523#L1228-1 assume !(1 == ~T4_E~0); 1474293#L1233-1 assume !(1 == ~T5_E~0); 1475093#L1238-1 assume !(1 == ~T6_E~0); 1474672#L1243-1 assume !(1 == ~T7_E~0); 1474673#L1248-1 assume !(1 == ~T8_E~0); 1474728#L1253-1 assume !(1 == ~T9_E~0); 1474729#L1258-1 assume !(1 == ~T10_E~0); 1474703#L1263-1 assume !(1 == ~T11_E~0); 1474704#L1268-1 assume !(1 == ~E_1~0); 1474509#L1273-1 assume !(1 == ~E_2~0); 1474510#L1278-1 assume !(1 == ~E_3~0); 1474077#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1474078#L1288-1 assume !(1 == ~E_5~0); 1474853#L1293-1 assume !(1 == ~E_6~0); 1474804#L1298-1 assume !(1 == ~E_7~0); 1474539#L1303-1 assume !(1 == ~E_8~0); 1474088#L1308-1 assume !(1 == ~E_9~0); 1473978#L1313-1 assume !(1 == ~E_10~0); 1473979#L1318-1 assume !(1 == ~E_11~0); 1473988#L1323-1 assume { :end_inline_reset_delta_events } true; 1473989#L1644-2 [2021-11-22 15:28:00,414 INFO L793 eck$LassoCheckResult]: Loop: 1473989#L1644-2 assume !false; 1548153#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1548146#L1065 assume !false; 1548140#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1547714#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1547703#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1547701#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1547698#L906 assume !(0 != eval_~tmp~0#1); 1547699#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1553334#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1553327#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1553319#L1090-5 assume !(0 == ~T1_E~0); 1553311#L1095-3 assume !(0 == ~T2_E~0); 1551512#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1551510#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1551508#L1110-3 assume !(0 == ~T5_E~0); 1551505#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1551503#L1120-3 assume !(0 == ~T7_E~0); 1551501#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1551499#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1551497#L1135-3 assume !(0 == ~T10_E~0); 1551495#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1551493#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1551491#L1150-3 assume !(0 == ~E_2~0); 1551489#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1551487#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1551485#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1551483#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1551479#L1175-3 assume !(0 == ~E_7~0); 1551477#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1551475#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1551473#L1190-3 assume !(0 == ~E_10~0); 1551470#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1551468#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1551466#L525-36 assume !(1 == ~m_pc~0); 1551464#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1551462#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1551460#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1551458#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1551456#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1551454#L544-36 assume !(1 == ~t1_pc~0); 1551451#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1551449#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1551447#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1551445#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1551443#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1551442#L563-36 assume 1 == ~t2_pc~0; 1551439#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1551436#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1551434#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1551429#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1551428#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1551427#L582-36 assume !(1 == ~t3_pc~0); 1551426#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1551425#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1551424#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1551423#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1551421#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1551420#L601-36 assume 1 == ~t4_pc~0; 1551418#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1551413#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1551411#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1551409#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1551407#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1551404#L620-36 assume !(1 == ~t5_pc~0); 1551402#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1551400#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1551398#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1551396#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1551394#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1551392#L639-36 assume 1 == ~t6_pc~0; 1551389#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1551385#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1551383#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1551381#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1551379#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1551377#L658-36 assume !(1 == ~t7_pc~0); 1550936#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1550935#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1550933#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1550931#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1550926#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1550924#L677-36 assume !(1 == ~t8_pc~0); 1548555#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1548551#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1548547#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1548542#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1548537#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1548533#L696-36 assume !(1 == ~t9_pc~0); 1548529#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1548524#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1548519#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1548514#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1548508#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1548502#L715-36 assume !(1 == ~t10_pc~0); 1548495#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1548490#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1548485#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1548480#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1548475#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1548470#L734-36 assume 1 == ~t11_pc~0; 1548464#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1548458#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1548453#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1548448#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1548442#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1548437#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1548432#L1213-5 assume !(1 == ~T1_E~0); 1548427#L1218-3 assume !(1 == ~T2_E~0); 1548422#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1548417#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1548412#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1548406#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1548400#L1243-3 assume !(1 == ~T7_E~0); 1548395#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1548390#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1548385#L1258-3 assume !(1 == ~T10_E~0); 1548380#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1548375#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1548369#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1548364#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1548359#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1548354#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1548349#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1548344#L1298-3 assume !(1 == ~E_7~0); 1548337#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1548331#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1548325#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1548319#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1548315#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1548272#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1548256#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1548251#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1548244#L1663 assume !(0 == start_simulation_~tmp~3#1); 1548242#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1548195#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1548186#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1548181#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1548177#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1548173#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1548169#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1548163#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1473989#L1644-2 [2021-11-22 15:28:00,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:28:00,415 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2021-11-22 15:28:00,415 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:28:00,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280767029] [2021-11-22 15:28:00,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:28:00,416 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:28:00,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:28:00,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:28:00,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:28:00,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280767029] [2021-11-22 15:28:00,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280767029] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:28:00,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:28:00,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:28:00,467 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155642605] [2021-11-22 15:28:00,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:28:00,467 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:28:00,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:28:00,468 INFO L85 PathProgramCache]: Analyzing trace with hash 51106375, now seen corresponding path program 1 times [2021-11-22 15:28:00,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:28:00,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973261260] [2021-11-22 15:28:00,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:28:00,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:28:00,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:28:00,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:28:00,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:28:00,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973261260] [2021-11-22 15:28:00,524 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973261260] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:28:00,524 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:28:00,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:28:00,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573035906] [2021-11-22 15:28:00,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:28:00,525 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:28:00,525 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:28:00,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:28:00,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:28:00,526 INFO L87 Difference]: Start difference. First operand 108040 states and 150385 transitions. cyclomatic complexity: 42377 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:28:02,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 15:28:02,254 INFO L93 Difference]: Finished difference Result 226717 states and 313610 transitions. [2021-11-22 15:28:02,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 15:28:02,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 226717 states and 313610 transitions. [2021-11-22 15:28:03,216 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 225640 [2021-11-22 15:28:04,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 226717 states to 226717 states and 313610 transitions. [2021-11-22 15:28:04,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 226717 [2021-11-22 15:28:04,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 226717 [2021-11-22 15:28:04,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226717 states and 313610 transitions. [2021-11-22 15:28:04,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 15:28:04,921 INFO L681 BuchiCegarLoop]: Abstraction has 226717 states and 313610 transitions. [2021-11-22 15:28:05,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226717 states and 313610 transitions. [2021-11-22 15:28:07,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226717 to 119829. [2021-11-22 15:28:07,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119829 states, 119829 states have (on average 1.3851822179939748) internal successors, (165985), 119828 states have internal predecessors, (165985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 15:28:07,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119829 states to 119829 states and 165985 transitions. [2021-11-22 15:28:07,399 INFO L704 BuchiCegarLoop]: Abstraction has 119829 states and 165985 transitions. [2021-11-22 15:28:07,399 INFO L587 BuchiCegarLoop]: Abstraction has 119829 states and 165985 transitions. [2021-11-22 15:28:07,399 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-22 15:28:07,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119829 states and 165985 transitions. [2021-11-22 15:28:07,747 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119222 [2021-11-22 15:28:07,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 15:28:07,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 15:28:07,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:28:07,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 15:28:07,751 INFO L791 eck$LassoCheckResult]: Stem: 1809413#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1809414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1809423#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1809424#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1809148#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1809149#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1809013#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808920#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1808630#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1808266#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1808267#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1808315#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1808316#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1809289#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1809290#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1809334#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1808736#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1808737#L1090 assume !(0 == ~M_E~0); 1808782#L1090-2 assume !(0 == ~T1_E~0); 1808783#L1095-1 assume !(0 == ~T2_E~0); 1809499#L1100-1 assume !(0 == ~T3_E~0); 1809500#L1105-1 assume !(0 == ~T4_E~0); 1808545#L1110-1 assume !(0 == ~T5_E~0); 1808546#L1115-1 assume !(0 == ~T6_E~0); 1808961#L1120-1 assume !(0 == ~T7_E~0); 1809263#L1125-1 assume !(0 == ~T8_E~0); 1809909#L1130-1 assume !(0 == ~T9_E~0); 1809522#L1135-1 assume !(0 == ~T10_E~0); 1808742#L1140-1 assume !(0 == ~T11_E~0); 1808743#L1145-1 assume !(0 == ~E_1~0); 1809446#L1150-1 assume !(0 == ~E_2~0); 1808936#L1155-1 assume !(0 == ~E_3~0); 1808937#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1809895#L1165-1 assume !(0 == ~E_5~0); 1809752#L1170-1 assume !(0 == ~E_6~0); 1809753#L1175-1 assume !(0 == ~E_7~0); 1810053#L1180-1 assume !(0 == ~E_8~0); 1810052#L1185-1 assume !(0 == ~E_9~0); 1808738#L1190-1 assume !(0 == ~E_10~0); 1808739#L1195-1 assume !(0 == ~E_11~0); 1809116#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1808951#L525 assume !(1 == ~m_pc~0); 1808353#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1808354#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1809119#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1809120#L1350 assume !(0 != activate_threads_~tmp~1#1); 1808724#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1808725#L544 assume !(1 == ~t1_pc~0); 1810043#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1809441#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1809442#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1808567#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1808568#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1810042#L563 assume !(1 == ~t2_pc~0); 1810041#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1808377#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1808378#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1808811#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1808812#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1809443#L582 assume !(1 == ~t3_pc~0); 1809444#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1809844#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1809845#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1809764#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1808447#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1808448#L601 assume !(1 == ~t4_pc~0); 1810037#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1810036#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1810035#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1810034#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1810033#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1810032#L620 assume !(1 == ~t5_pc~0); 1810031#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1810030#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1810029#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1810028#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1810027#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1810026#L639 assume !(1 == ~t6_pc~0); 1810024#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1810023#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1810022#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1810021#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1810020#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1810019#L658 assume !(1 == ~t7_pc~0); 1810017#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1810016#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1810015#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1810014#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1810013#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1810012#L677 assume !(1 == ~t8_pc~0); 1810011#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1810010#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1810009#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1810008#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1810007#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1810006#L696 assume !(1 == ~t9_pc~0); 1810005#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1810003#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1810001#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1809998#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1809997#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1809996#L715 assume !(1 == ~t10_pc~0); 1809995#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1809994#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1809993#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1809992#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1809991#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1809990#L734 assume !(1 == ~t11_pc~0); 1809988#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1809987#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1809986#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1809985#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1809984#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1809983#L1213 assume !(1 == ~M_E~0); 1809982#L1213-2 assume !(1 == ~T1_E~0); 1809981#L1218-1 assume !(1 == ~T2_E~0); 1809980#L1223-1 assume !(1 == ~T3_E~0); 1809979#L1228-1 assume !(1 == ~T4_E~0); 1809978#L1233-1 assume !(1 == ~T5_E~0); 1809977#L1238-1 assume !(1 == ~T6_E~0); 1809976#L1243-1 assume !(1 == ~T7_E~0); 1809975#L1248-1 assume !(1 == ~T8_E~0); 1809974#L1253-1 assume !(1 == ~T9_E~0); 1809973#L1258-1 assume !(1 == ~T10_E~0); 1809972#L1263-1 assume !(1 == ~T11_E~0); 1809971#L1268-1 assume !(1 == ~E_1~0); 1809970#L1273-1 assume !(1 == ~E_2~0); 1809969#L1278-1 assume !(1 == ~E_3~0); 1809968#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1808850#L1288-1 assume !(1 == ~E_5~0); 1809630#L1293-1 assume !(1 == ~E_6~0); 1809582#L1298-1 assume !(1 == ~E_7~0); 1809317#L1303-1 assume !(1 == ~E_8~0); 1808861#L1308-1 assume !(1 == ~E_9~0); 1808748#L1313-1 assume !(1 == ~E_10~0); 1808749#L1318-1 assume !(1 == ~E_11~0); 1808758#L1323-1 assume { :end_inline_reset_delta_events } true; 1808759#L1644-2 [2021-11-22 15:28:07,751 INFO L793 eck$LassoCheckResult]: Loop: 1808759#L1644-2 assume !false; 1902830#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1902825#L1065 assume !false; 1902824#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1902821#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1902811#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1902810#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1902809#L906 assume !(0 != eval_~tmp~0#1); 1828375#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1828373#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1828371#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1828369#L1090-5 assume !(0 == ~T1_E~0); 1828367#L1095-3 assume !(0 == ~T2_E~0); 1828365#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1828363#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1828361#L1110-3 assume !(0 == ~T5_E~0); 1828359#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1828357#L1120-3 assume !(0 == ~T7_E~0); 1828355#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1828353#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1828351#L1135-3 assume !(0 == ~T10_E~0); 1828349#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1828347#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1828345#L1150-3 assume !(0 == ~E_2~0); 1828343#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1828339#L1160-3 assume !(0 == ~E_4~0); 1828341#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1828763#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1828760#L1175-3 assume !(0 == ~E_7~0); 1828761#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1828755#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1828752#L1190-3 assume !(0 == ~E_10~0); 1828753#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1828747#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1828744#L525-36 assume !(1 == ~m_pc~0); 1828742#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1828740#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1828738#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1828736#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1828734#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1828732#L544-36 assume !(1 == ~t1_pc~0); 1828730#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1828728#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1828726#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1828724#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1828722#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1828720#L563-36 assume 1 == ~t2_pc~0; 1828718#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1828715#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1828713#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1828711#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1828709#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1828707#L582-36 assume !(1 == ~t3_pc~0); 1828705#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1828703#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1828701#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1828699#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1828697#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1828694#L601-36 assume !(1 == ~t4_pc~0); 1828270#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1828691#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1828689#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1828687#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1828685#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1828683#L620-36 assume !(1 == ~t5_pc~0); 1828681#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1828679#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1828677#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1828675#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1828673#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1828671#L639-36 assume 1 == ~t6_pc~0; 1828669#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1828666#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1828663#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1828661#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1828658#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1828659#L658-36 assume !(1 == ~t7_pc~0); 1903015#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1903011#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1903007#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1903005#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1903003#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1903000#L677-36 assume !(1 == ~t8_pc~0); 1902998#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1902996#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1902994#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1902992#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1902989#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1902987#L696-36 assume 1 == ~t9_pc~0; 1902985#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1902986#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1903010#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1902976#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1902972#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1902968#L715-36 assume !(1 == ~t10_pc~0); 1902967#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1902966#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1902965#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1902963#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1902962#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1902961#L734-36 assume 1 == ~t11_pc~0; 1902957#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1902954#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1902952#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1902950#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1902946#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1902944#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1902942#L1213-5 assume !(1 == ~T1_E~0); 1902940#L1218-3 assume !(1 == ~T2_E~0); 1902937#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1902935#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1902933#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1902931#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1902929#L1243-3 assume !(1 == ~T7_E~0); 1902927#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1902925#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1902923#L1258-3 assume !(1 == ~T10_E~0); 1902921#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1902916#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1902912#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1902908#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1902894#L1283-3 assume !(1 == ~E_4~0); 1902892#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1902890#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1902888#L1298-3 assume !(1 == ~E_7~0); 1902886#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1902884#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1902882#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1902880#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1902878#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1902876#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1902863#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1902861#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1902860#L1663 assume !(0 == start_simulation_~tmp~3#1); 1902858#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1902849#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1902841#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1902839#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1902837#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1902836#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1902835#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1902834#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1808759#L1644-2 [2021-11-22 15:28:07,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:28:07,752 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2021-11-22 15:28:07,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:28:07,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667898986] [2021-11-22 15:28:07,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:28:07,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:28:07,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:28:07,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:28:07,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:28:07,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667898986] [2021-11-22 15:28:07,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667898986] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:28:07,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:28:07,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 15:28:07,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159409160] [2021-11-22 15:28:07,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:28:07,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 15:28:07,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 15:28:07,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1324821555, now seen corresponding path program 1 times [2021-11-22 15:28:07,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 15:28:07,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253222013] [2021-11-22 15:28:07,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 15:28:07,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 15:28:07,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 15:28:07,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 15:28:07,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 15:28:07,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253222013] [2021-11-22 15:28:07,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253222013] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 15:28:07,828 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 15:28:07,828 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 15:28:07,829 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049226965] [2021-11-22 15:28:07,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 15:28:07,829 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 15:28:07,829 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 15:28:07,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 15:28:07,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 15:28:07,830 INFO L87 Difference]: Start difference. First operand 119829 states and 165985 transitions. cyclomatic complexity: 46188 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)