./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aef121e0 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-aef121e [2021-11-22 16:03:33,997 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-22 16:03:34,001 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-22 16:03:34,068 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-22 16:03:34,068 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-22 16:03:34,074 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-22 16:03:34,076 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-22 16:03:34,080 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-22 16:03:34,083 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-22 16:03:34,090 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-22 16:03:34,091 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-22 16:03:34,093 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-22 16:03:34,094 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-22 16:03:34,097 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-22 16:03:34,100 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-22 16:03:34,106 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-22 16:03:34,108 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-22 16:03:34,109 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-22 16:03:34,112 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-22 16:03:34,123 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-22 16:03:34,125 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-22 16:03:34,127 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-22 16:03:34,131 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-22 16:03:34,132 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-22 16:03:34,136 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-22 16:03:34,137 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-22 16:03:34,137 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-22 16:03:34,139 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-22 16:03:34,140 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-22 16:03:34,142 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-22 16:03:34,142 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-22 16:03:34,143 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-22 16:03:34,146 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-22 16:03:34,147 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-22 16:03:34,149 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-22 16:03:34,149 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-22 16:03:34,150 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-22 16:03:34,151 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-22 16:03:34,151 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-22 16:03:34,152 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-22 16:03:34,153 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-22 16:03:34,154 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-22 16:03:34,205 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-22 16:03:34,206 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-22 16:03:34,207 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-22 16:03:34,207 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-22 16:03:34,209 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-22 16:03:34,209 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-22 16:03:34,209 INFO L138 SettingsManager]: * Use SBE=true [2021-11-22 16:03:34,210 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-22 16:03:34,210 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-22 16:03:34,210 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-22 16:03:34,211 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-22 16:03:34,212 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-22 16:03:34,212 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-22 16:03:34,212 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-22 16:03:34,213 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-22 16:03:34,213 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-22 16:03:34,213 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-22 16:03:34,213 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-22 16:03:34,213 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-22 16:03:34,214 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-22 16:03:34,214 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-22 16:03:34,214 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-22 16:03:34,214 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-22 16:03:34,215 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-22 16:03:34,215 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-22 16:03:34,215 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-22 16:03:34,217 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-22 16:03:34,217 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-22 16:03:34,217 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-22 16:03:34,218 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-22 16:03:34,218 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-22 16:03:34,218 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-22 16:03:34,220 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-22 16:03:34,220 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2021-11-22 16:03:34,568 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-22 16:03:34,599 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-22 16:03:34,602 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-22 16:03:34,603 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-22 16:03:34,605 INFO L275 PluginConnector]: CDTParser initialized [2021-11-22 16:03:34,606 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/../../sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-11-22 16:03:34,696 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/data/80eaf4772/690558e3d70a4f55a2fbb42d93a0bd22/FLAGe29adeb32 [2021-11-22 16:03:35,246 INFO L306 CDTParser]: Found 1 translation units. [2021-11-22 16:03:35,246 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-11-22 16:03:35,263 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/data/80eaf4772/690558e3d70a4f55a2fbb42d93a0bd22/FLAGe29adeb32 [2021-11-22 16:03:35,524 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/data/80eaf4772/690558e3d70a4f55a2fbb42d93a0bd22 [2021-11-22 16:03:35,527 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-22 16:03:35,529 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-22 16:03:35,532 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-22 16:03:35,532 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-22 16:03:35,536 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-22 16:03:35,537 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 04:03:35" (1/1) ... [2021-11-22 16:03:35,538 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@146ee43e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:35, skipping insertion in model container [2021-11-22 16:03:35,538 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 04:03:35" (1/1) ... [2021-11-22 16:03:35,547 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-22 16:03:35,596 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-22 16:03:35,793 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-11-22 16:03:35,976 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-22 16:03:35,988 INFO L203 MainTranslator]: Completed pre-run [2021-11-22 16:03:36,000 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-11-22 16:03:36,092 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-22 16:03:36,121 INFO L208 MainTranslator]: Completed translation [2021-11-22 16:03:36,122 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36 WrapperNode [2021-11-22 16:03:36,122 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-22 16:03:36,124 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-22 16:03:36,124 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-22 16:03:36,124 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-22 16:03:36,132 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,157 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,284 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2021-11-22 16:03:36,284 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-22 16:03:36,285 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-22 16:03:36,285 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-22 16:03:36,286 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-22 16:03:36,295 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,296 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,306 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,307 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,367 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,433 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,443 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,461 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-22 16:03:36,463 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-22 16:03:36,464 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-22 16:03:36,465 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-22 16:03:36,466 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (1/1) ... [2021-11-22 16:03:36,474 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-22 16:03:36,490 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/z3 [2021-11-22 16:03:36,511 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-22 16:03:36,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d5209f32-3894-4232-80f3-09d28ce45448/bin/uautomizer-w2VwFs6gM0/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-22 16:03:36,567 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-22 16:03:36,567 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-22 16:03:36,567 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-22 16:03:36,567 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-22 16:03:36,777 INFO L236 CfgBuilder]: Building ICFG [2021-11-22 16:03:36,779 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-22 16:03:39,216 INFO L277 CfgBuilder]: Performing block encoding [2021-11-22 16:03:39,288 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-22 16:03:39,288 INFO L301 CfgBuilder]: Removed 17 assume(true) statements. [2021-11-22 16:03:39,320 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 04:03:39 BoogieIcfgContainer [2021-11-22 16:03:39,321 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-22 16:03:39,327 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-22 16:03:39,327 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-22 16:03:39,346 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-22 16:03:39,351 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 16:03:39,351 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.11 04:03:35" (1/3) ... [2021-11-22 16:03:39,352 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4ab926e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 04:03:39, skipping insertion in model container [2021-11-22 16:03:39,352 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 16:03:39,352 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 04:03:36" (2/3) ... [2021-11-22 16:03:39,353 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4ab926e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 04:03:39, skipping insertion in model container [2021-11-22 16:03:39,353 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-22 16:03:39,353 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 04:03:39" (3/3) ... [2021-11-22 16:03:39,354 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2021-11-22 16:03:39,414 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-22 16:03:39,415 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-22 16:03:39,415 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-22 16:03:39,415 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-22 16:03:39,415 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-22 16:03:39,415 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-22 16:03:39,415 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-22 16:03:39,416 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-22 16:03:39,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:39,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2021-11-22 16:03:39,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:39,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:39,613 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:39,613 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:39,613 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-22 16:03:39,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:39,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2021-11-22 16:03:39,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:39,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:39,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:39,666 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:39,687 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1834#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1760#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1073#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1411#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1402#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 796#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 684#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 804#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 834#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 921#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1400#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 710#L1268-1true assume !(0 == ~T3_E~0); 1366#L1273-1true assume !(0 == ~T4_E~0); 1749#L1278-1true assume !(0 == ~T5_E~0); 1153#L1283-1true assume !(0 == ~T6_E~0); 1781#L1288-1true assume !(0 == ~T7_E~0); 1569#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1540#L1298-1true assume !(0 == ~T9_E~0); 1384#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1839#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1790#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 974#L1338-1true assume !(0 == ~E_4~0); 1113#L1343-1true assume !(0 == ~E_5~0); 1651#L1348-1true assume !(0 == ~E_6~0); 1668#L1353-1true assume !(0 == ~E_7~0); 726#L1358-1true assume !(0 == ~E_8~0); 1000#L1363-1true assume !(0 == ~E_9~0); 1062#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1102#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730#L607true assume 1 == ~m_pc~0; 1010#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1109#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1627#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 668#L1560true assume !(0 != activate_threads_~tmp~1#1); 1725#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1267#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1908#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1337#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1301#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1900#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 653#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1705#L664true assume 1 == ~t3_pc~0; 1634#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1127#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1420#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1628#L683true assume !(1 == ~t4_pc~0); 987#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 786#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 811#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1695#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 932#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1685#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 926#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1392#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1238#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1525#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 868#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 758#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 763#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1374#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1844#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 924#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1084#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1671#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1568#L778true assume 1 == ~t9_pc~0; 1342#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1274#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 734#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1307#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1182#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 697#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1391#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1512#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L835true assume 1 == ~t12_pc~0; 706#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1784#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1443#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1082#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1231#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1241#L1406-1true assume !(1 == ~T2_E~0); 859#L1411-1true assume !(1 == ~T3_E~0); 1612#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1015#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 746#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1773#L1451-1true assume !(1 == ~T11_E~0); 1108#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 745#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1768#L1471-1true assume !(1 == ~E_2~0); 1083#L1476-1true assume !(1 == ~E_3~0); 1315#L1481-1true assume !(1 == ~E_4~0); 1593#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 757#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1038#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1172#L1892-2true [2021-11-22 16:03:39,690 INFO L793 eck$LassoCheckResult]: Loop: 1172#L1892-2true assume !false; 1868#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1514#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 805#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1630#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1899#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1604#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1619#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1906#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1621#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1789#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1169#L1298-3true assume !(0 == ~T9_E~0); 1694#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1428#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1168#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 659#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1302#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1673#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1056#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1541#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1312#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1353#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1885#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 885#L1378-3true assume !(0 == ~E_12~0); 1460#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1100#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1767#L607-42true assume !(1 == ~m_pc~0); 912#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1076#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 698#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1220#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1472#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1131#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1574#L645-42true assume !(1 == ~t2_pc~0); 1024#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1696#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1253#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1662#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1624#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1475#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1016#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1788#L683-42true assume !(1 == ~t4_pc~0); 732#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 841#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1769#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1412#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1904#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1163#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1734#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1288#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume !(1 == ~t6_pc~0); 1582#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1620#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1588#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 651#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1896#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 674#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1175#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 809#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1750#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 733#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1613#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 781#L797-42true assume 1 == ~t10_pc~0; 239#L798-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 938#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1376#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1877#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 810#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1709#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1852#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume 1 == ~t12_pc~0; 846#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1244#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1838#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1237#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 950#L854-42true assume 1 == ~t13_pc~0; 1782#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1855#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1094#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1680#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume !(1 == ~T5_E~0); 1053#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1145#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1136#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume !(1 == ~T13_E~0); 1611#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1817#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1687#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1482#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume !(1 == ~E_8~0); 1595#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 882#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 875#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1719#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 970#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1881#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 761#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1305#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 907#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1025#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 843#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1349#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1172#L1892-2true [2021-11-22 16:03:39,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:39,702 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2021-11-22 16:03:39,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:39,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523308320] [2021-11-22 16:03:39,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:39,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:39,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:40,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:40,029 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:40,029 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523308320] [2021-11-22 16:03:40,030 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523308320] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:40,031 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:40,031 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:40,033 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223737220] [2021-11-22 16:03:40,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:40,039 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:40,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:40,040 INFO L85 PathProgramCache]: Analyzing trace with hash -1573044070, now seen corresponding path program 1 times [2021-11-22 16:03:40,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:40,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190475607] [2021-11-22 16:03:40,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:40,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:40,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:40,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:40,159 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:40,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190475607] [2021-11-22 16:03:40,160 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190475607] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:40,160 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:40,160 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 16:03:40,160 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475153386] [2021-11-22 16:03:40,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:40,162 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:40,163 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:40,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-22 16:03:40,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-22 16:03:40,236 INFO L87 Difference]: Start difference. First operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:40,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:40,369 INFO L93 Difference]: Finished difference Result 1920 states and 2841 transitions. [2021-11-22 16:03:40,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-22 16:03:40,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2841 transitions. [2021-11-22 16:03:40,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:40,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1914 states and 2835 transitions. [2021-11-22 16:03:40,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:40,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:40,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2021-11-22 16:03:40,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:40,431 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-22 16:03:40,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2021-11-22 16:03:40,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:40,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:40,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2021-11-22 16:03:40,534 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-22 16:03:40,535 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-11-22 16:03:40,535 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-22 16:03:40,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2021-11-22 16:03:40,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:40,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:40,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:40,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:40,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:40,562 INFO L791 eck$LassoCheckResult]: Stem: 4711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4531#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4247#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4248#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5424#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5425#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4383#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4384#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4838#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4673#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4674#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4450#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4451#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5026#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5180#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5217#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4461#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5637#L1258-2 assume !(0 == ~T1_E~0); 4756#L1263-1 assume !(0 == ~T2_E~0); 4757#L1268-1 assume !(0 == ~T3_E~0); 5060#L1273-1 assume !(0 == ~T4_E~0); 5619#L1278-1 assume !(0 == ~T5_E~0); 5480#L1283-1 assume !(0 == ~T6_E~0); 5481#L1288-1 assume !(0 == ~T7_E~0); 5717#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5705#L1298-1 assume !(0 == ~T9_E~0); 5631#L1303-1 assume !(0 == ~T10_E~0); 4276#L1308-1 assume !(0 == ~T11_E~0); 4218#L1313-1 assume !(0 == ~T12_E~0); 4219#L1318-1 assume !(0 == ~T13_E~0); 4225#L1323-1 assume !(0 == ~E_1~0); 4226#L1328-1 assume !(0 == ~E_2~0); 4393#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5352#L1338-1 assume !(0 == ~E_4~0); 5353#L1343-1 assume !(0 == ~E_5~0); 5454#L1348-1 assume !(0 == ~E_6~0); 5740#L1353-1 assume !(0 == ~E_7~0); 5079#L1358-1 assume !(0 == ~E_8~0); 5080#L1363-1 assume !(0 == ~E_9~0); 5370#L1368-1 assume !(0 == ~E_10~0); 4055#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4056#L1378-1 assume !(0 == ~E_12~0); 4342#L1383-1 assume !(0 == ~E_13~0); 4343#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5086#L607 assume 1 == ~m_pc~0; 5087#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4413#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5452#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5006#L1560 assume !(0 != activate_threads_~tmp~1#1); 5007#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L626 assume !(1 == ~t1_pc~0); 4239#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4507#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4508#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4677#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4255#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4212#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4889#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4890#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4982#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L664 assume 1 == ~t3_pc~0; 5739#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3979#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3980#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4638#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4639#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5647#L683 assume !(1 == ~t4_pc~0); 5202#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5154#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5155#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5189#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5313#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4932#L702 assume 1 == ~t5_pc~0; 4933#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4858#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5308#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5606#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5547#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4027#L721 assume !(1 == ~t6_pc~0); 4001#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4002#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4165#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4647#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4648#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5249#L740 assume 1 == ~t7_pc~0; 4076#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3889#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3890#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3879#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3880#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4583#L759 assume !(1 == ~t8_pc~0); 4584#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4613#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5306#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5307#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5438#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5716#L778 assume 1 == ~t9_pc~0; 5603#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4054#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3994#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3923#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3924#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4251#L797 assume !(1 == ~t10_pc~0); 4252#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4370#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5504#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4754#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4755#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L816 assume 1 == ~t11_pc~0; 3959#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3960#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4715#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4654#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4655#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5179#L835 assume 1 == ~t12_pc~0; 5057#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4123#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4145#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4286#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4811#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4812#L854 assume !(1 == ~t13_pc~0); 4452#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4453#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4503#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4163#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4164#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5543#L1401 assume !(1 == ~M_E~0); 4642#L1401-2 assume !(1 == ~T1_E~0); 4643#L1406-1 assume !(1 == ~T2_E~0); 5238#L1411-1 assume !(1 == ~T3_E~0); 5239#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1421-1 assume !(1 == ~T5_E~0); 4448#L1426-1 assume !(1 == ~T6_E~0); 4449#L1431-1 assume !(1 == ~T7_E~0); 3997#L1436-1 assume !(1 == ~T8_E~0); 3998#L1441-1 assume !(1 == ~T9_E~0); 4745#L1446-1 assume !(1 == ~T10_E~0); 4746#L1451-1 assume !(1 == ~T11_E~0); 5451#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5105#L1461-1 assume !(1 == ~T13_E~0); 4666#L1466-1 assume !(1 == ~E_1~0); 4667#L1471-1 assume !(1 == ~E_2~0); 5436#L1476-1 assume !(1 == ~E_3~0); 5437#L1481-1 assume !(1 == ~E_4~0); 5585#L1486-1 assume !(1 == ~E_5~0); 4291#L1491-1 assume !(1 == ~E_6~0); 3931#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3932#L1501-1 assume !(1 == ~E_8~0); 4743#L1506-1 assume !(1 == ~E_9~0); 4744#L1511-1 assume !(1 == ~E_10~0); 4700#L1516-1 assume !(1 == ~E_11~0); 3875#L1521-1 assume !(1 == ~E_12~0); 3876#L1526-1 assume !(1 == ~E_13~0); 3930#L1531-1 assume { :end_inline_reset_delta_events } true; 4473#L1892-2 [2021-11-22 16:03:40,566 INFO L793 eck$LassoCheckResult]: Loop: 4473#L1892-2 assume !false; 5496#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5694#L1233 assume !false; 5677#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5009#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4989#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5147#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3973#L1046 assume !(0 != eval_~tmp~0#1); 3975#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4009#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5181#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5738#L1258-5 assume !(0 == ~T1_E~0); 4151#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4152#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5730#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5736#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5737#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4375#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4376#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L1298-3 assume !(0 == ~T9_E~0); 5494#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5653#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5492#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4993#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4153#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4154#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5577#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4296#L1338-3 assume !(0 == ~E_4~0); 4297#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5409#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5582#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5583#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4949#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4509#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4510#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5266#L1378-3 assume !(0 == ~E_12~0); 5267#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5448#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5449#L607-42 assume 1 == ~m_pc~0; 5062#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4790#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4791#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4523#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4524#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5045#L626-42 assume !(1 == ~t1_pc~0); 4609#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4608#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4912#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4913#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4188#L645-42 assume !(1 == ~t2_pc~0); 5387#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5388#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5553#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4394#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3901#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3902#L664-42 assume 1 == ~t3_pc~0; 4704#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4429#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5680#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5215#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5216#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5381#L683-42 assume !(1 == ~t4_pc~0); 5089#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5090#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5222#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5642#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5643#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5487#L702-42 assume !(1 == ~t5_pc~0); 4599#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4600#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4896#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5569#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3917#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3918#L721-42 assume 1 == ~t6_pc~0; 4071#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4091#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4555#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4727#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4573#L740-42 assume !(1 == ~t7_pc~0); 4310#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4311#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4852#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4707#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4981#L759-42 assume 1 == ~t8_pc~0; 4830#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4762#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4841#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4842#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4937#L778-42 assume 1 == ~t9_pc~0; 4774#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4776#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5186#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5091#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5092#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5149#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5318#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5627#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5187#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5188#L816-42 assume 1 == ~t11_pc~0; 3865#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3866#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4408#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4409#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4488#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4489#L835-42 assume !(1 == ~t12_pc~0); 4785#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4786#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4463#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4464#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5546#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5330#L854-42 assume 1 == ~t13_pc~0; 5331#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4407#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4017#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4018#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4664#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4665#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5443#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4254#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4118#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4119#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4718#L1421-3 assume !(1 == ~T5_E~0); 4719#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4294#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4295#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3881#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3882#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5471#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4802#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4455#L1461-3 assume !(1 == ~T13_E~0); 4456#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5733#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4395#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4396#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4796#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4423#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4424#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4836#L1501-3 assume !(1 == ~E_8~0); 4837#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5263#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5253#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5254#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4953#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4954#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5348#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4230#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5123#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4764#L1911 assume !(0 == start_simulation_~tmp~3#1); 4765#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5287#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4354#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5225#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4059#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4060#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4289#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4290#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4473#L1892-2 [2021-11-22 16:03:40,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:40,568 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2021-11-22 16:03:40,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:40,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254325045] [2021-11-22 16:03:40,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:40,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:40,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:40,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:40,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:40,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254325045] [2021-11-22 16:03:40,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254325045] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:40,724 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:40,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:40,725 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070850579] [2021-11-22 16:03:40,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:40,726 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:40,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:40,729 INFO L85 PathProgramCache]: Analyzing trace with hash -423565315, now seen corresponding path program 1 times [2021-11-22 16:03:40,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:40,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740435893] [2021-11-22 16:03:40,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:40,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:40,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:40,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:40,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:40,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740435893] [2021-11-22 16:03:40,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740435893] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:40,930 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:40,930 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:40,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853785692] [2021-11-22 16:03:40,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:40,934 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:40,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:40,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:40,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:40,936 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:41,044 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2021-11-22 16:03:41,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:41,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2021-11-22 16:03:41,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-11-22 16:03:41,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:41,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:41,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2021-11-22 16:03:41,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:41,093 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-22 16:03:41,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2021-11-22 16:03:41,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:41,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-11-22 16:03:41,138 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-22 16:03:41,138 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-11-22 16:03:41,138 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-22 16:03:41,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2021-11-22 16:03:41,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:41,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:41,157 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,158 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,158 INFO L791 eck$LassoCheckResult]: Stem: 8546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8366#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8082#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8083#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9259#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9260#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8218#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8219#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8673#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8508#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8285#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8286#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8684#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8861#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9015#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9052#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8296#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8297#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9472#L1258-2 assume !(0 == ~T1_E~0); 8591#L1263-1 assume !(0 == ~T2_E~0); 8592#L1268-1 assume !(0 == ~T3_E~0); 8895#L1273-1 assume !(0 == ~T4_E~0); 9454#L1278-1 assume !(0 == ~T5_E~0); 9315#L1283-1 assume !(0 == ~T6_E~0); 9316#L1288-1 assume !(0 == ~T7_E~0); 9552#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9540#L1298-1 assume !(0 == ~T9_E~0); 9466#L1303-1 assume !(0 == ~T10_E~0); 8111#L1308-1 assume !(0 == ~T11_E~0); 8053#L1313-1 assume !(0 == ~T12_E~0); 8054#L1318-1 assume !(0 == ~T13_E~0); 8060#L1323-1 assume !(0 == ~E_1~0); 8061#L1328-1 assume !(0 == ~E_2~0); 8228#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9187#L1338-1 assume !(0 == ~E_4~0); 9188#L1343-1 assume !(0 == ~E_5~0); 9289#L1348-1 assume !(0 == ~E_6~0); 9575#L1353-1 assume !(0 == ~E_7~0); 8914#L1358-1 assume !(0 == ~E_8~0); 8915#L1363-1 assume !(0 == ~E_9~0); 9205#L1368-1 assume !(0 == ~E_10~0); 7890#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7891#L1378-1 assume !(0 == ~E_12~0); 8177#L1383-1 assume !(0 == ~E_13~0); 8178#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8921#L607 assume 1 == ~m_pc~0; 8922#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8248#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9287#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8841#L1560 assume !(0 != activate_threads_~tmp~1#1); 8842#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8073#L626 assume !(1 == ~t1_pc~0); 8074#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8342#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8343#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8512#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7973#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L645 assume 1 == ~t2_pc~0; 8090#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8047#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8724#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8725#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8817#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8818#L664 assume 1 == ~t3_pc~0; 9574#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7814#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7815#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8473#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8474#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9482#L683 assume !(1 == ~t4_pc~0); 9037#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8989#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8990#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9024#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9148#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8767#L702 assume 1 == ~t5_pc~0; 8768#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8693#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9143#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9441#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9382#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7862#L721 assume !(1 == ~t6_pc~0); 7836#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7837#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8000#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8482#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9084#L740 assume 1 == ~t7_pc~0; 7911#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7724#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7725#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7714#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7715#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8418#L759 assume !(1 == ~t8_pc~0); 8419#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8448#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9141#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9142#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9273#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9551#L778 assume 1 == ~t9_pc~0; 9438#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7889#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7829#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7758#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7759#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8086#L797 assume !(1 == ~t10_pc~0); 8087#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8205#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9339#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8589#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8590#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8879#L816 assume 1 == ~t11_pc~0; 7794#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7795#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8550#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8489#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8490#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9014#L835 assume 1 == ~t12_pc~0; 8892#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7958#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7980#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8121#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8646#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8647#L854 assume !(1 == ~t13_pc~0); 8287#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8288#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8338#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7998#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7999#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9378#L1401 assume !(1 == ~M_E~0); 8477#L1401-2 assume !(1 == ~T1_E~0); 8478#L1406-1 assume !(1 == ~T2_E~0); 9073#L1411-1 assume !(1 == ~T3_E~0); 9074#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8740#L1421-1 assume !(1 == ~T5_E~0); 8283#L1426-1 assume !(1 == ~T6_E~0); 8284#L1431-1 assume !(1 == ~T7_E~0); 7832#L1436-1 assume !(1 == ~T8_E~0); 7833#L1441-1 assume !(1 == ~T9_E~0); 8580#L1446-1 assume !(1 == ~T10_E~0); 8581#L1451-1 assume !(1 == ~T11_E~0); 9286#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8940#L1461-1 assume !(1 == ~T13_E~0); 8501#L1466-1 assume !(1 == ~E_1~0); 8502#L1471-1 assume !(1 == ~E_2~0); 9271#L1476-1 assume !(1 == ~E_3~0); 9272#L1481-1 assume !(1 == ~E_4~0); 9420#L1486-1 assume !(1 == ~E_5~0); 8126#L1491-1 assume !(1 == ~E_6~0); 7766#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7767#L1501-1 assume !(1 == ~E_8~0); 8578#L1506-1 assume !(1 == ~E_9~0); 8579#L1511-1 assume !(1 == ~E_10~0); 8535#L1516-1 assume !(1 == ~E_11~0); 7710#L1521-1 assume !(1 == ~E_12~0); 7711#L1526-1 assume !(1 == ~E_13~0); 7765#L1531-1 assume { :end_inline_reset_delta_events } true; 8308#L1892-2 [2021-11-22 16:03:41,159 INFO L793 eck$LassoCheckResult]: Loop: 8308#L1892-2 assume !false; 9331#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9529#L1233 assume !false; 9512#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8844#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8824#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8982#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7808#L1046 assume !(0 != eval_~tmp~0#1); 7810#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7844#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9016#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9573#L1258-5 assume !(0 == ~T1_E~0); 7986#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7987#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9565#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9571#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9572#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8210#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8211#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9328#L1298-3 assume !(0 == ~T9_E~0); 9329#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9488#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9327#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8828#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7988#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7989#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9412#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8131#L1338-3 assume !(0 == ~E_4~0); 8132#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9244#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9417#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9418#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8784#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8344#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8345#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9101#L1378-3 assume !(0 == ~E_12~0); 9102#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9283#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9284#L607-42 assume 1 == ~m_pc~0; 8897#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8625#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8358#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8359#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8880#L626-42 assume 1 == ~t1_pc~0; 8442#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8443#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8747#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8748#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8022#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8023#L645-42 assume !(1 == ~t2_pc~0); 9222#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9223#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9388#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8229#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7736#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7737#L664-42 assume !(1 == ~t3_pc~0); 8263#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8264#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9515#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9050#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9051#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9216#L683-42 assume !(1 == ~t4_pc~0); 8924#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8925#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9057#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9477#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9478#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9322#L702-42 assume !(1 == ~t5_pc~0); 8434#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8435#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8731#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9404#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7752#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7753#L721-42 assume 1 == ~t6_pc~0; 7906#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7926#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9557#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8562#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L740-42 assume !(1 == ~t7_pc~0); 8145#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 8146#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8687#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8542#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 8543#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8816#L759-42 assume 1 == ~t8_pc~0; 8665#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8597#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8598#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8676#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8677#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8772#L778-42 assume 1 == ~t9_pc~0; 8609#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8611#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9021#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8926#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8927#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8984#L797-42 assume 1 == ~t10_pc~0; 8151#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8152#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9153#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9462#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9022#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9023#L816-42 assume 1 == ~t11_pc~0; 7700#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7701#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8243#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8244#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8323#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8324#L835-42 assume 1 == ~t12_pc~0; 8728#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8621#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8298#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8299#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9381#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9165#L854-42 assume !(1 == ~t13_pc~0); 8241#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 8242#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7852#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7853#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8499#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9278#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8089#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7953#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7954#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8553#L1421-3 assume !(1 == ~T5_E~0); 8554#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8130#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7716#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7717#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9306#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8637#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8290#L1461-3 assume !(1 == ~T13_E~0); 8291#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9568#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8230#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8231#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8631#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8258#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8259#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8671#L1501-3 assume !(1 == ~E_8~0); 8672#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9098#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9088#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9089#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8788#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8789#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9183#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8065#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8958#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8599#L1911 assume !(0 == start_simulation_~tmp~3#1); 8600#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9122#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8189#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9060#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7894#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7895#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8124#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8125#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8308#L1892-2 [2021-11-22 16:03:41,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,163 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2021-11-22 16:03:41,164 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059797756] [2021-11-22 16:03:41,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,165 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,258 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059797756] [2021-11-22 16:03:41,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059797756] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,260 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,260 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100886648] [2021-11-22 16:03:41,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,262 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:41,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,262 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 1 times [2021-11-22 16:03:41,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827638233] [2021-11-22 16:03:41,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,330 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,330 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827638233] [2021-11-22 16:03:41,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827638233] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,330 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349580815] [2021-11-22 16:03:41,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,331 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:41,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:41,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:41,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:41,333 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:41,383 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2021-11-22 16:03:41,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:41,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2021-11-22 16:03:41,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-11-22 16:03:41,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:41,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:41,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2021-11-22 16:03:41,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:41,459 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-22 16:03:41,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2021-11-22 16:03:41,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:41,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-11-22 16:03:41,510 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-22 16:03:41,510 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-11-22 16:03:41,510 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-22 16:03:41,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2021-11-22 16:03:41,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:41,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:41,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,529 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,529 INFO L791 eck$LassoCheckResult]: Stem: 12381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12201#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11917#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11918#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13094#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13095#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12053#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12054#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12508#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12343#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12344#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12120#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12121#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12519#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12696#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12850#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12887#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12131#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12132#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13307#L1258-2 assume !(0 == ~T1_E~0); 12426#L1263-1 assume !(0 == ~T2_E~0); 12427#L1268-1 assume !(0 == ~T3_E~0); 12730#L1273-1 assume !(0 == ~T4_E~0); 13289#L1278-1 assume !(0 == ~T5_E~0); 13150#L1283-1 assume !(0 == ~T6_E~0); 13151#L1288-1 assume !(0 == ~T7_E~0); 13387#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13375#L1298-1 assume !(0 == ~T9_E~0); 13301#L1303-1 assume !(0 == ~T10_E~0); 11946#L1308-1 assume !(0 == ~T11_E~0); 11888#L1313-1 assume !(0 == ~T12_E~0); 11889#L1318-1 assume !(0 == ~T13_E~0); 11895#L1323-1 assume !(0 == ~E_1~0); 11896#L1328-1 assume !(0 == ~E_2~0); 12063#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13022#L1338-1 assume !(0 == ~E_4~0); 13023#L1343-1 assume !(0 == ~E_5~0); 13124#L1348-1 assume !(0 == ~E_6~0); 13410#L1353-1 assume !(0 == ~E_7~0); 12749#L1358-1 assume !(0 == ~E_8~0); 12750#L1363-1 assume !(0 == ~E_9~0); 13040#L1368-1 assume !(0 == ~E_10~0); 11725#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11726#L1378-1 assume !(0 == ~E_12~0); 12012#L1383-1 assume !(0 == ~E_13~0); 12013#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12756#L607 assume 1 == ~m_pc~0; 12757#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12083#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13122#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12676#L1560 assume !(0 != activate_threads_~tmp~1#1); 12677#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11908#L626 assume !(1 == ~t1_pc~0); 11909#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12177#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12347#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11809#L645 assume 1 == ~t2_pc~0; 11925#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11882#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12559#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12560#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12652#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12653#L664 assume 1 == ~t3_pc~0; 13409#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11649#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11650#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12308#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12309#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13317#L683 assume !(1 == ~t4_pc~0); 12872#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12824#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12825#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12859#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12983#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12602#L702 assume 1 == ~t5_pc~0; 12603#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12528#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12978#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13276#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13217#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11697#L721 assume !(1 == ~t6_pc~0); 11671#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11672#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11835#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12317#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12318#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12919#L740 assume 1 == ~t7_pc~0; 11746#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11559#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11560#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11549#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11550#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12253#L759 assume !(1 == ~t8_pc~0); 12254#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12283#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12976#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12977#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13108#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13386#L778 assume 1 == ~t9_pc~0; 13273#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11724#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11664#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11593#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11594#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11921#L797 assume !(1 == ~t10_pc~0); 11922#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12040#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13174#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12424#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12425#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12714#L816 assume 1 == ~t11_pc~0; 11629#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11630#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12385#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12324#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12325#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12849#L835 assume 1 == ~t12_pc~0; 12727#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11793#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11815#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11956#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12481#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12482#L854 assume !(1 == ~t13_pc~0); 12122#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12123#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12173#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11833#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11834#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13213#L1401 assume !(1 == ~M_E~0); 12312#L1401-2 assume !(1 == ~T1_E~0); 12313#L1406-1 assume !(1 == ~T2_E~0); 12908#L1411-1 assume !(1 == ~T3_E~0); 12909#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12575#L1421-1 assume !(1 == ~T5_E~0); 12118#L1426-1 assume !(1 == ~T6_E~0); 12119#L1431-1 assume !(1 == ~T7_E~0); 11667#L1436-1 assume !(1 == ~T8_E~0); 11668#L1441-1 assume !(1 == ~T9_E~0); 12415#L1446-1 assume !(1 == ~T10_E~0); 12416#L1451-1 assume !(1 == ~T11_E~0); 13121#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12775#L1461-1 assume !(1 == ~T13_E~0); 12336#L1466-1 assume !(1 == ~E_1~0); 12337#L1471-1 assume !(1 == ~E_2~0); 13106#L1476-1 assume !(1 == ~E_3~0); 13107#L1481-1 assume !(1 == ~E_4~0); 13255#L1486-1 assume !(1 == ~E_5~0); 11961#L1491-1 assume !(1 == ~E_6~0); 11601#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11602#L1501-1 assume !(1 == ~E_8~0); 12413#L1506-1 assume !(1 == ~E_9~0); 12414#L1511-1 assume !(1 == ~E_10~0); 12370#L1516-1 assume !(1 == ~E_11~0); 11545#L1521-1 assume !(1 == ~E_12~0); 11546#L1526-1 assume !(1 == ~E_13~0); 11600#L1531-1 assume { :end_inline_reset_delta_events } true; 12143#L1892-2 [2021-11-22 16:03:41,530 INFO L793 eck$LassoCheckResult]: Loop: 12143#L1892-2 assume !false; 13166#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13364#L1233 assume !false; 13347#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12679#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12659#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12817#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11643#L1046 assume !(0 != eval_~tmp~0#1); 11645#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11679#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12851#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13408#L1258-5 assume !(0 == ~T1_E~0); 11821#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11822#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13400#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13406#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13407#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12045#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12046#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13163#L1298-3 assume !(0 == ~T9_E~0); 13164#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13323#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13162#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12663#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11823#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11824#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13247#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11966#L1338-3 assume !(0 == ~E_4~0); 11967#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13079#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13252#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13253#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12619#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12179#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12180#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12936#L1378-3 assume !(0 == ~E_12~0); 12937#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13118#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13119#L607-42 assume 1 == ~m_pc~0; 12732#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12460#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12461#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12193#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12194#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12715#L626-42 assume 1 == ~t1_pc~0; 12277#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12278#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12582#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12583#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11857#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11858#L645-42 assume !(1 == ~t2_pc~0); 13057#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13058#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13223#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12064#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11571#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11572#L664-42 assume !(1 == ~t3_pc~0); 12098#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12099#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13350#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12885#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12886#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13051#L683-42 assume !(1 == ~t4_pc~0); 12759#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12760#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13312#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13313#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13157#L702-42 assume 1 == ~t5_pc~0; 12645#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12270#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12566#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13239#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11587#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11588#L721-42 assume 1 == ~t6_pc~0; 11741#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11761#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13392#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12397#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12243#L740-42 assume 1 == ~t7_pc~0; 12244#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11981#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12522#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12377#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12378#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12651#L759-42 assume 1 == ~t8_pc~0; 12500#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12432#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12433#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12511#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12512#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12607#L778-42 assume 1 == ~t9_pc~0; 12444#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12446#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12856#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12761#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12762#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12819#L797-42 assume 1 == ~t10_pc~0; 11986#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11987#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12988#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13297#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12857#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12858#L816-42 assume !(1 == ~t11_pc~0); 11537#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11536#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12078#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12079#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12158#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12159#L835-42 assume 1 == ~t12_pc~0; 12563#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12456#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12133#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12134#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13216#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13000#L854-42 assume 1 == ~t13_pc~0; 13001#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12077#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11687#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11688#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12334#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12335#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13113#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11924#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11788#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11789#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12388#L1421-3 assume !(1 == ~T5_E~0); 12389#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11964#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11965#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11551#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11552#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13141#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12472#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12125#L1461-3 assume !(1 == ~T13_E~0); 12126#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13403#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12065#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12066#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12093#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12094#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12506#L1501-3 assume !(1 == ~E_8~0); 12507#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12933#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12923#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12924#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12623#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12624#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13018#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11900#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12793#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12434#L1911 assume !(0 == start_simulation_~tmp~3#1); 12435#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12957#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12024#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12895#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11729#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11730#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11959#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11960#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12143#L1892-2 [2021-11-22 16:03:41,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,531 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2021-11-22 16:03:41,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271764642] [2021-11-22 16:03:41,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,533 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,574 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271764642] [2021-11-22 16:03:41,575 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271764642] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,575 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,576 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,576 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36101347] [2021-11-22 16:03:41,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,577 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:41,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,578 INFO L85 PathProgramCache]: Analyzing trace with hash 2046766079, now seen corresponding path program 1 times [2021-11-22 16:03:41,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109346579] [2021-11-22 16:03:41,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,579 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109346579] [2021-11-22 16:03:41,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109346579] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,648 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382346471] [2021-11-22 16:03:41,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:41,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:41,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:41,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:41,651 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:41,703 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2021-11-22 16:03:41,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:41,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2021-11-22 16:03:41,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-11-22 16:03:41,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:41,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:41,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2021-11-22 16:03:41,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:41,746 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-22 16:03:41,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2021-11-22 16:03:41,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:41,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-11-22 16:03:41,793 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-22 16:03:41,793 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-11-22 16:03:41,793 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-22 16:03:41,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2021-11-22 16:03:41,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:41,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:41,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:41,831 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,831 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:41,831 INFO L791 eck$LassoCheckResult]: Stem: 16216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16036#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15752#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15753#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15888#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15889#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16343#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16178#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16179#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15955#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15956#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16354#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16531#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16685#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16722#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15966#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15967#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17142#L1258-2 assume !(0 == ~T1_E~0); 16261#L1263-1 assume !(0 == ~T2_E~0); 16262#L1268-1 assume !(0 == ~T3_E~0); 16565#L1273-1 assume !(0 == ~T4_E~0); 17124#L1278-1 assume !(0 == ~T5_E~0); 16985#L1283-1 assume !(0 == ~T6_E~0); 16986#L1288-1 assume !(0 == ~T7_E~0); 17222#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17210#L1298-1 assume !(0 == ~T9_E~0); 17136#L1303-1 assume !(0 == ~T10_E~0); 15781#L1308-1 assume !(0 == ~T11_E~0); 15723#L1313-1 assume !(0 == ~T12_E~0); 15724#L1318-1 assume !(0 == ~T13_E~0); 15730#L1323-1 assume !(0 == ~E_1~0); 15731#L1328-1 assume !(0 == ~E_2~0); 15898#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16857#L1338-1 assume !(0 == ~E_4~0); 16858#L1343-1 assume !(0 == ~E_5~0); 16959#L1348-1 assume !(0 == ~E_6~0); 17245#L1353-1 assume !(0 == ~E_7~0); 16584#L1358-1 assume !(0 == ~E_8~0); 16585#L1363-1 assume !(0 == ~E_9~0); 16875#L1368-1 assume !(0 == ~E_10~0); 15560#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15561#L1378-1 assume !(0 == ~E_12~0); 15847#L1383-1 assume !(0 == ~E_13~0); 15848#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16591#L607 assume 1 == ~m_pc~0; 16592#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15918#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16957#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16511#L1560 assume !(0 != activate_threads_~tmp~1#1); 16512#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15743#L626 assume !(1 == ~t1_pc~0); 15744#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16012#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16013#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16182#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15643#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15644#L645 assume 1 == ~t2_pc~0; 15760#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15717#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16394#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16395#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16487#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16488#L664 assume 1 == ~t3_pc~0; 17244#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15484#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15485#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16143#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16144#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17152#L683 assume !(1 == ~t4_pc~0); 16707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16659#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16660#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16818#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16437#L702 assume 1 == ~t5_pc~0; 16438#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16363#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16813#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17111#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17052#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L721 assume !(1 == ~t6_pc~0); 15506#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15507#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15670#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16152#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16153#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16754#L740 assume 1 == ~t7_pc~0; 15581#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15394#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15395#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15384#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15385#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16088#L759 assume !(1 == ~t8_pc~0); 16089#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16118#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16811#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16812#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17221#L778 assume 1 == ~t9_pc~0; 17108#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15559#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15499#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15428#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15429#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15756#L797 assume !(1 == ~t10_pc~0); 15757#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15875#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17009#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16259#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16260#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16549#L816 assume 1 == ~t11_pc~0; 15464#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15465#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16220#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16159#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16160#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16684#L835 assume 1 == ~t12_pc~0; 16562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15628#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15650#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15791#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16316#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16317#L854 assume !(1 == ~t13_pc~0); 15957#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15958#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16008#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15668#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15669#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17048#L1401 assume !(1 == ~M_E~0); 16147#L1401-2 assume !(1 == ~T1_E~0); 16148#L1406-1 assume !(1 == ~T2_E~0); 16743#L1411-1 assume !(1 == ~T3_E~0); 16744#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16410#L1421-1 assume !(1 == ~T5_E~0); 15953#L1426-1 assume !(1 == ~T6_E~0); 15954#L1431-1 assume !(1 == ~T7_E~0); 15502#L1436-1 assume !(1 == ~T8_E~0); 15503#L1441-1 assume !(1 == ~T9_E~0); 16250#L1446-1 assume !(1 == ~T10_E~0); 16251#L1451-1 assume !(1 == ~T11_E~0); 16956#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16610#L1461-1 assume !(1 == ~T13_E~0); 16171#L1466-1 assume !(1 == ~E_1~0); 16172#L1471-1 assume !(1 == ~E_2~0); 16941#L1476-1 assume !(1 == ~E_3~0); 16942#L1481-1 assume !(1 == ~E_4~0); 17090#L1486-1 assume !(1 == ~E_5~0); 15796#L1491-1 assume !(1 == ~E_6~0); 15436#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15437#L1501-1 assume !(1 == ~E_8~0); 16248#L1506-1 assume !(1 == ~E_9~0); 16249#L1511-1 assume !(1 == ~E_10~0); 16205#L1516-1 assume !(1 == ~E_11~0); 15380#L1521-1 assume !(1 == ~E_12~0); 15381#L1526-1 assume !(1 == ~E_13~0); 15435#L1531-1 assume { :end_inline_reset_delta_events } true; 15978#L1892-2 [2021-11-22 16:03:41,832 INFO L793 eck$LassoCheckResult]: Loop: 15978#L1892-2 assume !false; 17001#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17199#L1233 assume !false; 17182#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16514#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16494#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16652#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15478#L1046 assume !(0 != eval_~tmp~0#1); 15480#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15514#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16686#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17243#L1258-5 assume !(0 == ~T1_E~0); 15656#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15657#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17235#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17241#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17242#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15880#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15881#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16998#L1298-3 assume !(0 == ~T9_E~0); 16999#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17158#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16997#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16498#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15658#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15659#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17082#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15801#L1338-3 assume !(0 == ~E_4~0); 15802#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16914#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17087#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17088#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16454#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16014#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16015#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16771#L1378-3 assume !(0 == ~E_12~0); 16772#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16953#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16954#L607-42 assume 1 == ~m_pc~0; 16567#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16295#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16296#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16028#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16029#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16550#L626-42 assume 1 == ~t1_pc~0; 16112#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16113#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16417#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16418#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15692#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15693#L645-42 assume !(1 == ~t2_pc~0); 16892#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16893#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17058#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15899#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15406#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15407#L664-42 assume 1 == ~t3_pc~0; 16209#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15934#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17185#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16720#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16721#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16886#L683-42 assume !(1 == ~t4_pc~0); 16594#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16595#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16727#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17147#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17148#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16992#L702-42 assume 1 == ~t5_pc~0; 16480#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16105#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16401#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17074#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15422#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15423#L721-42 assume 1 == ~t6_pc~0; 15576#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15596#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16060#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17227#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16232#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16078#L740-42 assume !(1 == ~t7_pc~0); 15815#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15816#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16357#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16212#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 16213#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16486#L759-42 assume !(1 == ~t8_pc~0); 16336#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16267#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16268#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16346#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16347#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16442#L778-42 assume 1 == ~t9_pc~0; 16279#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16281#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16691#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16596#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16597#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16654#L797-42 assume 1 == ~t10_pc~0; 15821#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15822#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16823#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17132#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16692#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16693#L816-42 assume 1 == ~t11_pc~0; 15370#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15371#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15913#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15914#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15993#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15994#L835-42 assume !(1 == ~t12_pc~0); 16290#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16291#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15968#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15969#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17051#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16835#L854-42 assume 1 == ~t13_pc~0; 16836#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15912#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15522#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15523#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16169#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16170#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15759#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15623#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15624#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16223#L1421-3 assume !(1 == ~T5_E~0); 16224#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15799#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15800#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15386#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15387#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16976#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16307#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15960#L1461-3 assume !(1 == ~T13_E~0); 15961#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17238#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15900#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15901#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16301#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15928#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15929#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16341#L1501-3 assume !(1 == ~E_8~0); 16342#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16768#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16758#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16759#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16458#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16459#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16853#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15735#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16628#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16269#L1911 assume !(0 == start_simulation_~tmp~3#1); 16270#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16792#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15859#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16730#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15564#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15565#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15794#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15795#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15978#L1892-2 [2021-11-22 16:03:41,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,833 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2021-11-22 16:03:41,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100142742] [2021-11-22 16:03:41,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,834 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,869 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100142742] [2021-11-22 16:03:41,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100142742] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,869 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86161583] [2021-11-22 16:03:41,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,871 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:41,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:41,871 INFO L85 PathProgramCache]: Analyzing trace with hash 259811934, now seen corresponding path program 1 times [2021-11-22 16:03:41,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:41,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723931057] [2021-11-22 16:03:41,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:41,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:41,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:41,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:41,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:41,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723931057] [2021-11-22 16:03:41,922 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723931057] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:41,922 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:41,922 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:41,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764838324] [2021-11-22 16:03:41,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:41,923 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:41,923 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:41,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:41,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:41,924 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:41,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:41,970 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2021-11-22 16:03:41,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:41,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2021-11-22 16:03:41,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-11-22 16:03:42,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:42,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:42,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2021-11-22 16:03:42,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:42,009 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-22 16:03:42,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2021-11-22 16:03:42,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:42,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-11-22 16:03:42,052 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-22 16:03:42,052 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-11-22 16:03:42,053 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-22 16:03:42,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2021-11-22 16:03:42,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:42,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:42,064 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,065 INFO L791 eck$LassoCheckResult]: Stem: 20051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19871#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19587#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19588#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20764#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20765#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19723#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19724#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20178#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20013#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20014#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19790#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19791#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20189#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20366#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20520#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20557#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19801#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19802#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20977#L1258-2 assume !(0 == ~T1_E~0); 20096#L1263-1 assume !(0 == ~T2_E~0); 20097#L1268-1 assume !(0 == ~T3_E~0); 20400#L1273-1 assume !(0 == ~T4_E~0); 20959#L1278-1 assume !(0 == ~T5_E~0); 20820#L1283-1 assume !(0 == ~T6_E~0); 20821#L1288-1 assume !(0 == ~T7_E~0); 21057#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21045#L1298-1 assume !(0 == ~T9_E~0); 20971#L1303-1 assume !(0 == ~T10_E~0); 19616#L1308-1 assume !(0 == ~T11_E~0); 19558#L1313-1 assume !(0 == ~T12_E~0); 19559#L1318-1 assume !(0 == ~T13_E~0); 19565#L1323-1 assume !(0 == ~E_1~0); 19566#L1328-1 assume !(0 == ~E_2~0); 19733#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20692#L1338-1 assume !(0 == ~E_4~0); 20693#L1343-1 assume !(0 == ~E_5~0); 20794#L1348-1 assume !(0 == ~E_6~0); 21080#L1353-1 assume !(0 == ~E_7~0); 20419#L1358-1 assume !(0 == ~E_8~0); 20420#L1363-1 assume !(0 == ~E_9~0); 20710#L1368-1 assume !(0 == ~E_10~0); 19395#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19396#L1378-1 assume !(0 == ~E_12~0); 19682#L1383-1 assume !(0 == ~E_13~0); 19683#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20426#L607 assume 1 == ~m_pc~0; 20427#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19753#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20792#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20346#L1560 assume !(0 != activate_threads_~tmp~1#1); 20347#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19578#L626 assume !(1 == ~t1_pc~0); 19579#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19847#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19848#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20017#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19478#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19479#L645 assume 1 == ~t2_pc~0; 19595#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19552#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20229#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20230#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20322#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20323#L664 assume 1 == ~t3_pc~0; 21079#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19319#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19320#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19978#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19979#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20987#L683 assume !(1 == ~t4_pc~0); 20542#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20494#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20495#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20529#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20653#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20272#L702 assume 1 == ~t5_pc~0; 20273#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20198#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20648#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20946#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20887#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19367#L721 assume !(1 == ~t6_pc~0); 19341#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19342#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19505#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19987#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19988#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20589#L740 assume 1 == ~t7_pc~0; 19416#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19229#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19230#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19219#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19220#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19923#L759 assume !(1 == ~t8_pc~0); 19924#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19953#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20646#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20647#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20778#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21056#L778 assume 1 == ~t9_pc~0; 20943#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19394#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19334#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19263#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19264#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19591#L797 assume !(1 == ~t10_pc~0); 19592#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19710#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20844#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20094#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20095#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20384#L816 assume 1 == ~t11_pc~0; 19299#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19300#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20055#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19994#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19995#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20519#L835 assume 1 == ~t12_pc~0; 20397#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19463#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19485#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19626#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20151#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20152#L854 assume !(1 == ~t13_pc~0); 19792#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19793#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19843#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19503#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19504#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20883#L1401 assume !(1 == ~M_E~0); 19982#L1401-2 assume !(1 == ~T1_E~0); 19983#L1406-1 assume !(1 == ~T2_E~0); 20578#L1411-1 assume !(1 == ~T3_E~0); 20579#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20245#L1421-1 assume !(1 == ~T5_E~0); 19788#L1426-1 assume !(1 == ~T6_E~0); 19789#L1431-1 assume !(1 == ~T7_E~0); 19337#L1436-1 assume !(1 == ~T8_E~0); 19338#L1441-1 assume !(1 == ~T9_E~0); 20085#L1446-1 assume !(1 == ~T10_E~0); 20086#L1451-1 assume !(1 == ~T11_E~0); 20791#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20445#L1461-1 assume !(1 == ~T13_E~0); 20006#L1466-1 assume !(1 == ~E_1~0); 20007#L1471-1 assume !(1 == ~E_2~0); 20776#L1476-1 assume !(1 == ~E_3~0); 20777#L1481-1 assume !(1 == ~E_4~0); 20925#L1486-1 assume !(1 == ~E_5~0); 19631#L1491-1 assume !(1 == ~E_6~0); 19271#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19272#L1501-1 assume !(1 == ~E_8~0); 20083#L1506-1 assume !(1 == ~E_9~0); 20084#L1511-1 assume !(1 == ~E_10~0); 20040#L1516-1 assume !(1 == ~E_11~0); 19215#L1521-1 assume !(1 == ~E_12~0); 19216#L1526-1 assume !(1 == ~E_13~0); 19270#L1531-1 assume { :end_inline_reset_delta_events } true; 19813#L1892-2 [2021-11-22 16:03:42,066 INFO L793 eck$LassoCheckResult]: Loop: 19813#L1892-2 assume !false; 20836#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21034#L1233 assume !false; 21017#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20349#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20329#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20487#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19313#L1046 assume !(0 != eval_~tmp~0#1); 19315#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19349#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20521#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21078#L1258-5 assume !(0 == ~T1_E~0); 19491#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19492#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21070#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21076#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21077#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19715#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19716#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20833#L1298-3 assume !(0 == ~T9_E~0); 20834#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20993#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20832#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20333#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19493#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19494#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20917#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19636#L1338-3 assume !(0 == ~E_4~0); 19637#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20749#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20922#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20923#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20289#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19849#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19850#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20606#L1378-3 assume !(0 == ~E_12~0); 20607#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20788#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20789#L607-42 assume 1 == ~m_pc~0; 20402#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20130#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20131#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19863#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19864#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20385#L626-42 assume 1 == ~t1_pc~0; 19947#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19948#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20252#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20253#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19527#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19528#L645-42 assume !(1 == ~t2_pc~0); 20727#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20728#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20893#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19734#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19241#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19242#L664-42 assume !(1 == ~t3_pc~0); 19768#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19769#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21020#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20555#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20556#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20721#L683-42 assume !(1 == ~t4_pc~0); 20429#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20430#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20562#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20982#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20983#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20827#L702-42 assume !(1 == ~t5_pc~0); 19939#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19940#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20236#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20909#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19257#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19258#L721-42 assume 1 == ~t6_pc~0; 19411#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19431#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19895#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21062#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20067#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19913#L740-42 assume !(1 == ~t7_pc~0); 19650#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19651#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20192#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20047#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20048#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20321#L759-42 assume 1 == ~t8_pc~0; 20170#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20102#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20103#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20181#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20182#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20277#L778-42 assume 1 == ~t9_pc~0; 20114#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20116#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20526#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20431#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20432#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20489#L797-42 assume 1 == ~t10_pc~0; 19656#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19657#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20658#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20967#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20527#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20528#L816-42 assume 1 == ~t11_pc~0; 19205#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19206#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19748#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19749#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19828#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19829#L835-42 assume 1 == ~t12_pc~0; 20233#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20126#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19803#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19804#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20886#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20670#L854-42 assume !(1 == ~t13_pc~0); 19746#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19747#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19357#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19358#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20004#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20005#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20783#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19594#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19458#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19459#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20058#L1421-3 assume !(1 == ~T5_E~0); 20059#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19634#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19635#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19221#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19222#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20811#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20142#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19795#L1461-3 assume !(1 == ~T13_E~0); 19796#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21073#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19735#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19736#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20136#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19763#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19764#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20176#L1501-3 assume !(1 == ~E_8~0); 20177#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20603#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20593#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20594#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20293#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20294#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20688#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19570#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20463#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20104#L1911 assume !(0 == start_simulation_~tmp~3#1); 20105#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20627#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19694#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20565#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19399#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19400#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19629#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19630#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19813#L1892-2 [2021-11-22 16:03:42,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,067 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2021-11-22 16:03:42,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760431770] [2021-11-22 16:03:42,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,101 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760431770] [2021-11-22 16:03:42,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760431770] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,102 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,102 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,102 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878714351] [2021-11-22 16:03:42,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,103 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:42,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,104 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 2 times [2021-11-22 16:03:42,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977028036] [2021-11-22 16:03:42,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,110 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977028036] [2021-11-22 16:03:42,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977028036] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,188 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203017697] [2021-11-22 16:03:42,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,189 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:42,189 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:42,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:42,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:42,195 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:42,242 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2021-11-22 16:03:42,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:42,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2021-11-22 16:03:42,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-11-22 16:03:42,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:42,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:42,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2021-11-22 16:03:42,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:42,284 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-22 16:03:42,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2021-11-22 16:03:42,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:42,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-11-22 16:03:42,341 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-22 16:03:42,341 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-11-22 16:03:42,341 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-22 16:03:42,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2021-11-22 16:03:42,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:42,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:42,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,378 INFO L791 eck$LassoCheckResult]: Stem: 23886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23706#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23422#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23423#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24599#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24600#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23558#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23559#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24013#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23848#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23849#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23625#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23626#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24024#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24201#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24355#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24392#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23636#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23637#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24812#L1258-2 assume !(0 == ~T1_E~0); 23931#L1263-1 assume !(0 == ~T2_E~0); 23932#L1268-1 assume !(0 == ~T3_E~0); 24235#L1273-1 assume !(0 == ~T4_E~0); 24794#L1278-1 assume !(0 == ~T5_E~0); 24655#L1283-1 assume !(0 == ~T6_E~0); 24656#L1288-1 assume !(0 == ~T7_E~0); 24892#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24880#L1298-1 assume !(0 == ~T9_E~0); 24806#L1303-1 assume !(0 == ~T10_E~0); 23451#L1308-1 assume !(0 == ~T11_E~0); 23393#L1313-1 assume !(0 == ~T12_E~0); 23394#L1318-1 assume !(0 == ~T13_E~0); 23400#L1323-1 assume !(0 == ~E_1~0); 23401#L1328-1 assume !(0 == ~E_2~0); 23568#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24527#L1338-1 assume !(0 == ~E_4~0); 24528#L1343-1 assume !(0 == ~E_5~0); 24629#L1348-1 assume !(0 == ~E_6~0); 24915#L1353-1 assume !(0 == ~E_7~0); 24254#L1358-1 assume !(0 == ~E_8~0); 24255#L1363-1 assume !(0 == ~E_9~0); 24545#L1368-1 assume !(0 == ~E_10~0); 23230#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23231#L1378-1 assume !(0 == ~E_12~0); 23517#L1383-1 assume !(0 == ~E_13~0); 23518#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24261#L607 assume 1 == ~m_pc~0; 24262#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23588#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24627#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24181#L1560 assume !(0 != activate_threads_~tmp~1#1); 24182#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23413#L626 assume !(1 == ~t1_pc~0); 23414#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23682#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23683#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23852#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23313#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23314#L645 assume 1 == ~t2_pc~0; 23430#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23387#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24064#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24065#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24157#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24158#L664 assume 1 == ~t3_pc~0; 24914#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23154#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23155#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23813#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23814#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24822#L683 assume !(1 == ~t4_pc~0); 24377#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24329#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24330#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24364#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24488#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24107#L702 assume 1 == ~t5_pc~0; 24108#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24033#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24483#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24781#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24722#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23202#L721 assume !(1 == ~t6_pc~0); 23176#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23177#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23340#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23822#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23823#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24424#L740 assume 1 == ~t7_pc~0; 23251#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23064#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23065#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23054#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23055#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23758#L759 assume !(1 == ~t8_pc~0); 23759#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23788#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24481#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24482#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24613#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24891#L778 assume 1 == ~t9_pc~0; 24778#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23229#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23169#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23098#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23099#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23426#L797 assume !(1 == ~t10_pc~0); 23427#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23545#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24679#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23929#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23930#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24219#L816 assume 1 == ~t11_pc~0; 23134#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23135#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23890#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23829#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23830#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24354#L835 assume 1 == ~t12_pc~0; 24232#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23298#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23320#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23461#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23986#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23987#L854 assume !(1 == ~t13_pc~0); 23627#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23628#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23678#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23338#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23339#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24718#L1401 assume !(1 == ~M_E~0); 23817#L1401-2 assume !(1 == ~T1_E~0); 23818#L1406-1 assume !(1 == ~T2_E~0); 24413#L1411-1 assume !(1 == ~T3_E~0); 24414#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24080#L1421-1 assume !(1 == ~T5_E~0); 23623#L1426-1 assume !(1 == ~T6_E~0); 23624#L1431-1 assume !(1 == ~T7_E~0); 23172#L1436-1 assume !(1 == ~T8_E~0); 23173#L1441-1 assume !(1 == ~T9_E~0); 23920#L1446-1 assume !(1 == ~T10_E~0); 23921#L1451-1 assume !(1 == ~T11_E~0); 24626#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24280#L1461-1 assume !(1 == ~T13_E~0); 23841#L1466-1 assume !(1 == ~E_1~0); 23842#L1471-1 assume !(1 == ~E_2~0); 24611#L1476-1 assume !(1 == ~E_3~0); 24612#L1481-1 assume !(1 == ~E_4~0); 24760#L1486-1 assume !(1 == ~E_5~0); 23466#L1491-1 assume !(1 == ~E_6~0); 23106#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23107#L1501-1 assume !(1 == ~E_8~0); 23918#L1506-1 assume !(1 == ~E_9~0); 23919#L1511-1 assume !(1 == ~E_10~0); 23875#L1516-1 assume !(1 == ~E_11~0); 23050#L1521-1 assume !(1 == ~E_12~0); 23051#L1526-1 assume !(1 == ~E_13~0); 23105#L1531-1 assume { :end_inline_reset_delta_events } true; 23648#L1892-2 [2021-11-22 16:03:42,379 INFO L793 eck$LassoCheckResult]: Loop: 23648#L1892-2 assume !false; 24671#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24869#L1233 assume !false; 24852#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24184#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24164#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24322#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23148#L1046 assume !(0 != eval_~tmp~0#1); 23150#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23184#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24356#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24913#L1258-5 assume !(0 == ~T1_E~0); 23326#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23327#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24905#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24911#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24912#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23550#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23551#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24668#L1298-3 assume !(0 == ~T9_E~0); 24669#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24828#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24667#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24168#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23328#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23329#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24752#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23471#L1338-3 assume !(0 == ~E_4~0); 23472#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24584#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24757#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24758#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24124#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23684#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23685#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24441#L1378-3 assume !(0 == ~E_12~0); 24442#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24623#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24624#L607-42 assume 1 == ~m_pc~0; 24237#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23965#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23966#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23698#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23699#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24220#L626-42 assume 1 == ~t1_pc~0; 23782#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23783#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24087#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24088#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23362#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23363#L645-42 assume !(1 == ~t2_pc~0); 24562#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24563#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24728#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23569#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23076#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23077#L664-42 assume !(1 == ~t3_pc~0); 23603#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23604#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24855#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24390#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24391#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24556#L683-42 assume !(1 == ~t4_pc~0); 24264#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24265#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24397#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24817#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24818#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24662#L702-42 assume 1 == ~t5_pc~0; 24150#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23775#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24071#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24744#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23092#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23093#L721-42 assume 1 == ~t6_pc~0; 23246#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23266#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23730#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24897#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23902#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23748#L740-42 assume 1 == ~t7_pc~0; 23749#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23486#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24027#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23882#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 23883#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24156#L759-42 assume 1 == ~t8_pc~0; 24005#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23937#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23938#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24016#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24017#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24112#L778-42 assume 1 == ~t9_pc~0; 23949#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23951#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24361#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24266#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24267#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24324#L797-42 assume 1 == ~t10_pc~0; 23491#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23492#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24493#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24802#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24362#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24363#L816-42 assume 1 == ~t11_pc~0; 23040#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23041#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23583#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23584#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23663#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23664#L835-42 assume 1 == ~t12_pc~0; 24068#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23961#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23638#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23639#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24721#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24505#L854-42 assume 1 == ~t13_pc~0; 24506#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23582#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23192#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23193#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23839#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23840#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24618#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23429#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23293#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23294#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23893#L1421-3 assume !(1 == ~T5_E~0); 23894#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23469#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23470#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23056#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23057#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24646#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23977#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23630#L1461-3 assume !(1 == ~T13_E~0); 23631#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24908#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23570#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23571#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23971#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23598#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23599#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24011#L1501-3 assume !(1 == ~E_8~0); 24012#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24438#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24428#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24429#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24128#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24129#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24523#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23405#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24298#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23939#L1911 assume !(0 == start_simulation_~tmp~3#1); 23940#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24462#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23529#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24400#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23234#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23235#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23464#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23465#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23648#L1892-2 [2021-11-22 16:03:42,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2021-11-22 16:03:42,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047768267] [2021-11-22 16:03:42,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,423 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047768267] [2021-11-22 16:03:42,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047768267] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,424 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,424 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444603783] [2021-11-22 16:03:42,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,425 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:42,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1106553824, now seen corresponding path program 1 times [2021-11-22 16:03:42,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076377347] [2021-11-22 16:03:42,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076377347] [2021-11-22 16:03:42,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076377347] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,519 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571400743] [2021-11-22 16:03:42,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,520 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:42,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:42,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:42,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:42,521 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:42,572 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2021-11-22 16:03:42,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:42,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2021-11-22 16:03:42,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-11-22 16:03:42,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:42,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:42,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2021-11-22 16:03:42,612 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:42,612 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-22 16:03:42,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2021-11-22 16:03:42,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:42,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-11-22 16:03:42,658 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-22 16:03:42,658 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-11-22 16:03:42,658 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-22 16:03:42,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2021-11-22 16:03:42,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:42,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:42,671 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,671 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,672 INFO L791 eck$LassoCheckResult]: Stem: 27721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27541#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27257#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27258#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28434#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28435#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27393#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27394#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27848#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27683#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27684#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27460#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27461#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27859#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28036#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28190#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28227#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27471#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27472#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28647#L1258-2 assume !(0 == ~T1_E~0); 27766#L1263-1 assume !(0 == ~T2_E~0); 27767#L1268-1 assume !(0 == ~T3_E~0); 28070#L1273-1 assume !(0 == ~T4_E~0); 28629#L1278-1 assume !(0 == ~T5_E~0); 28490#L1283-1 assume !(0 == ~T6_E~0); 28491#L1288-1 assume !(0 == ~T7_E~0); 28727#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28715#L1298-1 assume !(0 == ~T9_E~0); 28641#L1303-1 assume !(0 == ~T10_E~0); 27286#L1308-1 assume !(0 == ~T11_E~0); 27228#L1313-1 assume !(0 == ~T12_E~0); 27229#L1318-1 assume !(0 == ~T13_E~0); 27235#L1323-1 assume !(0 == ~E_1~0); 27236#L1328-1 assume !(0 == ~E_2~0); 27403#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28362#L1338-1 assume !(0 == ~E_4~0); 28363#L1343-1 assume !(0 == ~E_5~0); 28464#L1348-1 assume !(0 == ~E_6~0); 28750#L1353-1 assume !(0 == ~E_7~0); 28089#L1358-1 assume !(0 == ~E_8~0); 28090#L1363-1 assume !(0 == ~E_9~0); 28380#L1368-1 assume !(0 == ~E_10~0); 27065#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27066#L1378-1 assume !(0 == ~E_12~0); 27352#L1383-1 assume !(0 == ~E_13~0); 27353#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28096#L607 assume 1 == ~m_pc~0; 28097#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27423#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28462#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28016#L1560 assume !(0 != activate_threads_~tmp~1#1); 28017#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27248#L626 assume !(1 == ~t1_pc~0); 27249#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27517#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27518#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27687#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27148#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27149#L645 assume 1 == ~t2_pc~0; 27265#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27222#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27899#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27900#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27992#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27993#L664 assume 1 == ~t3_pc~0; 28749#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26989#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26990#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27648#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27649#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28657#L683 assume !(1 == ~t4_pc~0); 28212#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28164#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28165#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28199#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28323#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27942#L702 assume 1 == ~t5_pc~0; 27943#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27868#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28318#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28616#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28557#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27037#L721 assume !(1 == ~t6_pc~0); 27011#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27012#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27175#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27657#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27658#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28259#L740 assume 1 == ~t7_pc~0; 27086#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26899#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26900#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26889#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26890#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27593#L759 assume !(1 == ~t8_pc~0); 27594#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27623#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28316#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28317#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28448#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28726#L778 assume 1 == ~t9_pc~0; 28613#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27064#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27004#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26933#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26934#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27261#L797 assume !(1 == ~t10_pc~0); 27262#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27380#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28514#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27764#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27765#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28054#L816 assume 1 == ~t11_pc~0; 26969#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26970#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27725#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27664#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27665#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28189#L835 assume 1 == ~t12_pc~0; 28067#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27133#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27155#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27296#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27821#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27822#L854 assume !(1 == ~t13_pc~0); 27462#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27463#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27513#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27173#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27174#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28553#L1401 assume !(1 == ~M_E~0); 27652#L1401-2 assume !(1 == ~T1_E~0); 27653#L1406-1 assume !(1 == ~T2_E~0); 28248#L1411-1 assume !(1 == ~T3_E~0); 28249#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27915#L1421-1 assume !(1 == ~T5_E~0); 27458#L1426-1 assume !(1 == ~T6_E~0); 27459#L1431-1 assume !(1 == ~T7_E~0); 27007#L1436-1 assume !(1 == ~T8_E~0); 27008#L1441-1 assume !(1 == ~T9_E~0); 27755#L1446-1 assume !(1 == ~T10_E~0); 27756#L1451-1 assume !(1 == ~T11_E~0); 28461#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28115#L1461-1 assume !(1 == ~T13_E~0); 27676#L1466-1 assume !(1 == ~E_1~0); 27677#L1471-1 assume !(1 == ~E_2~0); 28446#L1476-1 assume !(1 == ~E_3~0); 28447#L1481-1 assume !(1 == ~E_4~0); 28595#L1486-1 assume !(1 == ~E_5~0); 27301#L1491-1 assume !(1 == ~E_6~0); 26941#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26942#L1501-1 assume !(1 == ~E_8~0); 27753#L1506-1 assume !(1 == ~E_9~0); 27754#L1511-1 assume !(1 == ~E_10~0); 27710#L1516-1 assume !(1 == ~E_11~0); 26885#L1521-1 assume !(1 == ~E_12~0); 26886#L1526-1 assume !(1 == ~E_13~0); 26940#L1531-1 assume { :end_inline_reset_delta_events } true; 27483#L1892-2 [2021-11-22 16:03:42,672 INFO L793 eck$LassoCheckResult]: Loop: 27483#L1892-2 assume !false; 28506#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28704#L1233 assume !false; 28687#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28019#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27999#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28157#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26983#L1046 assume !(0 != eval_~tmp~0#1); 26985#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27019#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28191#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28748#L1258-5 assume !(0 == ~T1_E~0); 27161#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27162#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28740#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28746#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28747#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27385#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27386#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28503#L1298-3 assume !(0 == ~T9_E~0); 28504#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28663#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28502#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28003#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27163#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27164#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28587#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27306#L1338-3 assume !(0 == ~E_4~0); 27307#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28419#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28592#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28593#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27959#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27519#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27520#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28276#L1378-3 assume !(0 == ~E_12~0); 28277#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28458#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28459#L607-42 assume 1 == ~m_pc~0; 28072#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27800#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27801#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27533#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27534#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28055#L626-42 assume 1 == ~t1_pc~0; 27617#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27618#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27922#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27923#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27197#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27198#L645-42 assume 1 == ~t2_pc~0; 28656#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28563#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27404#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26911#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26912#L664-42 assume 1 == ~t3_pc~0; 27714#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27439#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28690#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28225#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28226#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28391#L683-42 assume !(1 == ~t4_pc~0); 28099#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28100#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28232#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28653#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28497#L702-42 assume 1 == ~t5_pc~0; 27985#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27610#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27906#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28579#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26927#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26928#L721-42 assume 1 == ~t6_pc~0; 27081#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27101#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27565#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28732#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27737#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27583#L740-42 assume 1 == ~t7_pc~0; 27584#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27321#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27862#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27717#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27718#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27991#L759-42 assume 1 == ~t8_pc~0; 27840#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27772#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27773#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27851#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27852#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27947#L778-42 assume 1 == ~t9_pc~0; 27784#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27786#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28196#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28102#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28159#L797-42 assume !(1 == ~t10_pc~0); 27328#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 27327#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28328#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28637#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28197#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28198#L816-42 assume 1 == ~t11_pc~0; 26875#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26876#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27418#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27419#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27498#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27499#L835-42 assume !(1 == ~t12_pc~0); 27795#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27796#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27473#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27474#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28556#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28340#L854-42 assume 1 == ~t13_pc~0; 28341#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27417#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27027#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27028#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27674#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27675#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28453#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27264#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27128#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27129#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27728#L1421-3 assume !(1 == ~T5_E~0); 27729#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27304#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27305#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26891#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26892#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28481#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27812#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27465#L1461-3 assume !(1 == ~T13_E~0); 27466#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28743#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27405#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27406#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27806#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27433#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27434#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27846#L1501-3 assume !(1 == ~E_8~0); 27847#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28273#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28263#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28264#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27963#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27964#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28358#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27240#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28133#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27774#L1911 assume !(0 == start_simulation_~tmp~3#1); 27775#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28297#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27364#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28235#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27069#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27070#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27299#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27300#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27483#L1892-2 [2021-11-22 16:03:42,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,673 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2021-11-22 16:03:42,674 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111555008] [2021-11-22 16:03:42,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,674 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111555008] [2021-11-22 16:03:42,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111555008] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084755385] [2021-11-22 16:03:42,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,715 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:42,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 1 times [2021-11-22 16:03:42,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666087789] [2021-11-22 16:03:42,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,725 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:42,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:42,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:42,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666087789] [2021-11-22 16:03:42,777 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666087789] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:42,777 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:42,777 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:42,778 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960732603] [2021-11-22 16:03:42,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:42,783 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:42,783 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:42,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:42,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:42,784 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:42,832 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2021-11-22 16:03:42,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:42,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2021-11-22 16:03:42,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-11-22 16:03:42,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:42,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:42,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2021-11-22 16:03:42,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:42,874 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-22 16:03:42,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2021-11-22 16:03:42,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:42,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:42,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-11-22 16:03:42,917 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-22 16:03:42,917 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-11-22 16:03:42,917 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-22 16:03:42,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2021-11-22 16:03:42,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:42,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:42,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:42,929 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:42,930 INFO L791 eck$LassoCheckResult]: Stem: 31556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31376#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31092#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31093#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32269#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32270#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31228#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31229#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31683#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31518#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31519#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31295#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31296#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31694#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31871#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32025#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32062#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31306#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31307#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32482#L1258-2 assume !(0 == ~T1_E~0); 31601#L1263-1 assume !(0 == ~T2_E~0); 31602#L1268-1 assume !(0 == ~T3_E~0); 31905#L1273-1 assume !(0 == ~T4_E~0); 32464#L1278-1 assume !(0 == ~T5_E~0); 32325#L1283-1 assume !(0 == ~T6_E~0); 32326#L1288-1 assume !(0 == ~T7_E~0); 32562#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32550#L1298-1 assume !(0 == ~T9_E~0); 32476#L1303-1 assume !(0 == ~T10_E~0); 31121#L1308-1 assume !(0 == ~T11_E~0); 31063#L1313-1 assume !(0 == ~T12_E~0); 31064#L1318-1 assume !(0 == ~T13_E~0); 31070#L1323-1 assume !(0 == ~E_1~0); 31071#L1328-1 assume !(0 == ~E_2~0); 31238#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32197#L1338-1 assume !(0 == ~E_4~0); 32198#L1343-1 assume !(0 == ~E_5~0); 32299#L1348-1 assume !(0 == ~E_6~0); 32585#L1353-1 assume !(0 == ~E_7~0); 31924#L1358-1 assume !(0 == ~E_8~0); 31925#L1363-1 assume !(0 == ~E_9~0); 32215#L1368-1 assume !(0 == ~E_10~0); 30900#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30901#L1378-1 assume !(0 == ~E_12~0); 31187#L1383-1 assume !(0 == ~E_13~0); 31188#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31931#L607 assume 1 == ~m_pc~0; 31932#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31258#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32297#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31851#L1560 assume !(0 != activate_threads_~tmp~1#1); 31852#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31083#L626 assume !(1 == ~t1_pc~0); 31084#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31352#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31353#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31522#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30983#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30984#L645 assume 1 == ~t2_pc~0; 31100#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31057#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31734#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31735#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31827#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31828#L664 assume 1 == ~t3_pc~0; 32584#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30824#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30825#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31483#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31484#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32492#L683 assume !(1 == ~t4_pc~0); 32047#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31999#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32000#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32034#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32158#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31777#L702 assume 1 == ~t5_pc~0; 31778#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31703#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32153#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32451#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32392#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30872#L721 assume !(1 == ~t6_pc~0); 30846#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30847#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31010#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31492#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31493#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32094#L740 assume 1 == ~t7_pc~0; 30921#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30734#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30735#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30724#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30725#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31428#L759 assume !(1 == ~t8_pc~0); 31429#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31458#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32151#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32152#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32283#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32561#L778 assume 1 == ~t9_pc~0; 32448#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30899#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30839#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30768#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30769#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31096#L797 assume !(1 == ~t10_pc~0); 31097#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31215#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32349#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31599#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31600#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31889#L816 assume 1 == ~t11_pc~0; 30804#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30805#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31560#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31499#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31500#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32024#L835 assume 1 == ~t12_pc~0; 31902#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30968#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30990#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31131#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31656#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31657#L854 assume !(1 == ~t13_pc~0); 31297#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31298#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31348#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31008#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31009#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32388#L1401 assume !(1 == ~M_E~0); 31487#L1401-2 assume !(1 == ~T1_E~0); 31488#L1406-1 assume !(1 == ~T2_E~0); 32083#L1411-1 assume !(1 == ~T3_E~0); 32084#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31750#L1421-1 assume !(1 == ~T5_E~0); 31293#L1426-1 assume !(1 == ~T6_E~0); 31294#L1431-1 assume !(1 == ~T7_E~0); 30842#L1436-1 assume !(1 == ~T8_E~0); 30843#L1441-1 assume !(1 == ~T9_E~0); 31590#L1446-1 assume !(1 == ~T10_E~0); 31591#L1451-1 assume !(1 == ~T11_E~0); 32296#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31950#L1461-1 assume !(1 == ~T13_E~0); 31511#L1466-1 assume !(1 == ~E_1~0); 31512#L1471-1 assume !(1 == ~E_2~0); 32281#L1476-1 assume !(1 == ~E_3~0); 32282#L1481-1 assume !(1 == ~E_4~0); 32430#L1486-1 assume !(1 == ~E_5~0); 31136#L1491-1 assume !(1 == ~E_6~0); 30776#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30777#L1501-1 assume !(1 == ~E_8~0); 31588#L1506-1 assume !(1 == ~E_9~0); 31589#L1511-1 assume !(1 == ~E_10~0); 31545#L1516-1 assume !(1 == ~E_11~0); 30720#L1521-1 assume !(1 == ~E_12~0); 30721#L1526-1 assume !(1 == ~E_13~0); 30775#L1531-1 assume { :end_inline_reset_delta_events } true; 31318#L1892-2 [2021-11-22 16:03:42,931 INFO L793 eck$LassoCheckResult]: Loop: 31318#L1892-2 assume !false; 32341#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32539#L1233 assume !false; 32522#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31854#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31834#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31992#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30818#L1046 assume !(0 != eval_~tmp~0#1); 30820#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30854#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32026#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32583#L1258-5 assume !(0 == ~T1_E~0); 30996#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30997#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32575#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32581#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32582#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31220#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31221#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32338#L1298-3 assume !(0 == ~T9_E~0); 32339#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32337#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31838#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30998#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30999#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32422#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31141#L1338-3 assume !(0 == ~E_4~0); 31142#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32254#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32427#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32428#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31794#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31354#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31355#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32111#L1378-3 assume !(0 == ~E_12~0); 32112#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32293#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32294#L607-42 assume 1 == ~m_pc~0; 31907#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31635#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31636#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31368#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31369#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31890#L626-42 assume 1 == ~t1_pc~0; 31452#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31453#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31757#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31758#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31032#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31033#L645-42 assume !(1 == ~t2_pc~0); 32232#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32233#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32398#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31239#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30746#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30747#L664-42 assume !(1 == ~t3_pc~0); 31273#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31274#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32525#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32060#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32061#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32226#L683-42 assume !(1 == ~t4_pc~0); 31934#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31935#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32067#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32487#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32488#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32332#L702-42 assume !(1 == ~t5_pc~0); 31444#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31445#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31741#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32414#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30762#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30763#L721-42 assume 1 == ~t6_pc~0; 30916#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30936#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31400#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32567#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31572#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31418#L740-42 assume !(1 == ~t7_pc~0); 31155#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31156#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31697#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31552#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 31553#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31826#L759-42 assume 1 == ~t8_pc~0; 31675#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31607#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31608#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31686#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31687#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31782#L778-42 assume 1 == ~t9_pc~0; 31619#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31621#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32031#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31936#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31937#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31994#L797-42 assume 1 == ~t10_pc~0; 31161#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31162#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32163#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32472#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32032#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32033#L816-42 assume 1 == ~t11_pc~0; 30710#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30711#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31253#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31254#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31333#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L835-42 assume 1 == ~t12_pc~0; 31738#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31631#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31308#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31309#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32391#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32175#L854-42 assume 1 == ~t13_pc~0; 32176#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31252#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30862#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30863#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31509#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31510#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32288#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31099#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30963#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30964#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31563#L1421-3 assume !(1 == ~T5_E~0); 31564#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31139#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31140#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30726#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30727#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32316#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31647#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31300#L1461-3 assume !(1 == ~T13_E~0); 31301#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32578#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31240#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31241#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31641#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31268#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31269#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31681#L1501-3 assume !(1 == ~E_8~0); 31682#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32108#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32098#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32099#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31798#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31799#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32193#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31075#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31968#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31609#L1911 assume !(0 == start_simulation_~tmp~3#1); 31610#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32132#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31199#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32070#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30904#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30905#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31134#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31135#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31318#L1892-2 [2021-11-22 16:03:42,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:42,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2021-11-22 16:03:42,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:42,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574102873] [2021-11-22 16:03:42,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:42,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:42,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,001 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,001 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574102873] [2021-11-22 16:03:43,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574102873] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,001 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274435765] [2021-11-22 16:03:43,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,002 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:43,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,003 INFO L85 PathProgramCache]: Analyzing trace with hash 1476580190, now seen corresponding path program 1 times [2021-11-22 16:03:43,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239867878] [2021-11-22 16:03:43,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,004 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,050 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239867878] [2021-11-22 16:03:43,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239867878] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,051 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684430419] [2021-11-22 16:03:43,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,052 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:43,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:43,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:43,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:43,054 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:43,095 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2021-11-22 16:03:43,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:43,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2021-11-22 16:03:43,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-11-22 16:03:43,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:43,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:43,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2021-11-22 16:03:43,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:43,126 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-22 16:03:43,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2021-11-22 16:03:43,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:43,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-11-22 16:03:43,173 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-22 16:03:43,173 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-11-22 16:03:43,173 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-22 16:03:43,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2021-11-22 16:03:43,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:43,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:43,185 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,185 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,186 INFO L791 eck$LassoCheckResult]: Stem: 35391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35211#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34927#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34928#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36104#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36105#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35063#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35064#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35522#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35353#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35354#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35130#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35131#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35529#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35706#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35861#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35897#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35143#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35144#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36317#L1258-2 assume !(0 == ~T1_E~0); 35436#L1263-1 assume !(0 == ~T2_E~0); 35437#L1268-1 assume !(0 == ~T3_E~0); 35740#L1273-1 assume !(0 == ~T4_E~0); 36299#L1278-1 assume !(0 == ~T5_E~0); 36160#L1283-1 assume !(0 == ~T6_E~0); 36161#L1288-1 assume !(0 == ~T7_E~0); 36398#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36385#L1298-1 assume !(0 == ~T9_E~0); 36311#L1303-1 assume !(0 == ~T10_E~0); 34956#L1308-1 assume !(0 == ~T11_E~0); 34901#L1313-1 assume !(0 == ~T12_E~0); 34902#L1318-1 assume !(0 == ~T13_E~0); 34907#L1323-1 assume !(0 == ~E_1~0); 34908#L1328-1 assume !(0 == ~E_2~0); 35073#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36032#L1338-1 assume !(0 == ~E_4~0); 36033#L1343-1 assume !(0 == ~E_5~0); 36134#L1348-1 assume !(0 == ~E_6~0); 36420#L1353-1 assume !(0 == ~E_7~0); 35759#L1358-1 assume !(0 == ~E_8~0); 35760#L1363-1 assume !(0 == ~E_9~0); 36051#L1368-1 assume !(0 == ~E_10~0); 34735#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34736#L1378-1 assume !(0 == ~E_12~0); 35024#L1383-1 assume !(0 == ~E_13~0); 35025#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35766#L607 assume 1 == ~m_pc~0; 35767#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35093#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36132#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35686#L1560 assume !(0 != activate_threads_~tmp~1#1); 35687#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34918#L626 assume !(1 == ~t1_pc~0); 34919#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35189#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35190#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35359#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34821#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34822#L645 assume 1 == ~t2_pc~0; 34935#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34892#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35572#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35573#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35662#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35663#L664 assume 1 == ~t3_pc~0; 36419#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34663#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34664#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35318#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35319#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36327#L683 assume !(1 == ~t4_pc~0); 35882#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35834#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35835#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35869#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35993#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35616#L702 assume 1 == ~t5_pc~0; 35617#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35539#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35988#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36287#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36228#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34707#L721 assume !(1 == ~t6_pc~0); 34681#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34682#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34845#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35327#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35328#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35929#L740 assume 1 == ~t7_pc~0; 34756#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34569#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34570#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34559#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34560#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35264#L759 assume !(1 == ~t8_pc~0); 35265#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35293#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35986#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35987#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36118#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36396#L778 assume 1 == ~t9_pc~0; 36285#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34734#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34674#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34603#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34604#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34932#L797 assume !(1 == ~t10_pc~0); 34933#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35050#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36184#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35434#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35435#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35724#L816 assume 1 == ~t11_pc~0; 34639#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34640#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35397#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35334#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35335#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35859#L835 assume 1 == ~t12_pc~0; 35737#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34803#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34825#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34966#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35491#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35492#L854 assume !(1 == ~t13_pc~0); 35132#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35133#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35185#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34843#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34844#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36223#L1401 assume !(1 == ~M_E~0); 35322#L1401-2 assume !(1 == ~T1_E~0); 35323#L1406-1 assume !(1 == ~T2_E~0); 35918#L1411-1 assume !(1 == ~T3_E~0); 35919#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35585#L1421-1 assume !(1 == ~T5_E~0); 35128#L1426-1 assume !(1 == ~T6_E~0); 35129#L1431-1 assume !(1 == ~T7_E~0); 34677#L1436-1 assume !(1 == ~T8_E~0); 34678#L1441-1 assume !(1 == ~T9_E~0); 35425#L1446-1 assume !(1 == ~T10_E~0); 35426#L1451-1 assume !(1 == ~T11_E~0); 36131#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35785#L1461-1 assume !(1 == ~T13_E~0); 35346#L1466-1 assume !(1 == ~E_1~0); 35347#L1471-1 assume !(1 == ~E_2~0); 36116#L1476-1 assume !(1 == ~E_3~0); 36117#L1481-1 assume !(1 == ~E_4~0); 36265#L1486-1 assume !(1 == ~E_5~0); 34971#L1491-1 assume !(1 == ~E_6~0); 34611#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34612#L1501-1 assume !(1 == ~E_8~0); 35423#L1506-1 assume !(1 == ~E_9~0); 35424#L1511-1 assume !(1 == ~E_10~0); 35380#L1516-1 assume !(1 == ~E_11~0); 34555#L1521-1 assume !(1 == ~E_12~0); 34556#L1526-1 assume !(1 == ~E_13~0); 34610#L1531-1 assume { :end_inline_reset_delta_events } true; 35153#L1892-2 [2021-11-22 16:03:43,187 INFO L793 eck$LassoCheckResult]: Loop: 35153#L1892-2 assume !false; 36176#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36374#L1233 assume !false; 36357#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35689#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35669#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35827#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34653#L1046 assume !(0 != eval_~tmp~0#1); 34655#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34689#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35860#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36418#L1258-5 assume !(0 == ~T1_E~0); 34831#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34832#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36410#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36416#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36417#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35055#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35056#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36173#L1298-3 assume !(0 == ~T9_E~0); 36174#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36333#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36172#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35673#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34833#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34834#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36257#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34976#L1338-3 assume !(0 == ~E_4~0); 34977#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36089#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36262#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36263#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35629#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35187#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35188#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35946#L1378-3 assume !(0 == ~E_12~0); 35947#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36128#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36129#L607-42 assume 1 == ~m_pc~0; 35742#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35470#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35471#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35203#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35204#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35725#L626-42 assume 1 == ~t1_pc~0; 35287#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35288#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35592#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35593#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34867#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34868#L645-42 assume !(1 == ~t2_pc~0); 36067#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36068#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36233#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35074#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34581#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34582#L664-42 assume !(1 == ~t3_pc~0); 35108#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35109#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36360#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35895#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35896#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36061#L683-42 assume !(1 == ~t4_pc~0); 35769#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35770#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35902#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36322#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36323#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36167#L702-42 assume 1 == ~t5_pc~0; 35655#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35280#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35576#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36249#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34597#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34598#L721-42 assume !(1 == ~t6_pc~0); 34752#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34771#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35235#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36402#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35407#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35253#L740-42 assume 1 == ~t7_pc~0; 35254#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34991#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35532#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35387#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35388#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35661#L759-42 assume 1 == ~t8_pc~0; 35510#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35442#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35443#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35520#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35521#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35615#L778-42 assume 1 == ~t9_pc~0; 35454#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35456#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35866#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35771#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35772#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35829#L797-42 assume 1 == ~t10_pc~0; 34996#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34997#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35998#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36307#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35867#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35868#L816-42 assume 1 == ~t11_pc~0; 34545#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34546#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35088#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35089#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35168#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35169#L835-42 assume 1 == ~t12_pc~0; 35571#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35466#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35141#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35142#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36226#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36010#L854-42 assume 1 == ~t13_pc~0; 36011#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35087#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34697#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34698#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35344#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35345#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36123#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34931#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34798#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34799#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35398#L1421-3 assume !(1 == ~T5_E~0); 35399#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34974#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34975#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34561#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34562#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36151#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35482#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35135#L1461-3 assume !(1 == ~T13_E~0); 35136#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36413#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35075#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35076#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35476#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35103#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35104#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35516#L1501-3 assume !(1 == ~E_8~0); 35517#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35943#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35933#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35934#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35633#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35634#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36028#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34910#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35803#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35444#L1911 assume !(0 == start_simulation_~tmp~3#1); 35445#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35967#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35034#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35905#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34739#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34740#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34969#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34970#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35153#L1892-2 [2021-11-22 16:03:43,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,188 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2021-11-22 16:03:43,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930987557] [2021-11-22 16:03:43,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,189 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930987557] [2021-11-22 16:03:43,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930987557] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,227 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144622818] [2021-11-22 16:03:43,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,230 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:43,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,231 INFO L85 PathProgramCache]: Analyzing trace with hash 95640511, now seen corresponding path program 1 times [2021-11-22 16:03:43,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8698798] [2021-11-22 16:03:43,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,289 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8698798] [2021-11-22 16:03:43,290 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8698798] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,290 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,290 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,290 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283969296] [2021-11-22 16:03:43,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,291 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:43,291 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:43,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:43,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:43,292 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:43,334 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2021-11-22 16:03:43,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:43,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2021-11-22 16:03:43,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-11-22 16:03:43,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:43,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:43,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2021-11-22 16:03:43,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:43,375 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-22 16:03:43,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2021-11-22 16:03:43,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:43,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-11-22 16:03:43,437 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-22 16:03:43,437 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-11-22 16:03:43,437 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-22 16:03:43,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2021-11-22 16:03:43,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:43,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:43,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,450 INFO L791 eck$LassoCheckResult]: Stem: 39226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39046#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38762#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38763#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39939#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39940#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38898#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38899#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39357#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39188#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39189#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38965#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38966#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39364#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39541#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39695#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39732#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38978#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38979#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40152#L1258-2 assume !(0 == ~T1_E~0); 39271#L1263-1 assume !(0 == ~T2_E~0); 39272#L1268-1 assume !(0 == ~T3_E~0); 39575#L1273-1 assume !(0 == ~T4_E~0); 40134#L1278-1 assume !(0 == ~T5_E~0); 39995#L1283-1 assume !(0 == ~T6_E~0); 39996#L1288-1 assume !(0 == ~T7_E~0); 40233#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40220#L1298-1 assume !(0 == ~T9_E~0); 40146#L1303-1 assume !(0 == ~T10_E~0); 38791#L1308-1 assume !(0 == ~T11_E~0); 38733#L1313-1 assume !(0 == ~T12_E~0); 38734#L1318-1 assume !(0 == ~T13_E~0); 38742#L1323-1 assume !(0 == ~E_1~0); 38743#L1328-1 assume !(0 == ~E_2~0); 38908#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39867#L1338-1 assume !(0 == ~E_4~0); 39868#L1343-1 assume !(0 == ~E_5~0); 39969#L1348-1 assume !(0 == ~E_6~0); 40255#L1353-1 assume !(0 == ~E_7~0); 39594#L1358-1 assume !(0 == ~E_8~0); 39595#L1363-1 assume !(0 == ~E_9~0); 39886#L1368-1 assume !(0 == ~E_10~0); 38570#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38571#L1378-1 assume !(0 == ~E_12~0); 38859#L1383-1 assume !(0 == ~E_13~0); 38860#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39601#L607 assume 1 == ~m_pc~0; 39602#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38928#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39967#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39521#L1560 assume !(0 != activate_threads_~tmp~1#1); 39522#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38753#L626 assume !(1 == ~t1_pc~0); 38754#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39024#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39025#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39194#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38655#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38656#L645 assume 1 == ~t2_pc~0; 38770#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38727#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39407#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39408#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39497#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39498#L664 assume 1 == ~t3_pc~0; 40254#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38498#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38499#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39153#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39154#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40162#L683 assume !(1 == ~t4_pc~0); 39717#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39669#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39670#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39704#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39828#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39451#L702 assume 1 == ~t5_pc~0; 39452#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39374#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39823#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40122#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40063#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38542#L721 assume !(1 == ~t6_pc~0); 38516#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38517#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38680#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39162#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39163#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39764#L740 assume 1 == ~t7_pc~0; 38591#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38404#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38405#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38394#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38395#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39099#L759 assume !(1 == ~t8_pc~0); 39100#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39128#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39821#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39822#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39953#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40231#L778 assume 1 == ~t9_pc~0; 40120#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38569#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38509#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38438#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38439#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38767#L797 assume !(1 == ~t10_pc~0); 38768#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38885#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40019#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39269#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39270#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39559#L816 assume 1 == ~t11_pc~0; 38474#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38475#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39232#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39169#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39170#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39694#L835 assume 1 == ~t12_pc~0; 39572#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38638#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38660#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38801#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39326#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39327#L854 assume !(1 == ~t13_pc~0); 38967#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38968#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39020#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38678#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38679#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40058#L1401 assume !(1 == ~M_E~0); 39157#L1401-2 assume !(1 == ~T1_E~0); 39158#L1406-1 assume !(1 == ~T2_E~0); 39753#L1411-1 assume !(1 == ~T3_E~0); 39754#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39420#L1421-1 assume !(1 == ~T5_E~0); 38963#L1426-1 assume !(1 == ~T6_E~0); 38964#L1431-1 assume !(1 == ~T7_E~0); 38512#L1436-1 assume !(1 == ~T8_E~0); 38513#L1441-1 assume !(1 == ~T9_E~0); 39262#L1446-1 assume !(1 == ~T10_E~0); 39263#L1451-1 assume !(1 == ~T11_E~0); 39966#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39620#L1461-1 assume !(1 == ~T13_E~0); 39181#L1466-1 assume !(1 == ~E_1~0); 39182#L1471-1 assume !(1 == ~E_2~0); 39951#L1476-1 assume !(1 == ~E_3~0); 39952#L1481-1 assume !(1 == ~E_4~0); 40100#L1486-1 assume !(1 == ~E_5~0); 38806#L1491-1 assume !(1 == ~E_6~0); 38446#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38447#L1501-1 assume !(1 == ~E_8~0); 39258#L1506-1 assume !(1 == ~E_9~0); 39259#L1511-1 assume !(1 == ~E_10~0); 39215#L1516-1 assume !(1 == ~E_11~0); 38392#L1521-1 assume !(1 == ~E_12~0); 38393#L1526-1 assume !(1 == ~E_13~0); 38445#L1531-1 assume { :end_inline_reset_delta_events } true; 38988#L1892-2 [2021-11-22 16:03:43,451 INFO L793 eck$LassoCheckResult]: Loop: 38988#L1892-2 assume !false; 40011#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40209#L1233 assume !false; 40192#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39524#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39504#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39662#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38488#L1046 assume !(0 != eval_~tmp~0#1); 38490#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38524#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40253#L1258-5 assume !(0 == ~T1_E~0); 38670#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38671#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40245#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40251#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40252#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38892#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38893#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40008#L1298-3 assume !(0 == ~T9_E~0); 40009#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40168#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40007#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39508#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38666#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38667#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40092#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38811#L1338-3 assume !(0 == ~E_4~0); 38812#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39924#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40097#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40098#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39464#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39022#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39023#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39781#L1378-3 assume !(0 == ~E_12~0); 39782#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39963#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39964#L607-42 assume 1 == ~m_pc~0; 39577#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39305#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39306#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39038#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39039#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39560#L626-42 assume 1 == ~t1_pc~0; 39122#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39123#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39427#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39428#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38702#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38703#L645-42 assume 1 == ~t2_pc~0; 40161#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39903#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40068#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38909#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38416#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38417#L664-42 assume 1 == ~t3_pc~0; 39219#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38944#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40195#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39730#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39731#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39896#L683-42 assume !(1 == ~t4_pc~0); 39604#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39605#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39737#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40157#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40158#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40002#L702-42 assume 1 == ~t5_pc~0; 39490#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39115#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39411#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40084#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38432#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38433#L721-42 assume 1 == ~t6_pc~0; 38586#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38606#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39070#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40237#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39242#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39088#L740-42 assume 1 == ~t7_pc~0; 39089#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38826#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39367#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39222#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 39223#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39496#L759-42 assume 1 == ~t8_pc~0; 39345#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39277#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39278#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39355#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39356#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39450#L778-42 assume 1 == ~t9_pc~0; 39289#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39291#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39700#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39606#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39607#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39664#L797-42 assume !(1 == ~t10_pc~0); 38833#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 38832#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39833#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40142#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39702#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39703#L816-42 assume 1 == ~t11_pc~0; 38380#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38381#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38923#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38924#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39003#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39004#L835-42 assume !(1 == ~t12_pc~0); 39300#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39301#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38976#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38977#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39845#L854-42 assume 1 == ~t13_pc~0; 39846#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38920#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38532#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38533#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39179#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39180#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39958#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38766#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38633#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38634#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39233#L1421-3 assume !(1 == ~T5_E~0); 39234#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38809#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38810#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38396#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38397#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39986#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39317#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38970#L1461-3 assume !(1 == ~T13_E~0); 38971#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40248#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38910#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38911#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39311#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38938#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38939#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39351#L1501-3 assume !(1 == ~E_8~0); 39352#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39778#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39768#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39769#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39468#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39469#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39863#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38745#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39638#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39279#L1911 assume !(0 == start_simulation_~tmp~3#1); 39280#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39802#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38869#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39740#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38574#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38575#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38804#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38805#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38988#L1892-2 [2021-11-22 16:03:43,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2021-11-22 16:03:43,452 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895500012] [2021-11-22 16:03:43,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895500012] [2021-11-22 16:03:43,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895500012] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,515 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963389741] [2021-11-22 16:03:43,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,516 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:43,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 2 times [2021-11-22 16:03:43,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837472644] [2021-11-22 16:03:43,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837472644] [2021-11-22 16:03:43,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837472644] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,573 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606326412] [2021-11-22 16:03:43,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,574 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:43,574 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:43,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:43,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:43,577 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:43,623 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2021-11-22 16:03:43,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:43,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2021-11-22 16:03:43,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-11-22 16:03:43,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:43,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:43,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2021-11-22 16:03:43,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:43,656 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-22 16:03:43,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2021-11-22 16:03:43,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:43,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-11-22 16:03:43,702 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-22 16:03:43,702 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-11-22 16:03:43,702 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-22 16:03:43,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2021-11-22 16:03:43,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:43,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:43,716 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,717 INFO L791 eck$LassoCheckResult]: Stem: 43061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42881#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42597#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42598#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43774#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43775#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42733#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42734#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43192#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43023#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43024#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42800#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42801#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43199#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43376#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43530#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43567#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42813#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42814#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43987#L1258-2 assume !(0 == ~T1_E~0); 43106#L1263-1 assume !(0 == ~T2_E~0); 43107#L1268-1 assume !(0 == ~T3_E~0); 43410#L1273-1 assume !(0 == ~T4_E~0); 43969#L1278-1 assume !(0 == ~T5_E~0); 43830#L1283-1 assume !(0 == ~T6_E~0); 43831#L1288-1 assume !(0 == ~T7_E~0); 44068#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44055#L1298-1 assume !(0 == ~T9_E~0); 43981#L1303-1 assume !(0 == ~T10_E~0); 42626#L1308-1 assume !(0 == ~T11_E~0); 42568#L1313-1 assume !(0 == ~T12_E~0); 42569#L1318-1 assume !(0 == ~T13_E~0); 42577#L1323-1 assume !(0 == ~E_1~0); 42578#L1328-1 assume !(0 == ~E_2~0); 42743#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43702#L1338-1 assume !(0 == ~E_4~0); 43703#L1343-1 assume !(0 == ~E_5~0); 43804#L1348-1 assume !(0 == ~E_6~0); 44090#L1353-1 assume !(0 == ~E_7~0); 43429#L1358-1 assume !(0 == ~E_8~0); 43430#L1363-1 assume !(0 == ~E_9~0); 43720#L1368-1 assume !(0 == ~E_10~0); 42405#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42406#L1378-1 assume !(0 == ~E_12~0); 42694#L1383-1 assume !(0 == ~E_13~0); 42695#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43436#L607 assume 1 == ~m_pc~0; 43437#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42763#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43802#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43356#L1560 assume !(0 != activate_threads_~tmp~1#1); 43357#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42588#L626 assume !(1 == ~t1_pc~0); 42589#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42857#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42858#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43029#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42490#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42491#L645 assume 1 == ~t2_pc~0; 42605#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42562#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43242#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43243#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43332#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43333#L664 assume 1 == ~t3_pc~0; 44089#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42333#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42334#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42988#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42989#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43997#L683 assume !(1 == ~t4_pc~0); 43552#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43504#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43505#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43539#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43663#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43286#L702 assume 1 == ~t5_pc~0; 43287#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43209#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43658#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43957#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43898#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42377#L721 assume !(1 == ~t6_pc~0); 42351#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42352#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42515#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42997#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42998#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43599#L740 assume 1 == ~t7_pc~0; 42426#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42239#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42240#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42229#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42230#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42934#L759 assume !(1 == ~t8_pc~0); 42935#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42963#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43656#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43657#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43788#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44066#L778 assume 1 == ~t9_pc~0; 43953#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42404#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42344#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42273#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42274#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42602#L797 assume !(1 == ~t10_pc~0); 42603#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42720#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43854#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43104#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43105#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43394#L816 assume 1 == ~t11_pc~0; 42309#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42310#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43067#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43004#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43005#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43529#L835 assume 1 == ~t12_pc~0; 43407#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42473#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42495#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42636#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43161#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43162#L854 assume !(1 == ~t13_pc~0); 42802#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42803#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42853#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42513#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42514#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1401 assume !(1 == ~M_E~0); 42992#L1401-2 assume !(1 == ~T1_E~0); 42993#L1406-1 assume !(1 == ~T2_E~0); 43588#L1411-1 assume !(1 == ~T3_E~0); 43589#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43255#L1421-1 assume !(1 == ~T5_E~0); 42798#L1426-1 assume !(1 == ~T6_E~0); 42799#L1431-1 assume !(1 == ~T7_E~0); 42347#L1436-1 assume !(1 == ~T8_E~0); 42348#L1441-1 assume !(1 == ~T9_E~0); 43097#L1446-1 assume !(1 == ~T10_E~0); 43098#L1451-1 assume !(1 == ~T11_E~0); 43801#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43455#L1461-1 assume !(1 == ~T13_E~0); 43016#L1466-1 assume !(1 == ~E_1~0); 43017#L1471-1 assume !(1 == ~E_2~0); 43786#L1476-1 assume !(1 == ~E_3~0); 43787#L1481-1 assume !(1 == ~E_4~0); 43935#L1486-1 assume !(1 == ~E_5~0); 42641#L1491-1 assume !(1 == ~E_6~0); 42281#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42282#L1501-1 assume !(1 == ~E_8~0); 43093#L1506-1 assume !(1 == ~E_9~0); 43094#L1511-1 assume !(1 == ~E_10~0); 43050#L1516-1 assume !(1 == ~E_11~0); 42227#L1521-1 assume !(1 == ~E_12~0); 42228#L1526-1 assume !(1 == ~E_13~0); 42280#L1531-1 assume { :end_inline_reset_delta_events } true; 42823#L1892-2 [2021-11-22 16:03:43,718 INFO L793 eck$LassoCheckResult]: Loop: 42823#L1892-2 assume !false; 43846#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44044#L1233 assume !false; 44027#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43359#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43339#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43497#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42323#L1046 assume !(0 != eval_~tmp~0#1); 42325#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42359#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43531#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44088#L1258-5 assume !(0 == ~T1_E~0); 42503#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42504#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44080#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44086#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44087#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42727#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42728#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43843#L1298-3 assume !(0 == ~T9_E~0); 43844#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44003#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43842#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43343#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42505#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42506#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43927#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42646#L1338-3 assume !(0 == ~E_4~0); 42647#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43759#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43933#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43934#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43301#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42859#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42860#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43616#L1378-3 assume !(0 == ~E_12~0); 43617#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43798#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43799#L607-42 assume 1 == ~m_pc~0; 43414#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43140#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43141#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42873#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42874#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43395#L626-42 assume 1 == ~t1_pc~0; 42957#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42958#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43262#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43263#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42537#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42538#L645-42 assume !(1 == ~t2_pc~0); 43736#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43737#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43903#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42744#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42251#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42252#L664-42 assume !(1 == ~t3_pc~0); 42778#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42779#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44030#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43565#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43566#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43731#L683-42 assume 1 == ~t4_pc~0; 44096#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43440#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43571#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43992#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43993#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43837#L702-42 assume !(1 == ~t5_pc~0); 42949#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42950#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43246#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43919#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42267#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42268#L721-42 assume 1 == ~t6_pc~0; 42421#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42441#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42905#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44072#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43077#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42923#L740-42 assume !(1 == ~t7_pc~0); 42660#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42661#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43202#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43057#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43058#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43331#L759-42 assume 1 == ~t8_pc~0; 43180#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43112#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43113#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43190#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43191#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43285#L778-42 assume 1 == ~t9_pc~0; 43124#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43126#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43535#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43441#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43442#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43499#L797-42 assume 1 == ~t10_pc~0; 42666#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42667#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43668#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43977#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43537#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43538#L816-42 assume 1 == ~t11_pc~0; 42215#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42216#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42758#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42759#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42838#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42839#L835-42 assume 1 == ~t12_pc~0; 43241#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43135#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42811#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42812#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43896#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43680#L854-42 assume 1 == ~t13_pc~0; 43681#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42755#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42367#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42368#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43014#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43015#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43793#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42601#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42468#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42469#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43068#L1421-3 assume !(1 == ~T5_E~0); 43069#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42644#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42645#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42231#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42232#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43821#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43152#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42805#L1461-3 assume !(1 == ~T13_E~0); 42806#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44083#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42745#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42746#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43146#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42773#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42774#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43185#L1501-3 assume !(1 == ~E_8~0); 43186#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43613#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43603#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43604#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43303#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43304#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43698#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42580#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43473#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43114#L1911 assume !(0 == start_simulation_~tmp~3#1); 43115#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43637#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42704#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43575#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42409#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42410#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42639#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42640#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42823#L1892-2 [2021-11-22 16:03:43,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2021-11-22 16:03:43,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382308143] [2021-11-22 16:03:43,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,721 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,756 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382308143] [2021-11-22 16:03:43,756 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382308143] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,758 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,759 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,760 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296925173] [2021-11-22 16:03:43,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,761 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:43,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,761 INFO L85 PathProgramCache]: Analyzing trace with hash -1815330241, now seen corresponding path program 1 times [2021-11-22 16:03:43,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725503700] [2021-11-22 16:03:43,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,807 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725503700] [2021-11-22 16:03:43,808 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725503700] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,808 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,808 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,808 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058296277] [2021-11-22 16:03:43,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,809 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:43,809 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:43,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:43,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:43,810 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:43,851 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2021-11-22 16:03:43,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:43,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2021-11-22 16:03:43,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-11-22 16:03:43,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:43,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:43,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2021-11-22 16:03:43,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:43,880 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-22 16:03:43,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2021-11-22 16:03:43,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:43,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:43,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-11-22 16:03:43,921 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-22 16:03:43,921 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-11-22 16:03:43,921 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-22 16:03:43,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2021-11-22 16:03:43,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:43,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:43,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:43,933 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:43,934 INFO L791 eck$LassoCheckResult]: Stem: 46896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46716#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46432#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46433#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47609#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47610#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46568#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46569#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47027#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46858#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46859#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46635#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46636#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47034#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47211#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47365#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47402#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46648#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46649#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47822#L1258-2 assume !(0 == ~T1_E~0); 46941#L1263-1 assume !(0 == ~T2_E~0); 46942#L1268-1 assume !(0 == ~T3_E~0); 47245#L1273-1 assume !(0 == ~T4_E~0); 47804#L1278-1 assume !(0 == ~T5_E~0); 47665#L1283-1 assume !(0 == ~T6_E~0); 47666#L1288-1 assume !(0 == ~T7_E~0); 47902#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47890#L1298-1 assume !(0 == ~T9_E~0); 47816#L1303-1 assume !(0 == ~T10_E~0); 46461#L1308-1 assume !(0 == ~T11_E~0); 46403#L1313-1 assume !(0 == ~T12_E~0); 46404#L1318-1 assume !(0 == ~T13_E~0); 46412#L1323-1 assume !(0 == ~E_1~0); 46413#L1328-1 assume !(0 == ~E_2~0); 46578#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47537#L1338-1 assume !(0 == ~E_4~0); 47538#L1343-1 assume !(0 == ~E_5~0); 47639#L1348-1 assume !(0 == ~E_6~0); 47925#L1353-1 assume !(0 == ~E_7~0); 47264#L1358-1 assume !(0 == ~E_8~0); 47265#L1363-1 assume !(0 == ~E_9~0); 47555#L1368-1 assume !(0 == ~E_10~0); 46240#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46241#L1378-1 assume !(0 == ~E_12~0); 46529#L1383-1 assume !(0 == ~E_13~0); 46530#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47271#L607 assume 1 == ~m_pc~0; 47272#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46598#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47637#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47191#L1560 assume !(0 != activate_threads_~tmp~1#1); 47192#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46423#L626 assume !(1 == ~t1_pc~0); 46424#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46692#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46693#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46862#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46325#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46326#L645 assume 1 == ~t2_pc~0; 46440#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46397#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47077#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47078#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47167#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47168#L664 assume 1 == ~t3_pc~0; 47924#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46166#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46167#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46823#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46824#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47832#L683 assume !(1 == ~t4_pc~0); 47387#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47339#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47340#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47374#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47498#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47121#L702 assume 1 == ~t5_pc~0; 47122#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47044#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47493#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47792#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47733#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46212#L721 assume !(1 == ~t6_pc~0); 46186#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46187#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46350#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46832#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46833#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47434#L740 assume 1 == ~t7_pc~0; 46261#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46074#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46075#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46064#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46065#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46769#L759 assume !(1 == ~t8_pc~0); 46770#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46798#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47491#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47492#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47623#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47901#L778 assume 1 == ~t9_pc~0; 47788#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46239#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46179#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46108#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46109#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46437#L797 assume !(1 == ~t10_pc~0); 46438#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46555#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47689#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46939#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46940#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47229#L816 assume 1 == ~t11_pc~0; 46144#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46145#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46902#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46839#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46840#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47364#L835 assume 1 == ~t12_pc~0; 47242#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46308#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46330#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46471#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46996#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46997#L854 assume !(1 == ~t13_pc~0); 46637#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46638#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46688#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46348#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46349#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47728#L1401 assume !(1 == ~M_E~0); 46827#L1401-2 assume !(1 == ~T1_E~0); 46828#L1406-1 assume !(1 == ~T2_E~0); 47423#L1411-1 assume !(1 == ~T3_E~0); 47424#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47090#L1421-1 assume !(1 == ~T5_E~0); 46633#L1426-1 assume !(1 == ~T6_E~0); 46634#L1431-1 assume !(1 == ~T7_E~0); 46182#L1436-1 assume !(1 == ~T8_E~0); 46183#L1441-1 assume !(1 == ~T9_E~0); 46932#L1446-1 assume !(1 == ~T10_E~0); 46933#L1451-1 assume !(1 == ~T11_E~0); 47636#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47290#L1461-1 assume !(1 == ~T13_E~0); 46851#L1466-1 assume !(1 == ~E_1~0); 46852#L1471-1 assume !(1 == ~E_2~0); 47621#L1476-1 assume !(1 == ~E_3~0); 47622#L1481-1 assume !(1 == ~E_4~0); 47770#L1486-1 assume !(1 == ~E_5~0); 46476#L1491-1 assume !(1 == ~E_6~0); 46116#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46117#L1501-1 assume !(1 == ~E_8~0); 46928#L1506-1 assume !(1 == ~E_9~0); 46929#L1511-1 assume !(1 == ~E_10~0); 46885#L1516-1 assume !(1 == ~E_11~0); 46062#L1521-1 assume !(1 == ~E_12~0); 46063#L1526-1 assume !(1 == ~E_13~0); 46115#L1531-1 assume { :end_inline_reset_delta_events } true; 46658#L1892-2 [2021-11-22 16:03:43,935 INFO L793 eck$LassoCheckResult]: Loop: 46658#L1892-2 assume !false; 47681#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47879#L1233 assume !false; 47862#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47194#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47174#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47332#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46158#L1046 assume !(0 != eval_~tmp~0#1); 46160#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46194#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47366#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47923#L1258-5 assume !(0 == ~T1_E~0); 46338#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46339#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47915#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47921#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47922#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46562#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46563#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47678#L1298-3 assume !(0 == ~T9_E~0); 47679#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47838#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47677#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47178#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46340#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46341#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47762#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46481#L1338-3 assume !(0 == ~E_4~0); 46482#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47594#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47768#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47769#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47136#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46694#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46695#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47451#L1378-3 assume !(0 == ~E_12~0); 47452#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47633#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47634#L607-42 assume 1 == ~m_pc~0; 47249#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46975#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46976#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46708#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46709#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47233#L626-42 assume 1 == ~t1_pc~0; 46795#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46796#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47097#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47098#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46372#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46373#L645-42 assume !(1 == ~t2_pc~0); 47572#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47573#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47738#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46579#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46086#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46087#L664-42 assume !(1 == ~t3_pc~0); 46610#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46611#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47865#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47400#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47401#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47566#L683-42 assume !(1 == ~t4_pc~0); 47273#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47274#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47406#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47827#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47828#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47672#L702-42 assume 1 == ~t5_pc~0; 47160#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46784#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47081#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47754#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46100#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46101#L721-42 assume 1 == ~t6_pc~0; 46256#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46276#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46740#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47907#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46912#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46758#L740-42 assume 1 == ~t7_pc~0; 46759#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46496#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47037#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46892#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 46893#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47166#L759-42 assume 1 == ~t8_pc~0; 47015#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46947#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46948#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47025#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47026#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47120#L778-42 assume !(1 == ~t9_pc~0); 46960#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 46961#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47370#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47275#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47276#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47334#L797-42 assume 1 == ~t10_pc~0; 46501#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46502#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47503#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47812#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47372#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47373#L816-42 assume 1 == ~t11_pc~0; 46050#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46051#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46593#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46594#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46673#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46674#L835-42 assume 1 == ~t12_pc~0; 47076#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46968#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46646#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46647#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47731#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47515#L854-42 assume 1 == ~t13_pc~0; 47516#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46590#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46202#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46203#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46849#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46850#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47628#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46436#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46303#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46304#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46903#L1421-3 assume !(1 == ~T5_E~0); 46904#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46479#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46480#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46066#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46067#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47656#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46987#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46640#L1461-3 assume !(1 == ~T13_E~0); 46641#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47918#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46580#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46581#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46981#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46608#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46609#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47020#L1501-3 assume !(1 == ~E_8~0); 47021#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47448#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47438#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47439#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47138#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47139#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47533#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46415#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47308#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46949#L1911 assume !(0 == start_simulation_~tmp~3#1); 46950#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47472#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46539#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47410#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46244#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46245#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46474#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46475#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46658#L1892-2 [2021-11-22 16:03:43,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,936 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2021-11-22 16:03:43,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751108556] [2021-11-22 16:03:43,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:43,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:43,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:43,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751108556] [2021-11-22 16:03:43,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751108556] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:43,970 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:43,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:43,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740709246] [2021-11-22 16:03:43,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:43,972 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:43,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:43,972 INFO L85 PathProgramCache]: Analyzing trace with hash -199797377, now seen corresponding path program 1 times [2021-11-22 16:03:43,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:43,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642768162] [2021-11-22 16:03:43,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:43,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:43,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:44,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:44,049 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:44,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642768162] [2021-11-22 16:03:44,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642768162] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:44,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:44,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:44,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431622223] [2021-11-22 16:03:44,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:44,050 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:44,050 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:44,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:44,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:44,051 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:44,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:44,115 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2021-11-22 16:03:44,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:44,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2021-11-22 16:03:44,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:44,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-11-22 16:03:44,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-11-22 16:03:44,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-11-22 16:03:44,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2021-11-22 16:03:44,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:44,155 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-22 16:03:44,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2021-11-22 16:03:44,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-11-22 16:03:44,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:44,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-11-22 16:03:44,194 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-22 16:03:44,194 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-11-22 16:03:44,194 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-22 16:03:44,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2021-11-22 16:03:44,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-11-22 16:03:44,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:44,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:44,206 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:44,206 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:44,207 INFO L791 eck$LassoCheckResult]: Stem: 50731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50551#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50267#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50268#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51444#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51445#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50403#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50404#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50860#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50693#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50694#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50470#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50471#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50869#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51046#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51200#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51237#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50483#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50484#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51657#L1258-2 assume !(0 == ~T1_E~0); 50776#L1263-1 assume !(0 == ~T2_E~0); 50777#L1268-1 assume !(0 == ~T3_E~0); 51080#L1273-1 assume !(0 == ~T4_E~0); 51639#L1278-1 assume !(0 == ~T5_E~0); 51500#L1283-1 assume !(0 == ~T6_E~0); 51501#L1288-1 assume !(0 == ~T7_E~0); 51737#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51725#L1298-1 assume !(0 == ~T9_E~0); 51651#L1303-1 assume !(0 == ~T10_E~0); 50296#L1308-1 assume !(0 == ~T11_E~0); 50238#L1313-1 assume !(0 == ~T12_E~0); 50239#L1318-1 assume !(0 == ~T13_E~0); 50247#L1323-1 assume !(0 == ~E_1~0); 50248#L1328-1 assume !(0 == ~E_2~0); 50413#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51372#L1338-1 assume !(0 == ~E_4~0); 51373#L1343-1 assume !(0 == ~E_5~0); 51474#L1348-1 assume !(0 == ~E_6~0); 51760#L1353-1 assume !(0 == ~E_7~0); 51099#L1358-1 assume !(0 == ~E_8~0); 51100#L1363-1 assume !(0 == ~E_9~0); 51390#L1368-1 assume !(0 == ~E_10~0); 50075#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50076#L1378-1 assume !(0 == ~E_12~0); 50364#L1383-1 assume !(0 == ~E_13~0); 50365#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51106#L607 assume 1 == ~m_pc~0; 51107#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50433#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51472#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51026#L1560 assume !(0 != activate_threads_~tmp~1#1); 51027#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50258#L626 assume !(1 == ~t1_pc~0); 50259#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50527#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50528#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50697#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50158#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50159#L645 assume 1 == ~t2_pc~0; 50275#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50232#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50912#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50913#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51002#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51003#L664 assume 1 == ~t3_pc~0; 51759#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49999#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50000#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50658#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50659#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51667#L683 assume !(1 == ~t4_pc~0); 51222#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51174#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51175#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51209#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51333#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50956#L702 assume 1 == ~t5_pc~0; 50957#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50879#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51328#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51627#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51568#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50047#L721 assume !(1 == ~t6_pc~0); 50021#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50022#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50185#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50667#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50668#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51269#L740 assume 1 == ~t7_pc~0; 50096#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49909#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49910#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49899#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49900#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50604#L759 assume !(1 == ~t8_pc~0); 50605#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50633#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51326#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51327#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51458#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51736#L778 assume 1 == ~t9_pc~0; 51623#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50074#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50014#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49943#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49944#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50272#L797 assume !(1 == ~t10_pc~0); 50273#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50390#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51524#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50774#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50775#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51064#L816 assume 1 == ~t11_pc~0; 49979#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49980#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50737#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50674#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50675#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51199#L835 assume 1 == ~t12_pc~0; 51077#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50143#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50165#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50306#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50831#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50832#L854 assume !(1 == ~t13_pc~0); 50472#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50473#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50523#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50183#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50184#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51563#L1401 assume !(1 == ~M_E~0); 50662#L1401-2 assume !(1 == ~T1_E~0); 50663#L1406-1 assume !(1 == ~T2_E~0); 51258#L1411-1 assume !(1 == ~T3_E~0); 51259#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50925#L1421-1 assume !(1 == ~T5_E~0); 50468#L1426-1 assume !(1 == ~T6_E~0); 50469#L1431-1 assume !(1 == ~T7_E~0); 50017#L1436-1 assume !(1 == ~T8_E~0); 50018#L1441-1 assume !(1 == ~T9_E~0); 50767#L1446-1 assume !(1 == ~T10_E~0); 50768#L1451-1 assume !(1 == ~T11_E~0); 51471#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51125#L1461-1 assume !(1 == ~T13_E~0); 50686#L1466-1 assume !(1 == ~E_1~0); 50687#L1471-1 assume !(1 == ~E_2~0); 51456#L1476-1 assume !(1 == ~E_3~0); 51457#L1481-1 assume !(1 == ~E_4~0); 51605#L1486-1 assume !(1 == ~E_5~0); 50311#L1491-1 assume !(1 == ~E_6~0); 49951#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49952#L1501-1 assume !(1 == ~E_8~0); 50763#L1506-1 assume !(1 == ~E_9~0); 50764#L1511-1 assume !(1 == ~E_10~0); 50720#L1516-1 assume !(1 == ~E_11~0); 49895#L1521-1 assume !(1 == ~E_12~0); 49896#L1526-1 assume !(1 == ~E_13~0); 49950#L1531-1 assume { :end_inline_reset_delta_events } true; 50493#L1892-2 [2021-11-22 16:03:44,207 INFO L793 eck$LassoCheckResult]: Loop: 50493#L1892-2 assume !false; 51516#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51714#L1233 assume !false; 51697#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51029#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51009#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51167#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49993#L1046 assume !(0 != eval_~tmp~0#1); 49995#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50029#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51201#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51758#L1258-5 assume !(0 == ~T1_E~0); 50171#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50172#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51750#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51756#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51757#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50397#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50398#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51513#L1298-3 assume !(0 == ~T9_E~0); 51514#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51673#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51512#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51013#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50173#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50174#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51597#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50316#L1338-3 assume !(0 == ~E_4~0); 50317#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51429#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51603#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51604#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50971#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50529#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50530#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51286#L1378-3 assume !(0 == ~E_12~0); 51287#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51468#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51469#L607-42 assume 1 == ~m_pc~0; 51084#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50810#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50811#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50543#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50544#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51068#L626-42 assume 1 == ~t1_pc~0; 50630#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50631#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50932#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50933#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50207#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50208#L645-42 assume 1 == ~t2_pc~0; 51666#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51408#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51573#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50414#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49921#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49922#L664-42 assume !(1 == ~t3_pc~0); 50449#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 50450#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51700#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51235#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51236#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51401#L683-42 assume 1 == ~t4_pc~0; 51766#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51112#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51242#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51662#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51663#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51510#L702-42 assume 1 == ~t5_pc~0; 50998#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50620#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50918#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51589#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49935#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49936#L721-42 assume 1 == ~t6_pc~0; 50090#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50111#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50575#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51742#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50747#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50591#L740-42 assume 1 == ~t7_pc~0; 50592#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50328#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50872#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50727#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 50728#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51001#L759-42 assume 1 == ~t8_pc~0; 50850#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50782#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50783#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50858#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50859#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50955#L778-42 assume 1 == ~t9_pc~0; 50794#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50796#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51204#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51108#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51109#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51169#L797-42 assume 1 == ~t10_pc~0; 50336#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50337#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51338#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51647#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51207#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51208#L816-42 assume 1 == ~t11_pc~0; 49885#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49886#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50428#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50429#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50508#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50509#L835-42 assume !(1 == ~t12_pc~0); 50802#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50803#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50481#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50482#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51566#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51350#L854-42 assume 1 == ~t13_pc~0; 51351#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50425#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50037#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50038#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50684#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50685#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51463#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50271#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50138#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50139#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50738#L1421-3 assume !(1 == ~T5_E~0); 50739#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50314#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50315#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49901#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49902#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51491#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50822#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50475#L1461-3 assume !(1 == ~T13_E~0); 50476#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51753#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50415#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50416#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50816#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50443#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50444#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50855#L1501-3 assume !(1 == ~E_8~0); 50856#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51283#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51272#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51273#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50973#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50974#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51368#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50250#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51143#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50784#L1911 assume !(0 == start_simulation_~tmp~3#1); 50785#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51307#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50374#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51245#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50079#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50080#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50309#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50310#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50493#L1892-2 [2021-11-22 16:03:44,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:44,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2021-11-22 16:03:44,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:44,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008659626] [2021-11-22 16:03:44,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:44,209 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:44,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:44,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:44,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:44,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008659626] [2021-11-22 16:03:44,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008659626] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:44,252 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:44,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 16:03:44,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432743365] [2021-11-22 16:03:44,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:44,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:44,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:44,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1807690879, now seen corresponding path program 1 times [2021-11-22 16:03:44,255 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:44,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494236928] [2021-11-22 16:03:44,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:44,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:44,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:44,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:44,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494236928] [2021-11-22 16:03:44,299 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494236928] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:44,299 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:44,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:44,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106356935] [2021-11-22 16:03:44,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:44,300 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:44,300 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:44,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:03:44,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:03:44,301 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:44,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:44,453 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2021-11-22 16:03:44,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:03:44,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2021-11-22 16:03:44,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-11-22 16:03:44,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-11-22 16:03:44,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2021-11-22 16:03:44,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2021-11-22 16:03:44,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2021-11-22 16:03:44,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:44,497 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-22 16:03:44,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2021-11-22 16:03:44,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2021-11-22 16:03:44,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:44,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-11-22 16:03:44,575 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-22 16:03:44,575 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-11-22 16:03:44,575 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-22 16:03:44,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2021-11-22 16:03:44,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-11-22 16:03:44,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:44,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:44,597 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:44,597 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:44,598 INFO L791 eck$LassoCheckResult]: Stem: 56211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56030#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55745#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55746#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55882#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55883#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56338#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56173#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56174#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55949#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55950#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56349#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56530#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56682#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56719#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55960#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55961#L1258 assume !(0 == ~M_E~0); 57166#L1258-2 assume !(0 == ~T1_E~0); 56256#L1263-1 assume !(0 == ~T2_E~0); 56257#L1268-1 assume !(0 == ~T3_E~0); 56564#L1273-1 assume !(0 == ~T4_E~0); 57145#L1278-1 assume !(0 == ~T5_E~0); 56987#L1283-1 assume !(0 == ~T6_E~0); 56988#L1288-1 assume !(0 == ~T7_E~0); 57269#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57160#L1303-1 assume !(0 == ~T10_E~0); 55775#L1308-1 assume !(0 == ~T11_E~0); 55716#L1313-1 assume !(0 == ~T12_E~0); 55717#L1318-1 assume !(0 == ~T13_E~0); 55723#L1323-1 assume !(0 == ~E_1~0); 55724#L1328-1 assume !(0 == ~E_2~0); 55892#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56856#L1338-1 assume !(0 == ~E_4~0); 56857#L1343-1 assume !(0 == ~E_5~0); 56960#L1348-1 assume !(0 == ~E_6~0); 57302#L1353-1 assume !(0 == ~E_7~0); 56583#L1358-1 assume !(0 == ~E_8~0); 56584#L1363-1 assume !(0 == ~E_9~0); 56875#L1368-1 assume !(0 == ~E_10~0); 55552#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55553#L1378-1 assume !(0 == ~E_12~0); 55841#L1383-1 assume !(0 == ~E_13~0); 55842#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56589#L607 assume !(1 == ~m_pc~0); 55911#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55912#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56958#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55736#L626 assume !(1 == ~t1_pc~0); 55737#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56006#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56007#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56177#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55635#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55636#L645 assume 1 == ~t2_pc~0; 55753#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55710#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56484#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56485#L664 assume 1 == ~t3_pc~0; 57299#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55475#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55476#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56138#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56139#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57177#L683 assume !(1 == ~t4_pc~0); 56704#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56656#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56657#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56691#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56817#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56812#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57130#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57062#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55524#L721 assume !(1 == ~t6_pc~0); 55497#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55498#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55662#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56147#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56148#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56752#L740 assume 1 == ~t7_pc~0; 55573#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55385#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55386#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55375#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55376#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56083#L759 assume !(1 == ~t8_pc~0); 56084#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56113#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56810#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56811#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57268#L778 assume 1 == ~t9_pc~0; 57127#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55551#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55490#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55419#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55420#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55749#L797 assume !(1 == ~t10_pc~0); 55750#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55869#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57015#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56254#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56255#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56548#L816 assume 1 == ~t11_pc~0; 55455#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55456#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56215#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56154#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56155#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56681#L835 assume 1 == ~t12_pc~0; 56561#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55620#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55642#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55785#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56311#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56312#L854 assume !(1 == ~t13_pc~0); 55951#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55952#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56002#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55660#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55661#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57057#L1401 assume !(1 == ~M_E~0); 56142#L1401-2 assume !(1 == ~T1_E~0); 56143#L1406-1 assume !(1 == ~T2_E~0); 56741#L1411-1 assume !(1 == ~T3_E~0); 56742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55947#L1426-1 assume !(1 == ~T6_E~0); 55948#L1431-1 assume !(1 == ~T7_E~0); 55493#L1436-1 assume !(1 == ~T8_E~0); 55494#L1441-1 assume !(1 == ~T9_E~0); 56245#L1446-1 assume !(1 == ~T10_E~0); 56246#L1451-1 assume !(1 == ~T11_E~0); 56957#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56607#L1461-1 assume !(1 == ~T13_E~0); 56166#L1466-1 assume !(1 == ~E_1~0); 56167#L1471-1 assume !(1 == ~E_2~0); 56941#L1476-1 assume !(1 == ~E_3~0); 56942#L1481-1 assume !(1 == ~E_4~0); 57107#L1486-1 assume !(1 == ~E_5~0); 55790#L1491-1 assume !(1 == ~E_6~0); 55427#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55428#L1501-1 assume !(1 == ~E_8~0); 56243#L1506-1 assume !(1 == ~E_9~0); 56244#L1511-1 assume !(1 == ~E_10~0); 56200#L1516-1 assume !(1 == ~E_11~0); 55371#L1521-1 assume !(1 == ~E_12~0); 55372#L1526-1 assume !(1 == ~E_13~0); 55426#L1531-1 assume { :end_inline_reset_delta_events } true; 55972#L1892-2 [2021-11-22 16:03:44,598 INFO L793 eck$LassoCheckResult]: Loop: 55972#L1892-2 assume !false; 57358#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57240#L1233 assume !false; 57241#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56491#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56649#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55469#L1046 assume !(0 != eval_~tmp~0#1); 55471#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58740#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58739#L1258-3 assume !(0 == ~M_E~0); 58738#L1258-5 assume !(0 == ~T1_E~0); 58737#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58736#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58735#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58733#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58732#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58731#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58730#L1298-3 assume !(0 == ~T9_E~0); 58729#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58728#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58727#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58726#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58725#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58724#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58442#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58441#L1338-3 assume !(0 == ~E_4~0); 58413#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58412#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58410#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58408#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58405#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58403#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58401#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58399#L1378-3 assume !(0 == ~E_12~0); 58397#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 58395#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58392#L607-42 assume !(1 == ~m_pc~0); 58389#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58387#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58385#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58383#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58381#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58378#L626-42 assume 1 == ~t1_pc~0; 58375#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58373#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58372#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58371#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58369#L645-42 assume 1 == ~t2_pc~0; 58368#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58366#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58365#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58364#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58363#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58362#L664-42 assume 1 == ~t3_pc~0; 58360#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58359#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58357#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58356#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58355#L683-42 assume !(1 == ~t4_pc~0); 58350#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58348#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58345#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58343#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58341#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58339#L702-42 assume 1 == ~t5_pc~0; 58336#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58334#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58333#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58332#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58286#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58285#L721-42 assume !(1 == ~t6_pc~0); 58282#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58280#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58277#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58275#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58263#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58260#L740-42 assume 1 == ~t7_pc~0; 58257#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58255#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58253#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58251#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 58250#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58249#L759-42 assume 1 == ~t8_pc~0; 58247#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58246#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56517#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56341#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56342#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56437#L778-42 assume 1 == ~t9_pc~0; 56274#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56276#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56688#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58233#L797-42 assume 1 == ~t10_pc~0; 58230#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58228#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58225#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58224#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58223#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58222#L816-42 assume !(1 == ~t11_pc~0); 58220#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58219#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58218#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58216#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58214#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57883#L835-42 assume 1 == ~t12_pc~0; 57881#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57065#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55962#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55963#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56834#L854-42 assume !(1 == ~t13_pc~0); 55905#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 55906#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55514#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55515#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56164#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56165#L1401-3 assume !(1 == ~M_E~0); 56948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55752#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55615#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55616#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56218#L1421-3 assume !(1 == ~T5_E~0); 56219#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55793#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55794#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55377#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55378#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56978#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56302#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55954#L1461-3 assume !(1 == ~T13_E~0); 55955#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57852#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57851#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57850#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57849#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57848#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57220#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56336#L1501-3 assume !(1 == ~E_8~0); 56337#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57846#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57845#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 57844#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57843#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57842#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57735#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57728#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57726#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57724#L1911 assume !(0 == start_simulation_~tmp~3#1); 57098#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56791#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 55853#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56727#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55556#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55557#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55788#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 55789#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55972#L1892-2 [2021-11-22 16:03:44,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:44,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2021-11-22 16:03:44,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:44,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326726272] [2021-11-22 16:03:44,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:44,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:44,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:44,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:44,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:44,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326726272] [2021-11-22 16:03:44,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326726272] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:44,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:44,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:44,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576898224] [2021-11-22 16:03:44,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:44,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:44,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:44,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1550267110, now seen corresponding path program 1 times [2021-11-22 16:03:44,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:44,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982467742] [2021-11-22 16:03:44,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:44,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:44,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:44,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:44,685 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:44,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982467742] [2021-11-22 16:03:44,686 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982467742] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:44,687 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:44,687 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:44,687 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030100388] [2021-11-22 16:03:44,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:44,688 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:44,688 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:44,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 16:03:44,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 16:03:44,689 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:44,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:44,925 INFO L93 Difference]: Finished difference Result 6963 states and 10201 transitions. [2021-11-22 16:03:44,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 16:03:44,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6963 states and 10201 transitions. [2021-11-22 16:03:44,959 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2021-11-22 16:03:44,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6963 states to 6963 states and 10201 transitions. [2021-11-22 16:03:44,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6963 [2021-11-22 16:03:44,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6963 [2021-11-22 16:03:44,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6963 states and 10201 transitions. [2021-11-22 16:03:45,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:45,002 INFO L681 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-22 16:03:45,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6963 states and 10201 transitions. [2021-11-22 16:03:45,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6963 to 6963. [2021-11-22 16:03:45,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6963 states, 6963 states have (on average 1.465029441332759) internal successors, (10201), 6962 states have internal predecessors, (10201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:45,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6963 states to 6963 states and 10201 transitions. [2021-11-22 16:03:45,142 INFO L704 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-22 16:03:45,143 INFO L587 BuchiCegarLoop]: Abstraction has 6963 states and 10201 transitions. [2021-11-22 16:03:45,143 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-22 16:03:45,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6963 states and 10201 transitions. [2021-11-22 16:03:45,169 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2021-11-22 16:03:45,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:45,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:45,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:45,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:45,174 INFO L791 eck$LassoCheckResult]: Stem: 66745#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 66560#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66271#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66272#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67496#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67497#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66409#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66410#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66875#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66704#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66705#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66477#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66478#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66886#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67068#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67224#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67265#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66490#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66491#L1258 assume !(0 == ~M_E~0); 67741#L1258-2 assume !(0 == ~T1_E~0); 66792#L1263-1 assume !(0 == ~T2_E~0); 66793#L1268-1 assume !(0 == ~T3_E~0); 67102#L1273-1 assume !(0 == ~T4_E~0); 67721#L1278-1 assume !(0 == ~T5_E~0); 67554#L1283-1 assume !(0 == ~T6_E~0); 67555#L1288-1 assume !(0 == ~T7_E~0); 67858#L1293-1 assume !(0 == ~T8_E~0); 67841#L1298-1 assume !(0 == ~T9_E~0); 67734#L1303-1 assume !(0 == ~T10_E~0); 66301#L1308-1 assume !(0 == ~T11_E~0); 66242#L1313-1 assume !(0 == ~T12_E~0); 66243#L1318-1 assume !(0 == ~T13_E~0); 66249#L1323-1 assume !(0 == ~E_1~0); 66250#L1328-1 assume !(0 == ~E_2~0); 66419#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67412#L1338-1 assume !(0 == ~E_4~0); 67413#L1343-1 assume !(0 == ~E_5~0); 67526#L1348-1 assume !(0 == ~E_6~0); 67896#L1353-1 assume !(0 == ~E_7~0); 67122#L1358-1 assume !(0 == ~E_8~0); 67123#L1363-1 assume !(0 == ~E_9~0); 67438#L1368-1 assume !(0 == ~E_10~0); 66079#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66080#L1378-1 assume !(0 == ~E_12~0); 66368#L1383-1 assume !(0 == ~E_13~0); 66369#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67129#L607 assume !(1 == ~m_pc~0); 66438#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66439#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67524#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67045#L1560 assume !(0 != activate_threads_~tmp~1#1); 67046#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66262#L626 assume !(1 == ~t1_pc~0); 66263#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66536#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66537#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66708#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66162#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66163#L645 assume 1 == ~t2_pc~0; 66279#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66236#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66928#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66929#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67021#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67022#L664 assume 1 == ~t3_pc~0; 67890#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66003#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66004#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66668#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66669#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67756#L683 assume !(1 == ~t4_pc~0); 67250#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67198#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67199#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67234#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67371#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66970#L702 assume 1 == ~t5_pc~0; 66971#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66895#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67366#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67707#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67630#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66051#L721 assume !(1 == ~t6_pc~0); 66025#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66026#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66189#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66678#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66679#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67301#L740 assume 1 == ~t7_pc~0; 66100#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65913#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65914#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65903#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65904#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66612#L759 assume !(1 == ~t8_pc~0); 66613#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66643#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67364#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67365#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67510#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67857#L778 assume 1 == ~t9_pc~0; 67703#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66078#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66018#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65947#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65948#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66276#L797 assume !(1 == ~t10_pc~0); 66277#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66396#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67582#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66790#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66791#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67086#L816 assume 1 == ~t11_pc~0; 65983#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65984#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66752#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66685#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66686#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67223#L835 assume 1 == ~t12_pc~0; 67099#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66147#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66169#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66311#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66847#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66848#L854 assume !(1 == ~t13_pc~0); 66479#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66480#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66532#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66187#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66188#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67625#L1401 assume !(1 == ~M_E~0); 66672#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66673#L1406-1 assume !(1 == ~T2_E~0); 67290#L1411-1 assume !(1 == ~T3_E~0); 67291#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66942#L1421-1 assume !(1 == ~T5_E~0); 66475#L1426-1 assume !(1 == ~T6_E~0); 66476#L1431-1 assume !(1 == ~T7_E~0); 66021#L1436-1 assume !(1 == ~T8_E~0); 66022#L1441-1 assume !(1 == ~T9_E~0); 66781#L1446-1 assume !(1 == ~T10_E~0); 66782#L1451-1 assume !(1 == ~T11_E~0); 67523#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67149#L1461-1 assume !(1 == ~T13_E~0); 66697#L1466-1 assume !(1 == ~E_1~0); 66698#L1471-1 assume !(1 == ~E_2~0); 67508#L1476-1 assume !(1 == ~E_3~0); 67509#L1481-1 assume !(1 == ~E_4~0); 67678#L1486-1 assume !(1 == ~E_5~0); 66316#L1491-1 assume !(1 == ~E_6~0); 65955#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65956#L1501-1 assume !(1 == ~E_8~0); 66779#L1506-1 assume !(1 == ~E_9~0); 66780#L1511-1 assume !(1 == ~E_10~0); 66734#L1516-1 assume !(1 == ~E_11~0); 65899#L1521-1 assume !(1 == ~E_12~0); 65900#L1526-1 assume !(1 == ~E_13~0); 65954#L1531-1 assume { :end_inline_reset_delta_events } true; 69419#L1892-2 [2021-11-22 16:03:45,174 INFO L793 eck$LassoCheckResult]: Loop: 69419#L1892-2 assume !false; 67977#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67821#L1233 assume !false; 67822#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67048#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67028#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67919#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65997#L1046 assume !(0 != eval_~tmp~0#1); 65999#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66033#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67225#L1258-3 assume !(0 == ~M_E~0); 67889#L1258-5 assume !(0 == ~T1_E~0); 72824#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72822#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72820#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72818#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72816#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72814#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72812#L1293-3 assume !(0 == ~T8_E~0); 72810#L1298-3 assume !(0 == ~T9_E~0); 72808#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 72806#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 72804#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 72802#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 72800#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72798#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72796#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72794#L1338-3 assume !(0 == ~E_4~0); 72792#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72790#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72788#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72786#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72784#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72782#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 72780#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 72778#L1378-3 assume !(0 == ~E_12~0); 72776#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 72774#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72772#L607-42 assume !(1 == ~m_pc~0); 72768#L607-44 is_master_triggered_~__retres1~0#1 := 0; 72766#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72695#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72694#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72693#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72692#L626-42 assume !(1 == ~t1_pc~0); 72691#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 72689#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72688#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72687#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72686#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72685#L645-42 assume !(1 == ~t2_pc~0); 72683#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 72682#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67637#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66420#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65925#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65926#L664-42 assume 1 == ~t3_pc~0; 66738#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66456#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67801#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67263#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67264#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67449#L683-42 assume 1 == ~t4_pc~0; 67905#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67133#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67271#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67749#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67750#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67562#L702-42 assume !(1 == ~t5_pc~0); 66629#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 66630#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66933#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67660#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65941#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65942#L721-42 assume !(1 == ~t6_pc~0); 66096#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66115#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66584#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67863#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66762#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66602#L740-42 assume !(1 == ~t7_pc~0); 66336#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 66337#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66889#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66741#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 66742#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67020#L759-42 assume 1 == ~t8_pc~0; 66867#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66798#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66799#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66878#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66879#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66975#L778-42 assume !(1 == ~t9_pc~0); 66811#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 66812#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67231#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70212#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70210#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70208#L797-42 assume 1 == ~t10_pc~0; 70203#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70201#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70199#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70197#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70021#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70019#L816-42 assume 1 == ~t11_pc~0; 70017#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70014#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70012#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70010#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 70009#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70008#L835-42 assume !(1 == ~t12_pc~0); 70005#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 70002#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70000#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69998#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69996#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69994#L854-42 assume 1 == ~t13_pc~0; 69991#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69988#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69986#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69984#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69982#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69979#L1401-3 assume !(1 == ~M_E~0); 69977#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69975#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69973#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69971#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69969#L1421-3 assume !(1 == ~T5_E~0); 69967#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69965#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69964#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69961#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69960#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69959#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69958#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69957#L1461-3 assume !(1 == ~T13_E~0); 69956#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69955#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69954#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69953#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69952#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69951#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69950#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69949#L1501-3 assume !(1 == ~E_8~0); 69948#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69947#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69946#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69945#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69944#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69238#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69239#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69198#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69199#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 69193#L1911 assume !(0 == start_simulation_~tmp~3#1); 69190#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69191#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67457#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67274#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 66083#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66084#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66314#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 66315#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 69419#L1892-2 [2021-11-22 16:03:45,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:45,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1174343799, now seen corresponding path program 1 times [2021-11-22 16:03:45,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:45,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090787680] [2021-11-22 16:03:45,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:45,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:45,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:45,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:45,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:45,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090787680] [2021-11-22 16:03:45,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090787680] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:45,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:45,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:45,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880258092] [2021-11-22 16:03:45,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:45,215 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:45,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:45,216 INFO L85 PathProgramCache]: Analyzing trace with hash 859455285, now seen corresponding path program 1 times [2021-11-22 16:03:45,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:45,216 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667748712] [2021-11-22 16:03:45,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:45,217 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:45,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:45,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:45,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:45,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667748712] [2021-11-22 16:03:45,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667748712] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:45,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:45,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:45,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646956434] [2021-11-22 16:03:45,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:45,263 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:45,263 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:45,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 16:03:45,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 16:03:45,264 INFO L87 Difference]: Start difference. First operand 6963 states and 10201 transitions. cyclomatic complexity: 3240 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:45,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:45,576 INFO L93 Difference]: Finished difference Result 13361 states and 19570 transitions. [2021-11-22 16:03:45,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 16:03:45,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13361 states and 19570 transitions. [2021-11-22 16:03:45,639 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2021-11-22 16:03:45,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13361 states to 13361 states and 19570 transitions. [2021-11-22 16:03:45,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13361 [2021-11-22 16:03:45,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13361 [2021-11-22 16:03:45,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13361 states and 19570 transitions. [2021-11-22 16:03:45,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:45,716 INFO L681 BuchiCegarLoop]: Abstraction has 13361 states and 19570 transitions. [2021-11-22 16:03:45,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13361 states and 19570 transitions. [2021-11-22 16:03:46,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13361 to 13357. [2021-11-22 16:03:46,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13357 states, 13357 states have (on average 1.4648498914426893) internal successors, (19566), 13356 states have internal predecessors, (19566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:46,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13357 states to 13357 states and 19566 transitions. [2021-11-22 16:03:46,081 INFO L704 BuchiCegarLoop]: Abstraction has 13357 states and 19566 transitions. [2021-11-22 16:03:46,081 INFO L587 BuchiCegarLoop]: Abstraction has 13357 states and 19566 transitions. [2021-11-22 16:03:46,081 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-22 16:03:46,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13357 states and 19566 transitions. [2021-11-22 16:03:46,139 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2021-11-22 16:03:46,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:46,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:46,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:46,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:46,144 INFO L791 eck$LassoCheckResult]: Stem: 87079#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87080#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86893#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86607#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86608#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87834#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87835#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86743#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86744#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87211#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87041#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87042#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86811#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86812#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87222#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87408#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87566#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87604#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86823#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86824#L1258 assume !(0 == ~M_E~0); 88085#L1258-2 assume !(0 == ~T1_E~0); 87125#L1263-1 assume !(0 == ~T2_E~0); 87126#L1268-1 assume !(0 == ~T3_E~0); 87442#L1273-1 assume !(0 == ~T4_E~0); 88067#L1278-1 assume !(0 == ~T5_E~0); 87902#L1283-1 assume !(0 == ~T6_E~0); 87903#L1288-1 assume !(0 == ~T7_E~0); 88190#L1293-1 assume !(0 == ~T8_E~0); 88175#L1298-1 assume !(0 == ~T9_E~0); 88079#L1303-1 assume !(0 == ~T10_E~0); 86636#L1308-1 assume !(0 == ~T11_E~0); 86578#L1313-1 assume !(0 == ~T12_E~0); 86579#L1318-1 assume !(0 == ~T13_E~0); 86585#L1323-1 assume !(0 == ~E_1~0); 86586#L1328-1 assume !(0 == ~E_2~0); 86753#L1333-1 assume !(0 == ~E_3~0); 87752#L1338-1 assume !(0 == ~E_4~0); 87753#L1343-1 assume !(0 == ~E_5~0); 87872#L1348-1 assume !(0 == ~E_6~0); 88224#L1353-1 assume !(0 == ~E_7~0); 87463#L1358-1 assume !(0 == ~E_8~0); 87464#L1363-1 assume !(0 == ~E_9~0); 87774#L1368-1 assume !(0 == ~E_10~0); 86415#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86416#L1378-1 assume !(0 == ~E_12~0); 86702#L1383-1 assume !(0 == ~E_13~0); 86703#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87469#L607 assume !(1 == ~m_pc~0); 86772#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86773#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87870#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87385#L1560 assume !(0 != activate_threads_~tmp~1#1); 87386#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86598#L626 assume !(1 == ~t1_pc~0); 86599#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86869#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86870#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87045#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86498#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86499#L645 assume 1 == ~t2_pc~0; 86615#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86572#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87263#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87264#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87360#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87361#L664 assume 1 == ~t3_pc~0; 88220#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86337#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86338#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87003#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87004#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88095#L683 assume !(1 == ~t4_pc~0); 87589#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87539#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87540#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87576#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87708#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87308#L702 assume 1 == ~t5_pc~0; 87309#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87231#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87703#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88050#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 87980#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86387#L721 assume !(1 == ~t6_pc~0); 86360#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86361#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86525#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87013#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87014#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87642#L740 assume 1 == ~t7_pc~0; 86436#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86247#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86248#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86237#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86238#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86948#L759 assume !(1 == ~t8_pc~0); 86949#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86978#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87701#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87702#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87849#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88189#L778 assume 1 == ~t9_pc~0; 88047#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86414#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86352#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86281#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86282#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86611#L797 assume !(1 == ~t10_pc~0); 86612#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86730#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87928#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87123#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87124#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87426#L816 assume 1 == ~t11_pc~0; 86317#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86318#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87083#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87022#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87023#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87565#L835 assume 1 == ~t12_pc~0; 87439#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86483#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86505#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86646#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87184#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87185#L854 assume !(1 == ~t13_pc~0); 86813#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86814#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86865#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86523#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86524#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87974#L1401 assume !(1 == ~M_E~0); 87007#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87008#L1406-1 assume !(1 == ~T2_E~0); 87630#L1411-1 assume !(1 == ~T3_E~0); 87631#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87279#L1421-1 assume !(1 == ~T5_E~0); 86809#L1426-1 assume !(1 == ~T6_E~0); 86810#L1431-1 assume !(1 == ~T7_E~0); 87785#L1436-1 assume !(1 == ~T8_E~0); 95527#L1441-1 assume !(1 == ~T9_E~0); 98421#L1446-1 assume !(1 == ~T10_E~0); 98419#L1451-1 assume !(1 == ~T11_E~0); 98417#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 98416#L1461-1 assume !(1 == ~T13_E~0); 98401#L1466-1 assume !(1 == ~E_1~0); 98399#L1471-1 assume !(1 == ~E_2~0); 98397#L1476-1 assume !(1 == ~E_3~0); 95500#L1481-1 assume !(1 == ~E_4~0); 98394#L1486-1 assume !(1 == ~E_5~0); 98392#L1491-1 assume !(1 == ~E_6~0); 98391#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 98390#L1501-1 assume !(1 == ~E_8~0); 98389#L1506-1 assume !(1 == ~E_9~0); 98388#L1511-1 assume !(1 == ~E_10~0); 98387#L1516-1 assume !(1 == ~E_11~0); 98386#L1521-1 assume !(1 == ~E_12~0); 98385#L1526-1 assume !(1 == ~E_13~0); 98384#L1531-1 assume { :end_inline_reset_delta_events } true; 98382#L1892-2 [2021-11-22 16:03:46,145 INFO L793 eck$LassoCheckResult]: Loop: 98382#L1892-2 assume !false; 95949#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95948#L1233 assume !false; 95947#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 95551#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 95549#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 95547#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95544#L1046 assume !(0 != eval_~tmp~0#1); 95542#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95541#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95540#L1258-3 assume !(0 == ~M_E~0); 95538#L1258-5 assume !(0 == ~T1_E~0); 95539#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 99324#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99323#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99322#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99321#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99320#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99319#L1293-3 assume !(0 == ~T8_E~0); 99318#L1298-3 assume !(0 == ~T9_E~0); 99317#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 99316#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 99315#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99314#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 99313#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99312#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99311#L1333-3 assume !(0 == ~E_3~0); 99310#L1338-3 assume !(0 == ~E_4~0); 99309#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99308#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99307#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 99306#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 99305#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99304#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 99303#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 99302#L1378-3 assume !(0 == ~E_12~0); 99301#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 99300#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99299#L607-42 assume !(1 == ~m_pc~0); 99297#L607-44 is_master_triggered_~__retres1~0#1 := 0; 99296#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99295#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99294#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99293#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99292#L626-42 assume !(1 == ~t1_pc~0); 99291#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 99289#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99288#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99287#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99286#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99285#L645-42 assume !(1 == ~t2_pc~0); 99283#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 99282#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99281#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99280#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99279#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99278#L664-42 assume !(1 == ~t3_pc~0); 99277#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 99275#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99274#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99273#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99272#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99271#L683-42 assume !(1 == ~t4_pc~0); 99269#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 99268#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99267#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99266#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99265#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99264#L702-42 assume !(1 == ~t5_pc~0); 99263#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 99261#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99260#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 99259#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 99258#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99257#L721-42 assume !(1 == ~t6_pc~0); 99255#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 99254#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99253#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99252#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99251#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99250#L740-42 assume !(1 == ~t7_pc~0); 99249#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 99247#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99246#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99245#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 99244#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99243#L759-42 assume 1 == ~t8_pc~0; 99241#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99240#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99239#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99238#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99237#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99236#L778-42 assume 1 == ~t9_pc~0; 99235#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99233#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99232#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99231#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 99230#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99229#L797-42 assume 1 == ~t10_pc~0; 99227#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 99226#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99225#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99224#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99223#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99222#L816-42 assume 1 == ~t11_pc~0; 99221#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 99219#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99218#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99217#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 99216#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99215#L835-42 assume 1 == ~t12_pc~0; 99213#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 99212#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99211#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 99210#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 99209#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 99208#L854-42 assume 1 == ~t13_pc~0; 99207#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 99205#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 99204#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 99203#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 99202#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99201#L1401-3 assume !(1 == ~M_E~0); 90585#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87858#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99200#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99199#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99198#L1421-3 assume !(1 == ~T5_E~0); 99197#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 99196#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 99195#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86785#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 99194#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 99193#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99192#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 99191#L1461-3 assume !(1 == ~T13_E~0); 99190#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99189#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86755#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86756#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87169#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86783#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86784#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87209#L1501-3 assume !(1 == ~E_8~0); 87210#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 87658#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 87648#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87649#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87330#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87331#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87748#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86590#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87508#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 87133#L1911 assume !(0 == start_simulation_~tmp~3#1); 87134#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98415#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98400#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98398#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 98396#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98395#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98393#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98383#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 98382#L1892-2 [2021-11-22 16:03:46,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:46,146 INFO L85 PathProgramCache]: Analyzing trace with hash 2121381685, now seen corresponding path program 1 times [2021-11-22 16:03:46,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:46,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077657345] [2021-11-22 16:03:46,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:46,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:46,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:46,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:46,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:46,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077657345] [2021-11-22 16:03:46,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077657345] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:46,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:46,192 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:46,192 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006173739] [2021-11-22 16:03:46,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:46,193 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:46,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:46,193 INFO L85 PathProgramCache]: Analyzing trace with hash 390421363, now seen corresponding path program 1 times [2021-11-22 16:03:46,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:46,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409849777] [2021-11-22 16:03:46,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:46,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:46,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:46,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:46,238 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:46,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409849777] [2021-11-22 16:03:46,238 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409849777] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:46,238 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:46,238 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:46,239 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060515051] [2021-11-22 16:03:46,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:46,239 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:46,240 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:46,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 16:03:46,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 16:03:46,240 INFO L87 Difference]: Start difference. First operand 13357 states and 19566 transitions. cyclomatic complexity: 6213 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:46,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:46,577 INFO L93 Difference]: Finished difference Result 25713 states and 37651 transitions. [2021-11-22 16:03:46,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 16:03:46,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25713 states and 37651 transitions. [2021-11-22 16:03:46,860 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2021-11-22 16:03:46,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25713 states to 25713 states and 37651 transitions. [2021-11-22 16:03:46,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25713 [2021-11-22 16:03:47,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25713 [2021-11-22 16:03:47,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25713 states and 37651 transitions. [2021-11-22 16:03:47,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:47,029 INFO L681 BuchiCegarLoop]: Abstraction has 25713 states and 37651 transitions. [2021-11-22 16:03:47,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25713 states and 37651 transitions. [2021-11-22 16:03:47,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25713 to 25705. [2021-11-22 16:03:47,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25705 states, 25705 states have (on average 1.4644232639564287) internal successors, (37643), 25704 states have internal predecessors, (37643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:47,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25705 states to 25705 states and 37643 transitions. [2021-11-22 16:03:47,711 INFO L704 BuchiCegarLoop]: Abstraction has 25705 states and 37643 transitions. [2021-11-22 16:03:47,712 INFO L587 BuchiCegarLoop]: Abstraction has 25705 states and 37643 transitions. [2021-11-22 16:03:47,712 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-22 16:03:47,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25705 states and 37643 transitions. [2021-11-22 16:03:47,801 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2021-11-22 16:03:47,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:47,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:47,804 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:47,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:47,805 INFO L791 eck$LassoCheckResult]: Stem: 126169#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 125978#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125687#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125688#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126938#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126939#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125825#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125826#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126299#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126128#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126129#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125895#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125896#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126310#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126503#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126664#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126703#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125906#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125907#L1258 assume !(0 == ~M_E~0); 127205#L1258-2 assume !(0 == ~T1_E~0); 126214#L1263-1 assume !(0 == ~T2_E~0); 126215#L1268-1 assume !(0 == ~T3_E~0); 126538#L1273-1 assume !(0 == ~T4_E~0); 127181#L1278-1 assume !(0 == ~T5_E~0); 127012#L1283-1 assume !(0 == ~T6_E~0); 127013#L1288-1 assume !(0 == ~T7_E~0); 127315#L1293-1 assume !(0 == ~T8_E~0); 127301#L1298-1 assume !(0 == ~T9_E~0); 127196#L1303-1 assume !(0 == ~T10_E~0); 125716#L1308-1 assume !(0 == ~T11_E~0); 125658#L1313-1 assume !(0 == ~T12_E~0); 125659#L1318-1 assume !(0 == ~T13_E~0); 125665#L1323-1 assume !(0 == ~E_1~0); 125666#L1328-1 assume !(0 == ~E_2~0); 125835#L1333-1 assume !(0 == ~E_3~0); 126855#L1338-1 assume !(0 == ~E_4~0); 126856#L1343-1 assume !(0 == ~E_5~0); 126981#L1348-1 assume !(0 == ~E_6~0); 127354#L1353-1 assume !(0 == ~E_7~0); 126558#L1358-1 assume !(0 == ~E_8~0); 126559#L1363-1 assume !(0 == ~E_9~0); 126877#L1368-1 assume !(0 == ~E_10~0); 125495#L1373-1 assume !(0 == ~E_11~0); 125496#L1378-1 assume !(0 == ~E_12~0); 125784#L1383-1 assume !(0 == ~E_13~0); 125785#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126564#L607 assume !(1 == ~m_pc~0); 125855#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125856#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126979#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126478#L1560 assume !(0 != activate_threads_~tmp~1#1); 126479#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125678#L626 assume !(1 == ~t1_pc~0); 125679#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125954#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125955#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126132#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125578#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125579#L645 assume 1 == ~t2_pc~0; 125695#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125652#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126351#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126352#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126453#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126454#L664 assume 1 == ~t3_pc~0; 127348#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125418#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125419#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126092#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126093#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127215#L683 assume !(1 == ~t4_pc~0); 126687#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126637#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126638#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126674#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126808#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126397#L702 assume 1 == ~t5_pc~0; 126398#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126319#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126803#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127164#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127089#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125467#L721 assume !(1 == ~t6_pc~0); 125441#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125442#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125605#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126102#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126103#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126740#L740 assume 1 == ~t7_pc~0; 125516#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125327#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125328#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125317#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125318#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126037#L759 assume !(1 == ~t8_pc~0); 126038#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126067#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126801#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126802#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126954#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127314#L778 assume 1 == ~t9_pc~0; 127161#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125494#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125433#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125361#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125362#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125691#L797 assume !(1 == ~t10_pc~0); 125692#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125812#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127040#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126212#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126213#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126522#L816 assume 1 == ~t11_pc~0; 125398#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125399#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126173#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126109#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126110#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126663#L835 assume 1 == ~t12_pc~0; 126535#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125563#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125585#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125727#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126271#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126272#L854 assume !(1 == ~t13_pc~0); 125897#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125898#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125950#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125603#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125604#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127084#L1401 assume !(1 == ~M_E~0); 126096#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126097#L1406-1 assume !(1 == ~T2_E~0); 149933#L1411-1 assume !(1 == ~T3_E~0); 142411#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 142408#L1421-1 assume !(1 == ~T5_E~0); 142406#L1426-1 assume !(1 == ~T6_E~0); 142404#L1431-1 assume !(1 == ~T7_E~0); 142402#L1436-1 assume !(1 == ~T8_E~0); 142400#L1441-1 assume !(1 == ~T9_E~0); 142398#L1446-1 assume !(1 == ~T10_E~0); 127391#L1451-1 assume !(1 == ~T11_E~0); 126978#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126583#L1461-1 assume !(1 == ~T13_E~0); 126121#L1466-1 assume !(1 == ~E_1~0); 126122#L1471-1 assume !(1 == ~E_2~0); 126952#L1476-1 assume !(1 == ~E_3~0); 126953#L1481-1 assume !(1 == ~E_4~0); 142773#L1486-1 assume !(1 == ~E_5~0); 142771#L1491-1 assume !(1 == ~E_6~0); 142768#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 142766#L1501-1 assume !(1 == ~E_8~0); 142764#L1506-1 assume !(1 == ~E_9~0); 142762#L1511-1 assume !(1 == ~E_10~0); 142760#L1516-1 assume !(1 == ~E_11~0); 140811#L1521-1 assume !(1 == ~E_12~0); 142756#L1526-1 assume !(1 == ~E_13~0); 142754#L1531-1 assume { :end_inline_reset_delta_events } true; 142751#L1892-2 [2021-11-22 16:03:47,806 INFO L793 eck$LassoCheckResult]: Loop: 142751#L1892-2 assume !false; 140196#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140194#L1233 assume !false; 140191#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 140141#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 140139#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 140137#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 140134#L1046 assume !(0 != eval_~tmp~0#1); 140131#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 140129#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 140127#L1258-3 assume !(0 == ~M_E~0); 140125#L1258-5 assume !(0 == ~T1_E~0); 140123#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 140121#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 140118#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 140116#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 140114#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 140112#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 140110#L1293-3 assume !(0 == ~T8_E~0); 140108#L1298-3 assume !(0 == ~T9_E~0); 140105#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 140103#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 140101#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 140099#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 140097#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 140096#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 140095#L1333-3 assume !(0 == ~E_3~0); 135721#L1338-3 assume !(0 == ~E_4~0); 135718#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 135716#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 135714#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 135712#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 135710#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 135708#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 135705#L1373-3 assume !(0 == ~E_11~0); 135703#L1378-3 assume !(0 == ~E_12~0); 135701#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 135699#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135697#L607-42 assume !(1 == ~m_pc~0); 135694#L607-44 is_master_triggered_~__retres1~0#1 := 0; 135693#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135690#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 135688#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135686#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135684#L626-42 assume !(1 == ~t1_pc~0); 135682#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 135679#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135676#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 135674#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135672#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135670#L645-42 assume !(1 == ~t2_pc~0); 135667#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 135665#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135662#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 135660#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135658#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135656#L664-42 assume !(1 == ~t3_pc~0); 135654#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 135651#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135648#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 135646#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 135644#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135642#L683-42 assume !(1 == ~t4_pc~0); 135639#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 135637#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135634#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 135632#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 135630#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 135628#L702-42 assume !(1 == ~t5_pc~0); 135626#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 135623#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135620#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 135618#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 135616#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 135614#L721-42 assume !(1 == ~t6_pc~0); 135611#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 135609#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 135606#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 135604#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 135602#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135600#L740-42 assume !(1 == ~t7_pc~0); 135598#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 135595#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 135592#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 135590#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 135588#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 135586#L759-42 assume !(1 == ~t8_pc~0); 135584#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 135582#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 135578#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 135576#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 135574#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 135573#L778-42 assume !(1 == ~t9_pc~0); 135571#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 135566#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 135560#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 135558#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 135556#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 135555#L797-42 assume !(1 == ~t10_pc~0); 135554#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 135552#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 135551#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 135550#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 135549#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 135548#L816-42 assume !(1 == ~t11_pc~0); 135546#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 135545#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 135544#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 135543#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 135542#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 135541#L835-42 assume 1 == ~t12_pc~0; 135539#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 135538#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 135537#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 135536#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 135535#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 135534#L854-42 assume !(1 == ~t13_pc~0); 135532#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 135531#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 135530#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 135529#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 135527#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135525#L1401-3 assume !(1 == ~M_E~0); 128721#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128080#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128078#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128076#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128074#L1421-3 assume !(1 == ~T5_E~0); 128072#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128069#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128067#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 128064#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 128062#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 128060#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 128058#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128056#L1461-3 assume !(1 == ~T13_E~0); 128054#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128052#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 128049#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128050#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 135369#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 135367#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 135364#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 135362#L1501-3 assume !(1 == ~E_8~0); 135360#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 135358#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 135356#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 135110#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 135353#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 135351#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 135329#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 135323#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 135321#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 135319#L1911 assume !(0 == start_simulation_~tmp~3#1); 127964#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 142803#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 142788#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 142786#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 142784#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 142782#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 142780#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 142753#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 142751#L1892-2 [2021-11-22 16:03:47,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:47,807 INFO L85 PathProgramCache]: Analyzing trace with hash 1788738547, now seen corresponding path program 1 times [2021-11-22 16:03:47,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:47,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203511659] [2021-11-22 16:03:47,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:47,808 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:47,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:47,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:47,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:47,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203511659] [2021-11-22 16:03:47,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203511659] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:47,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:47,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:47,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773399814] [2021-11-22 16:03:47,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:47,854 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:47,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:47,854 INFO L85 PathProgramCache]: Analyzing trace with hash -953209460, now seen corresponding path program 1 times [2021-11-22 16:03:47,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:47,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259665509] [2021-11-22 16:03:47,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:47,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:47,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:47,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:47,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:47,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259665509] [2021-11-22 16:03:47,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259665509] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:47,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:47,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:47,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774161222] [2021-11-22 16:03:47,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:47,896 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:47,897 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:47,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 16:03:47,898 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 16:03:47,898 INFO L87 Difference]: Start difference. First operand 25705 states and 37643 transitions. cyclomatic complexity: 11946 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:49,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:49,007 INFO L93 Difference]: Finished difference Result 74991 states and 108894 transitions. [2021-11-22 16:03:49,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 16:03:49,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74991 states and 108894 transitions. [2021-11-22 16:03:49,585 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2021-11-22 16:03:49,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74991 states to 74991 states and 108894 transitions. [2021-11-22 16:03:49,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74991 [2021-11-22 16:03:50,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74991 [2021-11-22 16:03:50,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74991 states and 108894 transitions. [2021-11-22 16:03:50,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:50,136 INFO L681 BuchiCegarLoop]: Abstraction has 74991 states and 108894 transitions. [2021-11-22 16:03:50,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74991 states and 108894 transitions. [2021-11-22 16:03:51,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74991 to 72679. [2021-11-22 16:03:51,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72679 states, 72679 states have (on average 1.454147690529589) internal successors, (105686), 72678 states have internal predecessors, (105686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:51,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72679 states to 72679 states and 105686 transitions. [2021-11-22 16:03:51,644 INFO L704 BuchiCegarLoop]: Abstraction has 72679 states and 105686 transitions. [2021-11-22 16:03:51,644 INFO L587 BuchiCegarLoop]: Abstraction has 72679 states and 105686 transitions. [2021-11-22 16:03:51,645 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-22 16:03:51,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72679 states and 105686 transitions. [2021-11-22 16:03:52,020 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2021-11-22 16:03:52,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:03:52,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:03:52,024 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:52,024 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:03:52,024 INFO L791 eck$LassoCheckResult]: Stem: 226862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226863#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 226676#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 226390#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 226391#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227635#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227636#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226527#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226528#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226991#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226822#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226823#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226595#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226596#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 227002#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227191#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227354#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227395#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226606#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226607#L1258 assume !(0 == ~M_E~0); 227898#L1258-2 assume !(0 == ~T1_E~0); 226907#L1263-1 assume !(0 == ~T2_E~0); 226908#L1268-1 assume !(0 == ~T3_E~0); 227226#L1273-1 assume !(0 == ~T4_E~0); 227873#L1278-1 assume !(0 == ~T5_E~0); 227698#L1283-1 assume !(0 == ~T6_E~0); 227699#L1288-1 assume !(0 == ~T7_E~0); 228019#L1293-1 assume !(0 == ~T8_E~0); 228000#L1298-1 assume !(0 == ~T9_E~0); 227890#L1303-1 assume !(0 == ~T10_E~0); 226418#L1308-1 assume !(0 == ~T11_E~0); 226361#L1313-1 assume !(0 == ~T12_E~0); 226362#L1318-1 assume !(0 == ~T13_E~0); 226368#L1323-1 assume !(0 == ~E_1~0); 226369#L1328-1 assume !(0 == ~E_2~0); 226537#L1333-1 assume !(0 == ~E_3~0); 227547#L1338-1 assume !(0 == ~E_4~0); 227548#L1343-1 assume !(0 == ~E_5~0); 227670#L1348-1 assume !(0 == ~E_6~0); 228064#L1353-1 assume !(0 == ~E_7~0); 227246#L1358-1 assume !(0 == ~E_8~0); 227247#L1363-1 assume !(0 == ~E_9~0); 227571#L1368-1 assume !(0 == ~E_10~0); 226198#L1373-1 assume !(0 == ~E_11~0); 226199#L1378-1 assume !(0 == ~E_12~0); 226485#L1383-1 assume !(0 == ~E_13~0); 226486#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227252#L607 assume !(1 == ~m_pc~0); 226556#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226557#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227668#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227169#L1560 assume !(0 != activate_threads_~tmp~1#1); 227170#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226381#L626 assume !(1 == ~t1_pc~0); 226382#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226652#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226653#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 226826#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226281#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226282#L645 assume !(1 == ~t2_pc~0); 226354#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226355#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227045#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 227046#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227145#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227146#L664 assume 1 == ~t3_pc~0; 228057#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226123#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226124#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226785#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226786#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227915#L683 assume !(1 == ~t4_pc~0); 227379#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227327#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227328#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227364#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227504#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227090#L702 assume 1 == ~t5_pc~0; 227091#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 227012#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227499#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227853#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227777#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226170#L721 assume !(1 == ~t6_pc~0); 226145#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226146#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226308#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226795#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226796#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227431#L740 assume 1 == ~t7_pc~0; 226219#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226033#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226034#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226023#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226024#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226729#L759 assume !(1 == ~t8_pc~0); 226730#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226760#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227497#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227498#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227650#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 228018#L778 assume 1 == ~t9_pc~0; 227850#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226197#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226138#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226067#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226068#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226394#L797 assume !(1 == ~t10_pc~0); 226395#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226514#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227726#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226905#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226906#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227209#L816 assume 1 == ~t11_pc~0; 226103#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226104#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 226866#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226802#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226803#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227353#L835 assume 1 == ~t12_pc~0; 227223#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226266#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226288#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226428#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226963#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226964#L854 assume !(1 == ~t13_pc~0); 226597#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226598#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226648#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226306#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226307#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227771#L1401 assume !(1 == ~M_E~0); 226789#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226790#L1406-1 assume !(1 == ~T2_E~0); 227420#L1411-1 assume !(1 == ~T3_E~0); 227421#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227062#L1421-1 assume !(1 == ~T5_E~0); 226593#L1426-1 assume !(1 == ~T6_E~0); 226594#L1431-1 assume !(1 == ~T7_E~0); 226141#L1436-1 assume !(1 == ~T8_E~0); 226142#L1441-1 assume !(1 == ~T9_E~0); 226896#L1446-1 assume !(1 == ~T10_E~0); 226897#L1451-1 assume !(1 == ~T11_E~0); 227667#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 227272#L1461-1 assume !(1 == ~T13_E~0); 226816#L1466-1 assume !(1 == ~E_1~0); 226817#L1471-1 assume !(1 == ~E_2~0); 227648#L1476-1 assume !(1 == ~E_3~0); 227649#L1481-1 assume !(1 == ~E_4~0); 227830#L1486-1 assume !(1 == ~E_5~0); 226433#L1491-1 assume !(1 == ~E_6~0); 226075#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 226076#L1501-1 assume !(1 == ~E_8~0); 226894#L1506-1 assume !(1 == ~E_9~0); 226895#L1511-1 assume !(1 == ~E_10~0); 226850#L1516-1 assume !(1 == ~E_11~0); 226851#L1521-1 assume !(1 == ~E_12~0); 292670#L1526-1 assume !(1 == ~E_13~0); 292660#L1531-1 assume { :end_inline_reset_delta_events } true; 292650#L1892-2 [2021-11-22 16:03:52,025 INFO L793 eck$LassoCheckResult]: Loop: 292650#L1892-2 assume !false; 292643#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 292637#L1233 assume !false; 292634#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 292614#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 290895#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 290894#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 290892#L1046 assume !(0 != eval_~tmp~0#1); 290893#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 293990#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 293988#L1258-3 assume !(0 == ~M_E~0); 293986#L1258-5 assume !(0 == ~T1_E~0); 293984#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 293982#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 293980#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 293978#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 293976#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 293973#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 293971#L1293-3 assume !(0 == ~T8_E~0); 293970#L1298-3 assume !(0 == ~T9_E~0); 293969#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 293968#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 293966#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 293964#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 293962#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 293960#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 293958#L1333-3 assume !(0 == ~E_3~0); 293956#L1338-3 assume !(0 == ~E_4~0); 293954#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 293951#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 293949#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 293947#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 293945#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 293939#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 293934#L1373-3 assume !(0 == ~E_11~0); 293924#L1378-3 assume !(0 == ~E_12~0); 293919#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 293913#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293906#L607-42 assume !(1 == ~m_pc~0); 293899#L607-44 is_master_triggered_~__retres1~0#1 := 0; 293892#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293886#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 293879#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293873#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293865#L626-42 assume 1 == ~t1_pc~0; 293857#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 293850#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293844#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 293838#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293832#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293825#L645-42 assume !(1 == ~t2_pc~0); 293818#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 293811#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293805#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 293798#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 293792#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293784#L664-42 assume 1 == ~t3_pc~0; 293776#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 293769#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293763#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 293756#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 293750#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293742#L683-42 assume !(1 == ~t4_pc~0); 293734#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 293727#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293721#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 293714#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 293708#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293700#L702-42 assume 1 == ~t5_pc~0; 293692#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 293685#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293679#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 293672#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293666#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293658#L721-42 assume !(1 == ~t6_pc~0); 293650#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 293643#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 293637#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 293631#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 293626#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 293621#L740-42 assume 1 == ~t7_pc~0; 293618#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 292857#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 292854#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 292852#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 292850#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292848#L759-42 assume 1 == ~t8_pc~0; 292845#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 292843#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 292840#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 292838#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 292836#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 292834#L778-42 assume !(1 == ~t9_pc~0); 292828#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 292826#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 292824#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 292822#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 228046#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 227320#L797-42 assume 1 == ~t10_pc~0; 226459#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 226460#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227509#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 227884#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 228141#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 292702#L816-42 assume 1 == ~t11_pc~0; 292700#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 292696#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 292694#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 292692#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 292691#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 292690#L835-42 assume 1 == ~t12_pc~0; 292688#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 292686#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 292685#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 228128#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 227775#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 227776#L854-42 assume !(1 == ~t13_pc~0); 292638#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 292612#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 292608#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 292604#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 292601#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 292598#L1401-3 assume !(1 == ~M_E~0); 290204#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 227658#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 292597#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 292596#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 292595#L1421-3 assume !(1 == ~T5_E~0); 292594#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 292593#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 292592#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 226569#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 292591#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 292590#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 292589#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 292588#L1461-3 assume !(1 == ~T13_E~0); 292586#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 292584#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 292582#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 272972#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 292579#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 292577#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 292574#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 292572#L1501-3 assume !(1 == ~E_8~0); 292570#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 292568#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 292566#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 257434#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 292562#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 292560#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 292534#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 292528#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 292526#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 292522#L1911 assume !(0 == start_simulation_~tmp~3#1); 292523#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 292725#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 292709#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 292707#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 292705#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 292703#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 292669#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 292659#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 292650#L1892-2 [2021-11-22 16:03:52,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:52,026 INFO L85 PathProgramCache]: Analyzing trace with hash 785681682, now seen corresponding path program 1 times [2021-11-22 16:03:52,026 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:52,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848499228] [2021-11-22 16:03:52,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:52,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:52,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:52,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:52,069 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:52,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848499228] [2021-11-22 16:03:52,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848499228] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:52,070 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:52,070 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:52,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269369900] [2021-11-22 16:03:52,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:52,071 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:03:52,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:03:52,072 INFO L85 PathProgramCache]: Analyzing trace with hash 1672167027, now seen corresponding path program 1 times [2021-11-22 16:03:52,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:03:52,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80182830] [2021-11-22 16:03:52,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:03:52,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:03:52,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:03:52,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:03:52,113 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:03:52,113 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80182830] [2021-11-22 16:03:52,113 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [80182830] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:03:52,113 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:03:52,114 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:03:52,114 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151687342] [2021-11-22 16:03:52,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:03:52,114 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:03:52,115 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:03:52,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-22 16:03:52,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-22 16:03:52,116 INFO L87 Difference]: Start difference. First operand 72679 states and 105686 transitions. cyclomatic complexity: 33023 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:53,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:03:53,395 INFO L93 Difference]: Finished difference Result 210030 states and 303419 transitions. [2021-11-22 16:03:53,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-22 16:03:53,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210030 states and 303419 transitions. [2021-11-22 16:03:54,754 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2021-11-22 16:03:55,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210030 states to 210030 states and 303419 transitions. [2021-11-22 16:03:55,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210030 [2021-11-22 16:03:55,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210030 [2021-11-22 16:03:55,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210030 states and 303419 transitions. [2021-11-22 16:03:55,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:03:55,967 INFO L681 BuchiCegarLoop]: Abstraction has 210030 states and 303419 transitions. [2021-11-22 16:03:56,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210030 states and 303419 transitions. [2021-11-22 16:03:58,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210030 to 202814. [2021-11-22 16:03:58,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202814 states, 202814 states have (on average 1.446897157000996) internal successors, (293451), 202813 states have internal predecessors, (293451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:03:58,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202814 states to 202814 states and 293451 transitions. [2021-11-22 16:03:58,846 INFO L704 BuchiCegarLoop]: Abstraction has 202814 states and 293451 transitions. [2021-11-22 16:03:58,846 INFO L587 BuchiCegarLoop]: Abstraction has 202814 states and 293451 transitions. [2021-11-22 16:03:58,846 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-22 16:03:58,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202814 states and 293451 transitions. [2021-11-22 16:04:00,197 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2021-11-22 16:04:00,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:04:00,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:04:00,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:04:00,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:04:00,202 INFO L791 eck$LassoCheckResult]: Stem: 509595#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 509596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509404#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509113#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509114#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510419#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510420#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509251#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509252#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509736#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509556#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509557#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509321#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509322#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509747#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509939#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510106#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510151#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509332#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509333#L1258 assume !(0 == ~M_E~0); 510711#L1258-2 assume !(0 == ~T1_E~0); 509646#L1263-1 assume !(0 == ~T2_E~0); 509647#L1268-1 assume !(0 == ~T3_E~0); 509974#L1273-1 assume !(0 == ~T4_E~0); 510686#L1278-1 assume !(0 == ~T5_E~0); 510490#L1283-1 assume !(0 == ~T6_E~0); 510491#L1288-1 assume !(0 == ~T7_E~0); 510847#L1293-1 assume !(0 == ~T8_E~0); 510824#L1298-1 assume !(0 == ~T9_E~0); 510703#L1303-1 assume !(0 == ~T10_E~0); 509142#L1308-1 assume !(0 == ~T11_E~0); 509084#L1313-1 assume !(0 == ~T12_E~0); 509085#L1318-1 assume !(0 == ~T13_E~0); 509091#L1323-1 assume !(0 == ~E_1~0); 509092#L1328-1 assume !(0 == ~E_2~0); 509261#L1333-1 assume !(0 == ~E_3~0); 510315#L1338-1 assume !(0 == ~E_4~0); 510316#L1343-1 assume !(0 == ~E_5~0); 510456#L1348-1 assume !(0 == ~E_6~0); 510905#L1353-1 assume !(0 == ~E_7~0); 509995#L1358-1 assume !(0 == ~E_8~0); 509996#L1363-1 assume !(0 == ~E_9~0); 510343#L1368-1 assume !(0 == ~E_10~0); 508918#L1373-1 assume !(0 == ~E_11~0); 508919#L1378-1 assume !(0 == ~E_12~0); 509209#L1383-1 assume !(0 == ~E_13~0); 509210#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 510001#L607 assume !(1 == ~m_pc~0); 509281#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509282#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 510453#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509919#L1560 assume !(0 != activate_threads_~tmp~1#1); 509920#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509104#L626 assume !(1 == ~t1_pc~0); 509105#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509379#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509380#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 509560#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 509004#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509005#L645 assume !(1 == ~t2_pc~0); 509077#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509078#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509788#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509789#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509894#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509895#L664 assume !(1 == ~t3_pc~0); 510376#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508842#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508843#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509518#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509519#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510730#L683 assume !(1 == ~t4_pc~0); 510133#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510076#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 510077#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 510117#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510266#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509840#L702 assume 1 == ~t5_pc~0; 509841#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509757#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510261#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510668#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510581#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508890#L721 assume !(1 == ~t6_pc~0); 508864#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508865#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509031#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509529#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509530#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510189#L740 assume 1 == ~t7_pc~0; 508940#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508752#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508753#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508742#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508743#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509460#L759 assume !(1 == ~t8_pc~0); 509461#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509490#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510259#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510260#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510434#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510846#L778 assume 1 == ~t9_pc~0; 510666#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508917#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 508857#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508785#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508786#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509117#L797 assume !(1 == ~t10_pc~0); 509118#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509238#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510522#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509644#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509645#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509958#L816 assume 1 == ~t11_pc~0; 508822#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508823#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509599#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509536#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509537#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510105#L835 assume 1 == ~t12_pc~0; 509971#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508989#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 509011#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 509152#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509707#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509708#L854 assume !(1 == ~t13_pc~0); 509323#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509324#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509374#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 509029#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 509030#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510570#L1401 assume !(1 == ~M_E~0); 509522#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 509523#L1406-1 assume !(1 == ~T2_E~0); 510584#L1411-1 assume !(1 == ~T3_E~0); 510888#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 510889#L1421-1 assume !(1 == ~T5_E~0); 509319#L1426-1 assume !(1 == ~T6_E~0); 509320#L1431-1 assume !(1 == ~T7_E~0); 508860#L1436-1 assume !(1 == ~T8_E~0); 508861#L1441-1 assume !(1 == ~T9_E~0); 509633#L1446-1 assume !(1 == ~T10_E~0); 509634#L1451-1 assume !(1 == ~T11_E~0); 510452#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 510020#L1461-1 assume !(1 == ~T13_E~0); 509550#L1466-1 assume !(1 == ~E_1~0); 509551#L1471-1 assume !(1 == ~E_2~0); 510432#L1476-1 assume !(1 == ~E_3~0); 510433#L1481-1 assume !(1 == ~E_4~0); 510867#L1486-1 assume !(1 == ~E_5~0); 510868#L1491-1 assume !(1 == ~E_6~0); 508793#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 508794#L1501-1 assume !(1 == ~E_8~0); 509629#L1506-1 assume !(1 == ~E_9~0); 509630#L1511-1 assume !(1 == ~E_10~0); 509583#L1516-1 assume !(1 == ~E_11~0); 508738#L1521-1 assume !(1 == ~E_12~0); 508739#L1526-1 assume !(1 == ~E_13~0); 508792#L1531-1 assume { :end_inline_reset_delta_events } true; 509344#L1892-2 [2021-11-22 16:04:00,202 INFO L793 eck$LassoCheckResult]: Loop: 509344#L1892-2 assume !false; 510510#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 510804#L1233 assume !false; 510805#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 509922#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 509901#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 704247#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 704246#L1046 assume !(0 != eval_~tmp~0#1); 508872#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 508873#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 510898#L1258-3 assume !(0 == ~M_E~0); 510899#L1258-5 assume !(0 == ~T1_E~0); 511028#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 708918#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 708917#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 708867#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 708866#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 708864#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 708863#L1293-3 assume !(0 == ~T8_E~0); 708861#L1298-3 assume !(0 == ~T9_E~0); 708859#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 708857#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 510506#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 509905#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 509019#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 509020#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 510628#L1333-3 assume !(0 == ~E_3~0); 509163#L1338-3 assume !(0 == ~E_4~0); 509164#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 510402#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 510635#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 510636#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 509858#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 509381#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 509382#L1373-3 assume !(0 == ~E_11~0); 510211#L1378-3 assume !(0 == ~E_12~0); 510212#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 510448#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 510449#L607-42 assume !(1 == ~m_pc~0); 510241#L607-44 is_master_triggered_~__retres1~0#1 := 0; 509679#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 509680#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 708823#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 708821#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 708819#L626-42 assume 1 == ~t1_pc~0; 708815#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 708813#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 708811#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 510469#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 509053#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509054#L645-42 assume !(1 == ~t2_pc~0); 510371#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 510372#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 510927#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708017#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 707950#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 707242#L664-42 assume !(1 == ~t3_pc~0); 707241#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 707240#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 707239#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 707238#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 510361#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510362#L683-42 assume !(1 == ~t4_pc~0); 706383#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 706382#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 706381#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 706380#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 706379#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 706378#L702-42 assume 1 == ~t5_pc~0; 706376#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 706375#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 706374#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 706373#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 706372#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 706371#L721-42 assume 1 == ~t6_pc~0; 706370#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 706368#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 706367#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 706366#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 706365#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 706364#L740-42 assume 1 == ~t7_pc~0; 706362#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 706361#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 706360#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 706359#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 706358#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 706357#L759-42 assume 1 == ~t8_pc~0; 706355#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 706354#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 706353#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 706352#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 706351#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 706350#L778-42 assume !(1 == ~t9_pc~0); 706348#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 706347#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 706346#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 706345#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 706344#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 706343#L797-42 assume !(1 == ~t10_pc~0); 706342#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 706340#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 706339#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 706338#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 706337#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 706336#L816-42 assume !(1 == ~t11_pc~0); 706334#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 706333#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 706332#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 706331#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 706330#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 706329#L835-42 assume !(1 == ~t12_pc~0); 706328#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 706326#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 706325#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 706324#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 706323#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 706322#L854-42 assume !(1 == ~t13_pc~0); 706320#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 706319#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 706318#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 706317#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 706316#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 706315#L1401-3 assume !(1 == ~M_E~0); 510440#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 510441#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 706202#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 706200#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 706198#L1421-3 assume !(1 == ~T5_E~0); 706196#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 706194#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 706191#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 666613#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 706190#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 706189#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 706188#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 706186#L1461-3 assume !(1 == ~T13_E~0); 706185#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 706184#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 706182#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 680535#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 706179#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 706177#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 706175#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 706170#L1501-3 assume !(1 == ~E_8~0); 706166#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 706163#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 706160#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 596941#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 706156#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 706155#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 704781#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 704776#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 704775#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 509654#L1911 assume !(0 == start_simulation_~tmp~3#1); 509655#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 510237#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 509221#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 510161#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 508922#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 508923#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 509155#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 509156#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 509344#L1892-2 [2021-11-22 16:04:00,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:04:00,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1058677105, now seen corresponding path program 1 times [2021-11-22 16:04:00,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:04:00,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812913402] [2021-11-22 16:04:00,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:04:00,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:04:00,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:04:00,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:04:00,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:04:00,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812913402] [2021-11-22 16:04:00,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812913402] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:04:00,252 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:04:00,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-22 16:04:00,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827015640] [2021-11-22 16:04:00,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:04:00,253 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:04:00,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:04:00,254 INFO L85 PathProgramCache]: Analyzing trace with hash -347001776, now seen corresponding path program 1 times [2021-11-22 16:04:00,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:04:00,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046799708] [2021-11-22 16:04:00,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:04:00,254 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:04:00,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:04:00,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:04:00,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:04:00,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046799708] [2021-11-22 16:04:00,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046799708] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:04:00,292 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:04:00,292 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:04:00,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662532209] [2021-11-22 16:04:00,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:04:00,293 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:04:00,293 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:04:00,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-22 16:04:00,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-22 16:04:00,294 INFO L87 Difference]: Start difference. First operand 202814 states and 293451 transitions. cyclomatic complexity: 90669 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:04:03,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:04:03,173 INFO L93 Difference]: Finished difference Result 547729 states and 795262 transitions. [2021-11-22 16:04:03,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-22 16:04:03,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547729 states and 795262 transitions. [2021-11-22 16:04:05,857 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2021-11-22 16:04:07,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547729 states to 547729 states and 795262 transitions. [2021-11-22 16:04:07,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547729 [2021-11-22 16:04:07,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547729 [2021-11-22 16:04:07,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547729 states and 795262 transitions. [2021-11-22 16:04:08,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:04:08,156 INFO L681 BuchiCegarLoop]: Abstraction has 547729 states and 795262 transitions. [2021-11-22 16:04:08,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547729 states and 795262 transitions. [2021-11-22 16:04:11,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547729 to 207977. [2021-11-22 16:04:11,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207977 states, 207977 states have (on average 1.4358029974468332) internal successors, (298614), 207976 states have internal predecessors, (298614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:04:12,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207977 states to 207977 states and 298614 transitions. [2021-11-22 16:04:12,070 INFO L704 BuchiCegarLoop]: Abstraction has 207977 states and 298614 transitions. [2021-11-22 16:04:12,070 INFO L587 BuchiCegarLoop]: Abstraction has 207977 states and 298614 transitions. [2021-11-22 16:04:12,070 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-22 16:04:12,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207977 states and 298614 transitions. [2021-11-22 16:04:13,456 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2021-11-22 16:04:13,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-22 16:04:13,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-22 16:04:13,461 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:04:13,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-22 16:04:13,462 INFO L791 eck$LassoCheckResult]: Stem: 1260137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1260138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1259950#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1259665#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1259666#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260913#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260914#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259801#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259802#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260269#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260097#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260098#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259869#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259870#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260276#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260460#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260629#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260673#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259882#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259883#L1258 assume !(0 == ~M_E~0); 1261168#L1258-2 assume !(0 == ~T1_E~0); 1260182#L1263-1 assume !(0 == ~T2_E~0); 1260183#L1268-1 assume !(0 == ~T3_E~0); 1260494#L1273-1 assume !(0 == ~T4_E~0); 1261144#L1278-1 assume !(0 == ~T5_E~0); 1260973#L1283-1 assume !(0 == ~T6_E~0); 1260974#L1288-1 assume !(0 == ~T7_E~0); 1261286#L1293-1 assume !(0 == ~T8_E~0); 1261265#L1298-1 assume !(0 == ~T9_E~0); 1261160#L1303-1 assume !(0 == ~T10_E~0); 1259693#L1308-1 assume !(0 == ~T11_E~0); 1259636#L1313-1 assume !(0 == ~T12_E~0); 1259637#L1318-1 assume !(0 == ~T13_E~0); 1259645#L1323-1 assume !(0 == ~E_1~0); 1259646#L1328-1 assume !(0 == ~E_2~0); 1259811#L1333-1 assume !(0 == ~E_3~0); 1260827#L1338-1 assume !(0 == ~E_4~0); 1260828#L1343-1 assume !(0 == ~E_5~0); 1260946#L1348-1 assume !(0 == ~E_6~0); 1261322#L1353-1 assume !(0 == ~E_7~0); 1260512#L1358-1 assume !(0 == ~E_8~0); 1260513#L1363-1 assume !(0 == ~E_9~0); 1260851#L1368-1 assume !(0 == ~E_10~0); 1259472#L1373-1 assume !(0 == ~E_11~0); 1259473#L1378-1 assume !(0 == ~E_12~0); 1259761#L1383-1 assume !(0 == ~E_13~0); 1259762#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260519#L607 assume !(1 == ~m_pc~0); 1259830#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259831#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260944#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260440#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260441#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259656#L626 assume !(1 == ~t1_pc~0); 1259657#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259928#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259929#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260103#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259559#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259560#L645 assume !(1 == ~t2_pc~0); 1259629#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259630#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1260320#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1260321#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260416#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260417#L664 assume !(1 == ~t3_pc~0); 1260878#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259401#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259402#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260059#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260060#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261184#L683 assume !(1 == ~t4_pc~0); 1260656#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260602#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260603#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261335#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260780#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260367#L702 assume 1 == ~t5_pc~0; 1260368#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260286#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260775#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261125#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261050#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259444#L721 assume !(1 == ~t6_pc~0); 1259419#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259420#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259583#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1260069#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260070#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260706#L740 assume 1 == ~t7_pc~0; 1259493#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259308#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259309#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259298#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259299#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1260002#L759 assume !(1 == ~t8_pc~0); 1260003#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260031#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260773#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260774#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260927#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261283#L778 assume 1 == ~t9_pc~0; 1261123#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259471#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259412#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259341#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259342#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259670#L797 assume !(1 == ~t10_pc~0); 1259671#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259788#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1261002#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260180#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260181#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260478#L816 assume 1 == ~t11_pc~0; 1259377#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259378#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260143#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260076#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260077#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260628#L835 assume 1 == ~t12_pc~0; 1260491#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259541#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259563#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259703#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260237#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260238#L854 assume !(1 == ~t13_pc~0); 1259871#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259872#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259924#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259581#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259582#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261044#L1401 assume !(1 == ~M_E~0); 1260063#L1401-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1260064#L1406-1 assume !(1 == ~T2_E~0); 1261052#L1411-1 assume !(1 == ~T3_E~0); 1261313#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1261314#L1421-1 assume !(1 == ~T5_E~0); 1259867#L1426-1 assume !(1 == ~T6_E~0); 1259868#L1431-1 assume !(1 == ~T7_E~0); 1259415#L1436-1 assume !(1 == ~T8_E~0); 1259416#L1441-1 assume !(1 == ~T9_E~0); 1343335#L1446-1 assume !(1 == ~T10_E~0); 1343333#L1451-1 assume !(1 == ~T11_E~0); 1343331#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1343329#L1461-1 assume !(1 == ~T13_E~0); 1343322#L1466-1 assume !(1 == ~E_1~0); 1343313#L1471-1 assume !(1 == ~E_2~0); 1260925#L1476-1 assume !(1 == ~E_3~0); 1260926#L1481-1 assume !(1 == ~E_4~0); 1261099#L1486-1 assume !(1 == ~E_5~0); 1259710#L1491-1 assume !(1 == ~E_6~0); 1259349#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1259350#L1501-1 assume !(1 == ~E_8~0); 1260169#L1506-1 assume !(1 == ~E_9~0); 1260170#L1511-1 assume !(1 == ~E_10~0); 1260124#L1516-1 assume !(1 == ~E_11~0); 1260125#L1521-1 assume !(1 == ~E_12~0); 1429358#L1526-1 assume !(1 == ~E_13~0); 1429356#L1531-1 assume { :end_inline_reset_delta_events } true; 1429353#L1892-2 [2021-11-22 16:04:13,463 INFO L793 eck$LassoCheckResult]: Loop: 1429353#L1892-2 assume !false; 1427510#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1427508#L1233 assume !false; 1427506#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1427473#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1427471#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1427469#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1427465#L1046 assume !(0 != eval_~tmp~0#1); 1427463#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1427461#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1427459#L1258-3 assume !(0 == ~M_E~0); 1427457#L1258-5 assume !(0 == ~T1_E~0); 1427455#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1427452#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1427450#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1427448#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1427446#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1427444#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1427442#L1293-3 assume !(0 == ~T8_E~0); 1427441#L1298-3 assume !(0 == ~T9_E~0); 1427440#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1427439#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1427438#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1427437#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1427436#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1427435#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1427434#L1333-3 assume !(0 == ~E_3~0); 1427433#L1338-3 assume !(0 == ~E_4~0); 1427432#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1427431#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1427430#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1427429#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1427428#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1427427#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1427426#L1373-3 assume !(0 == ~E_11~0); 1427425#L1378-3 assume !(0 == ~E_12~0); 1427424#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1427423#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1427422#L607-42 assume !(1 == ~m_pc~0); 1427421#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1427420#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1427419#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1427418#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1427417#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1427416#L626-42 assume !(1 == ~t1_pc~0); 1427415#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1427413#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1427412#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1427411#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1427410#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1427409#L645-42 assume !(1 == ~t2_pc~0); 1427408#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1427407#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1427406#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1427405#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1427404#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1427403#L664-42 assume !(1 == ~t3_pc~0); 1427402#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1427401#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1427400#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1427399#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1427398#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1427397#L683-42 assume !(1 == ~t4_pc~0); 1427396#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1427394#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1427392#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1427390#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1427387#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1427385#L702-42 assume 1 == ~t5_pc~0; 1427381#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1427379#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1427377#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1427375#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1427373#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1427371#L721-42 assume !(1 == ~t6_pc~0); 1427367#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1427365#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1427363#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1427361#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1427359#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1427357#L740-42 assume 1 == ~t7_pc~0; 1427353#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1427351#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1427349#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1427347#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 1427345#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1427343#L759-42 assume !(1 == ~t8_pc~0); 1427340#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1427337#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1427335#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1427333#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1427331#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1427329#L778-42 assume !(1 == ~t9_pc~0); 1427325#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1427323#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1427321#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1427319#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1427317#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1427315#L797-42 assume !(1 == ~t10_pc~0); 1427312#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1427309#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1427307#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1427305#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1427303#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1427301#L816-42 assume !(1 == ~t11_pc~0); 1427297#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1427295#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1427293#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1427291#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1427289#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1427287#L835-42 assume !(1 == ~t12_pc~0); 1427284#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1427281#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1427279#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1427277#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1427275#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1427273#L854-42 assume !(1 == ~t13_pc~0); 1427269#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1427267#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1427265#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1427263#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1427261#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1427259#L1401-3 assume !(1 == ~M_E~0); 1426495#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1339342#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1427255#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1427253#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1427251#L1421-3 assume !(1 == ~T5_E~0); 1427249#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1427247#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1427246#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1427226#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1427221#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1427215#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1427210#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1427203#L1461-3 assume !(1 == ~T13_E~0); 1427197#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1427191#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1427184#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1427176#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1427171#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1427165#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1427160#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1427155#L1501-3 assume !(1 == ~E_8~0); 1427149#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1427143#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1427138#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1373730#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1427129#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1427125#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1426673#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1426656#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1426650#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1426636#L1911 assume !(0 == start_simulation_~tmp~3#1); 1426637#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1429388#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1429373#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1429370#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1429368#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1429366#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1429364#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1429355#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1429353#L1892-2 [2021-11-22 16:04:13,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:04:13,464 INFO L85 PathProgramCache]: Analyzing trace with hash -820453841, now seen corresponding path program 1 times [2021-11-22 16:04:13,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:04:13,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027639401] [2021-11-22 16:04:13,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:04:13,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:04:13,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:04:13,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:04:13,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:04:13,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027639401] [2021-11-22 16:04:13,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027639401] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:04:13,508 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:04:13,508 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-22 16:04:13,508 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269276218] [2021-11-22 16:04:13,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:04:13,509 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-22 16:04:13,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-22 16:04:13,509 INFO L85 PathProgramCache]: Analyzing trace with hash -999675605, now seen corresponding path program 1 times [2021-11-22 16:04:13,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-22 16:04:13,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263652627] [2021-11-22 16:04:13,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-22 16:04:13,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-22 16:04:13,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-22 16:04:13,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-22 16:04:13,559 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-22 16:04:13,559 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263652627] [2021-11-22 16:04:13,559 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263652627] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-22 16:04:13,559 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-22 16:04:13,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-22 16:04:13,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346216417] [2021-11-22 16:04:13,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-22 16:04:13,560 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-22 16:04:13,561 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-22 16:04:13,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-22 16:04:13,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-22 16:04:13,562 INFO L87 Difference]: Start difference. First operand 207977 states and 298614 transitions. cyclomatic complexity: 90669 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-22 16:04:15,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-22 16:04:15,582 INFO L93 Difference]: Finished difference Result 399424 states and 571773 transitions. [2021-11-22 16:04:15,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-22 16:04:15,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399424 states and 571773 transitions. [2021-11-22 16:04:17,874 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2021-11-22 16:04:18,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399424 states to 399424 states and 571773 transitions. [2021-11-22 16:04:18,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399424 [2021-11-22 16:04:18,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399424 [2021-11-22 16:04:18,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399424 states and 571773 transitions. [2021-11-22 16:04:18,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-22 16:04:18,962 INFO L681 BuchiCegarLoop]: Abstraction has 399424 states and 571773 transitions. [2021-11-22 16:04:19,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399424 states and 571773 transitions.