./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 7e70badd Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-7e70bad [2021-11-23 14:13:23,187 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-23 14:13:23,190 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-23 14:13:23,265 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-23 14:13:23,266 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-23 14:13:23,268 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-23 14:13:23,270 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-23 14:13:23,274 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-23 14:13:23,277 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-23 14:13:23,278 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-23 14:13:23,280 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-23 14:13:23,282 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-23 14:13:23,283 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-23 14:13:23,285 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-23 14:13:23,287 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-23 14:13:23,289 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-23 14:13:23,291 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-23 14:13:23,292 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-23 14:13:23,295 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-23 14:13:23,299 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-23 14:13:23,302 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-23 14:13:23,304 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-23 14:13:23,314 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-23 14:13:23,318 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-23 14:13:23,324 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-23 14:13:23,326 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-23 14:13:23,327 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-23 14:13:23,330 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-23 14:13:23,332 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-23 14:13:23,334 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-23 14:13:23,334 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-23 14:13:23,335 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-23 14:13:23,339 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-23 14:13:23,341 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-23 14:13:23,343 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-23 14:13:23,344 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-23 14:13:23,345 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-23 14:13:23,345 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-23 14:13:23,345 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-23 14:13:23,347 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-23 14:13:23,347 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-23 14:13:23,349 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-11-23 14:13:23,403 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-23 14:13:23,410 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-23 14:13:23,411 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-23 14:13:23,412 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-23 14:13:23,414 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-23 14:13:23,414 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-23 14:13:23,414 INFO L138 SettingsManager]: * Use SBE=true [2021-11-23 14:13:23,415 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-23 14:13:23,415 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-23 14:13:23,415 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-23 14:13:23,416 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-23 14:13:23,417 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-23 14:13:23,417 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-23 14:13:23,417 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-23 14:13:23,418 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-23 14:13:23,418 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-23 14:13:23,418 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-23 14:13:23,419 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-23 14:13:23,419 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-23 14:13:23,419 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-23 14:13:23,419 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-23 14:13:23,420 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-23 14:13:23,420 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-23 14:13:23,420 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-23 14:13:23,420 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-23 14:13:23,421 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-23 14:13:23,423 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-23 14:13:23,423 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-23 14:13:23,423 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-23 14:13:23,425 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-23 14:13:23,426 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2021-11-23 14:13:23,851 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-23 14:13:23,896 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-23 14:13:23,900 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-23 14:13:23,901 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-23 14:13:23,902 INFO L275 PluginConnector]: CDTParser initialized [2021-11-23 14:13:23,904 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/../../sv-benchmarks/c/termination-15/array12_alloca.i [2021-11-23 14:13:24,015 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/data/3d9b8bcf7/c1408a16cf454ff6b5d34ad9827e8545/FLAG13e2c8029 [2021-11-23 14:13:24,769 INFO L306 CDTParser]: Found 1 translation units. [2021-11-23 14:13:24,769 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/sv-benchmarks/c/termination-15/array12_alloca.i [2021-11-23 14:13:24,785 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/data/3d9b8bcf7/c1408a16cf454ff6b5d34ad9827e8545/FLAG13e2c8029 [2021-11-23 14:13:25,033 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/data/3d9b8bcf7/c1408a16cf454ff6b5d34ad9827e8545 [2021-11-23 14:13:25,036 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-23 14:13:25,038 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-23 14:13:25,040 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-23 14:13:25,041 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-23 14:13:25,054 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-23 14:13:25,055 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,057 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@585c5dff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25, skipping insertion in model container [2021-11-23 14:13:25,057 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,068 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-23 14:13:25,111 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-23 14:13:25,565 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 14:13:25,577 INFO L203 MainTranslator]: Completed pre-run [2021-11-23 14:13:25,662 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 14:13:25,711 INFO L208 MainTranslator]: Completed translation [2021-11-23 14:13:25,712 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25 WrapperNode [2021-11-23 14:13:25,712 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-23 14:13:25,713 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-23 14:13:25,714 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-23 14:13:25,714 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-23 14:13:25,723 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,747 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,781 INFO L137 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2021-11-23 14:13:25,782 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-23 14:13:25,783 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-23 14:13:25,783 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-23 14:13:25,783 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-23 14:13:25,794 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,794 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,810 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,811 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,817 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,833 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,835 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,845 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-23 14:13:25,846 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-23 14:13:25,846 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-23 14:13:25,847 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-23 14:13:25,850 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (1/1) ... [2021-11-23 14:13:25,869 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:25,885 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:25,902 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:25,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-23 14:13:25,959 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-23 14:13:25,960 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-23 14:13:25,960 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-23 14:13:25,960 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-23 14:13:25,960 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-23 14:13:25,961 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-23 14:13:26,048 INFO L236 CfgBuilder]: Building ICFG [2021-11-23 14:13:26,051 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-23 14:13:26,258 INFO L277 CfgBuilder]: Performing block encoding [2021-11-23 14:13:26,267 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-23 14:13:26,267 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-11-23 14:13:26,270 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:13:26 BoogieIcfgContainer [2021-11-23 14:13:26,270 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-23 14:13:26,271 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-23 14:13:26,271 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-23 14:13:26,275 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-23 14:13:26,276 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:13:26,277 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:13:25" (1/3) ... [2021-11-23 14:13:26,278 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@641fc8de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:13:26, skipping insertion in model container [2021-11-23 14:13:26,279 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:13:26,279 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:13:25" (2/3) ... [2021-11-23 14:13:26,279 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@641fc8de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:13:26, skipping insertion in model container [2021-11-23 14:13:26,280 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:13:26,280 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:13:26" (3/3) ... [2021-11-23 14:13:26,281 INFO L388 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2021-11-23 14:13:26,339 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-23 14:13:26,339 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-23 14:13:26,339 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-23 14:13:26,340 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-23 14:13:26,340 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-23 14:13:26,340 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-23 14:13:26,340 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-23 14:13:26,340 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-23 14:13:26,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:26,384 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-23 14:13:26,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:26,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:26,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-23 14:13:26,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-23 14:13:26,393 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-23 14:13:26,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:26,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-23 14:13:26,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:26,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:26,398 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-23 14:13:26,398 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-23 14:13:26,407 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11#L367true assume !(main_~length~0#1 < 1); 8#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6#L370-3true [2021-11-23 14:13:26,408 INFO L793 eck$LassoCheckResult]: Loop: 6#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13#L372true assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6#L370-3true [2021-11-23 14:13:26,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:26,416 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2021-11-23 14:13:26,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:26,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803084016] [2021-11-23 14:13:26,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:26,430 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:26,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,547 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:26,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,585 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:26,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:26,589 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2021-11-23 14:13:26,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:26,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005264120] [2021-11-23 14:13:26,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:26,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:26,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,609 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:26,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,628 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:26,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:26,631 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2021-11-23 14:13:26,631 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:26,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127153866] [2021-11-23 14:13:26,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:26,632 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:26,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,660 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:26,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:26,689 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:27,047 INFO L210 LassoAnalysis]: Preferences: [2021-11-23 14:13:27,048 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-23 14:13:27,048 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-23 14:13:27,048 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-23 14:13:27,049 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-23 14:13:27,049 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:27,049 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-23 14:13:27,049 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-23 14:13:27,050 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2021-11-23 14:13:27,050 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-23 14:13:27,050 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-23 14:13:27,103 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,115 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,118 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,298 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,301 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,304 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,309 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,312 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,318 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,323 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:13:27,638 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-23 14:13:27,645 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-23 14:13:27,647 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:27,648 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:27,651 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:27,658 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:27,670 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:27,671 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:13:27,671 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:27,672 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:27,672 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:27,676 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:13:27,676 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:13:27,678 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-23 14:13:27,694 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:27,741 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:27,743 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:27,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:27,745 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:27,753 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:27,765 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:27,765 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:27,765 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:27,765 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:27,774 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:13:27,775 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:13:27,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-23 14:13:27,790 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:27,833 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:27,833 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:27,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:27,836 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:27,847 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:27,859 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:27,859 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:13:27,860 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:27,860 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:27,860 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:27,863 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:13:27,863 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:13:27,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-23 14:13:27,874 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:27,918 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:27,919 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:27,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:27,921 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:27,932 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:27,944 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:27,944 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:13:27,944 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:27,944 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:27,945 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:27,946 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:13:27,947 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:13:27,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-23 14:13:27,958 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:28,006 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:28,007 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:28,007 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:28,010 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:28,014 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-23 14:13:28,015 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:28,026 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:28,026 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:13:28,026 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:28,026 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:28,027 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:28,028 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:13:28,028 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:13:28,038 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:28,083 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:28,084 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:28,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:28,086 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:28,095 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:28,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:28,107 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:28,107 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:28,107 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:28,114 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:13:28,114 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:13:28,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-23 14:13:28,134 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:28,179 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:28,179 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:28,179 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:28,181 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:28,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-23 14:13:28,191 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:28,203 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:28,204 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:28,204 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:28,204 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:28,208 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:13:28,208 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:13:28,234 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:13:28,275 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:28,275 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:28,276 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:28,277 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:28,286 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-11-23 14:13:28,287 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:13:28,299 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:13:28,300 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:13:28,300 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:13:28,300 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:13:28,312 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:13:28,312 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:13:28,338 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-23 14:13:28,381 INFO L443 ModelExtractionUtils]: Simplification made 13 calls to the SMT solver. [2021-11-23 14:13:28,381 INFO L444 ModelExtractionUtils]: 6 out of 22 variables were initially zero. Simplification set additionally 12 variables to zero. [2021-11-23 14:13:28,383 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:13:28,383 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:28,386 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:13:28,392 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-23 14:13:28,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-11-23 14:13:28,420 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-23 14:13:28,420 INFO L513 LassoAnalysis]: Proved termination. [2021-11-23 14:13:28,421 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1) = -4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 Supporting invariants [] [2021-11-23 14:13:28,466 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:28,479 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-11-23 14:13:28,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:28,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:28,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-23 14:13:28,537 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:28,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:28,592 INFO L263 TraceCheckSpWp]: Trace formula consists of 18 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-23 14:13:28,593 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:28,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:28,699 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-23 14:13:28,701 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:28,783 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2021-11-23 14:13:28,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-23 14:13:28,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:28,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2021-11-23 14:13:28,798 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2021-11-23 14:13:28,799 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:13:28,799 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2021-11-23 14:13:28,800 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:13:28,800 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2021-11-23 14:13:28,801 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:13:28,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2021-11-23 14:13:28,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:28,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2021-11-23 14:13:28,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-23 14:13:28,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-23 14:13:28,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2021-11-23 14:13:28,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:28,817 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-23 14:13:28,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2021-11-23 14:13:28,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-11-23 14:13:28,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:28,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2021-11-23 14:13:28,848 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-23 14:13:28,848 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-23 14:13:28,849 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-23 14:13:28,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2021-11-23 14:13:28,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:28,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:28,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:28,850 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:28,851 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:28,851 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 121#L367 assume !(main_~length~0#1 < 1); 115#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 116#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 117#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 118#L370-4 main_~j~0#1 := 0; 119#L378-2 [2021-11-23 14:13:28,851 INFO L793 eck$LassoCheckResult]: Loop: 119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 120#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 119#L378-2 [2021-11-23 14:13:28,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:28,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2021-11-23 14:13:28,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:28,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061009809] [2021-11-23 14:13:28,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:28,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:28,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:28,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:28,934 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:28,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061009809] [2021-11-23 14:13:28,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061009809] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:13:28,935 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:13:28,935 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-11-23 14:13:28,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555626196] [2021-11-23 14:13:28,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:13:28,939 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:13:28,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:28,940 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2021-11-23 14:13:28,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:28,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167127397] [2021-11-23 14:13:28,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:28,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:28,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:28,957 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:28,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:28,965 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:29,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:29,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:13:29,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:13:29,052 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:29,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:29,106 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2021-11-23 14:13:29,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:13:29,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2021-11-23 14:13:29,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:29,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2021-11-23 14:13:29,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-11-23 14:13:29,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-23 14:13:29,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2021-11-23 14:13:29,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:29,116 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 19 transitions. [2021-11-23 14:13:29,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2021-11-23 14:13:29,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2021-11-23 14:13:29,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:29,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2021-11-23 14:13:29,120 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-23 14:13:29,121 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-23 14:13:29,121 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-23 14:13:29,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2021-11-23 14:13:29,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:29,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:29,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:29,125 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:29,125 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:29,127 INFO L791 eck$LassoCheckResult]: Stem: 146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 154#L367 assume !(main_~length~0#1 < 1); 148#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 149#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 156#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 151#L370-4 main_~j~0#1 := 0; 152#L378-2 [2021-11-23 14:13:29,127 INFO L793 eck$LassoCheckResult]: Loop: 152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 153#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 152#L378-2 [2021-11-23 14:13:29,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:29,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2021-11-23 14:13:29,129 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:29,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998840339] [2021-11-23 14:13:29,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:29,130 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:29,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:29,170 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:29,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:29,201 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:29,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:29,202 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2021-11-23 14:13:29,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:29,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958044613] [2021-11-23 14:13:29,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:29,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:29,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:29,210 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:29,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:29,218 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:29,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:29,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2021-11-23 14:13:29,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:29,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618011665] [2021-11-23 14:13:29,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:29,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:29,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:29,494 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:29,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:29,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618011665] [2021-11-23 14:13:29,495 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618011665] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:29,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1658431733] [2021-11-23 14:13:29,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:29,497 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:29,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:29,499 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:29,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-11-23 14:13:29,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:29,564 INFO L263 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-23 14:13:29,567 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:29,708 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-11-23 14:13:29,731 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-11-23 14:13:29,884 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:13:29,896 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:29,896 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:29,982 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-11-23 14:13:29,988 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 27 [2021-11-23 14:13:30,012 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:30,012 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1658431733] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:30,013 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:30,013 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 15 [2021-11-23 14:13:30,013 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215853595] [2021-11-23 14:13:30,014 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:30,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:30,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-23 14:13:30,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=182, Unknown=0, NotChecked=0, Total=240 [2021-11-23 14:13:30,080 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 16 states, 15 states have (on average 1.7333333333333334) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:30,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:30,248 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2021-11-23 14:13:30,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-23 14:13:30,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2021-11-23 14:13:30,251 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:30,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2021-11-23 14:13:30,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-11-23 14:13:30,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-11-23 14:13:30,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2021-11-23 14:13:30,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:30,253 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 30 transitions. [2021-11-23 14:13:30,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2021-11-23 14:13:30,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2021-11-23 14:13:30,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:30,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2021-11-23 14:13:30,270 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2021-11-23 14:13:30,270 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2021-11-23 14:13:30,270 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-23 14:13:30,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2021-11-23 14:13:30,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:30,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:30,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:30,278 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:30,278 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:30,278 INFO L791 eck$LassoCheckResult]: Stem: 271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 279#L367 assume !(main_~length~0#1 < 1); 273#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 274#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 275#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 280#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 281#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 282#L370-4 main_~j~0#1 := 0; 288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 276#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 277#L378-2 [2021-11-23 14:13:30,278 INFO L793 eck$LassoCheckResult]: Loop: 277#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 285#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 277#L378-2 [2021-11-23 14:13:30,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:30,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2021-11-23 14:13:30,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:30,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039390664] [2021-11-23 14:13:30,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:30,281 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:30,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:30,299 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:30,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:30,336 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:30,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:30,336 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2021-11-23 14:13:30,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:30,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40812769] [2021-11-23 14:13:30,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:30,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:30,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:30,342 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:30,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:30,348 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:30,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:30,349 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2021-11-23 14:13:30,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:30,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207508622] [2021-11-23 14:13:30,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:30,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:30,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:30,541 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:30,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:30,542 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207508622] [2021-11-23 14:13:30,542 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [207508622] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:30,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1942961400] [2021-11-23 14:13:30,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:30,543 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:30,543 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:30,550 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:30,570 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-11-23 14:13:30,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:30,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-23 14:13:30,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:30,737 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:30,737 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:30,814 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:30,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1942961400] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:30,815 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:30,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2021-11-23 14:13:30,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985443947] [2021-11-23 14:13:30,816 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:30,882 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:30,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-23 14:13:30,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2021-11-23 14:13:30,888 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 15 states, 15 states have (on average 1.8666666666666667) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:31,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:31,202 INFO L93 Difference]: Finished difference Result 42 states and 56 transitions. [2021-11-23 14:13:31,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-23 14:13:31,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 56 transitions. [2021-11-23 14:13:31,206 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:31,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 38 states and 50 transitions. [2021-11-23 14:13:31,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:13:31,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:13:31,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 50 transitions. [2021-11-23 14:13:31,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:31,212 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 50 transitions. [2021-11-23 14:13:31,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 50 transitions. [2021-11-23 14:13:31,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2021-11-23 14:13:31,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:31,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2021-11-23 14:13:31,218 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2021-11-23 14:13:31,218 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2021-11-23 14:13:31,218 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-23 14:13:31,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2021-11-23 14:13:31,220 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:31,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:31,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:31,221 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:31,221 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:31,221 INFO L791 eck$LassoCheckResult]: Stem: 438#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 447#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 440#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 441#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 442#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 449#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 458#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 460#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 443#L370-4 main_~j~0#1 := 0; 444#L378-2 [2021-11-23 14:13:31,222 INFO L793 eck$LassoCheckResult]: Loop: 444#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 454#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 444#L378-2 [2021-11-23 14:13:31,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:31,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2021-11-23 14:13:31,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:31,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901801005] [2021-11-23 14:13:31,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,224 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:31,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:31,321 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:31,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:31,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901801005] [2021-11-23 14:13:31,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901801005] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:31,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [676445697] [2021-11-23 14:13:31,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,323 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:31,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:31,347 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:31,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-11-23 14:13:31,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:31,424 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-23 14:13:31,425 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:31,507 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:31,507 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-23 14:13:31,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [676445697] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:13:31,508 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-11-23 14:13:31,512 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2021-11-23 14:13:31,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561762037] [2021-11-23 14:13:31,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:13:31,514 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:13:31,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:31,514 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2021-11-23 14:13:31,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:31,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796339198] [2021-11-23 14:13:31,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:31,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:31,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,552 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:31,614 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:31,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 14:13:31,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2021-11-23 14:13:31,616 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:31,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:31,666 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2021-11-23 14:13:31,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-23 14:13:31,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2021-11-23 14:13:31,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:31,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2021-11-23 14:13:31,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-11-23 14:13:31,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-11-23 14:13:31,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2021-11-23 14:13:31,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:31,677 INFO L681 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-11-23 14:13:31,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2021-11-23 14:13:31,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2021-11-23 14:13:31,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:31,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2021-11-23 14:13:31,680 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-11-23 14:13:31,680 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-11-23 14:13:31,680 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-23 14:13:31,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2021-11-23 14:13:31,682 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:31,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:31,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:31,683 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:31,683 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:31,683 INFO L791 eck$LassoCheckResult]: Stem: 546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 554#L367 assume !(main_~length~0#1 < 1); 548#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 549#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 555#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 556#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 557#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 562#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 553#L370-4 main_~j~0#1 := 0; 552#L378-2 [2021-11-23 14:13:31,683 INFO L793 eck$LassoCheckResult]: Loop: 552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 559#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 552#L378-2 [2021-11-23 14:13:31,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:31,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2021-11-23 14:13:31,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:31,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854736390] [2021-11-23 14:13:31,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,685 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:31,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,707 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:31,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,725 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:31,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:31,726 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2021-11-23 14:13:31,726 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:31,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428592133] [2021-11-23 14:13:31,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,727 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:31,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,732 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:31,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:31,738 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:31,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:31,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2021-11-23 14:13:31,739 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:31,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12246731] [2021-11-23 14:13:31,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:31,740 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:31,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:32,018 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:32,018 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:32,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12246731] [2021-11-23 14:13:32,019 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12246731] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:32,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [970839714] [2021-11-23 14:13:32,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:32,023 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:32,023 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:32,025 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:32,028 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-11-23 14:13:32,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:32,079 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-23 14:13:32,082 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:32,123 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:13:32,250 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:13:32,251 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-23 14:13:32,282 INFO L354 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2021-11-23 14:13:32,282 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 25 [2021-11-23 14:13:32,477 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:13:32,478 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:13:32,493 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:32,493 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:34,528 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-11-23 14:13:34,532 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 27 [2021-11-23 14:13:34,557 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:13:34,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [970839714] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:34,558 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:34,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 7] total 20 [2021-11-23 14:13:34,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890711222] [2021-11-23 14:13:34,558 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:34,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:34,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-23 14:13:34,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=310, Unknown=0, NotChecked=0, Total=420 [2021-11-23 14:13:34,623 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 21 states, 20 states have (on average 1.8) internal successors, (36), 21 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:34,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:34,871 INFO L93 Difference]: Finished difference Result 41 states and 54 transitions. [2021-11-23 14:13:34,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-23 14:13:34,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 54 transitions. [2021-11-23 14:13:34,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:34,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 41 states and 54 transitions. [2021-11-23 14:13:34,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-11-23 14:13:34,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-11-23 14:13:34,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 54 transitions. [2021-11-23 14:13:34,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:34,877 INFO L681 BuchiCegarLoop]: Abstraction has 41 states and 54 transitions. [2021-11-23 14:13:34,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 54 transitions. [2021-11-23 14:13:34,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 25. [2021-11-23 14:13:34,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.36) internal successors, (34), 24 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:34,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 34 transitions. [2021-11-23 14:13:34,881 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 34 transitions. [2021-11-23 14:13:34,881 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 34 transitions. [2021-11-23 14:13:34,881 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-23 14:13:34,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 34 transitions. [2021-11-23 14:13:34,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:34,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:34,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:34,884 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:34,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:34,884 INFO L791 eck$LassoCheckResult]: Stem: 726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 735#L367 assume !(main_~length~0#1 < 1); 728#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 729#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 730#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 736#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 738#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 750#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 749#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 733#L370-4 main_~j~0#1 := 0; 734#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 731#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 732#L378-2 [2021-11-23 14:13:34,884 INFO L793 eck$LassoCheckResult]: Loop: 732#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 742#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 732#L378-2 [2021-11-23 14:13:34,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:34,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2021-11-23 14:13:34,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:34,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250792513] [2021-11-23 14:13:34,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:34,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:34,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:34,902 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:34,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:34,921 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:34,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:34,922 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2021-11-23 14:13:34,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:34,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424395230] [2021-11-23 14:13:34,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:34,923 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:34,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:34,927 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:34,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:34,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:34,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:34,933 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2021-11-23 14:13:34,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:34,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770983813] [2021-11-23 14:13:34,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:34,934 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:34,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:35,105 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:35,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:35,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770983813] [2021-11-23 14:13:35,106 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770983813] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:35,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1211838826] [2021-11-23 14:13:35,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:35,107 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:35,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:35,109 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:35,114 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-11-23 14:13:35,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:35,171 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-23 14:13:35,173 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:35,277 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-23 14:13:35,379 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:13:35,396 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:35,396 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:35,485 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-11-23 14:13:35,488 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-23 14:13:35,527 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:35,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1211838826] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:35,528 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:35,528 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 18 [2021-11-23 14:13:35,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806074415] [2021-11-23 14:13:35,529 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:35,592 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:35,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-23 14:13:35,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2021-11-23 14:13:35,594 INFO L87 Difference]: Start difference. First operand 25 states and 34 transitions. cyclomatic complexity: 12 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:35,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:35,788 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2021-11-23 14:13:35,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-23 14:13:35,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 43 transitions. [2021-11-23 14:13:35,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:35,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 33 states and 43 transitions. [2021-11-23 14:13:35,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:13:35,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:13:35,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 43 transitions. [2021-11-23 14:13:35,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:35,792 INFO L681 BuchiCegarLoop]: Abstraction has 33 states and 43 transitions. [2021-11-23 14:13:35,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 43 transitions. [2021-11-23 14:13:35,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 28. [2021-11-23 14:13:35,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.3214285714285714) internal successors, (37), 27 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:35,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 37 transitions. [2021-11-23 14:13:35,797 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 37 transitions. [2021-11-23 14:13:35,797 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 37 transitions. [2021-11-23 14:13:35,797 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-23 14:13:35,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 37 transitions. [2021-11-23 14:13:35,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:35,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:35,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:35,799 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:35,799 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:35,800 INFO L791 eck$LassoCheckResult]: Stem: 908#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 916#L367 assume !(main_~length~0#1 < 1); 910#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 911#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 912#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 917#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 927#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 918#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 919#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 922#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 935#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 915#L370-4 main_~j~0#1 := 0; 914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 920#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 929#L378-2 [2021-11-23 14:13:35,800 INFO L793 eck$LassoCheckResult]: Loop: 929#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 928#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 929#L378-2 [2021-11-23 14:13:35,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:35,801 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2021-11-23 14:13:35,801 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:35,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506973152] [2021-11-23 14:13:35,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:35,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:35,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:35,817 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:35,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:35,834 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:35,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:35,835 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2021-11-23 14:13:35,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:35,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167652137] [2021-11-23 14:13:35,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:35,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:35,840 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:35,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:35,845 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:35,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:35,846 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2021-11-23 14:13:35,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:35,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186512874] [2021-11-23 14:13:35,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:35,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:35,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:35,984 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:35,984 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:35,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186512874] [2021-11-23 14:13:35,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186512874] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:35,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1396776177] [2021-11-23 14:13:35,985 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:13:35,985 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:35,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:35,988 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:36,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-23 14:13:36,053 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:13:36,053 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:13:36,054 INFO L263 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-23 14:13:36,056 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:36,091 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-23 14:13:36,224 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:13:36,227 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:36,228 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:36,321 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:13:36,325 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:13:36,350 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:36,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1396776177] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:36,351 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:36,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 13 [2021-11-23 14:13:36,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979659450] [2021-11-23 14:13:36,353 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:36,413 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:36,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-23 14:13:36,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2021-11-23 14:13:36,415 INFO L87 Difference]: Start difference. First operand 28 states and 37 transitions. cyclomatic complexity: 12 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:36,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:36,552 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2021-11-23 14:13:36,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-23 14:13:36,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 62 transitions. [2021-11-23 14:13:36,557 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:36,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 62 transitions. [2021-11-23 14:13:36,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2021-11-23 14:13:36,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2021-11-23 14:13:36,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 62 transitions. [2021-11-23 14:13:36,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:36,559 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 62 transitions. [2021-11-23 14:13:36,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 62 transitions. [2021-11-23 14:13:36,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 37. [2021-11-23 14:13:36,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3783783783783783) internal successors, (51), 36 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:36,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 51 transitions. [2021-11-23 14:13:36,569 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 51 transitions. [2021-11-23 14:13:36,569 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 51 transitions. [2021-11-23 14:13:36,569 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-23 14:13:36,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 51 transitions. [2021-11-23 14:13:36,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:36,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:36,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:36,573 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:36,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:36,575 INFO L791 eck$LassoCheckResult]: Stem: 1100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1108#L367 assume !(main_~length~0#1 < 1); 1102#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1103#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1104#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1109#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1110#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1111#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1135#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1133#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1134#L370-4 main_~j~0#1 := 0; 1136#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1105#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1106#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1121#L378-2 [2021-11-23 14:13:36,575 INFO L793 eck$LassoCheckResult]: Loop: 1121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1122#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1121#L378-2 [2021-11-23 14:13:36,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:36,576 INFO L85 PathProgramCache]: Analyzing trace with hash 123354082, now seen corresponding path program 2 times [2021-11-23 14:13:36,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:36,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296660869] [2021-11-23 14:13:36,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:36,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:36,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:36,612 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:36,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:36,648 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:36,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:36,657 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2021-11-23 14:13:36,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:36,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126625256] [2021-11-23 14:13:36,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:36,658 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:36,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:36,669 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:36,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:36,674 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:36,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:36,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1715810139, now seen corresponding path program 2 times [2021-11-23 14:13:36,675 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:36,675 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429382397] [2021-11-23 14:13:36,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:36,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:36,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:36,944 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:36,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:36,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429382397] [2021-11-23 14:13:36,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429382397] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:36,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1843641636] [2021-11-23 14:13:36,945 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:13:36,945 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:36,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:36,948 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:36,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-23 14:13:37,002 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:13:37,003 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:13:37,004 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-23 14:13:37,005 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:37,166 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:37,166 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:37,254 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:37,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1843641636] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:37,254 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:37,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2021-11-23 14:13:37,257 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126672061] [2021-11-23 14:13:37,257 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:37,320 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:37,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-23 14:13:37,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=298, Unknown=0, NotChecked=0, Total=380 [2021-11-23 14:13:37,321 INFO L87 Difference]: Start difference. First operand 37 states and 51 transitions. cyclomatic complexity: 19 Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:37,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:37,528 INFO L93 Difference]: Finished difference Result 49 states and 64 transitions. [2021-11-23 14:13:37,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-23 14:13:37,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 64 transitions. [2021-11-23 14:13:37,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:37,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 43 states and 57 transitions. [2021-11-23 14:13:37,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-23 14:13:37,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-23 14:13:37,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 57 transitions. [2021-11-23 14:13:37,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:37,533 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 57 transitions. [2021-11-23 14:13:37,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 57 transitions. [2021-11-23 14:13:37,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 39. [2021-11-23 14:13:37,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3333333333333333) internal successors, (52), 38 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:37,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 52 transitions. [2021-11-23 14:13:37,537 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 52 transitions. [2021-11-23 14:13:37,537 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 52 transitions. [2021-11-23 14:13:37,537 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-23 14:13:37,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 52 transitions. [2021-11-23 14:13:37,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:37,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:37,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:37,543 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:37,543 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:37,544 INFO L791 eck$LassoCheckResult]: Stem: 1327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1335#L367 assume !(main_~length~0#1 < 1); 1329#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1330#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1336#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1365#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1364#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1361#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1359#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1355#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1332#L370-4 main_~j~0#1 := 0; 1333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1340#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1343#L378-2 [2021-11-23 14:13:37,544 INFO L793 eck$LassoCheckResult]: Loop: 1343#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1344#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1343#L378-2 [2021-11-23 14:13:37,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:37,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164513, now seen corresponding path program 3 times [2021-11-23 14:13:37,545 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:37,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850509193] [2021-11-23 14:13:37,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:37,546 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:37,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:37,580 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:37,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:37,611 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:37,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:37,616 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2021-11-23 14:13:37,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:37,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013769786] [2021-11-23 14:13:37,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:37,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:37,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:37,630 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:13:37,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:13:37,640 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:13:37,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:37,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1462118108, now seen corresponding path program 3 times [2021-11-23 14:13:37,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:37,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515800700] [2021-11-23 14:13:37,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:37,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:37,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:37,812 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:37,812 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:37,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515800700] [2021-11-23 14:13:37,813 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515800700] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:37,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [142750854] [2021-11-23 14:13:37,813 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:13:37,814 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:37,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:37,816 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:37,837 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-23 14:13:37,875 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-23 14:13:37,876 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:13:37,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-23 14:13:37,879 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:37,919 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:13:37,962 INFO L354 Elim1Store]: treesize reduction 25, result has 37.5 percent of original size [2021-11-23 14:13:37,963 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 30 [2021-11-23 14:13:37,983 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2021-11-23 14:13:37,998 INFO L354 Elim1Store]: treesize reduction 25, result has 37.5 percent of original size [2021-11-23 14:13:37,999 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 41 treesize of output 51 [2021-11-23 14:13:38,089 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:13:38,103 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-11-23 14:13:38,103 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:13:42,700 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-11-23 14:13:42,703 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-23 14:13:42,737 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-11-23 14:13:42,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [142750854] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:13:42,737 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:13:42,737 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 16 [2021-11-23 14:13:42,738 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240581646] [2021-11-23 14:13:42,738 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:13:42,796 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:13:42,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-11-23 14:13:42,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2021-11-23 14:13:42,797 INFO L87 Difference]: Start difference. First operand 39 states and 52 transitions. cyclomatic complexity: 18 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:42,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:13:42,999 INFO L93 Difference]: Finished difference Result 67 states and 89 transitions. [2021-11-23 14:13:43,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-23 14:13:43,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 89 transitions. [2021-11-23 14:13:43,003 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:13:43,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 67 states and 89 transitions. [2021-11-23 14:13:43,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2021-11-23 14:13:43,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2021-11-23 14:13:43,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 89 transitions. [2021-11-23 14:13:43,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:13:43,009 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 89 transitions. [2021-11-23 14:13:43,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 89 transitions. [2021-11-23 14:13:43,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 48. [2021-11-23 14:13:43,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.3958333333333333) internal successors, (67), 47 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:13:43,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 67 transitions. [2021-11-23 14:13:43,026 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 67 transitions. [2021-11-23 14:13:43,026 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 67 transitions. [2021-11-23 14:13:43,026 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-23 14:13:43,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 67 transitions. [2021-11-23 14:13:43,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:13:43,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:13:43,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:13:43,028 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:13:43,028 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:13:43,029 INFO L791 eck$LassoCheckResult]: Stem: 1571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1579#L367 assume !(main_~length~0#1 < 1); 1573#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1574#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1575#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1580#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1593#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1587#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1581#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1582#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1588#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1589#L370-4 main_~j~0#1 := 0; 1597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1591#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1592#L378-2 [2021-11-23 14:13:43,029 INFO L793 eck$LassoCheckResult]: Loop: 1592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1598#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1592#L378-2 [2021-11-23 14:13:43,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:13:43,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1119422813, now seen corresponding path program 2 times [2021-11-23 14:13:43,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:13:43,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543878148] [2021-11-23 14:13:43,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:13:43,030 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:13:43,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:13:43,299 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:43,300 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:13:43,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543878148] [2021-11-23 14:13:43,300 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543878148] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:13:43,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1261855647] [2021-11-23 14:13:43,301 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:13:43,301 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:13:43,301 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:13:43,306 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:13:43,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-23 14:13:43,361 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:13:43,361 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:13:43,362 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-23 14:13:43,364 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:13:43,411 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:13:43,510 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:13:43,511 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-23 14:13:43,539 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:13:43,543 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-23 14:13:43,670 INFO L354 Elim1Store]: treesize reduction 72, result has 20.9 percent of original size [2021-11-23 14:13:43,671 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 42 treesize of output 44 [2021-11-23 14:13:43,865 INFO L354 Elim1Store]: treesize reduction 38, result has 7.3 percent of original size [2021-11-23 14:13:43,865 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 32 [2021-11-23 14:13:43,887 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:13:43,887 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:14:42,272 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 57 [2021-11-23 14:14:42,280 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 920 treesize of output 896 [2021-11-23 14:14:43,591 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:43,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1261855647] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:14:43,592 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:14:43,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 28 [2021-11-23 14:14:43,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466777896] [2021-11-23 14:14:43,592 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:14:43,592 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:14:43,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:43,593 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2021-11-23 14:14:43,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:43,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315056587] [2021-11-23 14:14:43,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:43,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:43,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:43,597 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:43,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:43,607 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:43,670 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:14:43,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-23 14:14:43,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=649, Unknown=5, NotChecked=0, Total=812 [2021-11-23 14:14:43,671 INFO L87 Difference]: Start difference. First operand 48 states and 67 transitions. cyclomatic complexity: 26 Second operand has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 29 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:44,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:14:44,036 INFO L93 Difference]: Finished difference Result 70 states and 94 transitions. [2021-11-23 14:14:44,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-23 14:14:44,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 94 transitions. [2021-11-23 14:14:44,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:44,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 70 states and 94 transitions. [2021-11-23 14:14:44,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2021-11-23 14:14:44,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2021-11-23 14:14:44,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 94 transitions. [2021-11-23 14:14:44,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:14:44,041 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 94 transitions. [2021-11-23 14:14:44,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 94 transitions. [2021-11-23 14:14:44,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 35. [2021-11-23 14:14:44,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.3428571428571427) internal successors, (47), 34 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:44,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 47 transitions. [2021-11-23 14:14:44,045 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 47 transitions. [2021-11-23 14:14:44,045 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 47 transitions. [2021-11-23 14:14:44,045 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-23 14:14:44,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 47 transitions. [2021-11-23 14:14:44,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:44,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:14:44,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:14:44,052 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:14:44,052 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:14:44,053 INFO L791 eck$LassoCheckResult]: Stem: 1836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1844#L367 assume !(main_~length~0#1 < 1); 1838#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1839#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1845#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1863#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1862#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1860#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1857#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1867#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1851#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1841#L370-4 main_~j~0#1 := 0; 1842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1850#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1856#L378-2 [2021-11-23 14:14:44,053 INFO L793 eck$LassoCheckResult]: Loop: 1856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1855#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1856#L378-2 [2021-11-23 14:14:44,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:44,054 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 4 times [2021-11-23 14:14:44,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:44,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651762532] [2021-11-23 14:14:44,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:44,055 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:44,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:44,072 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:44,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:44,102 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:44,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:44,104 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2021-11-23 14:14:44,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:44,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261092870] [2021-11-23 14:14:44,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:44,105 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:44,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:44,109 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:44,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:44,112 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:44,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:44,113 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 4 times [2021-11-23 14:14:44,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:44,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934848209] [2021-11-23 14:14:44,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:44,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:44,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:44,326 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:44,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:14:44,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934848209] [2021-11-23 14:14:44,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934848209] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:14:44,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [821249481] [2021-11-23 14:14:44,326 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:14:44,327 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:14:44,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:44,334 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:14:44,354 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-23 14:14:44,390 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:14:44,390 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:14:44,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-23 14:14:44,393 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:44,490 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:14:44,608 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:14:44,608 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:14:44,631 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:14:44,631 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:14:44,903 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:14:44,903 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:14:44,908 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:44,908 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:14:45,886 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:14:45,890 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:14:45,919 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:14:45,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [821249481] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:14:45,920 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:14:45,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 9] total 22 [2021-11-23 14:14:45,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427004687] [2021-11-23 14:14:45,921 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:14:45,980 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:14:45,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-23 14:14:45,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=407, Unknown=0, NotChecked=0, Total=506 [2021-11-23 14:14:45,982 INFO L87 Difference]: Start difference. First operand 35 states and 47 transitions. cyclomatic complexity: 16 Second operand has 23 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 23 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:46,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:14:46,227 INFO L93 Difference]: Finished difference Result 62 states and 81 transitions. [2021-11-23 14:14:46,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-23 14:14:46,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 81 transitions. [2021-11-23 14:14:46,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:46,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 62 states and 81 transitions. [2021-11-23 14:14:46,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-11-23 14:14:46,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-11-23 14:14:46,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 81 transitions. [2021-11-23 14:14:46,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:14:46,232 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 81 transitions. [2021-11-23 14:14:46,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 81 transitions. [2021-11-23 14:14:46,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 30. [2021-11-23 14:14:46,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.3333333333333333) internal successors, (40), 29 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:46,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 40 transitions. [2021-11-23 14:14:46,236 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 40 transitions. [2021-11-23 14:14:46,236 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 40 transitions. [2021-11-23 14:14:46,236 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-23 14:14:46,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 40 transitions. [2021-11-23 14:14:46,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:46,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:14:46,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:14:46,238 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:14:46,238 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:14:46,239 INFO L791 eck$LassoCheckResult]: Stem: 2081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2089#L367 assume !(main_~length~0#1 < 1); 2083#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2084#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2085#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2090#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2100#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2099#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2098#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2091#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2092#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2110#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2109#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2097#L370-4 main_~j~0#1 := 0; 2095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2086#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2087#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2104#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2103#L378-2 [2021-11-23 14:14:46,239 INFO L793 eck$LassoCheckResult]: Loop: 2103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2102#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2103#L378-2 [2021-11-23 14:14:46,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:46,240 INFO L85 PathProgramCache]: Analyzing trace with hash -761053528, now seen corresponding path program 5 times [2021-11-23 14:14:46,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:46,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135789065] [2021-11-23 14:14:46,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:46,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:46,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:46,253 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:46,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:46,269 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:46,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:46,270 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2021-11-23 14:14:46,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:46,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566190157] [2021-11-23 14:14:46,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:46,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:46,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:46,274 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:46,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:46,277 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:46,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:46,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1227998741, now seen corresponding path program 5 times [2021-11-23 14:14:46,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:46,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625989730] [2021-11-23 14:14:46,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:46,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:46,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:46,422 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:46,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:14:46,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625989730] [2021-11-23 14:14:46,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625989730] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:14:46,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2139573474] [2021-11-23 14:14:46,423 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:14:46,423 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:14:46,423 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:46,427 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:14:46,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-23 14:14:46,496 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-11-23 14:14:46,496 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:14:46,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-23 14:14:46,499 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:46,552 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:14:46,691 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:14:46,709 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:46,709 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:14:46,889 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2021-11-23 14:14:46,893 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 36 [2021-11-23 14:14:46,945 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:46,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2139573474] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:14:46,945 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:14:46,946 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 19 [2021-11-23 14:14:46,946 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037121383] [2021-11-23 14:14:46,946 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:14:47,004 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:14:47,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-23 14:14:47,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=319, Unknown=0, NotChecked=0, Total=380 [2021-11-23 14:14:47,005 INFO L87 Difference]: Start difference. First operand 30 states and 40 transitions. cyclomatic complexity: 13 Second operand has 20 states, 19 states have (on average 2.1052631578947367) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:47,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:14:47,209 INFO L93 Difference]: Finished difference Result 38 states and 48 transitions. [2021-11-23 14:14:47,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-23 14:14:47,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 48 transitions. [2021-11-23 14:14:47,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:47,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 38 states and 48 transitions. [2021-11-23 14:14:47,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-23 14:14:47,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-23 14:14:47,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 48 transitions. [2021-11-23 14:14:47,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:14:47,213 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 48 transitions. [2021-11-23 14:14:47,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 48 transitions. [2021-11-23 14:14:47,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 33. [2021-11-23 14:14:47,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.303030303030303) internal successors, (43), 32 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:47,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 43 transitions. [2021-11-23 14:14:47,215 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 43 transitions. [2021-11-23 14:14:47,216 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 43 transitions. [2021-11-23 14:14:47,216 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-23 14:14:47,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 43 transitions. [2021-11-23 14:14:47,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:47,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:14:47,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:14:47,217 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:14:47,217 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:14:47,217 INFO L791 eck$LassoCheckResult]: Stem: 2302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2310#L367 assume !(main_~length~0#1 < 1); 2304#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2305#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2311#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2322#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2323#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2312#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2313#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2334#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2307#L370-4 main_~j~0#1 := 0; 2308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2316#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2327#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2326#L378-2 [2021-11-23 14:14:47,218 INFO L793 eck$LassoCheckResult]: Loop: 2326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2325#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2326#L378-2 [2021-11-23 14:14:47,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:47,218 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 3 times [2021-11-23 14:14:47,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:47,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850606359] [2021-11-23 14:14:47,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:47,219 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:47,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:47,235 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:47,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:47,270 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:47,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:47,272 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2021-11-23 14:14:47,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:47,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970494460] [2021-11-23 14:14:47,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:47,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:47,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:47,277 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:47,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:47,281 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:47,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:47,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 3 times [2021-11-23 14:14:47,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:47,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105398318] [2021-11-23 14:14:47,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:47,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:47,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:47,478 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:47,478 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:14:47,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [105398318] [2021-11-23 14:14:47,478 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [105398318] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:14:47,479 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1251907679] [2021-11-23 14:14:47,479 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:14:47,479 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:14:47,479 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:47,482 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:14:47,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-23 14:14:47,553 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-23 14:14:47,553 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:14:47,554 INFO L263 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-23 14:14:47,556 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:47,661 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:14:48,031 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-23 14:14:48,031 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 21 [2021-11-23 14:14:48,036 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:48,037 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:14:48,481 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2021-11-23 14:14:48,485 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 43 [2021-11-23 14:14:48,519 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:48,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1251907679] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:14:48,519 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:14:48,520 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 12] total 28 [2021-11-23 14:14:48,520 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878264006] [2021-11-23 14:14:48,520 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:14:48,583 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:14:48,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-23 14:14:48,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=691, Unknown=0, NotChecked=0, Total=812 [2021-11-23 14:14:48,584 INFO L87 Difference]: Start difference. First operand 33 states and 43 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 1.75) internal successors, (49), 29 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:49,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:14:49,105 INFO L93 Difference]: Finished difference Result 47 states and 58 transitions. [2021-11-23 14:14:49,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-23 14:14:49,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 58 transitions. [2021-11-23 14:14:49,107 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:14:49,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 58 transitions. [2021-11-23 14:14:49,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-11-23 14:14:49,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-11-23 14:14:49,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2021-11-23 14:14:49,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:14:49,109 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 58 transitions. [2021-11-23 14:14:49,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2021-11-23 14:14:49,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 35. [2021-11-23 14:14:49,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.3142857142857143) internal successors, (46), 34 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:49,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 46 transitions. [2021-11-23 14:14:49,113 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 46 transitions. [2021-11-23 14:14:49,113 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 46 transitions. [2021-11-23 14:14:49,113 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-23 14:14:49,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 46 transitions. [2021-11-23 14:14:49,114 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:14:49,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:14:49,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:14:49,115 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:14:49,115 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:14:49,116 INFO L791 eck$LassoCheckResult]: Stem: 2572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2578#L367 assume !(main_~length~0#1 < 1); 2570#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2571#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2574#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2579#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2586#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2589#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2581#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2582#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2604#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2577#L370-4 main_~j~0#1 := 0; 2576#L378-2 [2021-11-23 14:14:49,116 INFO L793 eck$LassoCheckResult]: Loop: 2576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2575#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2576#L378-2 [2021-11-23 14:14:49,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:49,117 INFO L85 PathProgramCache]: Analyzing trace with hash 256561246, now seen corresponding path program 2 times [2021-11-23 14:14:49,117 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:49,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634561249] [2021-11-23 14:14:49,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:49,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:49,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,125 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:49,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,135 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:49,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:49,136 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2021-11-23 14:14:49,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:49,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253968275] [2021-11-23 14:14:49,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:49,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:49,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,140 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:49,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,143 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:49,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:49,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 6 times [2021-11-23 14:14:49,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:49,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372346523] [2021-11-23 14:14:49,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:49,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:49,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,154 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:49,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:49,166 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:49,876 INFO L210 LassoAnalysis]: Preferences: [2021-11-23 14:14:49,876 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-23 14:14:49,876 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-23 14:14:49,876 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-23 14:14:49,876 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-23 14:14:49,876 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:49,876 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-23 14:14:49,876 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-23 14:14:49,876 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration15_Lasso [2021-11-23 14:14:49,876 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-23 14:14:49,877 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-23 14:14:49,880 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:49,888 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,012 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,014 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,019 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,021 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,024 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,026 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,030 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-23 14:14:50,285 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-23 14:14:50,286 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-23 14:14:50,286 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,291 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-11-23 14:14:50,295 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,304 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,304 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:14:50,305 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,305 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,305 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,306 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:14:50,306 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:14:50,314 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,344 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,345 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,346 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,347 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-11-23 14:14:50,348 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,358 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,358 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,358 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,358 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,362 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,362 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,394 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,420 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,420 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,433 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,439 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,442 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2021-11-23 14:14:50,450 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,451 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,451 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,451 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,452 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,452 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,455 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,480 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,480 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,480 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,481 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2021-11-23 14:14:50,483 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,492 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,492 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,492 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,498 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,498 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,503 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,527 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,527 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,528 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,538 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2021-11-23 14:14:50,540 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,548 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,548 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-23 14:14:50,549 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,549 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,549 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,549 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-23 14:14:50,549 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-23 14:14:50,550 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,575 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,580 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,581 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,587 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2021-11-23 14:14:50,588 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,602 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,602 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,602 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,602 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,606 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,606 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,611 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,641 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2021-11-23 14:14:50,641 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,642 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2021-11-23 14:14:50,645 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,654 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,654 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,654 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,654 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,656 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,656 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,683 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-23 14:14:50,709 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,709 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,709 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,710 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,712 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2021-11-23 14:14:50,712 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-23 14:14:50,721 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-23 14:14:50,721 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-23 14:14:50,721 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-23 14:14:50,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-23 14:14:50,733 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-23 14:14:50,733 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-23 14:14:50,758 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-23 14:14:50,817 INFO L443 ModelExtractionUtils]: Simplification made 17 calls to the SMT solver. [2021-11-23 14:14:50,817 INFO L444 ModelExtractionUtils]: 7 out of 25 variables were initially zero. Simplification set additionally 14 variables to zero. [2021-11-23 14:14:50,817 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:14:50,817 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:50,826 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:14:50,828 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-23 14:14:50,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2021-11-23 14:14:50,859 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-23 14:14:50,860 INFO L513 LassoAnalysis]: Proved termination. [2021-11-23 14:14:50,860 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2, ULTIMATE.start_main_~j~0#1) = -1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 - 4*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2021-11-23 14:14:50,892 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:50,899 INFO L297 tatePredicateManager]: 2 out of 3 supporting invariants were superfluous and have been removed [2021-11-23 14:14:50,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:50,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:50,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-23 14:14:50,954 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:51,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:51,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-23 14:14:51,049 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:51,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:51,113 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2021-11-23 14:14:51,113 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 35 states and 46 transitions. cyclomatic complexity: 15 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:51,169 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 35 states and 46 transitions. cyclomatic complexity: 15. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 43 states and 57 transitions. Complement of second has 6 states. [2021-11-23 14:14:51,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2021-11-23 14:14:51,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:51,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2021-11-23 14:14:51,174 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 16 letters. Loop has 2 letters. [2021-11-23 14:14:51,174 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:14:51,174 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 18 letters. Loop has 2 letters. [2021-11-23 14:14:51,174 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:14:51,175 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 16 letters. Loop has 4 letters. [2021-11-23 14:14:51,175 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-23 14:14:51,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2021-11-23 14:14:51,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:51,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 36 states and 46 transitions. [2021-11-23 14:14:51,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-11-23 14:14:51,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:14:51,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 46 transitions. [2021-11-23 14:14:51,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:14:51,177 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 46 transitions. [2021-11-23 14:14:51,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 46 transitions. [2021-11-23 14:14:51,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2021-11-23 14:14:51,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.2857142857142858) internal successors, (45), 34 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:14:51,192 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2021-11-23 14:14:51,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 45 transitions. [2021-11-23 14:14:51,196 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 45 transitions. [2021-11-23 14:14:51,196 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 45 transitions. [2021-11-23 14:14:51,197 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-23 14:14:51,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 45 transitions. [2021-11-23 14:14:51,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:14:51,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:14:51,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:14:51,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:14:51,202 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:14:51,202 INFO L791 eck$LassoCheckResult]: Stem: 2742#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2753#L367 assume !(main_~length~0#1 < 1); 2744#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2745#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2746#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2754#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2755#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2756#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2776#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2775#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2773#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2774#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2772#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2769#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2768#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2759#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2747#L370-4 main_~j~0#1 := 0; 2748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2758#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2761#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2749#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2750#L378-2 [2021-11-23 14:14:51,203 INFO L793 eck$LassoCheckResult]: Loop: 2750#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2762#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2750#L378-2 [2021-11-23 14:14:51,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:51,203 INFO L85 PathProgramCache]: Analyzing trace with hash -34213284, now seen corresponding path program 6 times [2021-11-23 14:14:51,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:51,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987327069] [2021-11-23 14:14:51,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:51,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:51,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:14:51,411 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:51,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:14:51,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987327069] [2021-11-23 14:14:51,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987327069] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:14:51,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [663397003] [2021-11-23 14:14:51,412 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:14:51,412 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:14:51,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:14:51,414 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:14:51,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-23 14:14:51,489 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2021-11-23 14:14:51,490 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:14:51,491 INFO L263 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-23 14:14:51,493 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:14:51,535 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:14:51,625 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:14:51,626 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:14:51,653 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:14:51,654 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:14:51,774 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:14:51,775 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:14:51,987 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:14:51,987 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:14:51,999 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:51,999 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:14:59,726 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2021-11-23 14:14:59,730 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 83 [2021-11-23 14:14:59,806 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:14:59,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [663397003] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:14:59,807 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:14:59,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 12] total 22 [2021-11-23 14:14:59,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452668193] [2021-11-23 14:14:59,808 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:14:59,808 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:14:59,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:14:59,809 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2021-11-23 14:14:59,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:14:59,809 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856269281] [2021-11-23 14:14:59,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:14:59,809 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:14:59,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:59,813 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:14:59,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:14:59,816 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:14:59,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:14:59,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-23 14:14:59,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=401, Unknown=9, NotChecked=0, Total=506 [2021-11-23 14:14:59,878 INFO L87 Difference]: Start difference. First operand 35 states and 45 transitions. cyclomatic complexity: 14 Second operand has 23 states, 22 states have (on average 2.0) internal successors, (44), 23 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:00,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:00,937 INFO L93 Difference]: Finished difference Result 57 states and 74 transitions. [2021-11-23 14:15:00,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-23 14:15:00,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 74 transitions. [2021-11-23 14:15:00,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:00,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 56 states and 72 transitions. [2021-11-23 14:15:00,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-23 14:15:00,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-23 14:15:00,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 72 transitions. [2021-11-23 14:15:00,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:00,940 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 72 transitions. [2021-11-23 14:15:00,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 72 transitions. [2021-11-23 14:15:00,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 27. [2021-11-23 14:15:00,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2592592592592593) internal successors, (34), 26 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:00,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 34 transitions. [2021-11-23 14:15:00,944 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 34 transitions. [2021-11-23 14:15:00,944 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 34 transitions. [2021-11-23 14:15:00,945 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-23 14:15:00,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 34 transitions. [2021-11-23 14:15:00,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:00,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:00,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:00,946 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:00,946 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:00,947 INFO L791 eck$LassoCheckResult]: Stem: 2997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3008#L367 assume !(main_~length~0#1 < 1); 2999#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3000#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3009#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3020#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3019#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3015#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3022#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3021#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3010#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3011#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3012#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3018#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3002#L370-4 main_~j~0#1 := 0; 3003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3006#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3013#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3004#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3005#L378-2 [2021-11-23 14:15:00,947 INFO L793 eck$LassoCheckResult]: Loop: 3005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3016#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3005#L378-2 [2021-11-23 14:15:00,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:00,948 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 4 times [2021-11-23 14:15:00,948 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:00,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756395895] [2021-11-23 14:15:00,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:00,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:00,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:01,172 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:01,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:01,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756395895] [2021-11-23 14:15:01,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [756395895] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:01,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [746369007] [2021-11-23 14:15:01,173 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:15:01,173 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:01,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:01,178 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:01,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-23 14:15:01,240 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:15:01,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:01,241 INFO L263 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-23 14:15:01,243 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:01,379 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:01,519 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:01,519 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:15:01,720 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:15:01,723 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:01,723 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:01,909 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-11-23 14:15:01,912 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 36 [2021-11-23 14:15:01,975 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:01,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [746369007] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:01,976 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:01,976 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2021-11-23 14:15:01,976 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185269437] [2021-11-23 14:15:01,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:01,976 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:01,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:01,977 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2021-11-23 14:15:01,977 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:01,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157945125] [2021-11-23 14:15:01,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:01,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:01,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:01,981 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:01,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:01,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:02,048 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:02,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-23 14:15:02,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2021-11-23 14:15:02,050 INFO L87 Difference]: Start difference. First operand 27 states and 34 transitions. cyclomatic complexity: 10 Second operand has 27 states, 26 states have (on average 2.0) internal successors, (52), 27 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:02,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:02,464 INFO L93 Difference]: Finished difference Result 31 states and 38 transitions. [2021-11-23 14:15:02,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-23 14:15:02,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 38 transitions. [2021-11-23 14:15:02,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:02,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 30 states and 37 transitions. [2021-11-23 14:15:02,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-23 14:15:02,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-23 14:15:02,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2021-11-23 14:15:02,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:02,466 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 37 transitions. [2021-11-23 14:15:02,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2021-11-23 14:15:02,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2021-11-23 14:15:02,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.2413793103448276) internal successors, (36), 28 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:02,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 36 transitions. [2021-11-23 14:15:02,468 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 36 transitions. [2021-11-23 14:15:02,469 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 36 transitions. [2021-11-23 14:15:02,469 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-23 14:15:02,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 36 transitions. [2021-11-23 14:15:02,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:02,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:02,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:02,470 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:02,470 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:02,470 INFO L791 eck$LassoCheckResult]: Stem: 3241#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3250#L367 assume !(main_~length~0#1 < 1); 3239#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3240#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3243#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3251#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3254#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3252#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3253#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3264#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3263#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3262#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3261#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3260#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3258#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3259#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3257#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3244#L370-4 main_~j~0#1 := 0; 3245#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3248#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3267#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3255#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3256#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3246#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3247#L378-2 [2021-11-23 14:15:02,471 INFO L793 eck$LassoCheckResult]: Loop: 3247#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3266#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3247#L378-2 [2021-11-23 14:15:02,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:02,471 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 5 times [2021-11-23 14:15:02,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:02,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915734277] [2021-11-23 14:15:02,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:02,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:02,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:02,731 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:02,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:02,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915734277] [2021-11-23 14:15:02,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915734277] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:02,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1019016682] [2021-11-23 14:15:02,732 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:15:02,732 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:02,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:02,734 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:02,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-23 14:15:02,814 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2021-11-23 14:15:02,815 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:02,816 INFO L263 TraceCheckSpWp]: Trace formula consists of 117 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-23 14:15:02,818 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:02,893 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-23 14:15:03,156 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:03,160 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:03,160 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:03,322 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:03,326 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:03,397 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1019016682] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:03,397 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:03,397 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 21 [2021-11-23 14:15:03,397 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93427980] [2021-11-23 14:15:03,398 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:03,398 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:03,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:03,399 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2021-11-23 14:15:03,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:03,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289209714] [2021-11-23 14:15:03,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:03,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:03,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:03,403 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:03,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:03,407 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:03,468 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:03,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-23 14:15:03,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=395, Unknown=0, NotChecked=0, Total=462 [2021-11-23 14:15:03,470 INFO L87 Difference]: Start difference. First operand 29 states and 36 transitions. cyclomatic complexity: 10 Second operand has 22 states, 21 states have (on average 2.0476190476190474) internal successors, (43), 22 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:03,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:03,778 INFO L93 Difference]: Finished difference Result 49 states and 61 transitions. [2021-11-23 14:15:03,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-23 14:15:03,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 61 transitions. [2021-11-23 14:15:03,780 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:15:03,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 48 states and 60 transitions. [2021-11-23 14:15:03,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-23 14:15:03,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-23 14:15:03,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 60 transitions. [2021-11-23 14:15:03,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:03,781 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 60 transitions. [2021-11-23 14:15:03,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 60 transitions. [2021-11-23 14:15:03,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 37. [2021-11-23 14:15:03,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2702702702702702) internal successors, (47), 36 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:03,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 47 transitions. [2021-11-23 14:15:03,784 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 47 transitions. [2021-11-23 14:15:03,784 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 47 transitions. [2021-11-23 14:15:03,784 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-23 14:15:03,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 47 transitions. [2021-11-23 14:15:03,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:03,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:03,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:03,785 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:03,786 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:03,786 INFO L791 eck$LassoCheckResult]: Stem: 3500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3511#L367 assume !(main_~length~0#1 < 1); 3502#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3503#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3512#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3518#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3525#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3529#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3528#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3527#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3513#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3514#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3515#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3520#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3505#L370-4 main_~j~0#1 := 0; 3506#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3532#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3509#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3510#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3531#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3523#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3522#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3507#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3508#L378-2 [2021-11-23 14:15:03,786 INFO L793 eck$LassoCheckResult]: Loop: 3508#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3524#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3508#L378-2 [2021-11-23 14:15:03,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:03,786 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 6 times [2021-11-23 14:15:03,787 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:03,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493096483] [2021-11-23 14:15:03,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:03,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:03,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:04,111 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:04,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:04,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493096483] [2021-11-23 14:15:04,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493096483] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:04,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1483398869] [2021-11-23 14:15:04,113 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:15:04,113 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:04,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:04,126 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:04,128 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-23 14:15:04,186 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2021-11-23 14:15:04,186 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:04,187 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-23 14:15:04,188 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:04,480 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:04,480 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:04,645 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:04,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1483398869] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:04,646 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:04,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 30 [2021-11-23 14:15:04,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58222980] [2021-11-23 14:15:04,646 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:04,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:04,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:04,647 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2021-11-23 14:15:04,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:04,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960206769] [2021-11-23 14:15:04,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:04,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:04,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:04,650 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:04,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:04,654 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:04,713 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:04,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-23 14:15:04,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=702, Unknown=0, NotChecked=0, Total=870 [2021-11-23 14:15:04,715 INFO L87 Difference]: Start difference. First operand 37 states and 47 transitions. cyclomatic complexity: 14 Second operand has 30 states, 30 states have (on average 2.1333333333333333) internal successors, (64), 30 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:05,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:05,087 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2021-11-23 14:15:05,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-23 14:15:05,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 63 transitions. [2021-11-23 14:15:05,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:05,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 42 states and 53 transitions. [2021-11-23 14:15:05,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:15:05,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:15:05,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 53 transitions. [2021-11-23 14:15:05,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:05,090 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2021-11-23 14:15:05,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 53 transitions. [2021-11-23 14:15:05,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2021-11-23 14:15:05,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2564102564102564) internal successors, (49), 38 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:05,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2021-11-23 14:15:05,093 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-11-23 14:15:05,093 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-11-23 14:15:05,093 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-23 14:15:05,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 49 transitions. [2021-11-23 14:15:05,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:05,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:05,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:05,094 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:05,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:05,095 INFO L791 eck$LassoCheckResult]: Stem: 3802#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3813#L367 assume !(main_~length~0#1 < 1); 3804#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3805#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3806#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3814#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3819#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3815#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3840#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3839#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3838#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3837#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3836#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3835#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3833#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3826#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3832#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3829#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3828#L370-4 main_~j~0#1 := 0; 3817#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3809#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3810#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3821#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3807#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3808#L378-2 [2021-11-23 14:15:05,095 INFO L793 eck$LassoCheckResult]: Loop: 3808#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3822#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3808#L378-2 [2021-11-23 14:15:05,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:05,095 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 7 times [2021-11-23 14:15:05,096 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:05,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332002007] [2021-11-23 14:15:05,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:05,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:05,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:05,373 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:05,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:05,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332002007] [2021-11-23 14:15:05,374 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332002007] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:05,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [865062133] [2021-11-23 14:15:05,374 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:15:05,374 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:05,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:05,378 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:05,401 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-23 14:15:05,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:05,444 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-23 14:15:05,446 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:05,666 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:05,797 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:15:05,798 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:05,830 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:05,830 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:15:06,318 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:15:06,319 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:15:06,323 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:06,324 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:07,417 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:07,422 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:07,507 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 1 proven. 45 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:15:07,508 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [865062133] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:07,508 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:07,508 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 13] total 30 [2021-11-23 14:15:07,508 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314150180] [2021-11-23 14:15:07,508 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:07,509 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:07,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:07,509 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2021-11-23 14:15:07,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:07,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497402372] [2021-11-23 14:15:07,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:07,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:07,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:07,514 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:07,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:07,517 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:07,564 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:07,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-23 14:15:07,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=799, Unknown=0, NotChecked=0, Total=930 [2021-11-23 14:15:07,566 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.1) internal successors, (63), 31 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:07,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:07,883 INFO L93 Difference]: Finished difference Result 70 states and 86 transitions. [2021-11-23 14:15:07,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-23 14:15:07,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 86 transitions. [2021-11-23 14:15:07,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:07,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 69 states and 84 transitions. [2021-11-23 14:15:07,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-23 14:15:07,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-23 14:15:07,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 84 transitions. [2021-11-23 14:15:07,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:07,887 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 84 transitions. [2021-11-23 14:15:07,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 84 transitions. [2021-11-23 14:15:07,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 43. [2021-11-23 14:15:07,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.302325581395349) internal successors, (56), 42 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:07,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 56 transitions. [2021-11-23 14:15:07,890 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 56 transitions. [2021-11-23 14:15:07,890 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 56 transitions. [2021-11-23 14:15:07,890 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-23 14:15:07,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 56 transitions. [2021-11-23 14:15:07,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:07,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:07,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:07,918 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:07,918 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:07,918 INFO L791 eck$LassoCheckResult]: Stem: 4125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4136#L367 assume !(main_~length~0#1 < 1); 4127#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4128#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4167#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4139#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4145#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4166#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4165#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4164#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4163#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4161#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4160#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4159#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4158#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4134#L370-4 main_~j~0#1 := 0; 4135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4141#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4151#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4147#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4146#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4130#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4131#L378-2 [2021-11-23 14:15:07,919 INFO L793 eck$LassoCheckResult]: Loop: 4131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4148#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4131#L378-2 [2021-11-23 14:15:07,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:07,919 INFO L85 PathProgramCache]: Analyzing trace with hash -807596427, now seen corresponding path program 8 times [2021-11-23 14:15:07,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:07,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870824939] [2021-11-23 14:15:07,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:07,920 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:07,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:08,142 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:08,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:08,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870824939] [2021-11-23 14:15:08,143 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870824939] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:08,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1549504149] [2021-11-23 14:15:08,143 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:15:08,143 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:08,143 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:08,145 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:08,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-23 14:15:08,211 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:15:08,212 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:08,213 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-23 14:15:08,215 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:08,290 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:15:08,468 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:08,490 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:08,490 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:08,688 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-11-23 14:15:08,691 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-23 14:15:08,778 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:08,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1549504149] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:08,779 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:08,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 25 [2021-11-23 14:15:08,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814855652] [2021-11-23 14:15:08,779 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:08,780 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:08,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:08,780 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2021-11-23 14:15:08,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:08,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572749627] [2021-11-23 14:15:08,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:08,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:08,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:08,783 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:08,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:08,786 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:08,845 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:08,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-23 14:15:08,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=573, Unknown=0, NotChecked=0, Total=650 [2021-11-23 14:15:08,847 INFO L87 Difference]: Start difference. First operand 43 states and 56 transitions. cyclomatic complexity: 17 Second operand has 26 states, 25 states have (on average 2.24) internal successors, (56), 26 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:09,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:09,308 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2021-11-23 14:15:09,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-23 14:15:09,309 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 76 transitions. [2021-11-23 14:15:09,310 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:15:09,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 60 states and 75 transitions. [2021-11-23 14:15:09,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-23 14:15:09,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-23 14:15:09,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2021-11-23 14:15:09,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:09,312 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 75 transitions. [2021-11-23 14:15:09,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2021-11-23 14:15:09,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 47. [2021-11-23 14:15:09,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2765957446808511) internal successors, (60), 46 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:09,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 60 transitions. [2021-11-23 14:15:09,314 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 60 transitions. [2021-11-23 14:15:09,314 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 60 transitions. [2021-11-23 14:15:09,314 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-23 14:15:09,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 60 transitions. [2021-11-23 14:15:09,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:09,315 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:09,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:09,316 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:09,316 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:09,316 INFO L791 eck$LassoCheckResult]: Stem: 4446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4457#L367 assume !(main_~length~0#1 < 1); 4448#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4449#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4450#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4458#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4464#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4460#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4488#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4487#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4485#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4483#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4482#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4465#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4451#L370-4 main_~j~0#1 := 0; 4452#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4455#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4456#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4470#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4467#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4466#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4453#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4454#L378-2 [2021-11-23 14:15:09,316 INFO L793 eck$LassoCheckResult]: Loop: 4454#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4468#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4454#L378-2 [2021-11-23 14:15:09,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:09,317 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 7 times [2021-11-23 14:15:09,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:09,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855485871] [2021-11-23 14:15:09,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:09,317 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:09,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:09,576 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:09,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:09,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855485871] [2021-11-23 14:15:09,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855485871] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:09,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1845990157] [2021-11-23 14:15:09,577 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:15:09,577 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:09,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:09,579 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:09,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-23 14:15:09,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:09,642 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-23 14:15:09,643 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:09,851 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-23 14:15:10,170 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:15:10,173 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:10,173 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:10,301 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:10,305 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:10,387 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:10,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1845990157] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:10,387 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:10,387 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 14] total 30 [2021-11-23 14:15:10,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554921351] [2021-11-23 14:15:10,388 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:10,389 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:10,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:10,389 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2021-11-23 14:15:10,389 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:10,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853953910] [2021-11-23 14:15:10,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:10,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:10,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:10,392 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:10,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:10,400 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:10,460 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:10,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-23 14:15:10,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=821, Unknown=0, NotChecked=0, Total=930 [2021-11-23 14:15:10,461 INFO L87 Difference]: Start difference. First operand 47 states and 60 transitions. cyclomatic complexity: 17 Second operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 31 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:11,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:11,100 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2021-11-23 14:15:11,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-23 14:15:11,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96 states and 120 transitions. [2021-11-23 14:15:11,102 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2021-11-23 14:15:11,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96 states to 95 states and 119 transitions. [2021-11-23 14:15:11,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2021-11-23 14:15:11,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2021-11-23 14:15:11,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 119 transitions. [2021-11-23 14:15:11,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:11,105 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 119 transitions. [2021-11-23 14:15:11,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 119 transitions. [2021-11-23 14:15:11,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 72. [2021-11-23 14:15:11,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.3055555555555556) internal successors, (94), 71 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:11,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 94 transitions. [2021-11-23 14:15:11,108 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 94 transitions. [2021-11-23 14:15:11,109 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 94 transitions. [2021-11-23 14:15:11,109 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-23 14:15:11,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 94 transitions. [2021-11-23 14:15:11,110 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2021-11-23 14:15:11,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:11,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:11,111 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:11,111 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-23 14:15:11,111 INFO L791 eck$LassoCheckResult]: Stem: 4817#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4828#L367 assume !(main_~length~0#1 < 1); 4819#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4820#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4821#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4829#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4841#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4842#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4848#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4847#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4845#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4830#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4831#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4868#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4867#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4866#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4864#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4863#L370-4 main_~j~0#1 := 0; 4862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4857#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4849#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4851#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4882#L378-2 [2021-11-23 14:15:11,111 INFO L793 eck$LassoCheckResult]: Loop: 4882#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4884#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4883#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4881#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4882#L378-2 [2021-11-23 14:15:11,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:11,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1236423398, now seen corresponding path program 9 times [2021-11-23 14:15:11,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:11,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402549280] [2021-11-23 14:15:11,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:11,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:11,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:11,400 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:11,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:11,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402549280] [2021-11-23 14:15:11,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402549280] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:11,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [147383449] [2021-11-23 14:15:11,401 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:15:11,401 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:11,401 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:11,407 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:11,434 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-23 14:15:11,496 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2021-11-23 14:15:11,497 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:11,499 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-23 14:15:11,500 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:11,562 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:11,664 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:11,665 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:11,688 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:11,688 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:11,803 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:15:11,804 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:15:12,635 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:15:12,636 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:15:12,640 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:12,640 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:27,161 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2021-11-23 14:15:27,165 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 83 [2021-11-23 14:15:27,270 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:27,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [147383449] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:27,271 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:27,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 28 [2021-11-23 14:15:27,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011430319] [2021-11-23 14:15:27,272 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:27,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:27,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:27,273 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 1 times [2021-11-23 14:15:27,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:27,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798790862] [2021-11-23 14:15:27,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:27,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:27,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:27,279 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:27,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:27,286 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:27,404 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:27,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-23 14:15:27,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=680, Unknown=18, NotChecked=0, Total=812 [2021-11-23 14:15:27,405 INFO L87 Difference]: Start difference. First operand 72 states and 94 transitions. cyclomatic complexity: 29 Second operand has 29 states, 28 states have (on average 2.0714285714285716) internal successors, (58), 29 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:29,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:29,602 INFO L93 Difference]: Finished difference Result 120 states and 146 transitions. [2021-11-23 14:15:29,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-23 14:15:29,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 146 transitions. [2021-11-23 14:15:29,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:29,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 118 states and 142 transitions. [2021-11-23 14:15:29,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-23 14:15:29,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-23 14:15:29,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 142 transitions. [2021-11-23 14:15:29,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:29,606 INFO L681 BuchiCegarLoop]: Abstraction has 118 states and 142 transitions. [2021-11-23 14:15:29,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 142 transitions. [2021-11-23 14:15:29,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 42. [2021-11-23 14:15:29,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2619047619047619) internal successors, (53), 41 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:29,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 53 transitions. [2021-11-23 14:15:29,609 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2021-11-23 14:15:29,609 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2021-11-23 14:15:29,609 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-23 14:15:29,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 53 transitions. [2021-11-23 14:15:29,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:29,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:29,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:29,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:29,611 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:29,611 INFO L791 eck$LassoCheckResult]: Stem: 5238#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5249#L367 assume !(main_~length~0#1 < 1); 5240#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5241#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5242#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5250#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5251#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5252#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5257#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5258#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5278#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5276#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5275#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5274#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5272#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5265#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5243#L370-4 main_~j~0#1 := 0; 5244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5247#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5248#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5256#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5267#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5263#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5262#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5261#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5245#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5246#L378-2 [2021-11-23 14:15:29,611 INFO L793 eck$LassoCheckResult]: Loop: 5246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5259#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5246#L378-2 [2021-11-23 14:15:29,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:29,612 INFO L85 PathProgramCache]: Analyzing trace with hash 267849144, now seen corresponding path program 8 times [2021-11-23 14:15:29,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:29,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335572232] [2021-11-23 14:15:29,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:29,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:29,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:29,926 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:29,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:29,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335572232] [2021-11-23 14:15:29,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335572232] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:29,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1021019698] [2021-11-23 14:15:29,927 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:15:29,927 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:29,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:29,934 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:29,936 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-23 14:15:29,986 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:15:29,986 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:29,987 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-23 14:15:29,989 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:30,340 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:30,341 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:30,533 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:30,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1021019698] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:30,534 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:30,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15] total 35 [2021-11-23 14:15:30,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924925150] [2021-11-23 14:15:30,534 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:30,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:30,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:30,535 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2021-11-23 14:15:30,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:30,535 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306099950] [2021-11-23 14:15:30,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:30,536 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:30,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:30,546 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:30,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:30,563 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:30,630 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:30,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-23 14:15:30,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=967, Unknown=0, NotChecked=0, Total=1190 [2021-11-23 14:15:30,632 INFO L87 Difference]: Start difference. First operand 42 states and 53 transitions. cyclomatic complexity: 15 Second operand has 35 states, 35 states have (on average 2.1714285714285713) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:31,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:31,026 INFO L93 Difference]: Finished difference Result 59 states and 71 transitions. [2021-11-23 14:15:31,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-23 14:15:31,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 71 transitions. [2021-11-23 14:15:31,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:31,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 47 states and 59 transitions. [2021-11-23 14:15:31,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:15:31,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:15:31,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2021-11-23 14:15:31,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:31,029 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2021-11-23 14:15:31,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2021-11-23 14:15:31,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 44. [2021-11-23 14:15:31,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.25) internal successors, (55), 43 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:31,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 55 transitions. [2021-11-23 14:15:31,032 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 55 transitions. [2021-11-23 14:15:31,032 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 55 transitions. [2021-11-23 14:15:31,032 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-23 14:15:31,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 55 transitions. [2021-11-23 14:15:31,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:31,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:31,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:31,034 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:31,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:31,034 INFO L791 eck$LassoCheckResult]: Stem: 5589#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5600#L367 assume !(main_~length~0#1 < 1); 5591#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5592#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5593#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5601#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5606#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5630#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5629#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5628#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5627#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5624#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5623#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5615#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5618#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5617#L370-4 main_~j~0#1 := 0; 5604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5613#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5612#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5611#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5594#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5595#L378-2 [2021-11-23 14:15:31,034 INFO L793 eck$LassoCheckResult]: Loop: 5595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5609#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5595#L378-2 [2021-11-23 14:15:31,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:31,035 INFO L85 PathProgramCache]: Analyzing trace with hash -2080282897, now seen corresponding path program 10 times [2021-11-23 14:15:31,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:31,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117468657] [2021-11-23 14:15:31,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:31,036 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:31,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:31,312 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:31,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:31,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117468657] [2021-11-23 14:15:31,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117468657] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:31,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1680233052] [2021-11-23 14:15:31,313 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:15:31,313 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:31,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:31,314 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:31,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-23 14:15:31,371 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:15:31,371 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:31,372 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-23 14:15:31,373 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:31,593 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:31,706 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:15:31,707 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:31,733 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:31,733 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:15:32,220 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:15:32,221 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:15:32,225 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:32,225 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:33,119 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:33,123 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:33,211 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 1 proven. 69 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:15:33,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1680233052] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:33,212 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:33,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 15] total 34 [2021-11-23 14:15:33,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626365018] [2021-11-23 14:15:33,212 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:33,213 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:33,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:33,213 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2021-11-23 14:15:33,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:33,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72932433] [2021-11-23 14:15:33,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:33,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:33,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:33,217 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:33,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:33,219 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:33,277 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:33,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-23 14:15:33,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=1043, Unknown=0, NotChecked=0, Total=1190 [2021-11-23 14:15:33,279 INFO L87 Difference]: Start difference. First operand 44 states and 55 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.1470588235294117) internal successors, (73), 35 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:33,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:33,669 INFO L93 Difference]: Finished difference Result 85 states and 103 transitions. [2021-11-23 14:15:33,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-23 14:15:33,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 103 transitions. [2021-11-23 14:15:33,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:33,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 101 transitions. [2021-11-23 14:15:33,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:15:33,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:15:33,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 101 transitions. [2021-11-23 14:15:33,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:33,673 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 101 transitions. [2021-11-23 14:15:33,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 101 transitions. [2021-11-23 14:15:33,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 51. [2021-11-23 14:15:33,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.3137254901960784) internal successors, (67), 50 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:33,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 67 transitions. [2021-11-23 14:15:33,676 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 67 transitions. [2021-11-23 14:15:33,676 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 67 transitions. [2021-11-23 14:15:33,676 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-23 14:15:33,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 67 transitions. [2021-11-23 14:15:33,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:33,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:33,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:33,677 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:33,677 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:33,677 INFO L791 eck$LassoCheckResult]: Stem: 5964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5975#L367 assume !(main_~length~0#1 < 1); 5966#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5967#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5976#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5977#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5978#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5979#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6013#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6012#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6010#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6009#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6008#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6007#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6006#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6004#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6003#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5982#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5969#L370-4 main_~j~0#1 := 0; 5970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5973#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5980#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5990#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5989#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5988#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5987#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5984#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5971#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5972#L378-2 [2021-11-23 14:15:33,677 INFO L793 eck$LassoCheckResult]: Loop: 5972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5985#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5972#L378-2 [2021-11-23 14:15:33,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:33,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1992068108, now seen corresponding path program 11 times [2021-11-23 14:15:33,678 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:33,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320563490] [2021-11-23 14:15:33,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:33,678 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:33,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:33,925 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:33,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:33,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320563490] [2021-11-23 14:15:33,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320563490] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:33,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1657395499] [2021-11-23 14:15:33,926 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:15:33,926 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:33,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:33,929 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:33,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-23 14:15:34,002 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2021-11-23 14:15:34,003 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:34,005 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-23 14:15:34,006 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:34,101 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:15:34,334 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:34,354 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:34,355 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:34,672 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2021-11-23 14:15:34,675 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 36 [2021-11-23 14:15:34,797 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:34,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1657395499] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:34,798 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:34,798 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 31 [2021-11-23 14:15:34,798 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480564146] [2021-11-23 14:15:34,799 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:34,799 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:34,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:34,800 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2021-11-23 14:15:34,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:34,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864307573] [2021-11-23 14:15:34,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:34,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:34,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:34,803 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:34,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:34,806 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:34,865 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:34,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-23 14:15:34,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=892, Unknown=0, NotChecked=0, Total=992 [2021-11-23 14:15:34,867 INFO L87 Difference]: Start difference. First operand 51 states and 67 transitions. cyclomatic complexity: 21 Second operand has 32 states, 31 states have (on average 2.161290322580645) internal successors, (67), 32 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:35,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:35,521 INFO L93 Difference]: Finished difference Result 67 states and 84 transitions. [2021-11-23 14:15:35,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-23 14:15:35,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 84 transitions. [2021-11-23 14:15:35,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:35,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 66 states and 83 transitions. [2021-11-23 14:15:35,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-23 14:15:35,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-23 14:15:35,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 83 transitions. [2021-11-23 14:15:35,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:35,524 INFO L681 BuchiCegarLoop]: Abstraction has 66 states and 83 transitions. [2021-11-23 14:15:35,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 83 transitions. [2021-11-23 14:15:35,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 57. [2021-11-23 14:15:35,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2982456140350878) internal successors, (74), 56 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:35,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 74 transitions. [2021-11-23 14:15:35,526 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 74 transitions. [2021-11-23 14:15:35,526 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 74 transitions. [2021-11-23 14:15:35,526 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-23 14:15:35,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 74 transitions. [2021-11-23 14:15:35,527 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:35,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:35,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:35,527 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:35,527 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:35,528 INFO L791 eck$LassoCheckResult]: Stem: 6335#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6346#L367 assume !(main_~length~0#1 < 1); 6337#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6338#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6347#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6350#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6349#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6389#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6386#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6383#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6377#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6371#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6340#L370-4 main_~j~0#1 := 0; 6341#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6344#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6359#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6358#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6356#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6355#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6353#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6342#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6343#L378-2 [2021-11-23 14:15:35,528 INFO L793 eck$LassoCheckResult]: Loop: 6343#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6354#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6343#L378-2 [2021-11-23 14:15:35,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:35,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1281830834, now seen corresponding path program 9 times [2021-11-23 14:15:35,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:35,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802678339] [2021-11-23 14:15:35,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:35,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:35,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:35,875 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:35,876 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:35,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802678339] [2021-11-23 14:15:35,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802678339] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:35,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1859049672] [2021-11-23 14:15:35,876 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:15:35,876 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:35,877 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:35,882 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:35,884 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-23 14:15:35,981 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2021-11-23 14:15:35,982 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:35,984 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-23 14:15:35,985 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:36,185 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:36,912 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-23 14:15:36,912 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 21 [2021-11-23 14:15:36,917 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:36,917 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:38,070 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2021-11-23 14:15:38,073 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 43 [2021-11-23 14:15:38,120 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:38,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1859049672] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:38,120 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:38,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2021-11-23 14:15:38,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235045932] [2021-11-23 14:15:38,120 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:38,121 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:38,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:38,121 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2021-11-23 14:15:38,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:38,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073812439] [2021-11-23 14:15:38,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:38,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:38,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:38,123 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:38,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:38,125 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:38,172 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:38,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-23 14:15:38,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=1653, Unknown=1, NotChecked=0, Total=1892 [2021-11-23 14:15:38,174 INFO L87 Difference]: Start difference. First operand 57 states and 74 transitions. cyclomatic complexity: 22 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:39,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:39,250 INFO L93 Difference]: Finished difference Result 80 states and 98 transitions. [2021-11-23 14:15:39,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-23 14:15:39,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 98 transitions. [2021-11-23 14:15:39,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:39,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 53 states and 68 transitions. [2021-11-23 14:15:39,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:15:39,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:15:39,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 68 transitions. [2021-11-23 14:15:39,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:39,253 INFO L681 BuchiCegarLoop]: Abstraction has 53 states and 68 transitions. [2021-11-23 14:15:39,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 68 transitions. [2021-11-23 14:15:39,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2021-11-23 14:15:39,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.2830188679245282) internal successors, (68), 52 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:39,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 68 transitions. [2021-11-23 14:15:39,255 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 68 transitions. [2021-11-23 14:15:39,256 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 68 transitions. [2021-11-23 14:15:39,256 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-23 14:15:39,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 68 transitions. [2021-11-23 14:15:39,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:39,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:39,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:39,257 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:39,257 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:39,258 INFO L791 eck$LassoCheckResult]: Stem: 6795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6804#L367 assume !(main_~length~0#1 < 1); 6793#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6794#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6797#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6805#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6810#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6806#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6807#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6840#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6837#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6832#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6826#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6822#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6821#L370-4 main_~j~0#1 := 0; 6808#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6800#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6817#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6816#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6815#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6814#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6812#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6798#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6799#L378-2 [2021-11-23 14:15:39,258 INFO L793 eck$LassoCheckResult]: Loop: 6799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6813#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6799#L378-2 [2021-11-23 14:15:39,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:39,259 INFO L85 PathProgramCache]: Analyzing trace with hash -134390927, now seen corresponding path program 12 times [2021-11-23 14:15:39,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:39,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523294915] [2021-11-23 14:15:39,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:39,259 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:39,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:39,605 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:39,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:39,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523294915] [2021-11-23 14:15:39,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523294915] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:39,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1447143323] [2021-11-23 14:15:39,606 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:15:39,606 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:39,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:39,608 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:39,609 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-23 14:15:39,686 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-11-23 14:15:39,686 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:39,688 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-23 14:15:39,689 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:39,758 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-23 14:15:39,848 INFO L354 Elim1Store]: treesize reduction 25, result has 37.5 percent of original size [2021-11-23 14:15:39,848 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 30 [2021-11-23 14:15:39,897 INFO L354 Elim1Store]: treesize reduction 25, result has 37.5 percent of original size [2021-11-23 14:15:39,897 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 36 [2021-11-23 14:15:40,025 INFO L354 Elim1Store]: treesize reduction 56, result has 44.6 percent of original size [2021-11-23 14:15:40,025 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 47 treesize of output 73 [2021-11-23 14:15:40,407 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:40,410 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 2 proven. 86 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-11-23 14:15:40,410 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:43,978 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:43,980 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:44,064 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 83 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-11-23 14:15:44,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1447143323] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:44,064 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:44,064 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 15] total 27 [2021-11-23 14:15:44,065 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109491655] [2021-11-23 14:15:44,065 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:44,065 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:44,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:44,066 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2021-11-23 14:15:44,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:44,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933390015] [2021-11-23 14:15:44,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:44,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:44,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:44,069 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:44,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:44,072 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:44,133 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:44,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-23 14:15:44,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=658, Unknown=0, NotChecked=0, Total=756 [2021-11-23 14:15:44,134 INFO L87 Difference]: Start difference. First operand 53 states and 68 transitions. cyclomatic complexity: 20 Second operand has 28 states, 27 states have (on average 2.2222222222222223) internal successors, (60), 28 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:44,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:44,692 INFO L93 Difference]: Finished difference Result 74 states and 93 transitions. [2021-11-23 14:15:44,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-23 14:15:44,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74 states and 93 transitions. [2021-11-23 14:15:44,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:44,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74 states to 73 states and 92 transitions. [2021-11-23 14:15:44,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-23 14:15:44,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-23 14:15:44,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 92 transitions. [2021-11-23 14:15:44,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:44,695 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 92 transitions. [2021-11-23 14:15:44,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 92 transitions. [2021-11-23 14:15:44,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 42. [2021-11-23 14:15:44,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 41 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:44,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 52 transitions. [2021-11-23 14:15:44,698 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 52 transitions. [2021-11-23 14:15:44,698 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 52 transitions. [2021-11-23 14:15:44,698 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-23 14:15:44,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 52 transitions. [2021-11-23 14:15:44,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:44,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:44,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:44,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:44,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:44,706 INFO L791 eck$LassoCheckResult]: Stem: 7191#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7202#L367 assume !(main_~length~0#1 < 1); 7193#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7194#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7203#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7206#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7204#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7205#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7231#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7230#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7227#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7224#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7221#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7219#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7217#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7218#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7216#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7200#L370-4 main_~j~0#1 := 0; 7201#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7198#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7207#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7215#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7214#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7213#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7212#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7211#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7209#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7208#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7196#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7197#L378-2 [2021-11-23 14:15:44,706 INFO L793 eck$LassoCheckResult]: Loop: 7197#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7210#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7197#L378-2 [2021-11-23 14:15:44,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:44,706 INFO L85 PathProgramCache]: Analyzing trace with hash -1989602440, now seen corresponding path program 10 times [2021-11-23 14:15:44,707 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:44,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469100565] [2021-11-23 14:15:44,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:44,707 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:44,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:45,048 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:45,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:45,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469100565] [2021-11-23 14:15:45,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469100565] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:45,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [52906014] [2021-11-23 14:15:45,049 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:15:45,049 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:45,049 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:45,051 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:45,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-23 14:15:45,133 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:15:45,133 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:45,135 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-23 14:15:45,137 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:45,458 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:45,643 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:45,644 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:15:46,022 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:15:46,025 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:46,025 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:46,267 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-11-23 14:15:46,270 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 36 [2021-11-23 14:15:46,360 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:46,360 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [52906014] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:46,361 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:46,361 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 18] total 38 [2021-11-23 14:15:46,361 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378465205] [2021-11-23 14:15:46,361 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:46,362 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:46,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:46,362 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2021-11-23 14:15:46,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:46,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887405427] [2021-11-23 14:15:46,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:46,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:46,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:46,366 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:46,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:46,369 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:46,427 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:46,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-23 14:15:46,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=1339, Unknown=0, NotChecked=0, Total=1482 [2021-11-23 14:15:46,429 INFO L87 Difference]: Start difference. First operand 42 states and 52 transitions. cyclomatic complexity: 13 Second operand has 39 states, 38 states have (on average 2.1578947368421053) internal successors, (82), 39 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:47,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:47,138 INFO L93 Difference]: Finished difference Result 46 states and 56 transitions. [2021-11-23 14:15:47,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-23 14:15:47,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46 states and 56 transitions. [2021-11-23 14:15:47,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:47,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46 states to 45 states and 55 transitions. [2021-11-23 14:15:47,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-23 14:15:47,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-23 14:15:47,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 55 transitions. [2021-11-23 14:15:47,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:47,141 INFO L681 BuchiCegarLoop]: Abstraction has 45 states and 55 transitions. [2021-11-23 14:15:47,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 55 transitions. [2021-11-23 14:15:47,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 44. [2021-11-23 14:15:47,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.2272727272727273) internal successors, (54), 43 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:47,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 54 transitions. [2021-11-23 14:15:47,143 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 54 transitions. [2021-11-23 14:15:47,143 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 54 transitions. [2021-11-23 14:15:47,143 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-23 14:15:47,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 54 transitions. [2021-11-23 14:15:47,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:47,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:47,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:47,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:47,145 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:47,146 INFO L791 eck$LassoCheckResult]: Stem: 7571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7582#L367 assume !(main_~length~0#1 < 1); 7573#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7574#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7575#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7583#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7585#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7605#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7604#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7600#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7597#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7594#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7592#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7590#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7589#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7580#L370-4 main_~j~0#1 := 0; 7581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7586#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7578#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7576#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7577#L378-2 [2021-11-23 14:15:47,146 INFO L793 eck$LassoCheckResult]: Loop: 7577#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7606#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7577#L378-2 [2021-11-23 14:15:47,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:47,146 INFO L85 PathProgramCache]: Analyzing trace with hash -747494851, now seen corresponding path program 11 times [2021-11-23 14:15:47,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:47,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969729790] [2021-11-23 14:15:47,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:47,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:47,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:47,498 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:47,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:47,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969729790] [2021-11-23 14:15:47,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969729790] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:47,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1135845886] [2021-11-23 14:15:47,499 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:15:47,500 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:47,500 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:47,502 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:47,504 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-23 14:15:47,598 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-11-23 14:15:47,598 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:47,601 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-23 14:15:47,602 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:47,704 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-23 14:15:48,061 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:48,063 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:48,063 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:48,251 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:48,253 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:48,369 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:48,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1135845886] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:48,369 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:48,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 30 [2021-11-23 14:15:48,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264819764] [2021-11-23 14:15:48,370 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:48,370 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:48,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:48,371 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2021-11-23 14:15:48,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:48,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623411143] [2021-11-23 14:15:48,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:48,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:48,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:48,374 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:48,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:48,377 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:48,434 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:48,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-23 14:15:48,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=836, Unknown=0, NotChecked=0, Total=930 [2021-11-23 14:15:48,435 INFO L87 Difference]: Start difference. First operand 44 states and 54 transitions. cyclomatic complexity: 13 Second operand has 31 states, 30 states have (on average 2.1333333333333333) internal successors, (64), 31 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:48,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:48,986 INFO L93 Difference]: Finished difference Result 70 states and 85 transitions. [2021-11-23 14:15:48,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-23 14:15:48,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 85 transitions. [2021-11-23 14:15:48,990 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:15:48,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 69 states and 84 transitions. [2021-11-23 14:15:48,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-23 14:15:48,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-23 14:15:48,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 84 transitions. [2021-11-23 14:15:48,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:48,992 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 84 transitions. [2021-11-23 14:15:48,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 84 transitions. [2021-11-23 14:15:48,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 52. [2021-11-23 14:15:48,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.25) internal successors, (65), 51 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:48,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 65 transitions. [2021-11-23 14:15:48,994 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 65 transitions. [2021-11-23 14:15:48,994 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 65 transitions. [2021-11-23 14:15:48,994 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-23 14:15:48,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 65 transitions. [2021-11-23 14:15:48,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:48,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:48,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:48,996 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:48,996 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:48,997 INFO L791 eck$LassoCheckResult]: Stem: 7967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7978#L367 assume !(main_~length~0#1 < 1); 7969#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7970#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7971#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7979#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7984#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7980#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7981#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7985#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7986#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8002#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8001#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8000#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7999#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7998#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7997#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7996#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7995#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7994#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7993#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7992#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7991#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7990#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7989#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7987#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7976#L370-4 main_~j~0#1 := 0; 7977#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8014#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7974#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8013#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8012#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8011#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8010#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8009#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8008#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8007#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8005#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7972#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7973#L378-2 [2021-11-23 14:15:48,997 INFO L793 eck$LassoCheckResult]: Loop: 7973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8003#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7973#L378-2 [2021-11-23 14:15:48,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:48,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1083010110, now seen corresponding path program 12 times [2021-11-23 14:15:48,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:48,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158630776] [2021-11-23 14:15:48,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:48,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:49,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:49,530 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:49,531 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:49,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158630776] [2021-11-23 14:15:49,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158630776] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:49,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1869631085] [2021-11-23 14:15:49,531 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:15:49,531 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:49,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:49,538 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:49,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-23 14:15:49,661 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-11-23 14:15:49,661 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:49,664 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-23 14:15:49,665 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:50,144 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:50,144 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:50,407 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:50,407 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1869631085] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:50,408 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:50,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19] total 45 [2021-11-23 14:15:50,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072868130] [2021-11-23 14:15:50,408 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:50,408 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:50,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:50,409 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2021-11-23 14:15:50,409 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:50,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328046875] [2021-11-23 14:15:50,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:50,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:50,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:50,412 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:50,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:50,415 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:50,465 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:50,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-11-23 14:15:50,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1623, Unknown=0, NotChecked=0, Total=1980 [2021-11-23 14:15:50,466 INFO L87 Difference]: Start difference. First operand 52 states and 65 transitions. cyclomatic complexity: 17 Second operand has 45 states, 45 states have (on average 2.2222222222222223) internal successors, (100), 45 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:50,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:50,954 INFO L93 Difference]: Finished difference Result 73 states and 87 transitions. [2021-11-23 14:15:50,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-23 14:15:50,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 87 transitions. [2021-11-23 14:15:50,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:50,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 57 states and 71 transitions. [2021-11-23 14:15:50,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:15:50,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:15:50,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 71 transitions. [2021-11-23 14:15:50,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:50,957 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 71 transitions. [2021-11-23 14:15:50,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 71 transitions. [2021-11-23 14:15:50,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 54. [2021-11-23 14:15:50,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2407407407407407) internal successors, (67), 53 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:50,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 67 transitions. [2021-11-23 14:15:50,960 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-11-23 14:15:50,960 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-11-23 14:15:50,960 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-23 14:15:50,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 67 transitions. [2021-11-23 14:15:50,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:50,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:50,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:50,962 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:50,962 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:50,962 INFO L791 eck$LassoCheckResult]: Stem: 8416#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8427#L367 assume !(main_~length~0#1 < 1); 8418#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8419#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8420#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8428#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8469#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8429#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8430#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8431#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8433#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8468#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8467#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8466#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8465#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8464#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8463#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8462#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8461#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8459#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8458#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8457#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8456#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8454#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8452#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8434#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8421#L370-4 main_~j~0#1 := 0; 8422#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8432#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8447#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8446#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8445#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8444#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8442#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8440#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8437#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8436#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8423#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8424#L378-2 [2021-11-23 14:15:50,963 INFO L793 eck$LassoCheckResult]: Loop: 8424#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8438#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8424#L378-2 [2021-11-23 14:15:50,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:50,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1277041159, now seen corresponding path program 13 times [2021-11-23 14:15:50,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:50,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719222955] [2021-11-23 14:15:50,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:50,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:50,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:51,383 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:51,384 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:51,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719222955] [2021-11-23 14:15:51,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719222955] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:51,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [125338894] [2021-11-23 14:15:51,384 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:15:51,384 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:51,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:51,390 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:51,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-23 14:15:51,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:51,449 INFO L263 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-23 14:15:51,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:51,766 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:51,899 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:15:51,899 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:51,922 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:51,923 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:15:52,625 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:15:52,626 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:15:52,629 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:52,630 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:53,504 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:53,506 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:53,603 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 1 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:15:53,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [125338894] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:53,604 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:53,604 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 19] total 42 [2021-11-23 14:15:53,604 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271634471] [2021-11-23 14:15:53,604 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:53,605 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:53,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:53,605 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2021-11-23 14:15:53,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:53,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359756642] [2021-11-23 14:15:53,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:53,605 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:53,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:53,608 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:53,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:53,611 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:53,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:53,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-23 14:15:53,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=1627, Unknown=0, NotChecked=0, Total=1806 [2021-11-23 14:15:53,663 INFO L87 Difference]: Start difference. First operand 54 states and 67 transitions. cyclomatic complexity: 17 Second operand has 43 states, 42 states have (on average 2.2142857142857144) internal successors, (93), 43 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:54,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:54,167 INFO L93 Difference]: Finished difference Result 109 states and 129 transitions. [2021-11-23 14:15:54,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-23 14:15:54,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 129 transitions. [2021-11-23 14:15:54,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:54,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 108 states and 127 transitions. [2021-11-23 14:15:54,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:15:54,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:15:54,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 127 transitions. [2021-11-23 14:15:54,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:54,170 INFO L681 BuchiCegarLoop]: Abstraction has 108 states and 127 transitions. [2021-11-23 14:15:54,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 127 transitions. [2021-11-23 14:15:54,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 61. [2021-11-23 14:15:54,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.2950819672131149) internal successors, (79), 60 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:54,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 79 transitions. [2021-11-23 14:15:54,173 INFO L704 BuchiCegarLoop]: Abstraction has 61 states and 79 transitions. [2021-11-23 14:15:54,173 INFO L587 BuchiCegarLoop]: Abstraction has 61 states and 79 transitions. [2021-11-23 14:15:54,174 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-23 14:15:54,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 79 transitions. [2021-11-23 14:15:54,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:54,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:54,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:54,175 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:54,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:54,176 INFO L791 eck$LassoCheckResult]: Stem: 8893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8904#L367 assume !(main_~length~0#1 < 1); 8895#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8896#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8905#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8910#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8952#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8951#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8950#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8949#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8948#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8947#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8946#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8945#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8944#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8943#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8942#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8941#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8940#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8939#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8937#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8931#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8933#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8898#L370-4 main_~j~0#1 := 0; 8899#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8902#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8903#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8909#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8922#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8921#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8920#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8919#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8918#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8917#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8916#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8915#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8912#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8911#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8900#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8901#L378-2 [2021-11-23 14:15:54,176 INFO L793 eck$LassoCheckResult]: Loop: 8901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8913#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8901#L378-2 [2021-11-23 14:15:54,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:54,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1124096126, now seen corresponding path program 14 times [2021-11-23 14:15:54,177 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:54,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786906328] [2021-11-23 14:15:54,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:54,177 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:54,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:54,550 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:54,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:54,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786906328] [2021-11-23 14:15:54,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786906328] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:54,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1598291652] [2021-11-23 14:15:54,551 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:15:54,551 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:54,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:54,553 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:54,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-23 14:15:54,623 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:15:54,623 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:54,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-23 14:15:54,627 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:54,753 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:15:55,117 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:15:55,144 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:55,144 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:55,484 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-11-23 14:15:55,487 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-23 14:15:55,637 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:55,637 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1598291652] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:55,637 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:55,637 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19] total 37 [2021-11-23 14:15:55,637 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108403198] [2021-11-23 14:15:55,638 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:55,638 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:55,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:55,639 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2021-11-23 14:15:55,639 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:55,639 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168240368] [2021-11-23 14:15:55,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:55,639 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:55,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:55,642 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:55,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:55,644 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:55,729 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:55,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-23 14:15:55,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=1290, Unknown=0, NotChecked=0, Total=1406 [2021-11-23 14:15:55,731 INFO L87 Difference]: Start difference. First operand 61 states and 79 transitions. cyclomatic complexity: 23 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:56,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:56,469 INFO L93 Difference]: Finished difference Result 86 states and 107 transitions. [2021-11-23 14:15:56,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-23 14:15:56,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 107 transitions. [2021-11-23 14:15:56,475 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:15:56,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 85 states and 106 transitions. [2021-11-23 14:15:56,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-23 14:15:56,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-23 14:15:56,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 106 transitions. [2021-11-23 14:15:56,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:56,477 INFO L681 BuchiCegarLoop]: Abstraction has 85 states and 106 transitions. [2021-11-23 14:15:56,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 106 transitions. [2021-11-23 14:15:56,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 67. [2021-11-23 14:15:56,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2835820895522387) internal successors, (86), 66 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:56,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 86 transitions. [2021-11-23 14:15:56,480 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 86 transitions. [2021-11-23 14:15:56,480 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 86 transitions. [2021-11-23 14:15:56,480 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-23 14:15:56,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 86 transitions. [2021-11-23 14:15:56,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:15:56,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:56,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:56,483 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:56,483 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:15:56,483 INFO L791 eck$LassoCheckResult]: Stem: 9359#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9370#L367 assume !(main_~length~0#1 < 1); 9361#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9362#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9371#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9376#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9372#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9373#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9425#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9424#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9423#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9422#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9421#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9420#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9419#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9418#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9417#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9416#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9415#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9414#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9413#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9412#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9411#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9410#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9409#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9407#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9408#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9399#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9398#L370-4 main_~j~0#1 := 0; 9374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9366#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9367#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9392#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9391#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9390#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9389#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9388#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9386#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9385#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9384#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9383#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9381#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9380#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9364#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9365#L378-2 [2021-11-23 14:15:56,483 INFO L793 eck$LassoCheckResult]: Loop: 9365#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9382#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9365#L378-2 [2021-11-23 14:15:56,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:56,484 INFO L85 PathProgramCache]: Analyzing trace with hash 306447676, now seen corresponding path program 13 times [2021-11-23 14:15:56,484 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:56,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627705519] [2021-11-23 14:15:56,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:56,485 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:56,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:56,975 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:56,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:56,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627705519] [2021-11-23 14:15:56,976 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627705519] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:56,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1510070380] [2021-11-23 14:15:56,976 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:15:56,976 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:56,976 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:56,978 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:56,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-23 14:15:57,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:57,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 41 conjunts are in the unsatisfiable core [2021-11-23 14:15:57,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:57,409 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-23 14:15:57,952 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:15:57,955 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:57,955 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:15:58,086 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:15:58,088 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:15:58,200 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:58,201 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1510070380] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:15:58,201 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:15:58,201 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 20] total 42 [2021-11-23 14:15:58,201 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191734287] [2021-11-23 14:15:58,201 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:15:58,201 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:15:58,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:58,202 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2021-11-23 14:15:58,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:58,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735532214] [2021-11-23 14:15:58,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:58,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:58,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:58,204 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:15:58,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:15:58,206 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:15:58,251 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:15:58,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-23 14:15:58,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=1652, Unknown=0, NotChecked=0, Total=1806 [2021-11-23 14:15:58,252 INFO L87 Difference]: Start difference. First operand 67 states and 86 transitions. cyclomatic complexity: 24 Second operand has 43 states, 42 states have (on average 2.2857142857142856) internal successors, (96), 43 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:59,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:15:59,135 INFO L93 Difference]: Finished difference Result 137 states and 169 transitions. [2021-11-23 14:15:59,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-23 14:15:59,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137 states and 169 transitions. [2021-11-23 14:15:59,137 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18 [2021-11-23 14:15:59,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137 states to 136 states and 168 transitions. [2021-11-23 14:15:59,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2021-11-23 14:15:59,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2021-11-23 14:15:59,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 168 transitions. [2021-11-23 14:15:59,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:15:59,138 INFO L681 BuchiCegarLoop]: Abstraction has 136 states and 168 transitions. [2021-11-23 14:15:59,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 168 transitions. [2021-11-23 14:15:59,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 102. [2021-11-23 14:15:59,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.2941176470588236) internal successors, (132), 101 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:15:59,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 132 transitions. [2021-11-23 14:15:59,142 INFO L704 BuchiCegarLoop]: Abstraction has 102 states and 132 transitions. [2021-11-23 14:15:59,142 INFO L587 BuchiCegarLoop]: Abstraction has 102 states and 132 transitions. [2021-11-23 14:15:59,142 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-23 14:15:59,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 132 transitions. [2021-11-23 14:15:59,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2021-11-23 14:15:59,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:15:59,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:15:59,144 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:15:59,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-23 14:15:59,145 INFO L791 eck$LassoCheckResult]: Stem: 9893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9904#L367 assume !(main_~length~0#1 < 1); 9895#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9896#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9905#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9933#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9932#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9931#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9930#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9929#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9928#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9927#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9926#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9925#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9924#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9923#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9922#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9921#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9920#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9919#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9918#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9960#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9958#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9955#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9954#L370-4 main_~j~0#1 := 0; 9953#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9952#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9951#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9950#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9949#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9948#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9946#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9944#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9943#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9942#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9935#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9936#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9982#L378-2 [2021-11-23 14:15:59,145 INFO L793 eck$LassoCheckResult]: Loop: 9982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9984#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9985#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9986#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9982#L378-2 [2021-11-23 14:15:59,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:15:59,145 INFO L85 PathProgramCache]: Analyzing trace with hash 724598011, now seen corresponding path program 15 times [2021-11-23 14:15:59,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:15:59,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534409854] [2021-11-23 14:15:59,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:15:59,146 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:15:59,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:15:59,570 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:15:59,570 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:15:59,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534409854] [2021-11-23 14:15:59,570 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534409854] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:15:59,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [507382517] [2021-11-23 14:15:59,571 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:15:59,571 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:15:59,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:15:59,576 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:15:59,577 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-11-23 14:15:59,713 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-11-23 14:15:59,714 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:15:59,716 INFO L263 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 38 conjunts are in the unsatisfiable core [2021-11-23 14:15:59,717 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:15:59,826 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:15:59,929 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:59,929 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:15:59,949 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:15:59,949 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:00,059 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:16:00,059 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:16:01,036 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:16:01,036 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:16:01,040 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 1 proven. 158 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:01,040 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:02,171 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_324| Int)) (or (and (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_324| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (< 5 |v_ULTIMATE.start_main_~i~0#1_324|)) (< |v_ULTIMATE.start_main_~i~0#1_324| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2021-11-23 14:16:03,092 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2021-11-23 14:16:03,102 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 162 treesize of output 154 [2021-11-23 14:16:03,234 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 151 refuted. 0 times theorem prover too weak. 0 trivial. 8 not checked. [2021-11-23 14:16:03,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [507382517] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:03,235 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:03,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 37 [2021-11-23 14:16:03,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550582135] [2021-11-23 14:16:03,235 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:03,237 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:03,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:03,238 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 2 times [2021-11-23 14:16:03,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:03,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892446211] [2021-11-23 14:16:03,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:03,238 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:03,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:03,241 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:03,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:03,244 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:03,358 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:03,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-23 14:16:03,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=1200, Unknown=2, NotChecked=70, Total=1406 [2021-11-23 14:16:03,360 INFO L87 Difference]: Start difference. First operand 102 states and 132 transitions. cyclomatic complexity: 37 Second operand has 38 states, 37 states have (on average 2.135135135135135) internal successors, (79), 38 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:04,420 WARN L838 $PredicateComparison]: unable to prove that (and (<= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (forall ((|v_ULTIMATE.start_main_~i~0#1_324| Int)) (or (and (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_324| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (< 5 |v_ULTIMATE.start_main_~i~0#1_324|)) (< |v_ULTIMATE.start_main_~i~0#1_324| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) (<= |c_ULTIMATE.start_main_~i~0#1| 6) (<= 6 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-11-23 14:16:05,230 WARN L838 $PredicateComparison]: unable to prove that (and (<= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (<= 7 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_324| Int)) (or (and (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_324| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (< 5 |v_ULTIMATE.start_main_~i~0#1_324|)) (< |v_ULTIMATE.start_main_~i~0#1_324| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-11-23 14:16:06,094 WARN L838 $PredicateComparison]: unable to prove that (and (<= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (<= 7 |c_ULTIMATE.start_main_~i~0#1|) (exists ((|v_ULTIMATE.start_main_~i~0#1_321| Int)) (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_321| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (<= 7 |v_ULTIMATE.start_main_~i~0#1_321|))) (forall ((|v_ULTIMATE.start_main_~i~0#1_324| Int)) (or (and (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_324| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 24))) (< 5 |v_ULTIMATE.start_main_~i~0#1_324|)) (< |v_ULTIMATE.start_main_~i~0#1_324| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-11-23 14:16:06,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:06,163 INFO L93 Difference]: Finished difference Result 162 states and 190 transitions. [2021-11-23 14:16:06,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-23 14:16:06,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162 states and 190 transitions. [2021-11-23 14:16:06,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:06,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162 states to 160 states and 186 transitions. [2021-11-23 14:16:06,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-23 14:16:06,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-23 14:16:06,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 160 states and 186 transitions. [2021-11-23 14:16:06,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:06,168 INFO L681 BuchiCegarLoop]: Abstraction has 160 states and 186 transitions. [2021-11-23 14:16:06,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states and 186 transitions. [2021-11-23 14:16:06,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 57. [2021-11-23 14:16:06,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2456140350877194) internal successors, (71), 56 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:06,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 71 transitions. [2021-11-23 14:16:06,172 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 71 transitions. [2021-11-23 14:16:06,173 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 71 transitions. [2021-11-23 14:16:06,173 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-23 14:16:06,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 71 transitions. [2021-11-23 14:16:06,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:06,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:06,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:06,174 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:06,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:06,175 INFO L791 eck$LassoCheckResult]: Stem: 10490#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10501#L367 assume !(main_~length~0#1 < 1); 10492#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10493#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10494#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10502#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10504#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10505#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10508#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10545#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10544#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10543#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10542#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10539#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10536#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10532#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10530#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10524#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10515#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10495#L370-4 main_~j~0#1 := 0; 10496#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10525#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10499#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10500#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10523#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10522#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10521#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10520#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10519#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10518#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10517#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10514#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10513#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10512#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10511#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10510#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10497#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10498#L378-2 [2021-11-23 14:16:06,175 INFO L793 eck$LassoCheckResult]: Loop: 10498#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10509#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10498#L378-2 [2021-11-23 14:16:06,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:06,176 INFO L85 PathProgramCache]: Analyzing trace with hash -1856523519, now seen corresponding path program 14 times [2021-11-23 14:16:06,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:06,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868577899] [2021-11-23 14:16:06,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:06,177 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:06,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:06,714 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:06,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:06,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868577899] [2021-11-23 14:16:06,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868577899] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:06,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1569692957] [2021-11-23 14:16:06,715 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:16:06,715 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:06,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:06,717 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:06,717 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-11-23 14:16:06,776 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:16:06,776 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:06,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-23 14:16:06,779 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:07,287 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:07,287 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:07,635 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:07,636 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1569692957] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:07,636 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:07,636 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 50 [2021-11-23 14:16:07,636 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115937397] [2021-11-23 14:16:07,636 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:07,637 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:07,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:07,637 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2021-11-23 14:16:07,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:07,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599057930] [2021-11-23 14:16:07,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:07,638 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:07,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:07,640 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:07,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:07,643 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:07,703 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:07,703 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-11-23 14:16:07,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=436, Invalid=2014, Unknown=0, NotChecked=0, Total=2450 [2021-11-23 14:16:07,705 INFO L87 Difference]: Start difference. First operand 57 states and 71 transitions. cyclomatic complexity: 18 Second operand has 50 states, 50 states have (on average 2.24) internal successors, (112), 50 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:08,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:08,350 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2021-11-23 14:16:08,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-23 14:16:08,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2021-11-23 14:16:08,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:08,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 62 states and 77 transitions. [2021-11-23 14:16:08,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:16:08,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:16:08,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 77 transitions. [2021-11-23 14:16:08,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:08,354 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 77 transitions. [2021-11-23 14:16:08,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 77 transitions. [2021-11-23 14:16:08,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 59. [2021-11-23 14:16:08,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.2372881355932204) internal successors, (73), 58 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:08,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 73 transitions. [2021-11-23 14:16:08,356 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2021-11-23 14:16:08,356 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2021-11-23 14:16:08,357 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-23 14:16:08,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 73 transitions. [2021-11-23 14:16:08,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:08,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:08,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:08,358 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:08,358 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:08,359 INFO L791 eck$LassoCheckResult]: Stem: 10988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10999#L367 assume !(main_~length~0#1 < 1); 10990#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10991#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11000#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11002#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11005#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11045#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11042#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11039#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11036#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11035#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11033#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11032#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11031#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11030#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11028#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11026#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11006#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10993#L370-4 main_~j~0#1 := 0; 10994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11004#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11020#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11019#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11018#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11016#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11014#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11012#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11011#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11009#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11008#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10995#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10996#L378-2 [2021-11-23 14:16:08,359 INFO L793 eck$LassoCheckResult]: Loop: 10996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11010#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10996#L378-2 [2021-11-23 14:16:08,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:08,360 INFO L85 PathProgramCache]: Analyzing trace with hash -433799996, now seen corresponding path program 16 times [2021-11-23 14:16:08,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:08,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937736893] [2021-11-23 14:16:08,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:08,360 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:08,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:08,834 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:08,835 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:08,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937736893] [2021-11-23 14:16:08,835 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937736893] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:08,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1561470145] [2021-11-23 14:16:08,835 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:16:08,835 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:08,835 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:08,838 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:08,839 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-11-23 14:16:08,898 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:16:08,898 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:08,900 INFO L263 TraceCheckSpWp]: Trace formula consists of 221 conjuncts, 44 conjunts are in the unsatisfiable core [2021-11-23 14:16:08,901 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:09,298 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:09,475 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:16:09,476 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:09,504 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:09,504 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:16:10,407 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:16:10,407 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:16:10,411 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:10,411 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:11,325 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:16:11,327 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:16:11,445 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 1 proven. 171 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:16:11,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1561470145] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:11,446 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:11,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 21] total 46 [2021-11-23 14:16:11,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88442931] [2021-11-23 14:16:11,446 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:11,447 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:11,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:11,447 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2021-11-23 14:16:11,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:11,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529882119] [2021-11-23 14:16:11,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:11,448 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:11,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:11,451 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:11,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:11,453 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:11,498 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:11,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-11-23 14:16:11,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=1967, Unknown=0, NotChecked=0, Total=2162 [2021-11-23 14:16:11,500 INFO L87 Difference]: Start difference. First operand 59 states and 73 transitions. cyclomatic complexity: 18 Second operand has 47 states, 46 states have (on average 2.239130434782609) internal successors, (103), 47 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:12,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:12,187 INFO L93 Difference]: Finished difference Result 114 states and 134 transitions. [2021-11-23 14:16:12,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-23 14:16:12,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 134 transitions. [2021-11-23 14:16:12,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:12,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 113 states and 132 transitions. [2021-11-23 14:16:12,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-23 14:16:12,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-23 14:16:12,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 132 transitions. [2021-11-23 14:16:12,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:12,193 INFO L681 BuchiCegarLoop]: Abstraction has 113 states and 132 transitions. [2021-11-23 14:16:12,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 132 transitions. [2021-11-23 14:16:12,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 63. [2021-11-23 14:16:12,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.2698412698412698) internal successors, (80), 62 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:12,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 80 transitions. [2021-11-23 14:16:12,196 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 80 transitions. [2021-11-23 14:16:12,197 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 80 transitions. [2021-11-23 14:16:12,197 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-11-23 14:16:12,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 80 transitions. [2021-11-23 14:16:12,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:12,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:12,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:12,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:12,199 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:12,199 INFO L791 eck$LassoCheckResult]: Stem: 11511#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11522#L367 assume !(main_~length~0#1 < 1); 11513#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11514#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11523#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11525#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11573#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11572#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11571#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11570#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11569#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11568#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11565#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11564#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11563#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11559#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11557#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11554#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11553#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11552#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11551#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11516#L370-4 main_~j~0#1 := 0; 11517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11545#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11528#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11520#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11543#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11542#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11535#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11530#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11518#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11519#L378-2 [2021-11-23 14:16:12,199 INFO L793 eck$LassoCheckResult]: Loop: 11519#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11531#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11519#L378-2 [2021-11-23 14:16:12,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:12,204 INFO L85 PathProgramCache]: Analyzing trace with hash -269965175, now seen corresponding path program 17 times [2021-11-23 14:16:12,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:12,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99113927] [2021-11-23 14:16:12,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:12,205 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:12,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:12,733 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:12,734 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:12,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99113927] [2021-11-23 14:16:12,734 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99113927] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:12,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041526310] [2021-11-23 14:16:12,734 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:16:12,734 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:12,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:12,739 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:12,769 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-11-23 14:16:12,888 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-11-23 14:16:12,888 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:12,891 INFO L263 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 39 conjunts are in the unsatisfiable core [2021-11-23 14:16:12,893 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:13,051 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:16:13,484 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:16:13,514 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:13,514 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:14,014 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2021-11-23 14:16:14,016 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 36 [2021-11-23 14:16:14,176 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:14,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041526310] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:14,176 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:14,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 43 [2021-11-23 14:16:14,176 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991840327] [2021-11-23 14:16:14,176 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:14,177 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:14,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:14,177 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2021-11-23 14:16:14,177 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:14,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597525187] [2021-11-23 14:16:14,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:14,177 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:14,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:14,180 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:14,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:14,183 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:14,234 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:14,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-23 14:16:14,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=1753, Unknown=0, NotChecked=0, Total=1892 [2021-11-23 14:16:14,235 INFO L87 Difference]: Start difference. First operand 63 states and 80 transitions. cyclomatic complexity: 21 Second operand has 44 states, 43 states have (on average 2.186046511627907) internal successors, (94), 44 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:14,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:14,967 INFO L93 Difference]: Finished difference Result 84 states and 101 transitions. [2021-11-23 14:16:14,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-23 14:16:14,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 101 transitions. [2021-11-23 14:16:14,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:14,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 100 transitions. [2021-11-23 14:16:14,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-23 14:16:14,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-23 14:16:14,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 100 transitions. [2021-11-23 14:16:14,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:14,970 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 100 transitions. [2021-11-23 14:16:14,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 100 transitions. [2021-11-23 14:16:14,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 67. [2021-11-23 14:16:14,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2537313432835822) internal successors, (84), 66 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:14,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 84 transitions. [2021-11-23 14:16:14,972 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 84 transitions. [2021-11-23 14:16:14,972 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 84 transitions. [2021-11-23 14:16:14,972 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-11-23 14:16:14,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 84 transitions. [2021-11-23 14:16:14,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:14,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:14,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:14,974 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:14,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:14,975 INFO L791 eck$LassoCheckResult]: Stem: 12013#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12024#L367 assume !(main_~length~0#1 < 1); 12015#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12016#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12017#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12025#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12079#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12078#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12077#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12076#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12075#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12074#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12073#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12072#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12071#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12070#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12069#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12068#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12067#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12066#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12065#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12064#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12063#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12062#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12061#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12060#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12059#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12057#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12056#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12026#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12027#L370-4 main_~j~0#1 := 0; 12030#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12031#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12046#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12045#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12044#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12042#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12041#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12040#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12038#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12036#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12035#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12033#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12032#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12020#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12021#L378-2 [2021-11-23 14:16:14,975 INFO L793 eck$LassoCheckResult]: Loop: 12021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12034#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12021#L378-2 [2021-11-23 14:16:14,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:14,976 INFO L85 PathProgramCache]: Analyzing trace with hash -51110457, now seen corresponding path program 15 times [2021-11-23 14:16:14,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:14,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226809446] [2021-11-23 14:16:14,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:14,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:14,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:15,489 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:15,489 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:15,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226809446] [2021-11-23 14:16:15,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226809446] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:15,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1270367228] [2021-11-23 14:16:15,490 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:16:15,490 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:15,490 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:15,494 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:15,495 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-11-23 14:16:15,618 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-11-23 14:16:15,618 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:15,621 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-23 14:16:15,622 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:15,927 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:16,884 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-23 14:16:16,884 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 21 [2021-11-23 14:16:16,887 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:16,887 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:18,005 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2021-11-23 14:16:18,008 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 43 [2021-11-23 14:16:18,073 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:18,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1270367228] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:18,073 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:18,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2021-11-23 14:16:18,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793433199] [2021-11-23 14:16:18,074 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:18,074 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:18,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:18,074 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2021-11-23 14:16:18,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:18,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150714955] [2021-11-23 14:16:18,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:18,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:18,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:18,077 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:18,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:18,079 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:18,125 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:18,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2021-11-23 14:16:18,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3022, Unknown=0, NotChecked=0, Total=3422 [2021-11-23 14:16:18,128 INFO L87 Difference]: Start difference. First operand 67 states and 84 transitions. cyclomatic complexity: 21 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:19,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:19,992 INFO L93 Difference]: Finished difference Result 104 states and 123 transitions. [2021-11-23 14:16:19,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-23 14:16:19,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104 states and 123 transitions. [2021-11-23 14:16:20,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:20,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104 states to 65 states and 81 transitions. [2021-11-23 14:16:20,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:16:20,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:16:20,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 81 transitions. [2021-11-23 14:16:20,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:20,029 INFO L681 BuchiCegarLoop]: Abstraction has 65 states and 81 transitions. [2021-11-23 14:16:20,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 81 transitions. [2021-11-23 14:16:20,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2021-11-23 14:16:20,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.2461538461538462) internal successors, (81), 64 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:20,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 81 transitions. [2021-11-23 14:16:20,032 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 81 transitions. [2021-11-23 14:16:20,032 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 81 transitions. [2021-11-23 14:16:20,032 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-11-23 14:16:20,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 81 transitions. [2021-11-23 14:16:20,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:20,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:20,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:20,034 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:20,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:20,034 INFO L791 eck$LassoCheckResult]: Stem: 12640#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12641#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12651#L367 assume !(main_~length~0#1 < 1); 12642#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12643#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12654#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12704#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12703#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12702#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12701#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12699#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12697#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12696#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12695#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12693#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12692#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12691#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12690#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12689#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12688#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12687#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12686#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12685#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12683#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12684#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12682#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12657#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12645#L370-4 main_~j~0#1 := 0; 12646#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12656#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12671#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12669#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12668#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12667#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12666#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12665#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12663#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12662#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12660#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12659#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12647#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12648#L378-2 [2021-11-23 14:16:20,035 INFO L793 eck$LassoCheckResult]: Loop: 12648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12661#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12648#L378-2 [2021-11-23 14:16:20,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:20,035 INFO L85 PathProgramCache]: Analyzing trace with hash 687219962, now seen corresponding path program 18 times [2021-11-23 14:16:20,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:20,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673360262] [2021-11-23 14:16:20,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:20,036 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:20,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:20,527 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 0 proven. 201 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:20,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:20,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673360262] [2021-11-23 14:16:20,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673360262] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:20,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2055929083] [2021-11-23 14:16:20,528 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:16:20,528 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:20,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:20,532 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:20,533 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-11-23 14:16:20,707 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2021-11-23 14:16:20,707 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:20,709 INFO L263 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 43 conjunts are in the unsatisfiable core [2021-11-23 14:16:20,711 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:20,861 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:20,980 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:20,980 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:21,005 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:21,005 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:16:21,096 INFO L354 Elim1Store]: treesize reduction 66, result has 34.7 percent of original size [2021-11-23 14:16:21,096 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 50 treesize of output 66 [2021-11-23 14:16:22,108 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:16:22,108 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:16:22,111 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 0 proven. 201 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:22,111 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:25,455 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:16:25,458 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:16:25,567 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 2 proven. 194 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2021-11-23 14:16:25,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2055929083] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:25,567 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:25,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 21] total 38 [2021-11-23 14:16:25,568 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795509124] [2021-11-23 14:16:25,568 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:25,568 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:25,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:25,568 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2021-11-23 14:16:25,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:25,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124319666] [2021-11-23 14:16:25,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:25,569 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:25,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:25,570 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:25,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:25,572 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:25,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:25,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-23 14:16:25,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=149, Invalid=1333, Unknown=0, NotChecked=0, Total=1482 [2021-11-23 14:16:25,618 INFO L87 Difference]: Start difference. First operand 65 states and 81 transitions. cyclomatic complexity: 20 Second operand has 39 states, 38 states have (on average 2.263157894736842) internal successors, (86), 39 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:26,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:26,790 INFO L93 Difference]: Finished difference Result 103 states and 121 transitions. [2021-11-23 14:16:26,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-11-23 14:16:26,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 121 transitions. [2021-11-23 14:16:26,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:26,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 101 states and 119 transitions. [2021-11-23 14:16:26,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-23 14:16:26,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-23 14:16:26,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 119 transitions. [2021-11-23 14:16:26,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:26,801 INFO L681 BuchiCegarLoop]: Abstraction has 101 states and 119 transitions. [2021-11-23 14:16:26,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 119 transitions. [2021-11-23 14:16:26,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 57. [2021-11-23 14:16:26,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2280701754385965) internal successors, (70), 56 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:26,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 70 transitions. [2021-11-23 14:16:26,804 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 70 transitions. [2021-11-23 14:16:26,804 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 70 transitions. [2021-11-23 14:16:26,804 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-11-23 14:16:26,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 70 transitions. [2021-11-23 14:16:26,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:26,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:26,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:26,806 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:26,806 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:26,806 INFO L791 eck$LassoCheckResult]: Stem: 13188#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13199#L367 assume !(main_~length~0#1 < 1); 13190#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13191#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13200#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13244#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13202#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13203#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13205#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13243#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13242#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13241#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13240#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13239#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13238#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13237#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13236#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13235#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13234#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13233#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13231#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13229#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13228#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13227#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13226#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13225#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13224#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13223#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13210#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13212#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13209#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13193#L370-4 main_~j~0#1 := 0; 13194#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13197#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13198#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13204#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13222#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13221#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13219#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13217#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13216#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13215#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13214#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13213#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13211#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13208#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13207#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13195#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13196#L378-2 [2021-11-23 14:16:26,806 INFO L793 eck$LassoCheckResult]: Loop: 13196#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13206#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13196#L378-2 [2021-11-23 14:16:26,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:26,807 INFO L85 PathProgramCache]: Analyzing trace with hash -866028223, now seen corresponding path program 16 times [2021-11-23 14:16:26,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:26,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725376942] [2021-11-23 14:16:26,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:26,808 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:26,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:27,285 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:27,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:27,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725376942] [2021-11-23 14:16:27,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725376942] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:27,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [551701904] [2021-11-23 14:16:27,285 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:16:27,286 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:27,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:27,287 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:27,289 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-11-23 14:16:27,358 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:16:27,358 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:27,360 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-23 14:16:27,361 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:27,794 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:27,946 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:27,946 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:16:28,582 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:16:28,585 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:28,586 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:28,897 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-11-23 14:16:28,901 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 36 [2021-11-23 14:16:29,049 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:29,050 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [551701904] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:29,050 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:29,050 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 50 [2021-11-23 14:16:29,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091299242] [2021-11-23 14:16:29,050 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:29,051 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:29,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:29,054 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2021-11-23 14:16:29,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:29,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955757330] [2021-11-23 14:16:29,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:29,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:29,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:29,059 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:29,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:29,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:29,124 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:29,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-11-23 14:16:29,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=2365, Unknown=0, NotChecked=0, Total=2550 [2021-11-23 14:16:29,126 INFO L87 Difference]: Start difference. First operand 57 states and 70 transitions. cyclomatic complexity: 16 Second operand has 51 states, 50 states have (on average 2.24) internal successors, (112), 51 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:30,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:30,517 INFO L93 Difference]: Finished difference Result 61 states and 74 transitions. [2021-11-23 14:16:30,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-23 14:16:30,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 74 transitions. [2021-11-23 14:16:30,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:30,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 60 states and 73 transitions. [2021-11-23 14:16:30,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-23 14:16:30,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-23 14:16:30,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 73 transitions. [2021-11-23 14:16:30,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:30,520 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 73 transitions. [2021-11-23 14:16:30,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 73 transitions. [2021-11-23 14:16:30,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 59. [2021-11-23 14:16:30,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.2203389830508475) internal successors, (72), 58 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:30,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 72 transitions. [2021-11-23 14:16:30,521 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 72 transitions. [2021-11-23 14:16:30,521 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 72 transitions. [2021-11-23 14:16:30,521 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-11-23 14:16:30,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 72 transitions. [2021-11-23 14:16:30,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:30,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:30,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:30,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:30,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:30,522 INFO L791 eck$LassoCheckResult]: Stem: 13706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13717#L367 assume !(main_~length~0#1 < 1); 13708#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13709#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13718#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13723#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13719#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13720#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13749#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13747#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13745#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13744#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13741#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13738#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13737#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13736#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13735#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13732#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13731#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13730#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13729#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13727#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13725#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13726#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13724#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13715#L370-4 main_~j~0#1 := 0; 13716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13721#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13713#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13764#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13762#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13761#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13760#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13759#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13758#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13757#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13756#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13755#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13754#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13753#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13752#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13751#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13711#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13712#L378-2 [2021-11-23 14:16:30,523 INFO L793 eck$LassoCheckResult]: Loop: 13712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13750#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13712#L378-2 [2021-11-23 14:16:30,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:30,523 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 17 times [2021-11-23 14:16:30,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:30,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650225055] [2021-11-23 14:16:30,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:30,523 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:30,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:31,115 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:31,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:31,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650225055] [2021-11-23 14:16:31,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650225055] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:31,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1190710732] [2021-11-23 14:16:31,116 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:16:31,116 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:31,116 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:31,119 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:31,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-11-23 14:16:31,325 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2021-11-23 14:16:31,325 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:31,329 INFO L263 TraceCheckSpWp]: Trace formula consists of 249 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-23 14:16:31,331 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:32,028 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-23 14:16:33,383 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-23 14:16:33,384 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 29 [2021-11-23 14:16:33,388 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:33,388 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:33,640 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:16:33,648 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:16:33,891 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:33,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1190710732] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:33,892 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:33,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 27, 27] total 55 [2021-11-23 14:16:33,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435478380] [2021-11-23 14:16:33,892 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:33,892 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:33,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:33,893 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2021-11-23 14:16:33,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:33,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064053275] [2021-11-23 14:16:33,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:33,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:33,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:33,896 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:33,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:33,899 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:33,946 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:33,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2021-11-23 14:16:33,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=2847, Unknown=0, NotChecked=0, Total=3080 [2021-11-23 14:16:33,948 INFO L87 Difference]: Start difference. First operand 59 states and 72 transitions. cyclomatic complexity: 16 Second operand has 56 states, 55 states have (on average 2.1636363636363636) internal successors, (119), 56 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:34,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:34,634 INFO L93 Difference]: Finished difference Result 84 states and 99 transitions. [2021-11-23 14:16:34,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-23 14:16:34,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 99 transitions. [2021-11-23 14:16:34,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:34,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 98 transitions. [2021-11-23 14:16:34,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:16:34,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:16:34,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 98 transitions. [2021-11-23 14:16:34,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:34,637 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 98 transitions. [2021-11-23 14:16:34,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 98 transitions. [2021-11-23 14:16:34,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 66. [2021-11-23 14:16:34,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.2272727272727273) internal successors, (81), 65 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:34,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 81 transitions. [2021-11-23 14:16:34,640 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 81 transitions. [2021-11-23 14:16:34,640 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 81 transitions. [2021-11-23 14:16:34,640 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-11-23 14:16:34,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 81 transitions. [2021-11-23 14:16:34,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:34,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:34,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:34,642 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:34,642 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:34,642 INFO L791 eck$LassoCheckResult]: Stem: 14252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14263#L367 assume !(main_~length~0#1 < 1); 14254#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14255#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14256#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14264#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14302#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14265#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14266#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14269#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14270#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14301#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14299#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14298#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14297#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14295#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14294#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14292#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14291#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14290#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14289#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14287#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14286#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14285#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14284#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14283#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14282#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14279#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14274#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14261#L370-4 main_~j~0#1 := 0; 14262#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14314#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14313#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14312#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14311#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14309#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14307#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14306#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14305#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14304#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14303#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14280#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14278#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14272#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14271#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14257#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14258#L378-2 [2021-11-23 14:16:34,642 INFO L793 eck$LassoCheckResult]: Loop: 14258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14273#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14258#L378-2 [2021-11-23 14:16:34,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:34,643 INFO L85 PathProgramCache]: Analyzing trace with hash 677570827, now seen corresponding path program 18 times [2021-11-23 14:16:34,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:34,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762156472] [2021-11-23 14:16:34,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:34,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:34,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:35,306 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:35,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:35,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762156472] [2021-11-23 14:16:35,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762156472] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:35,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [464949257] [2021-11-23 14:16:35,307 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:16:35,307 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:35,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:35,315 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:35,317 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-11-23 14:16:35,508 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2021-11-23 14:16:35,509 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:35,512 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-23 14:16:35,513 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:35,790 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:36,749 INFO L354 Elim1Store]: treesize reduction 15, result has 6.3 percent of original size [2021-11-23 14:16:36,749 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 18 [2021-11-23 14:16:36,752 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:36,752 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:38,010 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2021-11-23 14:16:38,012 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 43 [2021-11-23 14:16:38,133 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 90 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:38,134 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [464949257] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:38,134 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:38,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27, 27] total 68 [2021-11-23 14:16:38,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100469622] [2021-11-23 14:16:38,134 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:38,135 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:38,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:38,135 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2021-11-23 14:16:38,135 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:38,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688403765] [2021-11-23 14:16:38,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:38,135 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:38,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:38,138 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:38,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:38,141 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:38,203 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:38,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2021-11-23 14:16:38,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=722, Invalid=3834, Unknown=0, NotChecked=0, Total=4556 [2021-11-23 14:16:38,206 INFO L87 Difference]: Start difference. First operand 66 states and 81 transitions. cyclomatic complexity: 18 Second operand has 68 states, 68 states have (on average 2.1323529411764706) internal successors, (145), 68 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:40,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:40,541 INFO L93 Difference]: Finished difference Result 112 states and 129 transitions. [2021-11-23 14:16:40,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2021-11-23 14:16:40,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 129 transitions. [2021-11-23 14:16:40,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:40,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 86 states and 102 transitions. [2021-11-23 14:16:40,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-11-23 14:16:40,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2021-11-23 14:16:40,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 102 transitions. [2021-11-23 14:16:40,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:40,545 INFO L681 BuchiCegarLoop]: Abstraction has 86 states and 102 transitions. [2021-11-23 14:16:40,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 102 transitions. [2021-11-23 14:16:40,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 85. [2021-11-23 14:16:40,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.188235294117647) internal successors, (101), 84 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:40,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 101 transitions. [2021-11-23 14:16:40,548 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 101 transitions. [2021-11-23 14:16:40,548 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 101 transitions. [2021-11-23 14:16:40,548 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-11-23 14:16:40,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 101 transitions. [2021-11-23 14:16:40,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:40,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:40,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:40,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:40,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:40,551 INFO L791 eck$LassoCheckResult]: Stem: 14958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14969#L367 assume !(main_~length~0#1 < 1); 14960#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14961#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14970#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14971#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14972#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14973#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14975#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15004#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15002#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15001#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15000#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14999#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14998#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14997#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14996#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14995#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14994#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14993#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14992#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14991#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14989#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14988#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14987#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14986#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14985#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14984#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14983#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14982#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14980#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14981#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14979#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14976#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14977#L370-4 main_~j~0#1 := 0; 15006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15007#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14967#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15039#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15035#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15033#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15031#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15029#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15027#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15025#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15023#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15019#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15014#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15010#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15011#L378-2 [2021-11-23 14:16:40,553 INFO L793 eck$LassoCheckResult]: Loop: 15011#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15012#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15011#L378-2 [2021-11-23 14:16:40,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:40,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1414945998, now seen corresponding path program 19 times [2021-11-23 14:16:40,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:40,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549749840] [2021-11-23 14:16:40,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:40,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:40,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:41,213 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:41,213 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:41,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549749840] [2021-11-23 14:16:41,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549749840] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:41,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [843275589] [2021-11-23 14:16:41,214 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:16:41,214 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:41,214 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:41,216 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:41,216 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-11-23 14:16:41,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:41,320 INFO L263 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 52 conjunts are in the unsatisfiable core [2021-11-23 14:16:41,322 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:41,838 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:42,016 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:16:42,016 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:42,034 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:42,034 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:16:43,288 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:16:43,288 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:16:43,291 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:43,291 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:53,609 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 30 [2021-11-23 14:16:53,612 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 149 [2021-11-23 14:16:53,779 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 2 proven. 264 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:53,780 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [843275589] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:53,780 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:53,780 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 26] total 55 [2021-11-23 14:16:53,780 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512017384] [2021-11-23 14:16:53,780 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:53,781 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:53,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:53,782 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2021-11-23 14:16:53,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:53,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006188481] [2021-11-23 14:16:53,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:53,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:53,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:53,784 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:53,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:53,786 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:53,834 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:53,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2021-11-23 14:16:53,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=247, Invalid=2819, Unknown=14, NotChecked=0, Total=3080 [2021-11-23 14:16:53,836 INFO L87 Difference]: Start difference. First operand 85 states and 101 transitions. cyclomatic complexity: 19 Second operand has 56 states, 55 states have (on average 2.2363636363636363) internal successors, (123), 56 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:54,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:54,636 INFO L93 Difference]: Finished difference Result 133 states and 153 transitions. [2021-11-23 14:16:54,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-23 14:16:54,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 153 transitions. [2021-11-23 14:16:54,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:54,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 112 states and 130 transitions. [2021-11-23 14:16:54,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-23 14:16:54,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-23 14:16:54,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112 states and 130 transitions. [2021-11-23 14:16:54,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:54,643 INFO L681 BuchiCegarLoop]: Abstraction has 112 states and 130 transitions. [2021-11-23 14:16:54,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states and 130 transitions. [2021-11-23 14:16:54,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 72. [2021-11-23 14:16:54,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 71 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:54,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 89 transitions. [2021-11-23 14:16:54,646 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 89 transitions. [2021-11-23 14:16:54,646 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 89 transitions. [2021-11-23 14:16:54,647 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-11-23 14:16:54,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 89 transitions. [2021-11-23 14:16:54,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:54,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:54,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:54,648 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:54,648 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:54,649 INFO L791 eck$LassoCheckResult]: Stem: 15593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15604#L367 assume !(main_~length~0#1 < 1); 15595#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15596#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15608#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15607#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15664#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15662#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15661#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15660#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15659#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15658#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15656#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15653#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15650#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15648#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15647#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15646#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15645#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15644#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15643#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15642#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15641#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15638#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15636#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15631#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15615#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15598#L370-4 main_~j~0#1 := 0; 15599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15634#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15602#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15603#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15630#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15629#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15628#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15627#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15626#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15624#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15621#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15617#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15614#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15600#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15601#L378-2 [2021-11-23 14:16:54,649 INFO L793 eck$LassoCheckResult]: Loop: 15601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15613#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15601#L378-2 [2021-11-23 14:16:54,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:54,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1741525485, now seen corresponding path program 20 times [2021-11-23 14:16:54,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:54,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636896500] [2021-11-23 14:16:54,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:54,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:54,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:55,286 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:55,286 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:55,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636896500] [2021-11-23 14:16:55,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636896500] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:55,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1920589397] [2021-11-23 14:16:55,286 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:16:55,286 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:55,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:55,289 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:55,290 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-11-23 14:16:55,364 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:16:55,364 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:55,366 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-23 14:16:55,367 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:55,525 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2021-11-23 14:16:56,025 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:16:56,058 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:56,058 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:16:56,594 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-11-23 14:16:56,596 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-23 14:16:56,753 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:56,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1920589397] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:16:56,753 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:16:56,753 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 49 [2021-11-23 14:16:56,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80819215] [2021-11-23 14:16:56,753 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:16:56,754 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:16:56,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:56,754 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2021-11-23 14:16:56,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:56,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346349763] [2021-11-23 14:16:56,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:56,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:56,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:56,756 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:16:56,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:16:56,758 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:16:56,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:16:56,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-11-23 14:16:56,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=2295, Unknown=0, NotChecked=0, Total=2450 [2021-11-23 14:16:56,804 INFO L87 Difference]: Start difference. First operand 72 states and 89 transitions. cyclomatic complexity: 21 Second operand has 50 states, 49 states have (on average 2.2448979591836733) internal successors, (110), 50 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:57,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:16:57,926 INFO L93 Difference]: Finished difference Result 103 states and 123 transitions. [2021-11-23 14:16:57,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-23 14:16:57,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 123 transitions. [2021-11-23 14:16:57,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:16:57,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 102 states and 122 transitions. [2021-11-23 14:16:57,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-23 14:16:57,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-23 14:16:57,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 122 transitions. [2021-11-23 14:16:57,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:16:57,929 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 122 transitions. [2021-11-23 14:16:57,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 122 transitions. [2021-11-23 14:16:57,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 78. [2021-11-23 14:16:57,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 77 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:16:57,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 96 transitions. [2021-11-23 14:16:57,931 INFO L704 BuchiCegarLoop]: Abstraction has 78 states and 96 transitions. [2021-11-23 14:16:57,931 INFO L587 BuchiCegarLoop]: Abstraction has 78 states and 96 transitions. [2021-11-23 14:16:57,931 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-11-23 14:16:57,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 96 transitions. [2021-11-23 14:16:57,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:16:57,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:16:57,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:16:57,932 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:16:57,932 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:16:57,933 INFO L791 eck$LassoCheckResult]: Stem: 16189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16200#L367 assume !(main_~length~0#1 < 1); 16191#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16192#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16193#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16201#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16206#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16240#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16239#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16238#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16237#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16236#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16234#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16233#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16231#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16230#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16227#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16224#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16221#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16219#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16218#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16216#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16215#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16213#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16210#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16209#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16203#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16212#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16263#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16262#L370-4 main_~j~0#1 := 0; 16260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16257#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16255#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16253#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16252#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16251#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16250#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16249#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16248#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16247#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16245#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16242#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16194#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16195#L378-2 [2021-11-23 14:16:57,933 INFO L793 eck$LassoCheckResult]: Loop: 16195#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16243#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16195#L378-2 [2021-11-23 14:16:57,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:16:57,934 INFO L85 PathProgramCache]: Analyzing trace with hash -696609148, now seen corresponding path program 21 times [2021-11-23 14:16:57,934 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:16:57,934 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997886672] [2021-11-23 14:16:57,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:16:57,934 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:16:57,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:16:58,538 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:16:58,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:16:58,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997886672] [2021-11-23 14:16:58,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997886672] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:16:58,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1667586176] [2021-11-23 14:16:58,539 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:16:58,540 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:16:58,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:16:58,541 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:16:58,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-11-23 14:16:58,880 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2021-11-23 14:16:58,880 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:16:58,883 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 50 conjunts are in the unsatisfiable core [2021-11-23 14:16:58,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:16:59,024 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:16:59,129 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:59,129 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:59,147 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:16:59,147 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:16:59,274 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:16:59,275 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:17:00,291 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:17:00,292 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:17:00,295 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 299 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:00,295 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:28,442 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2021-11-23 14:17:28,447 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 83 [2021-11-23 14:17:28,601 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 294 refuted. 5 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:28,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1667586176] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:28,601 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:28,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 28] total 46 [2021-11-23 14:17:28,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749290419] [2021-11-23 14:17:28,602 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:28,602 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:28,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:28,603 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2021-11-23 14:17:28,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:28,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568528976] [2021-11-23 14:17:28,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:28,603 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:28,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:28,606 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:28,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:28,608 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:28,652 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:28,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-11-23 14:17:28,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=1962, Unknown=32, NotChecked=0, Total=2162 [2021-11-23 14:17:28,653 INFO L87 Difference]: Start difference. First operand 78 states and 96 transitions. cyclomatic complexity: 22 Second operand has 47 states, 46 states have (on average 2.1739130434782608) internal successors, (100), 47 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:29,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:29,928 INFO L93 Difference]: Finished difference Result 142 states and 165 transitions. [2021-11-23 14:17:29,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-23 14:17:29,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142 states and 165 transitions. [2021-11-23 14:17:29,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:29,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142 states to 141 states and 163 transitions. [2021-11-23 14:17:29,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-23 14:17:29,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-23 14:17:29,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141 states and 163 transitions. [2021-11-23 14:17:29,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:29,932 INFO L681 BuchiCegarLoop]: Abstraction has 141 states and 163 transitions. [2021-11-23 14:17:29,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states and 163 transitions. [2021-11-23 14:17:29,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 73. [2021-11-23 14:17:29,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2191780821917808) internal successors, (89), 72 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:29,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 89 transitions. [2021-11-23 14:17:29,935 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 89 transitions. [2021-11-23 14:17:29,935 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 89 transitions. [2021-11-23 14:17:29,935 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-11-23 14:17:29,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 89 transitions. [2021-11-23 14:17:29,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:29,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:29,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:29,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:29,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:29,937 INFO L791 eck$LassoCheckResult]: Stem: 16834#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16845#L367 assume !(main_~length~0#1 < 1); 16836#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16837#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16906#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16905#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16904#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16903#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16901#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16900#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16899#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16898#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16897#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16896#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16895#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16894#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16893#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16892#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16891#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16890#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16889#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16888#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16887#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16886#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16885#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16884#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16883#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16882#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16880#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16877#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16875#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16874#L370-4 main_~j~0#1 := 0; 16873#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16872#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16850#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16843#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16871#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16870#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16869#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16868#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16867#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16865#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16863#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16857#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16855#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16854#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16853#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16841#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16842#L378-2 [2021-11-23 14:17:29,937 INFO L793 eck$LassoCheckResult]: Loop: 16842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16852#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16842#L378-2 [2021-11-23 14:17:29,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:29,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1431257624, now seen corresponding path program 22 times [2021-11-23 14:17:29,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:29,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013662433] [2021-11-23 14:17:29,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:29,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:29,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:30,649 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:30,649 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:30,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013662433] [2021-11-23 14:17:30,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013662433] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:30,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1342773794] [2021-11-23 14:17:30,654 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:17:30,654 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:30,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:30,657 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:30,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-11-23 14:17:30,739 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:17:30,739 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:17:30,740 INFO L263 TraceCheckSpWp]: Trace formula consists of 287 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-23 14:17:30,742 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:31,477 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:31,478 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:31,868 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:31,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1342773794] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:31,868 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:31,868 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27, 27] total 65 [2021-11-23 14:17:31,868 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255384373] [2021-11-23 14:17:31,868 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:31,869 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:31,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:31,869 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2021-11-23 14:17:31,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:31,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982081683] [2021-11-23 14:17:31,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:31,870 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:31,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:31,872 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:31,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:31,875 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:31,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:31,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2021-11-23 14:17:31,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=721, Invalid=3439, Unknown=0, NotChecked=0, Total=4160 [2021-11-23 14:17:31,923 INFO L87 Difference]: Start difference. First operand 73 states and 89 transitions. cyclomatic complexity: 19 Second operand has 65 states, 65 states have (on average 2.276923076923077) internal successors, (148), 65 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:32,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:32,659 INFO L93 Difference]: Finished difference Result 95 states and 111 transitions. [2021-11-23 14:17:32,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-23 14:17:32,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 111 transitions. [2021-11-23 14:17:32,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:32,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 71 states and 87 transitions. [2021-11-23 14:17:32,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-23 14:17:32,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-23 14:17:32,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 87 transitions. [2021-11-23 14:17:32,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:32,661 INFO L681 BuchiCegarLoop]: Abstraction has 71 states and 87 transitions. [2021-11-23 14:17:32,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 87 transitions. [2021-11-23 14:17:32,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 67. [2021-11-23 14:17:32,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2238805970149254) internal successors, (82), 66 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:32,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 82 transitions. [2021-11-23 14:17:32,663 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 82 transitions. [2021-11-23 14:17:32,663 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 82 transitions. [2021-11-23 14:17:32,663 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-11-23 14:17:32,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 82 transitions. [2021-11-23 14:17:32,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:32,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:32,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:32,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:32,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:32,665 INFO L791 eck$LassoCheckResult]: Stem: 17474#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17485#L367 assume !(main_~length~0#1 < 1); 17476#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17477#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17478#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17486#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17487#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17488#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17540#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17539#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17538#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17537#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17536#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17535#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17533#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17532#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17531#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17530#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17529#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17528#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17527#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17526#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17523#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17521#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17520#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17517#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17514#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17492#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17493#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17491#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17483#L370-4 main_~j~0#1 := 0; 17484#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17481#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17482#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17490#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17511#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17510#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17509#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17508#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17506#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17504#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17502#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17500#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17499#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17498#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17497#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17496#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17495#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17479#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17480#L378-2 [2021-11-23 14:17:32,665 INFO L793 eck$LassoCheckResult]: Loop: 17480#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17494#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17480#L378-2 [2021-11-23 14:17:32,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:32,666 INFO L85 PathProgramCache]: Analyzing trace with hash 1959713611, now seen corresponding path program 19 times [2021-11-23 14:17:32,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:32,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498099187] [2021-11-23 14:17:32,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:32,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:32,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:33,297 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:33,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:33,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498099187] [2021-11-23 14:17:33,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498099187] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:33,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [851886597] [2021-11-23 14:17:33,298 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:17:33,298 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:33,298 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:33,323 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:33,324 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-11-23 14:17:33,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:33,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 55 conjunts are in the unsatisfiable core [2021-11-23 14:17:33,393 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:33,926 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:17:34,108 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:17:34,109 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:17:34,852 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:17:34,855 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:34,856 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:35,138 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-11-23 14:17:35,140 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 36 [2021-11-23 14:17:35,299 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:35,299 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [851886597] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:35,299 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:35,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 28] total 58 [2021-11-23 14:17:35,300 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303582437] [2021-11-23 14:17:35,300 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:35,300 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:35,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:35,300 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2021-11-23 14:17:35,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:35,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45818958] [2021-11-23 14:17:35,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:35,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:35,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:35,302 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:35,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:35,304 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:35,342 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:35,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2021-11-23 14:17:35,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=3209, Unknown=0, NotChecked=0, Total=3422 [2021-11-23 14:17:35,344 INFO L87 Difference]: Start difference. First operand 67 states and 82 transitions. cyclomatic complexity: 18 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:36,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:36,995 INFO L93 Difference]: Finished difference Result 71 states and 86 transitions. [2021-11-23 14:17:36,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-23 14:17:36,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 86 transitions. [2021-11-23 14:17:36,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:36,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 85 transitions. [2021-11-23 14:17:36,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-23 14:17:36,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-23 14:17:36,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 85 transitions. [2021-11-23 14:17:36,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:36,998 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 85 transitions. [2021-11-23 14:17:36,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 85 transitions. [2021-11-23 14:17:36,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2021-11-23 14:17:36,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.2173913043478262) internal successors, (84), 68 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:36,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 84 transitions. [2021-11-23 14:17:36,999 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 84 transitions. [2021-11-23 14:17:36,999 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 84 transitions. [2021-11-23 14:17:37,000 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-11-23 14:17:37,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 84 transitions. [2021-11-23 14:17:37,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:37,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:37,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:37,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:37,001 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:37,001 INFO L791 eck$LassoCheckResult]: Stem: 18084#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18095#L367 assume !(main_~length~0#1 < 1); 18086#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18087#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18088#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18096#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18097#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18098#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18133#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18132#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18131#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18130#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18128#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18127#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18125#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18123#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18122#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18121#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18119#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18118#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18117#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18116#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18115#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18114#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18113#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18112#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18111#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18110#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18109#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18107#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18106#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18103#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18104#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18102#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18093#L370-4 main_~j~0#1 := 0; 18094#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18099#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18100#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18091#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18092#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18152#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18148#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18147#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18146#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18144#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18143#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18142#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18140#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18139#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18089#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18090#L378-2 [2021-11-23 14:17:37,001 INFO L793 eck$LassoCheckResult]: Loop: 18090#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18134#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18090#L378-2 [2021-11-23 14:17:37,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:37,002 INFO L85 PathProgramCache]: Analyzing trace with hash 2089107792, now seen corresponding path program 20 times [2021-11-23 14:17:37,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:37,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522894719] [2021-11-23 14:17:37,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:37,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:37,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:37,628 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:37,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:37,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522894719] [2021-11-23 14:17:37,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522894719] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:37,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2084697821] [2021-11-23 14:17:37,629 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:17:37,629 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:37,629 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:37,630 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:37,631 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-11-23 14:17:37,706 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:17:37,706 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:17:37,708 INFO L263 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 53 conjunts are in the unsatisfiable core [2021-11-23 14:17:37,710 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:37,877 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-23 14:17:38,542 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-23 14:17:38,545 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:38,545 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:38,717 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:17:38,719 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:17:38,888 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:38,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2084697821] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:38,889 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:38,889 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 28, 28] total 43 [2021-11-23 14:17:38,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346814423] [2021-11-23 14:17:38,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:38,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:38,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:38,890 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2021-11-23 14:17:38,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:38,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12989826] [2021-11-23 14:17:38,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:38,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:38,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:38,892 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:38,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:38,894 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:38,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:38,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-23 14:17:38,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1763, Unknown=0, NotChecked=0, Total=1892 [2021-11-23 14:17:38,938 INFO L87 Difference]: Start difference. First operand 69 states and 84 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.255813953488372) internal successors, (97), 44 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:40,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:40,176 INFO L93 Difference]: Finished difference Result 105 states and 125 transitions. [2021-11-23 14:17:40,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-23 14:17:40,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 125 transitions. [2021-11-23 14:17:40,177 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-23 14:17:40,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 124 transitions. [2021-11-23 14:17:40,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-23 14:17:40,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-23 14:17:40,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 124 transitions. [2021-11-23 14:17:40,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:40,179 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 124 transitions. [2021-11-23 14:17:40,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 124 transitions. [2021-11-23 14:17:40,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 77. [2021-11-23 14:17:40,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.2337662337662338) internal successors, (95), 76 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:40,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 95 transitions. [2021-11-23 14:17:40,182 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 95 transitions. [2021-11-23 14:17:40,182 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 95 transitions. [2021-11-23 14:17:40,182 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-11-23 14:17:40,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 95 transitions. [2021-11-23 14:17:40,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:40,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:40,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:40,184 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:40,184 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:40,184 INFO L791 eck$LassoCheckResult]: Stem: 18703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18714#L367 assume !(main_~length~0#1 < 1); 18705#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18706#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18707#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18715#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18717#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18722#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18753#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18752#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18751#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18750#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18749#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18747#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18745#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18744#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18741#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18738#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18737#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18736#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18735#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18732#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18731#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18730#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18729#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18727#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18726#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18723#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18712#L370-4 main_~j~0#1 := 0; 18713#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18775#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18719#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18710#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18774#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18772#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18770#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18768#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18766#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18764#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18762#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18761#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18760#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18759#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18758#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18757#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18756#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18755#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18708#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18709#L378-2 [2021-11-23 14:17:40,185 INFO L793 eck$LassoCheckResult]: Loop: 18709#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18754#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18709#L378-2 [2021-11-23 14:17:40,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:40,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1882864149, now seen corresponding path program 21 times [2021-11-23 14:17:40,185 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:40,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464294961] [2021-11-23 14:17:40,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:40,186 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:40,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:40,971 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 133 proven. 233 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:40,971 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:40,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464294961] [2021-11-23 14:17:40,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464294961] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:40,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1460020855] [2021-11-23 14:17:40,972 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:17:40,972 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:40,972 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:40,974 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:40,975 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-11-23 14:17:41,194 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2021-11-23 14:17:41,194 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:17:41,197 INFO L263 TraceCheckSpWp]: Trace formula consists of 304 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-23 14:17:41,199 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:42,067 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 156 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:42,067 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:42,525 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 156 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:42,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1460020855] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:42,525 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:42,526 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29, 29] total 70 [2021-11-23 14:17:42,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169985459] [2021-11-23 14:17:42,526 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:42,526 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:42,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:42,527 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2021-11-23 14:17:42,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:42,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86166525] [2021-11-23 14:17:42,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:42,527 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:42,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:42,530 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:42,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:42,532 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:42,584 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:42,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2021-11-23 14:17:42,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=832, Invalid=3998, Unknown=0, NotChecked=0, Total=4830 [2021-11-23 14:17:42,586 INFO L87 Difference]: Start difference. First operand 77 states and 95 transitions. cyclomatic complexity: 22 Second operand has 70 states, 70 states have (on average 2.2857142857142856) internal successors, (160), 70 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:43,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:43,505 INFO L93 Difference]: Finished difference Result 108 states and 127 transitions. [2021-11-23 14:17:43,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-23 14:17:43,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 127 transitions. [2021-11-23 14:17:43,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:43,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 82 states and 101 transitions. [2021-11-23 14:17:43,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:17:43,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:17:43,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 101 transitions. [2021-11-23 14:17:43,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:43,508 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 101 transitions. [2021-11-23 14:17:43,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 101 transitions. [2021-11-23 14:17:43,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 79. [2021-11-23 14:17:43,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.2278481012658229) internal successors, (97), 78 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:43,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 97 transitions. [2021-11-23 14:17:43,511 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-11-23 14:17:43,511 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-11-23 14:17:43,511 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-11-23 14:17:43,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 97 transitions. [2021-11-23 14:17:43,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:43,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:43,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:43,513 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:43,513 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:43,513 INFO L791 eck$LassoCheckResult]: Stem: 19397#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19408#L367 assume !(main_~length~0#1 < 1); 19399#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19400#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19401#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19409#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19414#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19410#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19411#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19474#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19473#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19472#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19471#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19470#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19469#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19468#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19467#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19466#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19465#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19464#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19463#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19462#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19461#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19458#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19457#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19455#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19453#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19452#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19451#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19450#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19449#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19447#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19446#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19444#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19437#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19443#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19440#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19439#L370-4 main_~j~0#1 := 0; 19412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19404#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19435#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19434#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19433#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19432#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19431#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19429#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19428#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19427#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19426#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19425#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19424#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19423#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19422#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19421#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19420#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19419#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19418#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19416#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19415#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19402#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19403#L378-2 [2021-11-23 14:17:43,514 INFO L793 eck$LassoCheckResult]: Loop: 19403#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19417#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19403#L378-2 [2021-11-23 14:17:43,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:43,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1975564248, now seen corresponding path program 23 times [2021-11-23 14:17:43,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:43,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965908531] [2021-11-23 14:17:43,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:43,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:43,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:44,292 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:44,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:44,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965908531] [2021-11-23 14:17:44,293 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965908531] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:44,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [485694965] [2021-11-23 14:17:44,293 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:17:44,293 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:44,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:44,294 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:44,295 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-11-23 14:17:44,450 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2021-11-23 14:17:44,451 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:17:44,454 INFO L263 TraceCheckSpWp]: Trace formula consists of 309 conjuncts, 56 conjunts are in the unsatisfiable core [2021-11-23 14:17:44,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:44,630 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:17:44,769 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-23 14:17:44,769 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 38 treesize of output 37 [2021-11-23 14:17:44,803 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-23 14:17:44,804 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 38 treesize of output 37 [2021-11-23 14:17:46,737 INFO L354 Elim1Store]: treesize reduction 46, result has 6.1 percent of original size [2021-11-23 14:17:46,738 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 30 [2021-11-23 14:17:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:46,743 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:47,750 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:17:47,752 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:17:47,931 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 1 proven. 377 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:17:47,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [485694965] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:47,931 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:47,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 30] total 50 [2021-11-23 14:17:47,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421903965] [2021-11-23 14:17:47,931 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:47,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:47,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:47,932 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2021-11-23 14:17:47,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:47,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478317657] [2021-11-23 14:17:47,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:47,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:47,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:47,934 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:47,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:47,936 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:47,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:47,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-11-23 14:17:47,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=2353, Unknown=0, NotChecked=0, Total=2550 [2021-11-23 14:17:47,994 INFO L87 Difference]: Start difference. First operand 79 states and 97 transitions. cyclomatic complexity: 22 Second operand has 51 states, 50 states have (on average 2.16) internal successors, (108), 51 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:48,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:48,872 INFO L93 Difference]: Finished difference Result 166 states and 191 transitions. [2021-11-23 14:17:48,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-23 14:17:48,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166 states and 191 transitions. [2021-11-23 14:17:48,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:48,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166 states to 165 states and 189 transitions. [2021-11-23 14:17:48,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:17:48,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:17:48,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 165 states and 189 transitions. [2021-11-23 14:17:48,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:48,876 INFO L681 BuchiCegarLoop]: Abstraction has 165 states and 189 transitions. [2021-11-23 14:17:48,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states and 189 transitions. [2021-11-23 14:17:48,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 88. [2021-11-23 14:17:48,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.2613636363636365) internal successors, (111), 87 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:48,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 111 transitions. [2021-11-23 14:17:48,879 INFO L704 BuchiCegarLoop]: Abstraction has 88 states and 111 transitions. [2021-11-23 14:17:48,879 INFO L587 BuchiCegarLoop]: Abstraction has 88 states and 111 transitions. [2021-11-23 14:17:48,879 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-11-23 14:17:48,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 111 transitions. [2021-11-23 14:17:48,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:48,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:48,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:48,881 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:48,881 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:48,882 INFO L791 eck$LassoCheckResult]: Stem: 20111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20122#L367 assume !(main_~length~0#1 < 1); 20113#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20114#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20123#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20126#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20124#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20125#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20196#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20195#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20194#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20193#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20192#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20191#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20186#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20183#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20182#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20180#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20178#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20177#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20176#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20175#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20174#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20173#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20172#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20171#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20170#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20169#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20167#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20168#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20161#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20160#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20116#L370-4 main_~j~0#1 := 0; 20117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20120#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20127#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20148#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20147#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20146#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20144#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20143#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20142#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20140#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20139#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20134#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20129#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20128#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20118#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20119#L378-2 [2021-11-23 14:17:48,882 INFO L793 eck$LassoCheckResult]: Loop: 20119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20130#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20119#L378-2 [2021-11-23 14:17:48,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:48,883 INFO L85 PathProgramCache]: Analyzing trace with hash 214087323, now seen corresponding path program 24 times [2021-11-23 14:17:48,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:48,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992267966] [2021-11-23 14:17:48,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:48,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:48,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:49,688 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:49,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:49,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992267966] [2021-11-23 14:17:49,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992267966] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:49,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1499431615] [2021-11-23 14:17:49,688 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:17:49,689 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:49,689 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:49,691 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:49,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-11-23 14:17:50,106 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2021-11-23 14:17:50,106 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:17:50,110 INFO L263 TraceCheckSpWp]: Trace formula consists of 325 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-23 14:17:50,112 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:50,656 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:17:52,127 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-23 14:17:52,127 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 21 [2021-11-23 14:17:52,177 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 144 proven. 259 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:52,178 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:53,880 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 25 [2021-11-23 14:17:53,882 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 36 [2021-11-23 14:17:53,996 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 132 proven. 271 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:53,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1499431615] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:53,997 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:53,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31, 31] total 76 [2021-11-23 14:17:53,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938342610] [2021-11-23 14:17:53,997 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:53,998 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:53,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:53,998 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2021-11-23 14:17:53,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:53,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468192905] [2021-11-23 14:17:53,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:53,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:54,002 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:54,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:54,005 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:54,065 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:54,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2021-11-23 14:17:54,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=648, Invalid=5204, Unknown=0, NotChecked=0, Total=5852 [2021-11-23 14:17:54,066 INFO L87 Difference]: Start difference. First operand 88 states and 111 transitions. cyclomatic complexity: 28 Second operand has 77 states, 76 states have (on average 2.223684210526316) internal successors, (169), 77 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:56,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:17:56,541 INFO L93 Difference]: Finished difference Result 145 states and 170 transitions. [2021-11-23 14:17:56,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2021-11-23 14:17:56,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145 states and 170 transitions. [2021-11-23 14:17:56,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:56,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145 states to 114 states and 138 transitions. [2021-11-23 14:17:56,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:17:56,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:17:56,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114 states and 138 transitions. [2021-11-23 14:17:56,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:17:56,557 INFO L681 BuchiCegarLoop]: Abstraction has 114 states and 138 transitions. [2021-11-23 14:17:56,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states and 138 transitions. [2021-11-23 14:17:56,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 91. [2021-11-23 14:17:56,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.2637362637362637) internal successors, (115), 90 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:17:56,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 115 transitions. [2021-11-23 14:17:56,560 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 115 transitions. [2021-11-23 14:17:56,560 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 115 transitions. [2021-11-23 14:17:56,560 INFO L425 BuchiCegarLoop]: ======== Iteration 53============ [2021-11-23 14:17:56,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 115 transitions. [2021-11-23 14:17:56,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:17:56,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:17:56,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:17:56,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:17:56,562 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:17:56,562 INFO L791 eck$LassoCheckResult]: Stem: 20944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20955#L367 assume !(main_~length~0#1 < 1); 20946#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20947#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20956#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20959#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20957#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20958#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21032#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21029#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21026#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21025#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21024#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21023#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21021#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21020#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21018#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21017#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21016#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21015#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21014#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21013#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21012#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21011#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21010#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21008#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21007#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21005#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21002#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21004#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20991#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20994#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20986#L370-4 main_~j~0#1 := 0; 20960#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20953#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20954#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20961#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20985#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20984#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20982#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20981#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20980#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20979#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20978#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20977#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20976#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20974#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20972#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20971#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20970#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20969#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20968#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20967#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20965#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20951#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20952#L378-2 [2021-11-23 14:17:56,562 INFO L793 eck$LassoCheckResult]: Loop: 20952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20966#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20952#L378-2 [2021-11-23 14:17:56,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:56,562 INFO L85 PathProgramCache]: Analyzing trace with hash 236719577, now seen corresponding path program 25 times [2021-11-23 14:17:56,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:56,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449507143] [2021-11-23 14:17:56,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:56,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:56,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:57,457 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:57,457 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:17:57,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449507143] [2021-11-23 14:17:57,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449507143] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:17:57,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1309504304] [2021-11-23 14:17:57,457 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-23 14:17:57,458 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:17:57,458 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:17:57,460 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:17:57,488 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-11-23 14:17:57,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:17:57,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 320 conjuncts, 61 conjunts are in the unsatisfiable core [2021-11-23 14:17:57,567 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:17:58,332 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-23 14:17:59,370 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-23 14:17:59,373 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:59,373 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:17:59,563 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:17:59,565 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:17:59,749 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:17:59,750 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1309504304] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:17:59,750 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:17:59,750 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 30] total 62 [2021-11-23 14:17:59,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614014210] [2021-11-23 14:17:59,750 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:17:59,750 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:17:59,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:17:59,751 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 49 times [2021-11-23 14:17:59,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:17:59,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152447462] [2021-11-23 14:17:59,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:17:59,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:17:59,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:59,756 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:17:59,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:17:59,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:17:59,814 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:17:59,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2021-11-23 14:17:59,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=229, Invalid=3677, Unknown=0, NotChecked=0, Total=3906 [2021-11-23 14:17:59,815 INFO L87 Difference]: Start difference. First operand 91 states and 115 transitions. cyclomatic complexity: 29 Second operand has 63 states, 62 states have (on average 2.3548387096774195) internal successors, (146), 63 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:18:01,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:18:01,932 INFO L93 Difference]: Finished difference Result 180 states and 222 transitions. [2021-11-23 14:18:01,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-23 14:18:01,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 222 transitions. [2021-11-23 14:18:01,933 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 28 [2021-11-23 14:18:01,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 179 states and 221 transitions. [2021-11-23 14:18:01,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47 [2021-11-23 14:18:01,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2021-11-23 14:18:01,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 221 transitions. [2021-11-23 14:18:01,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:18:01,935 INFO L681 BuchiCegarLoop]: Abstraction has 179 states and 221 transitions. [2021-11-23 14:18:01,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 221 transitions. [2021-11-23 14:18:01,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 150. [2021-11-23 14:18:01,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.2666666666666666) internal successors, (190), 149 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:18:01,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 190 transitions. [2021-11-23 14:18:01,940 INFO L704 BuchiCegarLoop]: Abstraction has 150 states and 190 transitions. [2021-11-23 14:18:01,940 INFO L587 BuchiCegarLoop]: Abstraction has 150 states and 190 transitions. [2021-11-23 14:18:01,940 INFO L425 BuchiCegarLoop]: ======== Iteration 54============ [2021-11-23 14:18:01,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 190 transitions. [2021-11-23 14:18:01,941 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2021-11-23 14:18:01,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:18:01,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:18:01,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 12, 12, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:18:01,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-23 14:18:01,942 INFO L791 eck$LassoCheckResult]: Stem: 21715#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21726#L367 assume !(main_~length~0#1 < 1); 21717#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21718#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21719#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21727#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21776#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21775#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21774#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21773#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21770#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21769#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21768#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21767#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21766#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21765#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21764#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21763#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21762#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21761#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21760#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21759#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21758#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21756#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21755#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21754#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21753#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21752#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21751#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21750#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21749#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21748#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21747#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21745#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21741#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21742#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21728#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21729#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21810#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21808#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21807#L370-4 main_~j~0#1 := 0; 21806#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21805#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21803#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21801#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21799#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21798#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21797#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21796#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21795#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21794#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21793#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21792#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21791#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21790#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21789#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21787#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21785#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21778#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21780#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21842#L378-2 [2021-11-23 14:18:01,943 INFO L793 eck$LassoCheckResult]: Loop: 21842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21844#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21841#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21842#L378-2 [2021-11-23 14:18:01,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:18:01,943 INFO L85 PathProgramCache]: Analyzing trace with hash 1273617104, now seen corresponding path program 26 times [2021-11-23 14:18:01,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:18:01,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436199550] [2021-11-23 14:18:01,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:18:01,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:18:01,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:18:02,711 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 0 proven. 419 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:18:02,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:18:02,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436199550] [2021-11-23 14:18:02,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436199550] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:18:02,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [274788154] [2021-11-23 14:18:02,712 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-23 14:18:02,712 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:18:02,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:18:02,714 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:18:02,715 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-11-23 14:18:02,801 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-23 14:18:02,801 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:18:02,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 325 conjuncts, 56 conjunts are in the unsatisfiable core [2021-11-23 14:18:02,805 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:18:02,973 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:18:03,030 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:18:03,030 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:18:03,048 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:18:03,048 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:18:03,197 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:18:03,197 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:18:04,438 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:18:04,438 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:18:04,495 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 1 proven. 418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:18:04,495 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:18:17,273 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int)) (or (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2021-11-23 14:18:18,163 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2021-11-23 14:18:19,050 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_419| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_419|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|))))) is different from false [2021-11-23 14:24:19,325 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 39 [2021-11-23 14:24:19,328 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 351 treesize of output 343 [2021-11-23 14:24:19,667 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 40 not checked. [2021-11-23 14:24:19,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [274788154] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:24:19,667 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:24:19,668 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31, 32] total 64 [2021-11-23 14:24:19,668 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375453059] [2021-11-23 14:24:19,668 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:24:19,668 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:24:19,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:24:19,668 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2021-11-23 14:24:19,668 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:24:19,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723649438] [2021-11-23 14:24:19,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:24:19,669 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:24:19,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:24:19,671 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:24:19,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:24:19,673 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:24:19,758 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:24:19,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2021-11-23 14:24:19,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=3528, Unknown=33, NotChecked=366, Total=4160 [2021-11-23 14:24:19,759 INFO L87 Difference]: Start difference. First operand 150 states and 190 transitions. cyclomatic complexity: 47 Second operand has 65 states, 64 states have (on average 2.140625) internal successors, (137), 65 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:24:21,003 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (<= 12 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_419| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_419|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))))) is different from false [2021-11-23 14:24:21,671 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (<= 12 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-11-23 14:24:33,674 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (<= 12 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int)) (or (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) (= 0 (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))))) is different from false [2021-11-23 14:24:34,452 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (exists ((|v_ULTIMATE.start_main_~i~0#1_740| Int)) (and (<= 12 |v_ULTIMATE.start_main_~i~0#1_740|) (<= (+ |v_ULTIMATE.start_main_~i~0#1_740| 1) |c_ULTIMATE.start_main_~i~0#1|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_740| 4))) 0))) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_419| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_419|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))))) is different from false [2021-11-23 14:24:35,236 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (not (= 44 (* 4 |c_ULTIMATE.start_main_~i~0#1|))) (exists ((|v_ULTIMATE.start_main_~i~0#1_740| Int)) (and (<= 12 |v_ULTIMATE.start_main_~i~0#1_740|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_740| 4))) 0))) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_419| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_419|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))))) is different from false [2021-11-23 14:24:36,053 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (exists ((|v_ULTIMATE.start_main_~i~0#1_740| Int)) (and (<= 12 |v_ULTIMATE.start_main_~i~0#1_740|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_740| 4))) 0))) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-11-23 14:24:36,868 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_742| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (<= 0 (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_742| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|))) (< |v_ULTIMATE.start_main_~i~0#1_742| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-11-23 14:24:37,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:24:37,043 INFO L93 Difference]: Finished difference Result 324 states and 376 transitions. [2021-11-23 14:24:37,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2021-11-23 14:24:37,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324 states and 376 transitions. [2021-11-23 14:24:37,045 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2021-11-23 14:24:37,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324 states to 320 states and 372 transitions. [2021-11-23 14:24:37,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57 [2021-11-23 14:24:37,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57 [2021-11-23 14:24:37,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 320 states and 372 transitions. [2021-11-23 14:24:37,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:24:37,049 INFO L681 BuchiCegarLoop]: Abstraction has 320 states and 372 transitions. [2021-11-23 14:24:37,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states and 372 transitions. [2021-11-23 14:24:37,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 169. [2021-11-23 14:24:37,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 169 states, 169 states have (on average 1.301775147928994) internal successors, (220), 168 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:24:37,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 220 transitions. [2021-11-23 14:24:37,054 INFO L704 BuchiCegarLoop]: Abstraction has 169 states and 220 transitions. [2021-11-23 14:24:37,054 INFO L587 BuchiCegarLoop]: Abstraction has 169 states and 220 transitions. [2021-11-23 14:24:37,054 INFO L425 BuchiCegarLoop]: ======== Iteration 55============ [2021-11-23 14:24:37,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 169 states and 220 transitions. [2021-11-23 14:24:37,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2021-11-23 14:24:37,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:24:37,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:24:37,056 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 12, 12, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:24:37,056 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:24:37,056 INFO L791 eck$LassoCheckResult]: Stem: 22708#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22719#L367 assume !(main_~length~0#1 < 1); 22710#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22711#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22712#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22720#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22721#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22722#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22772#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22771#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22770#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22769#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22768#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22767#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22766#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22765#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22764#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22763#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22762#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22761#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22760#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22759#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22758#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22757#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22756#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22755#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22754#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22753#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22752#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22751#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22750#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22749#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22747#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22745#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22743#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22741#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22733#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22726#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22728#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22840#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22838#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22837#L370-4 main_~j~0#1 := 0; 22836#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22835#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22834#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22833#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22832#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22831#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22830#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22829#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22828#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22827#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22826#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22825#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22824#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22823#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22822#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22821#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22819#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22818#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22776#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22778#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22781#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22714#L378-2 [2021-11-23 14:24:37,056 INFO L793 eck$LassoCheckResult]: Loop: 22714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22853#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22714#L378-2 [2021-11-23 14:24:37,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:24:37,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1810277228, now seen corresponding path program 27 times [2021-11-23 14:24:37,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:24:37,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143145008] [2021-11-23 14:24:37,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:24:37,058 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:24:37,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:24:37,677 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 0 proven. 419 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:24:37,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:24:37,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143145008] [2021-11-23 14:24:37,677 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143145008] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:24:37,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87208595] [2021-11-23 14:24:37,677 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-23 14:24:37,678 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:24:37,678 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:24:37,679 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:24:37,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-11-23 14:24:37,990 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2021-11-23 14:24:37,991 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:24:37,995 INFO L263 TraceCheckSpWp]: Trace formula consists of 325 conjuncts, 56 conjunts are in the unsatisfiable core [2021-11-23 14:24:37,996 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:24:38,196 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:24:38,251 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:24:38,251 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:24:38,310 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:24:38,310 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:24:38,325 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-23 14:24:38,325 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-23 14:24:39,328 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-23 14:24:39,328 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-23 14:24:39,369 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 2 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:24:39,369 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:25:17,514 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_771| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_771| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_771| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))))) is different from false [2021-11-23 14:25:17,532 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 27 [2021-11-23 14:25:17,535 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 79 [2021-11-23 14:25:17,766 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 1 proven. 404 refuted. 0 times theorem prover too weak. 1 trivial. 13 not checked. [2021-11-23 14:25:17,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87208595] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:25:17,766 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:25:17,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 30, 30] total 62 [2021-11-23 14:25:17,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565605071] [2021-11-23 14:25:17,766 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:25:17,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:25:17,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:25:17,767 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 50 times [2021-11-23 14:25:17,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:25:17,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549190265] [2021-11-23 14:25:17,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:25:17,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:25:17,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:25:17,770 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:25:17,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:25:17,772 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:25:17,829 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:25:17,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2021-11-23 14:25:17,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=260, Invalid=3525, Unknown=1, NotChecked=120, Total=3906 [2021-11-23 14:25:17,830 INFO L87 Difference]: Start difference. First operand 169 states and 220 transitions. cyclomatic complexity: 58 Second operand has 63 states, 62 states have (on average 2.193548387096774) internal successors, (136), 63 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:25:30,476 WARN L838 $PredicateComparison]: unable to prove that (and (<= |c_ULTIMATE.start_main_~i~0#1| 11) (forall ((|v_ULTIMATE.start_main_~i~0#1_771| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_771| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_771| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ 44 |c_ULTIMATE.start_main_~arr~0#1.offset|)))))) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= 11 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-11-23 14:25:46,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:25:46,728 INFO L93 Difference]: Finished difference Result 340 states and 402 transitions. [2021-11-23 14:25:46,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-11-23 14:25:46,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 340 states and 402 transitions. [2021-11-23 14:25:46,729 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 28 [2021-11-23 14:25:46,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 340 states to 337 states and 399 transitions. [2021-11-23 14:25:46,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59 [2021-11-23 14:25:46,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59 [2021-11-23 14:25:46,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 337 states and 399 transitions. [2021-11-23 14:25:46,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:25:46,732 INFO L681 BuchiCegarLoop]: Abstraction has 337 states and 399 transitions. [2021-11-23 14:25:46,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states and 399 transitions. [2021-11-23 14:25:46,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 158. [2021-11-23 14:25:46,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 158 states, 158 states have (on average 1.2784810126582278) internal successors, (202), 157 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:25:46,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 202 transitions. [2021-11-23 14:25:46,736 INFO L704 BuchiCegarLoop]: Abstraction has 158 states and 202 transitions. [2021-11-23 14:25:46,736 INFO L587 BuchiCegarLoop]: Abstraction has 158 states and 202 transitions. [2021-11-23 14:25:46,736 INFO L425 BuchiCegarLoop]: ======== Iteration 56============ [2021-11-23 14:25:46,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 158 states and 202 transitions. [2021-11-23 14:25:46,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2021-11-23 14:25:46,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:25:46,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:25:46,738 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 13, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:25:46,738 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-23 14:25:46,738 INFO L791 eck$LassoCheckResult]: Stem: 23791#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 23792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 23802#L367 assume !(main_~length~0#1 < 1); 23793#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 23794#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 23795#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23803#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23885#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23884#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23883#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23882#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23880#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23877#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23874#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23871#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23868#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23866#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23865#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23864#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23862#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23860#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23856#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23855#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23852#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23851#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23850#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23848#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23847#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23844#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 23843#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23841#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 23840#L370-4 main_~j~0#1 := 0; 23839#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23838#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23837#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23836#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23835#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23834#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23832#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23831#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23830#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23829#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23828#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23827#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23826#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23820#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23819#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23813#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23926#L378-2 [2021-11-23 14:25:46,739 INFO L793 eck$LassoCheckResult]: Loop: 23926#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23928#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23925#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23926#L378-2 [2021-11-23 14:25:46,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:25:46,739 INFO L85 PathProgramCache]: Analyzing trace with hash -970366194, now seen corresponding path program 28 times [2021-11-23 14:25:46,739 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:25:46,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818310366] [2021-11-23 14:25:46,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:25:46,740 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:25:46,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:25:47,577 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 0 proven. 419 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:25:47,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:25:47,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818310366] [2021-11-23 14:25:47,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818310366] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:25:47,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1252563669] [2021-11-23 14:25:47,577 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:25:47,578 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:25:47,578 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:25:47,580 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:25:47,598 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2021-11-23 14:25:47,682 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:25:47,682 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:25:47,685 INFO L263 TraceCheckSpWp]: Trace formula consists of 320 conjuncts, 62 conjunts are in the unsatisfiable core [2021-11-23 14:25:47,688 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:25:48,462 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:25:48,613 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:25:48,613 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:25:48,629 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-23 14:25:48,630 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-23 14:25:48,791 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-23 14:25:48,791 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-23 14:25:50,009 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-23 14:25:50,009 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 13 [2021-11-23 14:25:50,012 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 1 proven. 418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:25:50,012 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:26:02,039 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2021-11-23 14:26:02,041 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 83 [2021-11-23 14:26:02,187 INFO L134 CoverageAnalysis]: Checked inductivity of 419 backedges. 1 proven. 418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:02,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1252563669] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:26:02,187 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:26:02,187 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 33, 32] total 67 [2021-11-23 14:26:02,187 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139887740] [2021-11-23 14:26:02,187 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:26:02,188 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:26:02,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:02,188 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 4 times [2021-11-23 14:26:02,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:02,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605509413] [2021-11-23 14:26:02,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:02,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:02,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:02,190 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:26:02,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:02,192 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:26:02,257 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:26:02,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2021-11-23 14:26:02,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=4262, Unknown=18, NotChecked=0, Total=4556 [2021-11-23 14:26:02,258 INFO L87 Difference]: Start difference. First operand 158 states and 202 transitions. cyclomatic complexity: 53 Second operand has 68 states, 67 states have (on average 2.253731343283582) internal successors, (151), 68 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:27,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:26:27,934 INFO L93 Difference]: Finished difference Result 289 states and 331 transitions. [2021-11-23 14:26:27,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-11-23 14:26:27,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 289 states and 331 transitions. [2021-11-23 14:26:27,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:27,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 289 states to 287 states and 327 transitions. [2021-11-23 14:26:27,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-23 14:26:27,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-23 14:26:27,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 287 states and 327 transitions. [2021-11-23 14:26:27,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:26:27,938 INFO L681 BuchiCegarLoop]: Abstraction has 287 states and 327 transitions. [2021-11-23 14:26:27,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states and 327 transitions. [2021-11-23 14:26:27,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 84. [2021-11-23 14:26:27,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.2261904761904763) internal successors, (103), 83 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:27,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 103 transitions. [2021-11-23 14:26:27,941 INFO L704 BuchiCegarLoop]: Abstraction has 84 states and 103 transitions. [2021-11-23 14:26:27,941 INFO L587 BuchiCegarLoop]: Abstraction has 84 states and 103 transitions. [2021-11-23 14:26:27,941 INFO L425 BuchiCegarLoop]: ======== Iteration 57============ [2021-11-23 14:26:27,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 103 transitions. [2021-11-23 14:26:27,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:27,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:26:27,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:26:27,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:26:27,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:26:27,943 INFO L791 eck$LassoCheckResult]: Stem: 24801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24812#L367 assume !(main_~length~0#1 < 1); 24803#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24804#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24805#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24813#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24884#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24883#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24882#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24880#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24877#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24874#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24871#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24868#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24866#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24865#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24864#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24862#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24860#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24856#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24855#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24853#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24852#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24851#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24849#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24848#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24826#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24810#L370-4 main_~j~0#1 := 0; 24811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24808#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24817#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24843#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24841#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24840#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24839#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24838#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24837#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24836#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24835#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24834#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24833#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24832#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24831#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24830#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24829#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24828#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24827#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24806#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24807#L378-2 [2021-11-23 14:26:27,943 INFO L793 eck$LassoCheckResult]: Loop: 24807#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24820#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24807#L378-2 [2021-11-23 14:26:27,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:27,943 INFO L85 PathProgramCache]: Analyzing trace with hash -989755424, now seen corresponding path program 22 times [2021-11-23 14:26:27,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:27,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293100894] [2021-11-23 14:26:27,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:27,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:27,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:26:28,763 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 157 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:28,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:26:28,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293100894] [2021-11-23 14:26:28,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293100894] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:26:28,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2004044648] [2021-11-23 14:26:28,763 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-23 14:26:28,763 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:26:28,764 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:26:28,767 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:26:28,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2021-11-23 14:26:28,850 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-23 14:26:28,850 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:26:28,852 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-23 14:26:28,854 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:26:29,718 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 182 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:29,718 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:26:30,138 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 182 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:30,138 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2004044648] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:26:30,138 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:26:30,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31, 31] total 75 [2021-11-23 14:26:30,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448489821] [2021-11-23 14:26:30,139 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:26:30,139 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:26:30,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:30,139 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 51 times [2021-11-23 14:26:30,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:30,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868781281] [2021-11-23 14:26:30,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:30,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:30,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:30,141 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:26:30,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:30,143 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:26:30,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:26:30,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2021-11-23 14:26:30,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=951, Invalid=4599, Unknown=0, NotChecked=0, Total=5550 [2021-11-23 14:26:30,211 INFO L87 Difference]: Start difference. First operand 84 states and 103 transitions. cyclomatic complexity: 23 Second operand has 75 states, 75 states have (on average 2.2933333333333334) internal successors, (172), 75 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:30,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:26:30,993 INFO L93 Difference]: Finished difference Result 117 states and 137 transitions. [2021-11-23 14:26:30,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-23 14:26:30,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 137 transitions. [2021-11-23 14:26:30,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:30,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 89 states and 109 transitions. [2021-11-23 14:26:30,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-23 14:26:30,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-23 14:26:30,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 109 transitions. [2021-11-23 14:26:30,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:26:30,995 INFO L681 BuchiCegarLoop]: Abstraction has 89 states and 109 transitions. [2021-11-23 14:26:30,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 109 transitions. [2021-11-23 14:26:30,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 84. [2021-11-23 14:26:30,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.2261904761904763) internal successors, (103), 83 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:30,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 103 transitions. [2021-11-23 14:26:30,996 INFO L704 BuchiCegarLoop]: Abstraction has 84 states and 103 transitions. [2021-11-23 14:26:30,996 INFO L587 BuchiCegarLoop]: Abstraction has 84 states and 103 transitions. [2021-11-23 14:26:30,996 INFO L425 BuchiCegarLoop]: ======== Iteration 58============ [2021-11-23 14:26:30,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 103 transitions. [2021-11-23 14:26:30,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:30,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:26:30,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:26:30,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:26:30,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:26:30,997 INFO L791 eck$LassoCheckResult]: Stem: 25548#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 25549#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 25559#L367 assume !(main_~length~0#1 < 1); 25550#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 25551#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 25552#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25560#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25561#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25631#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25630#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25629#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25628#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25627#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25626#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25625#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25624#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25623#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25622#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25621#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25620#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25616#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25615#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25614#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25613#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25602#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25601#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25600#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 25598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25590#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25593#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25592#L370-4 main_~j~0#1 := 0; 25563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25555#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25556#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25586#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25584#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25583#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25582#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25580#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25578#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25577#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25576#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25574#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25572#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25570#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25567#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25566#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25553#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25554#L378-2 [2021-11-23 14:26:30,997 INFO L793 eck$LassoCheckResult]: Loop: 25554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25568#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25554#L378-2 [2021-11-23 14:26:30,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:30,997 INFO L85 PathProgramCache]: Analyzing trace with hash -609024745, now seen corresponding path program 29 times [2021-11-23 14:26:30,997 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:30,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232184056] [2021-11-23 14:26:30,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:30,997 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:31,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:26:31,656 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 0 proven. 443 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:31,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:26:31,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232184056] [2021-11-23 14:26:31,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232184056] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:26:31,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2145062285] [2021-11-23 14:26:31,656 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-23 14:26:31,656 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:26:31,657 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:26:31,658 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:26:31,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2021-11-23 14:26:32,002 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 15 check-sat command(s) [2021-11-23 14:26:32,002 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:26:32,005 INFO L263 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 60 conjunts are in the unsatisfiable core [2021-11-23 14:26:32,007 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-23 14:26:32,145 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-23 14:26:32,251 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-23 14:26:32,251 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 38 treesize of output 37 [2021-11-23 14:26:32,272 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-23 14:26:32,272 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 38 treesize of output 37 [2021-11-23 14:26:33,941 INFO L354 Elim1Store]: treesize reduction 46, result has 6.1 percent of original size [2021-11-23 14:26:33,941 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 30 [2021-11-23 14:26:33,945 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 0 proven. 443 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:33,945 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-23 14:26:34,796 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-11-23 14:26:34,799 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2021-11-23 14:26:34,952 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 1 proven. 441 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-23 14:26:34,952 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2145062285] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-23 14:26:34,952 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-23 14:26:34,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 32] total 53 [2021-11-23 14:26:34,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821242919] [2021-11-23 14:26:34,953 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-23 14:26:34,953 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:26:34,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:34,953 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 52 times [2021-11-23 14:26:34,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:34,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098805143] [2021-11-23 14:26:34,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:34,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:34,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:34,956 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:26:34,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:26:34,958 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:26:34,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:26:34,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2021-11-23 14:26:34,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=208, Invalid=2654, Unknown=0, NotChecked=0, Total=2862 [2021-11-23 14:26:34,994 INFO L87 Difference]: Start difference. First operand 84 states and 103 transitions. cyclomatic complexity: 23 Second operand has 54 states, 53 states have (on average 2.169811320754717) internal successors, (115), 54 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:35,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:26:35,631 INFO L93 Difference]: Finished difference Result 175 states and 201 transitions. [2021-11-23 14:26:35,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-11-23 14:26:35,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 201 transitions. [2021-11-23 14:26:35,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:35,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 174 states and 199 transitions. [2021-11-23 14:26:35,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-23 14:26:35,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-23 14:26:35,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 199 transitions. [2021-11-23 14:26:35,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-23 14:26:35,633 INFO L681 BuchiCegarLoop]: Abstraction has 174 states and 199 transitions. [2021-11-23 14:26:35,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 199 transitions. [2021-11-23 14:26:35,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 91. [2021-11-23 14:26:35,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.2637362637362637) internal successors, (115), 90 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:26:35,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 115 transitions. [2021-11-23 14:26:35,639 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 115 transitions. [2021-11-23 14:26:35,639 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 115 transitions. [2021-11-23 14:26:35,639 INFO L425 BuchiCegarLoop]: ======== Iteration 59============ [2021-11-23 14:26:35,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 115 transitions. [2021-11-23 14:26:35,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-23 14:26:35,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:26:35,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:26:35,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:26:35,640 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-23 14:26:35,641 INFO L791 eck$LassoCheckResult]: Stem: 26309#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26320#L367 assume !(main_~length~0#1 < 1); 26311#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26312#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26313#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26321#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26399#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26322#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26323#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26398#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26397#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26396#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26395#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26393#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26392#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26389#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26386#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26383#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26380#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26379#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26378#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26377#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26376#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26375#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26374#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26373#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26372#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26371#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26370#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26369#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26368#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 26367#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26365#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26359#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26361#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26314#L370-4 main_~j~0#1 := 0; 26315#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26318#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26319#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26325#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26350#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26349#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26347#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26345#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26343#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26341#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26339#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26338#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26337#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26336#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26335#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26334#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26333#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26332#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26331#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26330#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26329#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26316#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26317#L378-2 [2021-11-23 14:26:35,641 INFO L793 eck$LassoCheckResult]: Loop: 26317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26327#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26317#L378-2 [2021-11-23 14:26:35,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:26:35,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1157224420, now seen corresponding path program 30 times [2021-11-23 14:26:35,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:26:35,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616073225] [2021-11-23 14:26:35,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:26:35,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:26:35,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:26:36,352 INFO L134 CoverageAnalysis]: Checked inductivity of 469 backedges. 0 proven. 469 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:26:36,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:26:36,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616073225] [2021-11-23 14:26:36,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616073225] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-23 14:26:36,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [953005665] [2021-11-23 14:26:36,353 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-23 14:26:36,353 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-23 14:26:36,353 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:26:36,355 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-23 14:26:36,381 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ea4b4746-3330-4b06-80bc-805ada60f600/bin/uautomizer-wIGwrQj20G/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2021-11-23 14:26:36,863 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2021-11-23 14:26:36,863 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-23 14:26:36,867 INFO L263 TraceCheckSpWp]: Trace formula consists of 342 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-23 14:26:36,868 INFO L286 TraceCheckSpWp]: Computing forward predicates...