./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 7e70badd Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.1-dev-7e70bad [2021-11-23 14:02:25,090 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-23 14:02:25,093 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-23 14:02:25,128 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-23 14:02:25,129 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-23 14:02:25,130 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-23 14:02:25,132 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-23 14:02:25,135 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-23 14:02:25,138 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-23 14:02:25,139 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-23 14:02:25,141 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-23 14:02:25,143 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-23 14:02:25,143 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-23 14:02:25,145 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-23 14:02:25,147 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-23 14:02:25,149 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-23 14:02:25,151 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-23 14:02:25,152 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-23 14:02:25,155 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-23 14:02:25,158 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-23 14:02:25,161 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-23 14:02:25,163 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-23 14:02:25,165 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-23 14:02:25,166 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-23 14:02:25,171 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-23 14:02:25,171 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-23 14:02:25,172 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-23 14:02:25,173 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-23 14:02:25,174 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-23 14:02:25,175 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-23 14:02:25,176 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-23 14:02:25,178 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-23 14:02:25,179 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-23 14:02:25,181 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-23 14:02:25,182 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-23 14:02:25,183 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-23 14:02:25,184 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-23 14:02:25,185 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-23 14:02:25,185 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-23 14:02:25,187 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-23 14:02:25,188 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-23 14:02:25,189 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-23 14:02:25,224 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-23 14:02:25,224 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-23 14:02:25,225 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-23 14:02:25,225 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-23 14:02:25,227 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-23 14:02:25,227 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-23 14:02:25,227 INFO L138 SettingsManager]: * Use SBE=true [2021-11-23 14:02:25,228 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-23 14:02:25,228 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-23 14:02:25,228 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-23 14:02:25,236 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-23 14:02:25,237 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-23 14:02:25,238 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-23 14:02:25,238 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-23 14:02:25,238 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-23 14:02:25,239 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-23 14:02:25,239 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-23 14:02:25,239 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-23 14:02:25,239 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-23 14:02:25,240 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-23 14:02:25,240 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-23 14:02:25,240 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-23 14:02:25,241 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-23 14:02:25,241 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-23 14:02:25,242 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-23 14:02:25,242 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-23 14:02:25,244 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-23 14:02:25,244 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-23 14:02:25,245 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-23 14:02:25,245 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-23 14:02:25,245 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-23 14:02:25,246 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-23 14:02:25,247 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-23 14:02:25,248 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2021-11-23 14:02:25,656 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-23 14:02:25,682 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-23 14:02:25,686 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-23 14:02:25,688 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-23 14:02:25,689 INFO L275 PluginConnector]: CDTParser initialized [2021-11-23 14:02:25,691 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-11-23 14:02:25,767 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/data/353b2d7cb/01e74bc04f2b4b82918846caafa3fd44/FLAGfb1704a09 [2021-11-23 14:02:26,361 INFO L306 CDTParser]: Found 1 translation units. [2021-11-23 14:02:26,376 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-11-23 14:02:26,394 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/data/353b2d7cb/01e74bc04f2b4b82918846caafa3fd44/FLAGfb1704a09 [2021-11-23 14:02:26,671 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/data/353b2d7cb/01e74bc04f2b4b82918846caafa3fd44 [2021-11-23 14:02:26,673 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-23 14:02:26,675 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-23 14:02:26,678 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-23 14:02:26,678 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-23 14:02:26,682 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-23 14:02:26,682 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:02:26" (1/1) ... [2021-11-23 14:02:26,684 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15169add and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:26, skipping insertion in model container [2021-11-23 14:02:26,684 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:02:26" (1/1) ... [2021-11-23 14:02:26,690 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-23 14:02:26,760 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-23 14:02:26,931 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2021-11-23 14:02:27,016 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 14:02:27,026 INFO L203 MainTranslator]: Completed pre-run [2021-11-23 14:02:27,038 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2021-11-23 14:02:27,096 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 14:02:27,117 INFO L208 MainTranslator]: Completed translation [2021-11-23 14:02:27,118 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27 WrapperNode [2021-11-23 14:02:27,118 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-23 14:02:27,121 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-23 14:02:27,121 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-23 14:02:27,121 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-23 14:02:27,129 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,157 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,238 INFO L137 Inliner]: procedures = 38, calls = 45, calls flagged for inlining = 40, calls inlined = 86, statements flattened = 1229 [2021-11-23 14:02:27,238 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-23 14:02:27,239 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-23 14:02:27,239 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-23 14:02:27,240 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-23 14:02:27,248 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,249 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,253 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,254 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,272 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,290 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,293 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,305 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-23 14:02:27,317 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-23 14:02:27,317 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-23 14:02:27,317 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-23 14:02:27,318 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (1/1) ... [2021-11-23 14:02:27,327 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 14:02:27,338 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 14:02:27,357 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 14:02:27,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a6f7ca2-3b4c-4595-8c72-f83989ff0f61/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-23 14:02:27,405 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-23 14:02:27,405 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-23 14:02:27,406 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-23 14:02:27,406 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-23 14:02:27,566 INFO L236 CfgBuilder]: Building ICFG [2021-11-23 14:02:27,568 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-23 14:02:28,831 INFO L277 CfgBuilder]: Performing block encoding [2021-11-23 14:02:28,849 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-23 14:02:28,849 INFO L301 CfgBuilder]: Removed 9 assume(true) statements. [2021-11-23 14:02:28,853 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:02:28 BoogieIcfgContainer [2021-11-23 14:02:28,853 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-23 14:02:28,855 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-23 14:02:28,855 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-23 14:02:28,863 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-23 14:02:28,864 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:02:28,865 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:02:26" (1/3) ... [2021-11-23 14:02:28,866 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48683683 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:02:28, skipping insertion in model container [2021-11-23 14:02:28,866 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:02:28,867 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:02:27" (2/3) ... [2021-11-23 14:02:28,867 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48683683 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:02:28, skipping insertion in model container [2021-11-23 14:02:28,868 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 14:02:28,868 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:02:28" (3/3) ... [2021-11-23 14:02:28,870 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2021-11-23 14:02:28,939 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-23 14:02:28,939 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-23 14:02:28,939 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-23 14:02:28,940 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-23 14:02:28,940 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-23 14:02:28,940 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-23 14:02:28,940 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-23 14:02:28,941 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-23 14:02:28,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:29,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2021-11-23 14:02:29,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:29,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:29,078 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,078 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-23 14:02:29,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:29,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2021-11-23 14:02:29,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:29,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:29,110 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,110 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,128 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 410#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 389#L863true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 385#L394true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 255#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 343#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 106#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 401#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 384#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 460#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 326#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 119#L586-2true assume !(0 == ~T1_E~0); 231#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 269#L601-1true assume !(0 == ~T4_E~0); 247#L606-1true assume !(0 == ~T5_E~0); 462#L611-1true assume !(0 == ~E_1~0); 341#L616-1true assume !(0 == ~E_2~0); 349#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 50#L626-1true assume !(0 == ~E_4~0); 301#L631-1true assume !(0 == ~E_5~0); 140#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 366#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#L291true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 268#L720true assume !(0 != activate_threads_~tmp~1#1); 484#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144#L298true assume !(1 == ~t1_pc~0); 26#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 451#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181#L310true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55#L728true assume !(0 != activate_threads_~tmp___0~0#1); 260#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122#L317true assume 1 == ~t2_pc~0; 238#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 466#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 402#L329true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 150#L736true assume !(0 != activate_threads_~tmp___1~0#1); 421#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323#L336true assume 1 == ~t3_pc~0; 185#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 485#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230#L348true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 277#L744true assume !(0 != activate_threads_~tmp___2~0#1); 333#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 405#L355true assume !(1 == ~t4_pc~0); 331#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 98#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258#L367true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 316#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369#L374true assume 1 == ~t5_pc~0; 382#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 386#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 188#L386true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425#L760true assume !(0 != activate_threads_~tmp___4~0#1); 233#L760-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 493#L649-2true assume !(1 == ~T1_E~0); 41#L654-1true assume !(1 == ~T2_E~0); 265#L659-1true assume !(1 == ~T3_E~0); 149#L664-1true assume !(1 == ~T4_E~0); 37#L669-1true assume !(1 == ~T5_E~0); 318#L674-1true assume !(1 == ~E_1~0); 329#L679-1true assume !(1 == ~E_2~0); 90#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L689-1true assume !(1 == ~E_4~0); 480#L694-1true assume !(1 == ~E_5~0); 200#L699-1true assume { :end_inline_reset_delta_events } true; 469#L900-2true [2021-11-23 14:02:29,131 INFO L793 eck$LassoCheckResult]: Loop: 469#L900-2true assume !false; 502#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60#L561true assume !true; 454#L576true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419#L394-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 422#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 317#L586-5true assume !(0 == ~T1_E~0); 217#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 101#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 228#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 372#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 257#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 261#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 44#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 24#L626-3true assume !(0 == ~E_4~0); 503#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 28#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 431#L279-18true assume !(1 == ~m_pc~0); 161#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151#L291-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 391#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 344#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232#L298-18true assume 1 == ~t1_pc~0; 14#L299-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133#L310-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L317-18true assume 1 == ~t2_pc~0; 135#L318-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 240#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102#L329-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 353#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348#L336-18true assume !(1 == ~t3_pc~0); 488#L336-20true is_transmit3_triggered_~__retres1~3#1 := 0; 394#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153#L348-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 287#L355-18true assume 1 == ~t4_pc~0; 412#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 418#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123#L367-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332#L374-18true assume 1 == ~t5_pc~0; 458#L375-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 171#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 288#L386-6true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 445#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L760-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 184#L649-5true assume !(1 == ~T1_E~0); 168#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 79#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 450#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 29#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 474#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 23#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 179#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 3#L689-3true assume !(1 == ~E_4~0); 131#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 21#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 416#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 473#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 347#L472-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 199#L919true assume !(0 == start_simulation_~tmp~3#1); 483#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 299#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 375#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 157#L472-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 192#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155#L882true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 328#L932true assume !(0 != start_simulation_~tmp___0~1#1); 469#L900-2true [2021-11-23 14:02:29,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:29,139 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2021-11-23 14:02:29,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:29,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695984920] [2021-11-23 14:02:29,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:29,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:29,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:29,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:29,381 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:29,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695984920] [2021-11-23 14:02:29,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695984920] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:29,383 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:29,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:29,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806992970] [2021-11-23 14:02:29,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:29,393 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:29,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:29,395 INFO L85 PathProgramCache]: Analyzing trace with hash -129051228, now seen corresponding path program 1 times [2021-11-23 14:02:29,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:29,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021801177] [2021-11-23 14:02:29,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:29,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:29,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:29,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:29,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:29,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021801177] [2021-11-23 14:02:29,435 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021801177] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:29,436 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:29,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 14:02:29,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418941338] [2021-11-23 14:02:29,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:29,439 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:29,440 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:29,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:29,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:29,485 INFO L87 Difference]: Start difference. First operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:29,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:29,548 INFO L93 Difference]: Finished difference Result 504 states and 752 transitions. [2021-11-23 14:02:29,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:29,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 752 transitions. [2021-11-23 14:02:29,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:29,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 498 states and 746 transitions. [2021-11-23 14:02:29,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-11-23 14:02:29,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-11-23 14:02:29,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 746 transitions. [2021-11-23 14:02:29,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:29,607 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-11-23 14:02:29,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 746 transitions. [2021-11-23 14:02:29,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-11-23 14:02:29,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:29,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 746 transitions. [2021-11-23 14:02:29,714 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-11-23 14:02:29,715 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-11-23 14:02:29,716 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-23 14:02:29,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 746 transitions. [2021-11-23 14:02:29,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:29,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:29,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:29,734 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,735 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:29,736 INFO L791 eck$LassoCheckResult]: Stem: 1515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1493#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1491#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1405#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1406#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1211#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1212#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1489#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1490#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1183#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1184#L586-2 assume !(0 == ~T1_E~0); 1237#L591-1 assume !(0 == ~T2_E~0); 1357#L596-1 assume !(0 == ~T3_E~0); 1358#L601-1 assume !(0 == ~T4_E~0); 1396#L606-1 assume !(0 == ~T5_E~0); 1397#L611-1 assume !(0 == ~E_1~0); 1468#L616-1 assume !(0 == ~E_2~0); 1469#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1116#L626-1 assume !(0 == ~E_4~0); 1117#L631-1 assume !(0 == ~E_5~0); 1272#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1111#L279 assume 1 == ~m_pc~0; 1112#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1363#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1339#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1340#L720 assume !(0 != activate_threads_~tmp~1#1); 1413#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1276#L298 assume !(1 == ~t1_pc~0); 1068#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1069#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1328#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1125#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1126#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243#L317 assume 1 == ~t2_pc~0; 1244#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1390#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1285#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1286#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460#L336 assume 1 == ~t3_pc~0; 1332#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1333#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1380#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1381#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1421#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465#L355 assume !(1 == ~t4_pc~0); 1354#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1197#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1198#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1409#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1135#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1136#L374 assume 1 == ~t5_pc~0; 1483#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1264#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1338#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1383#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1384#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1506#L649-2 assume !(1 == ~T1_E~0); 1100#L654-1 assume !(1 == ~T2_E~0); 1101#L659-1 assume !(1 == ~T3_E~0); 1284#L664-1 assume !(1 == ~T4_E~0); 1093#L669-1 assume !(1 == ~T5_E~0); 1094#L674-1 assume !(1 == ~E_1~0); 1456#L679-1 assume !(1 == ~E_2~0); 1188#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1189#L689-1 assume !(1 == ~E_4~0); 1351#L694-1 assume !(1 == ~E_5~0); 1349#L699-1 assume { :end_inline_reset_delta_events } true; 1350#L900-2 [2021-11-23 14:02:29,740 INFO L793 eck$LassoCheckResult]: Loop: 1350#L900-2 assume !false; 1513#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047#L561 assume !false; 1132#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1313#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1070#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1071#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1176#L486 assume !(0 != eval_~tmp~0#1); 1178#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1503#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1504#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1455#L586-5 assume !(0 == ~T1_E~0); 1364#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1202#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1203#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1377#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1407#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1408#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1065#L626-3 assume !(0 == ~E_4~0); 1066#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1072#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1073#L279-18 assume 1 == ~m_pc~0; 1165#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1166#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1287#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1288#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1471#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382#L298-18 assume 1 == ~t1_pc~0; 1044#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1210#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1233#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1234#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1359#L317-18 assume 1 == ~t2_pc~0; 1265#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1267#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1204#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1205#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1213#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474#L336-18 assume 1 == ~t3_pc~0; 1457#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1458#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1290#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1291#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1157#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1158#L355-18 assume 1 == ~t4_pc~0; 1431#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1420#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1246#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1253#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1254#L374-18 assume 1 == ~t5_pc~0; 1464#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1318#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1432#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1414#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1331#L649-5 assume !(1 == ~T1_E~0); 1312#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1168#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1169#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1074#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1064#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018#L689-3 assume !(1 == ~E_4~0); 1019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1058#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1059#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1061#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1473#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1348#L919 assume !(0 == start_simulation_~tmp~3#1); 1077#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1444#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1052#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1297#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1298#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1343#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1293#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1350#L900-2 [2021-11-23 14:02:29,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:29,743 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2021-11-23 14:02:29,743 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:29,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799700542] [2021-11-23 14:02:29,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:29,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:29,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:29,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:29,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:29,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799700542] [2021-11-23 14:02:29,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799700542] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:29,841 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:29,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:29,842 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420056842] [2021-11-23 14:02:29,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:29,843 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:29,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:29,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1476238801, now seen corresponding path program 1 times [2021-11-23 14:02:29,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:29,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375573936] [2021-11-23 14:02:29,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:29,856 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:29,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:29,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:29,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:29,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375573936] [2021-11-23 14:02:29,978 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375573936] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:29,978 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:29,978 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:29,978 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849834301] [2021-11-23 14:02:29,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:29,979 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:29,979 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:29,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:29,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:29,980 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:30,017 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2021-11-23 14:02:30,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:30,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 745 transitions. [2021-11-23 14:02:30,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 745 transitions. [2021-11-23 14:02:30,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-11-23 14:02:30,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-11-23 14:02:30,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 745 transitions. [2021-11-23 14:02:30,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:30,037 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-11-23 14:02:30,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 745 transitions. [2021-11-23 14:02:30,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-11-23 14:02:30,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 745 transitions. [2021-11-23 14:02:30,059 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-11-23 14:02:30,059 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-11-23 14:02:30,060 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-23 14:02:30,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 745 transitions. [2021-11-23 14:02:30,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:30,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:30,071 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,072 INFO L791 eck$LassoCheckResult]: Stem: 2518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2496#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2494#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2408#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2409#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2214#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2215#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2492#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2493#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2465#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2186#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2187#L586-2 assume !(0 == ~T1_E~0); 2240#L591-1 assume !(0 == ~T2_E~0); 2360#L596-1 assume !(0 == ~T3_E~0); 2361#L601-1 assume !(0 == ~T4_E~0); 2399#L606-1 assume !(0 == ~T5_E~0); 2400#L611-1 assume !(0 == ~E_1~0); 2471#L616-1 assume !(0 == ~E_2~0); 2472#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2119#L626-1 assume !(0 == ~E_4~0); 2120#L631-1 assume !(0 == ~E_5~0); 2275#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2114#L279 assume 1 == ~m_pc~0; 2115#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2366#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2342#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2343#L720 assume !(0 != activate_threads_~tmp~1#1); 2416#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2279#L298 assume !(1 == ~t1_pc~0); 2071#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2072#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2331#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2128#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2129#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L317 assume 1 == ~t2_pc~0; 2247#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2393#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2500#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2288#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2289#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2463#L336 assume 1 == ~t3_pc~0; 2335#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2336#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2383#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2384#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2424#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2468#L355 assume !(1 == ~t4_pc~0); 2357#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2200#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2201#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2412#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2138#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2139#L374 assume 1 == ~t5_pc~0; 2486#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2267#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2340#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2341#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2386#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2387#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L649-2 assume !(1 == ~T1_E~0); 2103#L654-1 assume !(1 == ~T2_E~0); 2104#L659-1 assume !(1 == ~T3_E~0); 2287#L664-1 assume !(1 == ~T4_E~0); 2096#L669-1 assume !(1 == ~T5_E~0); 2097#L674-1 assume !(1 == ~E_1~0); 2459#L679-1 assume !(1 == ~E_2~0); 2191#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2192#L689-1 assume !(1 == ~E_4~0); 2354#L694-1 assume !(1 == ~E_5~0); 2352#L699-1 assume { :end_inline_reset_delta_events } true; 2353#L900-2 [2021-11-23 14:02:30,074 INFO L793 eck$LassoCheckResult]: Loop: 2353#L900-2 assume !false; 2516#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2050#L561 assume !false; 2135#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2316#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2073#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2074#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2179#L486 assume !(0 != eval_~tmp~0#1); 2181#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2506#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2507#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2458#L586-5 assume !(0 == ~T1_E~0); 2367#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2205#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2206#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2380#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2410#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2411#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2107#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2068#L626-3 assume !(0 == ~E_4~0); 2069#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2075#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2076#L279-18 assume 1 == ~m_pc~0; 2168#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2169#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2290#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2291#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2474#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2385#L298-18 assume !(1 == ~t1_pc~0); 2040#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2041#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2213#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2236#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2237#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2362#L317-18 assume 1 == ~t2_pc~0; 2268#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2270#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2207#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2208#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2216#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2477#L336-18 assume 1 == ~t3_pc~0; 2460#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2461#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2293#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2294#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2160#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2161#L355-18 assume 1 == ~t4_pc~0; 2434#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2423#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2249#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2250#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2256#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L374-18 assume 1 == ~t5_pc~0; 2467#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2321#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2322#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2435#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2417#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2418#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L649-5 assume !(1 == ~T1_E~0); 2315#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2171#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2172#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2077#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2078#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2066#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2067#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2021#L689-3 assume !(1 == ~E_4~0); 2022#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2061#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2062#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2064#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2476#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2351#L919 assume !(0 == start_simulation_~tmp~3#1); 2080#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2447#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2055#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2300#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2301#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2346#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2296#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2297#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2353#L900-2 [2021-11-23 14:02:30,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,078 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2021-11-23 14:02:30,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221008427] [2021-11-23 14:02:30,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,079 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221008427] [2021-11-23 14:02:30,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221008427] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,129 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614652616] [2021-11-23 14:02:30,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:30,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1373437554, now seen corresponding path program 1 times [2021-11-23 14:02:30,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497433505] [2021-11-23 14:02:30,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,132 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,178 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497433505] [2021-11-23 14:02:30,178 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1497433505] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,179 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,179 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,179 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745715296] [2021-11-23 14:02:30,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,180 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:30,180 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:30,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:30,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:30,181 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:30,195 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2021-11-23 14:02:30,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:30,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 744 transitions. [2021-11-23 14:02:30,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 744 transitions. [2021-11-23 14:02:30,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-11-23 14:02:30,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-11-23 14:02:30,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 744 transitions. [2021-11-23 14:02:30,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:30,210 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-11-23 14:02:30,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 744 transitions. [2021-11-23 14:02:30,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-11-23 14:02:30,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 744 transitions. [2021-11-23 14:02:30,224 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-11-23 14:02:30,224 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-11-23 14:02:30,225 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-23 14:02:30,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 744 transitions. [2021-11-23 14:02:30,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:30,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:30,231 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,231 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,232 INFO L791 eck$LassoCheckResult]: Stem: 3521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3499#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3497#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3411#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3412#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3217#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3218#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3495#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3496#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3468#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3189#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L586-2 assume !(0 == ~T1_E~0); 3243#L591-1 assume !(0 == ~T2_E~0); 3363#L596-1 assume !(0 == ~T3_E~0); 3364#L601-1 assume !(0 == ~T4_E~0); 3402#L606-1 assume !(0 == ~T5_E~0); 3403#L611-1 assume !(0 == ~E_1~0); 3474#L616-1 assume !(0 == ~E_2~0); 3475#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3122#L626-1 assume !(0 == ~E_4~0); 3123#L631-1 assume !(0 == ~E_5~0); 3278#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3117#L279 assume 1 == ~m_pc~0; 3118#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3369#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3345#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3346#L720 assume !(0 != activate_threads_~tmp~1#1); 3419#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3282#L298 assume !(1 == ~t1_pc~0); 3074#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3075#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3334#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3131#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3132#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3249#L317 assume 1 == ~t2_pc~0; 3250#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3396#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3503#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3291#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3292#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L336 assume 1 == ~t3_pc~0; 3338#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3339#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3386#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3387#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3427#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3471#L355 assume !(1 == ~t4_pc~0); 3360#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3203#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3204#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3415#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3141#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3142#L374 assume 1 == ~t5_pc~0; 3489#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3270#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3343#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3344#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3389#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3390#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3512#L649-2 assume !(1 == ~T1_E~0); 3106#L654-1 assume !(1 == ~T2_E~0); 3107#L659-1 assume !(1 == ~T3_E~0); 3290#L664-1 assume !(1 == ~T4_E~0); 3099#L669-1 assume !(1 == ~T5_E~0); 3100#L674-1 assume !(1 == ~E_1~0); 3462#L679-1 assume !(1 == ~E_2~0); 3194#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3195#L689-1 assume !(1 == ~E_4~0); 3357#L694-1 assume !(1 == ~E_5~0); 3355#L699-1 assume { :end_inline_reset_delta_events } true; 3356#L900-2 [2021-11-23 14:02:30,232 INFO L793 eck$LassoCheckResult]: Loop: 3356#L900-2 assume !false; 3519#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3053#L561 assume !false; 3138#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3319#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3076#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3077#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3182#L486 assume !(0 != eval_~tmp~0#1); 3184#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3509#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3510#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3461#L586-5 assume !(0 == ~T1_E~0); 3370#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3208#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3209#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3413#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3414#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3110#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3071#L626-3 assume !(0 == ~E_4~0); 3072#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3078#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3079#L279-18 assume 1 == ~m_pc~0; 3171#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3294#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3477#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3388#L298-18 assume !(1 == ~t1_pc~0); 3043#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3044#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3239#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3240#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3365#L317-18 assume 1 == ~t2_pc~0; 3271#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3273#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3210#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3211#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3219#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3480#L336-18 assume 1 == ~t3_pc~0; 3463#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3296#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3297#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3163#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3164#L355-18 assume !(1 == ~t4_pc~0); 3425#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3426#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3252#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3253#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3259#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3260#L374-18 assume !(1 == ~t5_pc~0); 3444#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3324#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3325#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3438#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3420#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3337#L649-5 assume !(1 == ~T1_E~0); 3318#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3174#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3175#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3080#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3081#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3069#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3070#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3024#L689-3 assume !(1 == ~E_4~0); 3025#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3064#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3065#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3067#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3479#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3354#L919 assume !(0 == start_simulation_~tmp~3#1); 3083#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3450#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3058#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3303#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3304#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3349#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3299#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3300#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3356#L900-2 [2021-11-23 14:02:30,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,234 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2021-11-23 14:02:30,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567228290] [2021-11-23 14:02:30,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567228290] [2021-11-23 14:02:30,310 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567228290] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,310 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,310 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,310 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315217385] [2021-11-23 14:02:30,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,311 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:30,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1099568908, now seen corresponding path program 1 times [2021-11-23 14:02:30,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544525341] [2021-11-23 14:02:30,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,392 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544525341] [2021-11-23 14:02:30,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544525341] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,392 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,393 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:30,393 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287263090] [2021-11-23 14:02:30,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:30,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:30,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:30,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:30,396 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:30,412 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2021-11-23 14:02:30,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:30,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 743 transitions. [2021-11-23 14:02:30,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 743 transitions. [2021-11-23 14:02:30,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-11-23 14:02:30,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-11-23 14:02:30,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 743 transitions. [2021-11-23 14:02:30,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:30,435 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-11-23 14:02:30,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 743 transitions. [2021-11-23 14:02:30,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-11-23 14:02:30,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 743 transitions. [2021-11-23 14:02:30,446 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-11-23 14:02:30,446 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-11-23 14:02:30,446 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-23 14:02:30,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 743 transitions. [2021-11-23 14:02:30,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:30,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:30,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,458 INFO L791 eck$LassoCheckResult]: Stem: 4526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4504#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4502#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4416#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4417#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4222#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4223#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4500#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4501#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4473#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4194#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4195#L586-2 assume !(0 == ~T1_E~0); 4248#L591-1 assume !(0 == ~T2_E~0); 4368#L596-1 assume !(0 == ~T3_E~0); 4369#L601-1 assume !(0 == ~T4_E~0); 4407#L606-1 assume !(0 == ~T5_E~0); 4408#L611-1 assume !(0 == ~E_1~0); 4479#L616-1 assume !(0 == ~E_2~0); 4480#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4127#L626-1 assume !(0 == ~E_4~0); 4128#L631-1 assume !(0 == ~E_5~0); 4283#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4122#L279 assume 1 == ~m_pc~0; 4123#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4374#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4350#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4351#L720 assume !(0 != activate_threads_~tmp~1#1); 4424#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4287#L298 assume !(1 == ~t1_pc~0); 4079#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4080#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4339#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4137#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4254#L317 assume 1 == ~t2_pc~0; 4255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4401#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4508#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4296#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4297#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4471#L336 assume 1 == ~t3_pc~0; 4343#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4344#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4391#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4392#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4432#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4476#L355 assume !(1 == ~t4_pc~0); 4365#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4208#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4209#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4420#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4146#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4147#L374 assume 1 == ~t5_pc~0; 4494#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4275#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4348#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4349#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4394#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4395#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4517#L649-2 assume !(1 == ~T1_E~0); 4111#L654-1 assume !(1 == ~T2_E~0); 4112#L659-1 assume !(1 == ~T3_E~0); 4295#L664-1 assume !(1 == ~T4_E~0); 4104#L669-1 assume !(1 == ~T5_E~0); 4105#L674-1 assume !(1 == ~E_1~0); 4467#L679-1 assume !(1 == ~E_2~0); 4199#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4200#L689-1 assume !(1 == ~E_4~0); 4362#L694-1 assume !(1 == ~E_5~0); 4360#L699-1 assume { :end_inline_reset_delta_events } true; 4361#L900-2 [2021-11-23 14:02:30,458 INFO L793 eck$LassoCheckResult]: Loop: 4361#L900-2 assume !false; 4524#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4058#L561 assume !false; 4143#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4324#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4081#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4082#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4187#L486 assume !(0 != eval_~tmp~0#1); 4189#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4514#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4515#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4466#L586-5 assume !(0 == ~T1_E~0); 4375#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4213#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4214#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4388#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4418#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4419#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4115#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4076#L626-3 assume !(0 == ~E_4~0); 4077#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4083#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4084#L279-18 assume 1 == ~m_pc~0; 4176#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4177#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4298#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4299#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4482#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4393#L298-18 assume !(1 == ~t1_pc~0); 4048#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4049#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4221#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4244#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4245#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4370#L317-18 assume 1 == ~t2_pc~0; 4276#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4215#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4216#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4224#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L336-18 assume 1 == ~t3_pc~0; 4468#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4469#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4301#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4302#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4168#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169#L355-18 assume 1 == ~t4_pc~0; 4442#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4431#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4257#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4258#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4264#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4265#L374-18 assume !(1 == ~t5_pc~0); 4449#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 4329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4330#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4443#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4425#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4426#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4342#L649-5 assume !(1 == ~T1_E~0); 4323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4179#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4180#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4085#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4086#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4074#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4075#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4029#L689-3 assume !(1 == ~E_4~0); 4030#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4069#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4070#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4072#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4484#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4359#L919 assume !(0 == start_simulation_~tmp~3#1); 4088#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4455#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4063#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4308#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4309#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4354#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4304#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4305#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4361#L900-2 [2021-11-23 14:02:30,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2021-11-23 14:02:30,459 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572086502] [2021-11-23 14:02:30,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,460 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572086502] [2021-11-23 14:02:30,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572086502] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,533 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298521121] [2021-11-23 14:02:30,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:30,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1430581779, now seen corresponding path program 1 times [2021-11-23 14:02:30,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225943282] [2021-11-23 14:02:30,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,585 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,585 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225943282] [2021-11-23 14:02:30,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225943282] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,585 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,586 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059782308] [2021-11-23 14:02:30,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,586 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:30,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:30,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:30,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:30,587 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:30,602 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2021-11-23 14:02:30,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:30,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 742 transitions. [2021-11-23 14:02:30,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 742 transitions. [2021-11-23 14:02:30,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-11-23 14:02:30,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-11-23 14:02:30,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 742 transitions. [2021-11-23 14:02:30,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:30,616 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-11-23 14:02:30,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 742 transitions. [2021-11-23 14:02:30,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-11-23 14:02:30,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 742 transitions. [2021-11-23 14:02:30,629 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-11-23 14:02:30,629 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-11-23 14:02:30,629 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-23 14:02:30,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 742 transitions. [2021-11-23 14:02:30,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-11-23 14:02:30,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:30,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:30,638 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,638 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,638 INFO L791 eck$LassoCheckResult]: Stem: 5529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5507#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5505#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5419#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5420#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5225#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5226#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5503#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5504#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5476#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5197#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5198#L586-2 assume !(0 == ~T1_E~0); 5251#L591-1 assume !(0 == ~T2_E~0); 5371#L596-1 assume !(0 == ~T3_E~0); 5372#L601-1 assume !(0 == ~T4_E~0); 5410#L606-1 assume !(0 == ~T5_E~0); 5411#L611-1 assume !(0 == ~E_1~0); 5482#L616-1 assume !(0 == ~E_2~0); 5483#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5130#L626-1 assume !(0 == ~E_4~0); 5131#L631-1 assume !(0 == ~E_5~0); 5286#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5125#L279 assume 1 == ~m_pc~0; 5126#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5377#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5353#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5354#L720 assume !(0 != activate_threads_~tmp~1#1); 5427#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5290#L298 assume !(1 == ~t1_pc~0); 5082#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5083#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5342#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5139#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5140#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5257#L317 assume 1 == ~t2_pc~0; 5258#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5404#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5511#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5299#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5300#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5474#L336 assume 1 == ~t3_pc~0; 5346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5394#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5395#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5435#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5479#L355 assume !(1 == ~t4_pc~0); 5368#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5211#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5212#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5423#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5149#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5150#L374 assume 1 == ~t5_pc~0; 5497#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5278#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5351#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5352#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5397#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5520#L649-2 assume !(1 == ~T1_E~0); 5114#L654-1 assume !(1 == ~T2_E~0); 5115#L659-1 assume !(1 == ~T3_E~0); 5298#L664-1 assume !(1 == ~T4_E~0); 5107#L669-1 assume !(1 == ~T5_E~0); 5108#L674-1 assume !(1 == ~E_1~0); 5470#L679-1 assume !(1 == ~E_2~0); 5202#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5203#L689-1 assume !(1 == ~E_4~0); 5365#L694-1 assume !(1 == ~E_5~0); 5363#L699-1 assume { :end_inline_reset_delta_events } true; 5364#L900-2 [2021-11-23 14:02:30,639 INFO L793 eck$LassoCheckResult]: Loop: 5364#L900-2 assume !false; 5527#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5061#L561 assume !false; 5146#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5327#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5084#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5085#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5190#L486 assume !(0 != eval_~tmp~0#1); 5192#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5517#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5518#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5469#L586-5 assume !(0 == ~T1_E~0); 5378#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5216#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5217#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5391#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5421#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5422#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5118#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5079#L626-3 assume !(0 == ~E_4~0); 5080#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5086#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5087#L279-18 assume 1 == ~m_pc~0; 5179#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5180#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5301#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5302#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5485#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5396#L298-18 assume 1 == ~t1_pc~0; 5058#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5052#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5224#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5247#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5248#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5373#L317-18 assume !(1 == ~t2_pc~0); 5280#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 5281#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5218#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5219#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5227#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5488#L336-18 assume !(1 == ~t3_pc~0); 5473#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5472#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5304#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5305#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5171#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5172#L355-18 assume 1 == ~t4_pc~0; 5445#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5434#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5260#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5261#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5267#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5268#L374-18 assume 1 == ~t5_pc~0; 5478#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5332#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5333#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5446#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5428#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5429#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5345#L649-5 assume !(1 == ~T1_E~0); 5326#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5182#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5183#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5088#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5089#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5077#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5078#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5032#L689-3 assume !(1 == ~E_4~0); 5033#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5072#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5073#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5075#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5487#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5362#L919 assume !(0 == start_simulation_~tmp~3#1); 5091#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5458#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5066#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5311#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5312#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5357#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5307#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5308#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5364#L900-2 [2021-11-23 14:02:30,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2021-11-23 14:02:30,640 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622837591] [2021-11-23 14:02:30,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,640 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622837591] [2021-11-23 14:02:30,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622837591] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 14:02:30,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131056361] [2021-11-23 14:02:30,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,677 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:30,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,681 INFO L85 PathProgramCache]: Analyzing trace with hash 2096048813, now seen corresponding path program 1 times [2021-11-23 14:02:30,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534327025] [2021-11-23 14:02:30,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534327025] [2021-11-23 14:02:30,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534327025] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,729 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,730 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813695141] [2021-11-23 14:02:30,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,731 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:30,731 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:30,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:30,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:30,732 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:30,810 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2021-11-23 14:02:30,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:30,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 875 states and 1292 transitions. [2021-11-23 14:02:30,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2021-11-23 14:02:30,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 875 states to 875 states and 1292 transitions. [2021-11-23 14:02:30,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 875 [2021-11-23 14:02:30,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 875 [2021-11-23 14:02:30,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 875 states and 1292 transitions. [2021-11-23 14:02:30,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:30,834 INFO L681 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-11-23 14:02:30,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states and 1292 transitions. [2021-11-23 14:02:30,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 875. [2021-11-23 14:02:30,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:30,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1292 transitions. [2021-11-23 14:02:30,863 INFO L704 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-11-23 14:02:30,863 INFO L587 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-11-23 14:02:30,863 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-23 14:02:30,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1292 transitions. [2021-11-23 14:02:30,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2021-11-23 14:02:30,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:30,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:30,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:30,872 INFO L791 eck$LassoCheckResult]: Stem: 6939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6919#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6910#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6908#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6808#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6809#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6608#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6609#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6906#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6907#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6871#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6581#L586 assume !(0 == ~M_E~0); 6582#L586-2 assume !(0 == ~T1_E~0); 6635#L591-1 assume !(0 == ~T2_E~0); 6760#L596-1 assume !(0 == ~T3_E~0); 6761#L601-1 assume !(0 == ~T4_E~0); 6799#L606-1 assume !(0 == ~T5_E~0); 6800#L611-1 assume !(0 == ~E_1~0); 6878#L616-1 assume !(0 == ~E_2~0); 6879#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6509#L626-1 assume !(0 == ~E_4~0); 6510#L631-1 assume !(0 == ~E_5~0); 6670#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6504#L279 assume !(1 == ~m_pc~0); 6506#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6817#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6741#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6742#L720 assume !(0 != activate_threads_~tmp~1#1); 6816#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6676#L298 assume !(1 == ~t1_pc~0); 6462#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6463#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6729#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6518#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6519#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6641#L317 assume 1 == ~t2_pc~0; 6642#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6793#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6914#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6690#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6691#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6869#L336 assume 1 == ~t3_pc~0; 6733#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6734#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6782#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6783#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6825#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6875#L355 assume !(1 == ~t4_pc~0); 6759#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6596#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6597#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6812#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6531#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6532#L374 assume 1 == ~t5_pc~0; 6897#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6665#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6740#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6785#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6786#L649 assume !(1 == ~M_E~0); 6927#L649-2 assume !(1 == ~T1_E~0); 6493#L654-1 assume !(1 == ~T2_E~0); 6494#L659-1 assume !(1 == ~T3_E~0); 6684#L664-1 assume !(1 == ~T4_E~0); 6486#L669-1 assume !(1 == ~T5_E~0); 6487#L674-1 assume !(1 == ~E_1~0); 6863#L679-1 assume !(1 == ~E_2~0); 6583#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6584#L689-1 assume !(1 == ~E_4~0); 6754#L694-1 assume !(1 == ~E_5~0); 6752#L699-1 assume { :end_inline_reset_delta_events } true; 6753#L900-2 [2021-11-23 14:02:30,873 INFO L793 eck$LassoCheckResult]: Loop: 6753#L900-2 assume !false; 6936#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6441#L561 assume !false; 6525#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6714#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6464#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6465#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6570#L486 assume !(0 != eval_~tmp~0#1); 6572#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6922#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6923#L586-3 assume !(0 == ~M_E~0); 6925#L586-5 assume !(0 == ~T1_E~0); 7098#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7097#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7096#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7095#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7094#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7093#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7092#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7091#L626-3 assume !(0 == ~E_4~0); 7090#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6466#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6467#L279-18 assume !(1 == ~m_pc~0); 6559#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6701#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6686#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6881#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6784#L298-18 assume 1 == ~t1_pc~0; 6438#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6432#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6607#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6631#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6632#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L317-18 assume 1 == ~t2_pc~0; 6661#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6663#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6600#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6610#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6884#L336-18 assume 1 == ~t3_pc~0; 6864#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6865#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6688#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6689#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6550#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6551#L355-18 assume 1 == ~t4_pc~0; 6837#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6824#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6644#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6645#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6651#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6652#L374-18 assume 1 == ~t5_pc~0; 6873#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6719#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6720#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6838#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6818#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6819#L649-3 assume !(1 == ~M_E~0); 6732#L649-5 assume !(1 == ~T1_E~0); 6713#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6560#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6561#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6468#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6469#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6457#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6458#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6412#L689-3 assume !(1 == ~E_4~0); 6413#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6452#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6453#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6455#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6883#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6750#L919 assume !(0 == start_simulation_~tmp~3#1); 6471#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6938#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7074#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7073#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7072#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6885#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6693#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6694#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6753#L900-2 [2021-11-23 14:02:30,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,873 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2021-11-23 14:02:30,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755892104] [2021-11-23 14:02:30,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,934 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755892104] [2021-11-23 14:02:30,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755892104] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2138922167] [2021-11-23 14:02:30,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,937 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:30,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:30,937 INFO L85 PathProgramCache]: Analyzing trace with hash 855131594, now seen corresponding path program 1 times [2021-11-23 14:02:30,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:30,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216672902] [2021-11-23 14:02:30,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:30,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:30,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:30,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:30,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:30,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216672902] [2021-11-23 14:02:30,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [216672902] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:30,974 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:30,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:30,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664764491] [2021-11-23 14:02:30,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:30,975 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:30,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:30,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:02:30,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:02:30,977 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:31,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:31,135 INFO L93 Difference]: Finished difference Result 1597 states and 2359 transitions. [2021-11-23 14:02:31,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:02:31,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1597 states and 2359 transitions. [2021-11-23 14:02:31,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2021-11-23 14:02:31,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1597 states to 1597 states and 2359 transitions. [2021-11-23 14:02:31,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1597 [2021-11-23 14:02:31,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1597 [2021-11-23 14:02:31,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1597 states and 2359 transitions. [2021-11-23 14:02:31,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:31,214 INFO L681 BuchiCegarLoop]: Abstraction has 1597 states and 2359 transitions. [2021-11-23 14:02:31,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1597 states and 2359 transitions. [2021-11-23 14:02:31,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1597 to 1595. [2021-11-23 14:02:31,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1595 states, 1595 states have (on average 1.477742946708464) internal successors, (2357), 1594 states have internal predecessors, (2357), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:31,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1595 states to 1595 states and 2357 transitions. [2021-11-23 14:02:31,270 INFO L704 BuchiCegarLoop]: Abstraction has 1595 states and 2357 transitions. [2021-11-23 14:02:31,271 INFO L587 BuchiCegarLoop]: Abstraction has 1595 states and 2357 transitions. [2021-11-23 14:02:31,271 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-23 14:02:31,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1595 states and 2357 transitions. [2021-11-23 14:02:31,285 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2021-11-23 14:02:31,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:31,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:31,287 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:31,287 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:31,287 INFO L791 eck$LassoCheckResult]: Stem: 9483#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9434#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9432#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9322#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9323#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9096#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9097#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9430#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9431#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9395#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9067#L586 assume !(0 == ~M_E~0); 9068#L586-2 assume !(0 == ~T1_E~0); 9124#L591-1 assume !(0 == ~T2_E~0); 9261#L596-1 assume !(0 == ~T3_E~0); 9262#L601-1 assume !(0 == ~T4_E~0); 9313#L606-1 assume !(0 == ~T5_E~0); 9314#L611-1 assume !(0 == ~E_1~0); 9400#L616-1 assume !(0 == ~E_2~0); 9401#L621-1 assume !(0 == ~E_3~0); 8993#L626-1 assume !(0 == ~E_4~0); 8994#L631-1 assume !(0 == ~E_5~0); 9161#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L279 assume !(1 == ~m_pc~0); 8990#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9335#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9235#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9236#L720 assume !(0 != activate_threads_~tmp~1#1); 9334#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9165#L298 assume !(1 == ~t1_pc~0); 8947#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8948#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9222#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9002#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9003#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9131#L317 assume 1 == ~t2_pc~0; 9132#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9303#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9446#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9179#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9180#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9393#L336 assume 1 == ~t3_pc~0; 9229#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9230#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9291#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9292#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9344#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9398#L355 assume !(1 == ~t4_pc~0); 9260#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9083#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9084#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9326#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9018#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9019#L374 assume 1 == ~t5_pc~0; 9422#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9156#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9233#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9234#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9294#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9295#L649 assume !(1 == ~M_E~0); 9462#L649-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9484#L654-1 assume !(1 == ~T2_E~0); 10465#L659-1 assume !(1 == ~T3_E~0); 10464#L664-1 assume !(1 == ~T4_E~0); 10463#L669-1 assume !(1 == ~T5_E~0); 10462#L674-1 assume !(1 == ~E_1~0); 10461#L679-1 assume !(1 == ~E_2~0); 10460#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9071#L689-1 assume !(1 == ~E_4~0); 10458#L694-1 assume !(1 == ~E_5~0); 10457#L699-1 assume { :end_inline_reset_delta_events } true; 10454#L900-2 [2021-11-23 14:02:31,292 INFO L793 eck$LassoCheckResult]: Loop: 10454#L900-2 assume !false; 10252#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9011#L561 assume !false; 9012#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9203#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9129#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9513#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9508#L486 assume !(0 != eval_~tmp~0#1); 9470#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9458#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9459#L586-3 assume !(0 == ~M_E~0); 10241#L586-5 assume !(0 == ~T1_E~0); 10240#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9086#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9087#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9288#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9324#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9325#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8981#L621-3 assume !(0 == ~E_3~0); 8942#L626-3 assume !(0 == ~E_4~0); 8943#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8949#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8950#L279-18 assume !(1 == ~m_pc~0); 9047#L279-20 is_master_triggered_~__retres1~0#1 := 0; 9193#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9174#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9175#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9404#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9293#L298-18 assume !(1 == ~t1_pc~0); 8913#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 8914#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10197#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10196#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10195#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10194#L317-18 assume 1 == ~t2_pc~0; 9152#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9154#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10189#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10188#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10187#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10186#L336-18 assume 1 == ~t3_pc~0; 10184#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10181#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10179#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10177#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10176#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10175#L355-18 assume !(1 == ~t4_pc~0); 10173#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 10172#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10171#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10170#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10169#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10168#L374-18 assume 1 == ~t5_pc~0; 10166#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9208#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9209#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9356#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9336#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9337#L649-3 assume !(1 == ~M_E~0); 9472#L649-5 assume !(1 == ~T1_E~0); 9772#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9770#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9768#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9765#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9763#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9682#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9681#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9680#L689-3 assume !(1 == ~E_4~0); 9679#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9678#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9673#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9667#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9666#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9248#L919 assume !(0 == start_simulation_~tmp~3#1); 9249#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10475#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10470#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10469#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 10468#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10467#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10466#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 10456#L932 assume !(0 != start_simulation_~tmp___0~1#1); 10454#L900-2 [2021-11-23 14:02:31,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:31,293 INFO L85 PathProgramCache]: Analyzing trace with hash 352597313, now seen corresponding path program 1 times [2021-11-23 14:02:31,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:31,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774179508] [2021-11-23 14:02:31,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:31,294 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:31,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:31,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:31,335 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:31,336 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774179508] [2021-11-23 14:02:31,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774179508] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:31,337 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:31,338 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:31,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458877985] [2021-11-23 14:02:31,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:31,339 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:31,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:31,339 INFO L85 PathProgramCache]: Analyzing trace with hash -861276666, now seen corresponding path program 1 times [2021-11-23 14:02:31,340 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:31,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368231425] [2021-11-23 14:02:31,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:31,346 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:31,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:31,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:31,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:31,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368231425] [2021-11-23 14:02:31,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368231425] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:31,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:31,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:31,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610729722] [2021-11-23 14:02:31,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:31,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:31,403 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:31,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:02:31,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:02:31,404 INFO L87 Difference]: Start difference. First operand 1595 states and 2357 transitions. cyclomatic complexity: 764 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:31,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:31,645 INFO L93 Difference]: Finished difference Result 4405 states and 6414 transitions. [2021-11-23 14:02:31,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:02:31,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4405 states and 6414 transitions. [2021-11-23 14:02:31,704 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4116 [2021-11-23 14:02:31,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4405 states to 4405 states and 6414 transitions. [2021-11-23 14:02:31,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4405 [2021-11-23 14:02:31,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4405 [2021-11-23 14:02:31,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4405 states and 6414 transitions. [2021-11-23 14:02:31,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:31,767 INFO L681 BuchiCegarLoop]: Abstraction has 4405 states and 6414 transitions. [2021-11-23 14:02:31,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4405 states and 6414 transitions. [2021-11-23 14:02:31,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4405 to 4163. [2021-11-23 14:02:31,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4163 states, 4163 states have (on average 1.4633677636319962) internal successors, (6092), 4162 states have internal predecessors, (6092), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:31,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4163 states to 4163 states and 6092 transitions. [2021-11-23 14:02:31,969 INFO L704 BuchiCegarLoop]: Abstraction has 4163 states and 6092 transitions. [2021-11-23 14:02:31,969 INFO L587 BuchiCegarLoop]: Abstraction has 4163 states and 6092 transitions. [2021-11-23 14:02:31,970 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-23 14:02:31,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4163 states and 6092 transitions. [2021-11-23 14:02:32,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4058 [2021-11-23 14:02:32,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:32,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:32,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:32,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:32,005 INFO L791 eck$LassoCheckResult]: Stem: 15501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15442#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15440#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15325#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 15326#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15102#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15103#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15438#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15439#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15400#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15071#L586 assume !(0 == ~M_E~0); 15072#L586-2 assume !(0 == ~T1_E~0); 15128#L591-1 assume !(0 == ~T2_E~0); 15272#L596-1 assume !(0 == ~T3_E~0); 15273#L601-1 assume !(0 == ~T4_E~0); 15314#L606-1 assume !(0 == ~T5_E~0); 15315#L611-1 assume !(0 == ~E_1~0); 15412#L616-1 assume !(0 == ~E_2~0); 15413#L621-1 assume !(0 == ~E_3~0); 15003#L626-1 assume !(0 == ~E_4~0); 15004#L631-1 assume !(0 == ~E_5~0); 15167#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14999#L279 assume !(1 == ~m_pc~0); 15000#L279-2 is_master_triggered_~__retres1~0#1 := 0; 15337#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15245#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15246#L720 assume !(0 != activate_threads_~tmp~1#1); 15336#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15173#L298 assume !(1 == ~t1_pc~0); 14956#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14957#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15231#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15012#L728 assume !(0 != activate_threads_~tmp___0~0#1); 15013#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15134#L317 assume !(1 == ~t2_pc~0); 15135#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15356#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15457#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15182#L736 assume !(0 != activate_threads_~tmp___1~0#1); 15183#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15398#L336 assume 1 == ~t3_pc~0; 15237#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15238#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15299#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15300#L744 assume !(0 != activate_threads_~tmp___2~0#1); 15345#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15405#L355 assume !(1 == ~t4_pc~0); 15269#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15087#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15088#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15329#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15022#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15023#L374 assume 1 == ~t5_pc~0; 15432#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15157#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15243#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15244#L760 assume !(0 != activate_threads_~tmp___4~0#1); 15302#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15303#L649 assume !(1 == ~M_E~0); 15476#L649-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14988#L654-1 assume !(1 == ~T2_E~0); 14989#L659-1 assume !(1 == ~T3_E~0); 15181#L664-1 assume !(1 == ~T4_E~0); 14981#L669-1 assume !(1 == ~T5_E~0); 14982#L674-1 assume !(1 == ~E_1~0); 15392#L679-1 assume !(1 == ~E_2~0); 17077#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15078#L689-1 assume !(1 == ~E_4~0); 15499#L694-1 assume !(1 == ~E_5~0); 15261#L699-1 assume { :end_inline_reset_delta_events } true; 15262#L900-2 [2021-11-23 14:02:32,006 INFO L793 eck$LassoCheckResult]: Loop: 15262#L900-2 assume !false; 15506#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14935#L561 assume !false; 15019#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18403#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18393#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18094#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18087#L486 assume !(0 != eval_~tmp~0#1); 18089#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18642#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18624#L586-3 assume !(0 == ~M_E~0); 18620#L586-5 assume !(0 == ~T1_E~0); 18618#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18617#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18616#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18615#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18563#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18562#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18561#L621-3 assume !(0 == ~E_3~0); 18560#L626-3 assume !(0 == ~E_4~0); 18559#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18557#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18555#L279-18 assume !(1 == ~m_pc~0); 18553#L279-20 is_master_triggered_~__retres1~0#1 := 0; 18551#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18549#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18547#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18545#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18542#L298-18 assume 1 == ~t1_pc~0; 18539#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18537#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18535#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18533#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18531#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18529#L317-18 assume !(1 == ~t2_pc~0); 18527#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18525#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18523#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18521#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18519#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18516#L336-18 assume 1 == ~t3_pc~0; 18513#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15448#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15187#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15188#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18507#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18504#L355-18 assume !(1 == ~t4_pc~0); 18501#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 18499#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15136#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15137#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15143#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15144#L374-18 assume !(1 == ~t5_pc~0); 15367#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 15368#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18485#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15481#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15338#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15339#L649-3 assume !(1 == ~M_E~0); 15484#L649-5 assume !(1 == ~T1_E~0); 17903#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19003#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19002#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19001#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19000#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18999#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18998#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17880#L689-3 assume !(1 == ~E_4~0); 15151#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15152#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18996#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18989#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18987#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18983#L919 assume !(0 == start_simulation_~tmp~3#1); 18982#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18980#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18975#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18974#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18972#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18967#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18966#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18965#L932 assume !(0 != start_simulation_~tmp___0~1#1); 15262#L900-2 [2021-11-23 14:02:32,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:32,007 INFO L85 PathProgramCache]: Analyzing trace with hash -1412219296, now seen corresponding path program 1 times [2021-11-23 14:02:32,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:32,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77261215] [2021-11-23 14:02:32,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:32,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:32,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:32,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:32,069 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:32,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77261215] [2021-11-23 14:02:32,069 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77261215] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:32,070 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:32,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:32,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142998540] [2021-11-23 14:02:32,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:32,074 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:32,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:32,075 INFO L85 PathProgramCache]: Analyzing trace with hash 411612581, now seen corresponding path program 1 times [2021-11-23 14:02:32,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:32,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480004112] [2021-11-23 14:02:32,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:32,076 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:32,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:32,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:32,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:32,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480004112] [2021-11-23 14:02:32,132 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480004112] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:32,132 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:32,132 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:32,133 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667081816] [2021-11-23 14:02:32,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:32,133 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:32,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:32,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:02:32,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:02:32,135 INFO L87 Difference]: Start difference. First operand 4163 states and 6092 transitions. cyclomatic complexity: 1933 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:32,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:32,384 INFO L93 Difference]: Finished difference Result 11352 states and 16462 transitions. [2021-11-23 14:02:32,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:02:32,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11352 states and 16462 transitions. [2021-11-23 14:02:32,485 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10788 [2021-11-23 14:02:32,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11352 states to 11352 states and 16462 transitions. [2021-11-23 14:02:32,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11352 [2021-11-23 14:02:32,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11352 [2021-11-23 14:02:32,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11352 states and 16462 transitions. [2021-11-23 14:02:32,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:32,620 INFO L681 BuchiCegarLoop]: Abstraction has 11352 states and 16462 transitions. [2021-11-23 14:02:32,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11352 states and 16462 transitions. [2021-11-23 14:02:32,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11352 to 10668. [2021-11-23 14:02:32,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10668 states, 10668 states have (on average 1.4595050618672667) internal successors, (15570), 10667 states have internal predecessors, (15570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:32,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10668 states to 10668 states and 15570 transitions. [2021-11-23 14:02:32,987 INFO L704 BuchiCegarLoop]: Abstraction has 10668 states and 15570 transitions. [2021-11-23 14:02:32,987 INFO L587 BuchiCegarLoop]: Abstraction has 10668 states and 15570 transitions. [2021-11-23 14:02:32,987 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-23 14:02:32,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10668 states and 15570 transitions. [2021-11-23 14:02:33,048 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10524 [2021-11-23 14:02:33,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:33,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:33,050 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:33,050 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:33,051 INFO L791 eck$LassoCheckResult]: Stem: 31006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 30974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30960#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30958#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30841#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 30842#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30633#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30634#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30956#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30957#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30915#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30601#L586 assume !(0 == ~M_E~0); 30602#L586-2 assume !(0 == ~T1_E~0); 30660#L591-1 assume !(0 == ~T2_E~0); 30791#L596-1 assume !(0 == ~T3_E~0); 30792#L601-1 assume !(0 == ~T4_E~0); 30832#L606-1 assume !(0 == ~T5_E~0); 30833#L611-1 assume !(0 == ~E_1~0); 30927#L616-1 assume !(0 == ~E_2~0); 30928#L621-1 assume !(0 == ~E_3~0); 30530#L626-1 assume !(0 == ~E_4~0); 30531#L631-1 assume !(0 == ~E_5~0); 30694#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30526#L279 assume !(1 == ~m_pc~0); 30527#L279-2 is_master_triggered_~__retres1~0#1 := 0; 30856#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30769#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30770#L720 assume !(0 != activate_threads_~tmp~1#1); 30855#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30700#L298 assume !(1 == ~t1_pc~0); 30483#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30484#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30759#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30539#L728 assume !(0 != activate_threads_~tmp___0~0#1); 30540#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30666#L317 assume !(1 == ~t2_pc~0); 30667#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30874#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30968#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30710#L736 assume !(0 != activate_threads_~tmp___1~0#1); 30711#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30912#L336 assume !(1 == ~t3_pc~0); 30913#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30990#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30816#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30817#L744 assume !(0 != activate_threads_~tmp___2~0#1); 30864#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30921#L355 assume !(1 == ~t4_pc~0); 30788#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30618#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30619#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30846#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30551#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30552#L374 assume 1 == ~t5_pc~0; 30948#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30685#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30767#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30768#L760 assume !(0 != activate_threads_~tmp___4~0#1); 30819#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30820#L649 assume !(1 == ~M_E~0); 30983#L649-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31007#L654-1 assume !(1 == ~T2_E~0); 30850#L659-1 assume !(1 == ~T3_E~0); 30851#L664-1 assume !(1 == ~T4_E~0); 30508#L669-1 assume !(1 == ~T5_E~0); 30509#L674-1 assume !(1 == ~E_1~0); 30918#L679-1 assume !(1 == ~E_2~0); 30919#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 30608#L689-1 assume !(1 == ~E_4~0); 30785#L694-1 assume !(1 == ~E_5~0); 30783#L699-1 assume { :end_inline_reset_delta_events } true; 30784#L900-2 [2021-11-23 14:02:33,051 INFO L793 eck$LassoCheckResult]: Loop: 30784#L900-2 assume !false; 40550#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40548#L561 assume !false; 40547#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40545#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40540#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40539#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40538#L486 assume !(0 != eval_~tmp~0#1); 40537#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40535#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40533#L586-3 assume !(0 == ~M_E~0); 40532#L586-5 assume !(0 == ~T1_E~0); 40531#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30624#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30625#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30813#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30844#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30845#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30519#L621-3 assume !(0 == ~E_3~0); 30480#L626-3 assume !(0 == ~E_4~0); 30481#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30487#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30488#L279-18 assume !(1 == ~m_pc~0); 30730#L279-20 is_master_triggered_~__retres1~0#1 := 0; 30731#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30712#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30713#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30930#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30818#L298-18 assume !(1 == ~t1_pc~0); 30452#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 30453#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30632#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30656#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30657#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30793#L317-18 assume !(1 == ~t2_pc~0); 30794#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 30812#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40700#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40699#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30935#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30933#L336-18 assume !(1 == ~t3_pc~0); 30934#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 30963#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30714#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30715#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30574#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30575#L355-18 assume !(1 == ~t4_pc~0); 30862#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 30863#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30668#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30669#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30675#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30676#L374-18 assume !(1 == ~t5_pc~0); 30885#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 30744#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30745#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30879#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30857#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30858#L649-3 assume !(1 == ~M_E~0); 30763#L649-5 assume !(1 == ~T1_E~0); 30741#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30584#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30585#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30489#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30490#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30478#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30479#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30433#L689-3 assume !(1 == ~E_4~0); 30434#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30473#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30474#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30476#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30932#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 30780#L919 assume !(0 == start_simulation_~tmp~3#1); 30781#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40385#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40592#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40591#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 40590#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40589#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40588#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 40587#L932 assume !(0 != start_simulation_~tmp___0~1#1); 30784#L900-2 [2021-11-23 14:02:33,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:33,052 INFO L85 PathProgramCache]: Analyzing trace with hash -1469363521, now seen corresponding path program 1 times [2021-11-23 14:02:33,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:33,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994744271] [2021-11-23 14:02:33,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:33,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:33,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:33,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:33,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:33,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994744271] [2021-11-23 14:02:33,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994744271] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:33,187 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:33,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:33,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063223532] [2021-11-23 14:02:33,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:33,189 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:33,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:33,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1641100573, now seen corresponding path program 1 times [2021-11-23 14:02:33,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:33,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95353308] [2021-11-23 14:02:33,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:33,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:33,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:33,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:33,232 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:33,233 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95353308] [2021-11-23 14:02:33,233 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95353308] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:33,233 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:33,233 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:33,233 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390523201] [2021-11-23 14:02:33,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:33,234 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:33,234 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:33,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 14:02:33,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-23 14:02:33,236 INFO L87 Difference]: Start difference. First operand 10668 states and 15570 transitions. cyclomatic complexity: 4910 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:33,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:33,587 INFO L93 Difference]: Finished difference Result 26239 states and 38611 transitions. [2021-11-23 14:02:33,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-23 14:02:33,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26239 states and 38611 transitions. [2021-11-23 14:02:33,790 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25924 [2021-11-23 14:02:33,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26239 states to 26239 states and 38611 transitions. [2021-11-23 14:02:33,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26239 [2021-11-23 14:02:33,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26239 [2021-11-23 14:02:33,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26239 states and 38611 transitions. [2021-11-23 14:02:33,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:33,971 INFO L681 BuchiCegarLoop]: Abstraction has 26239 states and 38611 transitions. [2021-11-23 14:02:33,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26239 states and 38611 transitions. [2021-11-23 14:02:34,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26239 to 11151. [2021-11-23 14:02:34,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11151 states, 11151 states have (on average 1.4396018294323378) internal successors, (16053), 11150 states have internal predecessors, (16053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:34,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11151 states to 11151 states and 16053 transitions. [2021-11-23 14:02:34,417 INFO L704 BuchiCegarLoop]: Abstraction has 11151 states and 16053 transitions. [2021-11-23 14:02:34,418 INFO L587 BuchiCegarLoop]: Abstraction has 11151 states and 16053 transitions. [2021-11-23 14:02:34,418 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-23 14:02:34,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11151 states and 16053 transitions. [2021-11-23 14:02:34,458 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11004 [2021-11-23 14:02:34,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:34,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:34,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:34,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:34,461 INFO L791 eck$LassoCheckResult]: Stem: 67940#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 67902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 67889#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67887#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67769#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 67770#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67555#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67556#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67885#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67886#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67848#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67525#L586 assume !(0 == ~M_E~0); 67526#L586-2 assume !(0 == ~T1_E~0); 67583#L591-1 assume !(0 == ~T2_E~0); 67716#L596-1 assume !(0 == ~T3_E~0); 67717#L601-1 assume !(0 == ~T4_E~0); 67759#L606-1 assume !(0 == ~T5_E~0); 67760#L611-1 assume !(0 == ~E_1~0); 67857#L616-1 assume !(0 == ~E_2~0); 67858#L621-1 assume !(0 == ~E_3~0); 67453#L626-1 assume !(0 == ~E_4~0); 67454#L631-1 assume !(0 == ~E_5~0); 67616#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67449#L279 assume !(1 == ~m_pc~0); 67450#L279-2 is_master_triggered_~__retres1~0#1 := 0; 67781#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67688#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67689#L720 assume !(0 != activate_threads_~tmp~1#1); 67780#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67620#L298 assume !(1 == ~t1_pc~0); 67405#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67406#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67678#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67462#L728 assume !(0 != activate_threads_~tmp___0~0#1); 67463#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67589#L317 assume !(1 == ~t2_pc~0); 67590#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67801#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67896#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67629#L736 assume !(0 != activate_threads_~tmp___1~0#1); 67630#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67845#L336 assume !(1 == ~t3_pc~0); 67846#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67924#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67741#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67742#L744 assume !(0 != activate_threads_~tmp___2~0#1); 67790#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67852#L355 assume !(1 == ~t4_pc~0); 67713#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67541#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67542#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67838#L752 assume !(0 != activate_threads_~tmp___3~0#1); 67477#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67478#L374 assume 1 == ~t5_pc~0; 67877#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67608#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67686#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67687#L760 assume !(0 != activate_threads_~tmp___4~0#1); 67744#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67745#L649 assume !(1 == ~M_E~0); 67912#L649-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67437#L654-1 assume !(1 == ~T2_E~0); 67438#L659-1 assume !(1 == ~T3_E~0); 67628#L664-1 assume !(1 == ~T4_E~0); 67430#L669-1 assume !(1 == ~T5_E~0); 67431#L674-1 assume !(1 == ~E_1~0); 67841#L679-1 assume !(1 == ~E_2~0); 67530#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 67531#L689-1 assume !(1 == ~E_4~0); 67708#L694-1 assume !(1 == ~E_5~0); 67706#L699-1 assume { :end_inline_reset_delta_events } true; 67707#L900-2 [2021-11-23 14:02:34,461 INFO L793 eck$LassoCheckResult]: Loop: 67707#L900-2 assume !false; 77885#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77878#L561 assume !false; 77856#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 67660#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 67407#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 67408#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67518#L486 assume !(0 != eval_~tmp~0#1); 67520#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78490#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78488#L586-3 assume !(0 == ~M_E~0); 77324#L586-5 assume !(0 == ~T1_E~0); 77322#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77320#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77317#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77315#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77313#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77311#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77309#L621-3 assume !(0 == ~E_3~0); 77306#L626-3 assume !(0 == ~E_4~0); 77304#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77302#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77301#L279-18 assume !(1 == ~m_pc~0); 77300#L279-20 is_master_triggered_~__retres1~0#1 := 0; 77299#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77298#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77297#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77296#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77295#L298-18 assume 1 == ~t1_pc~0; 77293#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77292#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77291#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77290#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77289#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77288#L317-18 assume !(1 == ~t2_pc~0); 77287#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 77286#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77285#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77284#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77283#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77282#L336-18 assume !(1 == ~t3_pc~0); 77281#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 77280#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77279#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77278#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77277#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77276#L355-18 assume !(1 == ~t4_pc~0); 77275#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 77273#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77271#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77269#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 77267#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77266#L374-18 assume !(1 == ~t5_pc~0); 77265#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 77263#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77262#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77261#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77260#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77259#L649-3 assume !(1 == ~M_E~0); 77196#L649-5 assume !(1 == ~T1_E~0); 74884#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77255#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77254#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77253#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77252#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77251#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77250#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74868#L689-3 assume !(1 == ~E_4~0); 77249#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77248#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 77247#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 77241#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 77240#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 77238#L919 assume !(0 == start_simulation_~tmp~3#1); 77239#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 77921#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 77915#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 77913#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 77911#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77909#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77907#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 77905#L932 assume !(0 != start_simulation_~tmp___0~1#1); 67707#L900-2 [2021-11-23 14:02:34,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:34,462 INFO L85 PathProgramCache]: Analyzing trace with hash 2007955325, now seen corresponding path program 1 times [2021-11-23 14:02:34,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:34,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716913732] [2021-11-23 14:02:34,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:34,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:34,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:34,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:34,615 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:34,615 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716913732] [2021-11-23 14:02:34,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716913732] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:34,615 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:34,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 14:02:34,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973083335] [2021-11-23 14:02:34,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:34,616 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:34,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:34,617 INFO L85 PathProgramCache]: Analyzing trace with hash -1469142206, now seen corresponding path program 1 times [2021-11-23 14:02:34,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:34,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368386252] [2021-11-23 14:02:34,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:34,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:34,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:34,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:34,655 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:34,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368386252] [2021-11-23 14:02:34,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368386252] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:34,656 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:34,656 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:34,656 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857468225] [2021-11-23 14:02:34,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:34,657 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:34,657 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:34,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:34,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:34,659 INFO L87 Difference]: Start difference. First operand 11151 states and 16053 transitions. cyclomatic complexity: 4910 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:34,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:34,811 INFO L93 Difference]: Finished difference Result 22018 states and 31460 transitions. [2021-11-23 14:02:34,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:34,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22018 states and 31460 transitions. [2021-11-23 14:02:34,942 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21740 [2021-11-23 14:02:35,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22018 states to 22018 states and 31460 transitions. [2021-11-23 14:02:35,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22018 [2021-11-23 14:02:35,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22018 [2021-11-23 14:02:35,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22018 states and 31460 transitions. [2021-11-23 14:02:35,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:35,216 INFO L681 BuchiCegarLoop]: Abstraction has 22018 states and 31460 transitions. [2021-11-23 14:02:35,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22018 states and 31460 transitions. [2021-11-23 14:02:35,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22018 to 21874. [2021-11-23 14:02:35,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21874 states, 21874 states have (on average 1.430008228947609) internal successors, (31280), 21873 states have internal predecessors, (31280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:35,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21874 states to 21874 states and 31280 transitions. [2021-11-23 14:02:35,739 INFO L704 BuchiCegarLoop]: Abstraction has 21874 states and 31280 transitions. [2021-11-23 14:02:35,740 INFO L587 BuchiCegarLoop]: Abstraction has 21874 states and 31280 transitions. [2021-11-23 14:02:35,740 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-23 14:02:35,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21874 states and 31280 transitions. [2021-11-23 14:02:35,836 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2021-11-23 14:02:35,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:35,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:35,838 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:35,838 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:35,839 INFO L791 eck$LassoCheckResult]: Stem: 101119#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 101082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 101068#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101064#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100942#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 100943#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100729#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100730#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101062#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101063#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101022#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100697#L586 assume !(0 == ~M_E~0); 100698#L586-2 assume !(0 == ~T1_E~0); 100756#L591-1 assume !(0 == ~T2_E~0); 100888#L596-1 assume !(0 == ~T3_E~0); 100889#L601-1 assume !(0 == ~T4_E~0); 100933#L606-1 assume !(0 == ~T5_E~0); 100934#L611-1 assume !(0 == ~E_1~0); 101033#L616-1 assume !(0 == ~E_2~0); 101034#L621-1 assume !(0 == ~E_3~0); 100628#L626-1 assume !(0 == ~E_4~0); 100629#L631-1 assume !(0 == ~E_5~0); 100792#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100624#L279 assume !(1 == ~m_pc~0); 100625#L279-2 is_master_triggered_~__retres1~0#1 := 0; 100955#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100865#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 100866#L720 assume !(0 != activate_threads_~tmp~1#1); 100954#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100796#L298 assume !(1 == ~t1_pc~0); 100582#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100583#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100854#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100638#L728 assume !(0 != activate_threads_~tmp___0~0#1); 100639#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100762#L317 assume !(1 == ~t2_pc~0); 100763#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100975#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101074#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100808#L736 assume !(0 != activate_threads_~tmp___1~0#1); 100809#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101020#L336 assume !(1 == ~t3_pc~0); 101021#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101104#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100915#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100916#L744 assume !(0 != activate_threads_~tmp___2~0#1); 100964#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101028#L355 assume !(1 == ~t4_pc~0); 100885#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100714#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100715#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100948#L752 assume !(0 != activate_threads_~tmp___3~0#1); 100651#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100652#L374 assume !(1 == ~t5_pc~0); 100782#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100783#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100863#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100864#L760 assume !(0 != activate_threads_~tmp___4~0#1); 100918#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100919#L649 assume !(1 == ~M_E~0); 101097#L649-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100613#L654-1 assume !(1 == ~T2_E~0); 100614#L659-1 assume !(1 == ~T3_E~0); 100804#L664-1 assume !(1 == ~T4_E~0); 100805#L669-1 assume !(1 == ~T5_E~0); 112080#L674-1 assume !(1 == ~E_1~0); 112078#L679-1 assume !(1 == ~E_2~0); 100702#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 100703#L689-1 assume !(1 == ~E_4~0); 100881#L694-1 assume !(1 == ~E_5~0); 100879#L699-1 assume { :end_inline_reset_delta_events } true; 100880#L900-2 [2021-11-23 14:02:35,839 INFO L793 eck$LassoCheckResult]: Loop: 100880#L900-2 assume !false; 117380#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117375#L561 assume !false; 117369#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117344#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117338#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117336#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 117334#L486 assume !(0 != eval_~tmp~0#1); 101107#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 101089#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101090#L586-3 assume !(0 == ~M_E~0); 101091#L586-5 assume !(0 == ~T1_E~0); 117637#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117636#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117634#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117633#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117632#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117631#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117630#L621-3 assume !(0 == ~E_3~0); 117628#L626-3 assume !(0 == ~E_4~0); 117626#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117624#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117622#L279-18 assume !(1 == ~m_pc~0); 117620#L279-20 is_master_triggered_~__retres1~0#1 := 0; 117618#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117616#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 117614#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117612#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117610#L298-18 assume 1 == ~t1_pc~0; 117607#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 117605#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117603#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117601#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117599#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117597#L317-18 assume !(1 == ~t2_pc~0); 117595#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 117593#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117591#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117589#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117586#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117584#L336-18 assume !(1 == ~t3_pc~0); 117582#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 117580#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117578#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 117576#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117574#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117569#L355-18 assume 1 == ~t4_pc~0; 117570#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117571#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117635#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 117560#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117558#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117556#L374-18 assume !(1 == ~t5_pc~0); 117554#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 117536#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117531#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117525#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117519#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117513#L649-3 assume !(1 == ~M_E~0); 117507#L649-5 assume !(1 == ~T1_E~0); 112272#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117503#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117502#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117501#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117500#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 117498#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 117496#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112262#L689-3 assume !(1 == ~E_4~0); 117493#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117491#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117489#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117479#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117472#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 117465#L919 assume !(0 == start_simulation_~tmp~3#1); 117461#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117423#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117415#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117408#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 117402#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117399#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117398#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 117397#L932 assume !(0 != start_simulation_~tmp___0~1#1); 100880#L900-2 [2021-11-23 14:02:35,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:35,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1146660260, now seen corresponding path program 1 times [2021-11-23 14:02:35,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:35,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24051471] [2021-11-23 14:02:35,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:35,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:35,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:35,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:35,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:35,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24051471] [2021-11-23 14:02:35,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24051471] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:35,872 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:35,872 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 14:02:35,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479927539] [2021-11-23 14:02:35,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:35,873 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:35,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:35,874 INFO L85 PathProgramCache]: Analyzing trace with hash 20914789, now seen corresponding path program 1 times [2021-11-23 14:02:35,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:35,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254788700] [2021-11-23 14:02:35,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:35,875 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:35,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:35,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:35,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:35,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254788700] [2021-11-23 14:02:35,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254788700] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:35,902 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:35,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:35,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328709528] [2021-11-23 14:02:35,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:35,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:35,904 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:35,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:35,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:35,905 INFO L87 Difference]: Start difference. First operand 21874 states and 31280 transitions. cyclomatic complexity: 9422 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:36,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:36,022 INFO L93 Difference]: Finished difference Result 21867 states and 31085 transitions. [2021-11-23 14:02:36,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:36,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21867 states and 31085 transitions. [2021-11-23 14:02:36,359 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2021-11-23 14:02:36,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21867 states to 21867 states and 31085 transitions. [2021-11-23 14:02:36,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21867 [2021-11-23 14:02:36,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21867 [2021-11-23 14:02:36,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21867 states and 31085 transitions. [2021-11-23 14:02:36,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:36,518 INFO L681 BuchiCegarLoop]: Abstraction has 21867 states and 31085 transitions. [2021-11-23 14:02:36,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21867 states and 31085 transitions. [2021-11-23 14:02:36,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21867 to 11243. [2021-11-23 14:02:36,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4189273325624834) internal successors, (15953), 11242 states have internal predecessors, (15953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:36,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15953 transitions. [2021-11-23 14:02:36,918 INFO L704 BuchiCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2021-11-23 14:02:36,918 INFO L587 BuchiCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2021-11-23 14:02:36,919 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-23 14:02:36,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15953 transitions. [2021-11-23 14:02:36,959 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2021-11-23 14:02:36,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:36,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:36,961 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:36,961 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:36,961 INFO L791 eck$LassoCheckResult]: Stem: 144881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 144837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 144822#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144818#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144694#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 144695#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144478#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144479#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144816#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144817#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144778#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144452#L586 assume !(0 == ~M_E~0); 144453#L586-2 assume !(0 == ~T1_E~0); 144507#L591-1 assume !(0 == ~T2_E~0); 144639#L596-1 assume !(0 == ~T3_E~0); 144640#L601-1 assume !(0 == ~T4_E~0); 144684#L606-1 assume !(0 == ~T5_E~0); 144685#L611-1 assume !(0 == ~E_1~0); 144785#L616-1 assume !(0 == ~E_2~0); 144786#L621-1 assume !(0 == ~E_3~0); 144375#L626-1 assume !(0 == ~E_4~0); 144376#L631-1 assume !(0 == ~E_5~0); 144542#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144373#L279 assume !(1 == ~m_pc~0); 144374#L279-2 is_master_triggered_~__retres1~0#1 := 0; 144707#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144613#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144614#L720 assume !(0 != activate_threads_~tmp~1#1); 144706#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144546#L298 assume !(1 == ~t1_pc~0); 144331#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 144332#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144602#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 144385#L728 assume !(0 != activate_threads_~tmp___0~0#1); 144386#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144513#L317 assume !(1 == ~t2_pc~0); 144514#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 144728#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144832#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144560#L736 assume !(0 != activate_threads_~tmp___1~0#1); 144561#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144775#L336 assume !(1 == ~t3_pc~0); 144776#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144864#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144667#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144668#L744 assume !(0 != activate_threads_~tmp___2~0#1); 144717#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144782#L355 assume !(1 == ~t4_pc~0); 144638#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144780#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144886#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144765#L752 assume !(0 != activate_threads_~tmp___3~0#1); 144401#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144402#L374 assume !(1 == ~t5_pc~0); 144535#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 144536#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144611#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144612#L760 assume !(0 != activate_threads_~tmp___4~0#1); 144670#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144671#L649 assume !(1 == ~M_E~0); 144856#L649-2 assume !(1 == ~T1_E~0); 144360#L654-1 assume !(1 == ~T2_E~0); 144361#L659-1 assume !(1 == ~T3_E~0); 144554#L664-1 assume !(1 == ~T4_E~0); 144353#L669-1 assume !(1 == ~T5_E~0); 144354#L674-1 assume !(1 == ~E_1~0); 144766#L679-1 assume !(1 == ~E_2~0); 144454#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 144455#L689-1 assume !(1 == ~E_4~0); 144632#L694-1 assume !(1 == ~E_5~0); 144630#L699-1 assume { :end_inline_reset_delta_events } true; 144631#L900-2 [2021-11-23 14:02:36,962 INFO L793 eck$LassoCheckResult]: Loop: 144631#L900-2 assume !false; 144874#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 144394#L561 assume !false; 144395#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 152359#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 152349#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 152347#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 152345#L486 assume !(0 != eval_~tmp~0#1); 152344#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 152343#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 152342#L586-3 assume !(0 == ~M_E~0); 152340#L586-5 assume !(0 == ~T1_E~0); 152339#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 152338#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 152331#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152329#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152328#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152327#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152324#L621-3 assume !(0 == ~E_3~0); 152321#L626-3 assume !(0 == ~E_4~0); 152320#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152319#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152318#L279-18 assume !(1 == ~m_pc~0); 152317#L279-20 is_master_triggered_~__retres1~0#1 := 0; 152315#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152312#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 152311#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 152310#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152309#L298-18 assume 1 == ~t1_pc~0; 152306#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 152305#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152304#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 152302#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152300#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152298#L317-18 assume !(1 == ~t2_pc~0); 152296#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 152294#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152292#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 152290#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152288#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152285#L336-18 assume !(1 == ~t3_pc~0); 152283#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 152281#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152279#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152277#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 152275#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152270#L355-18 assume 1 == ~t4_pc~0; 152271#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 152272#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152308#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152261#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 152259#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152257#L374-18 assume !(1 == ~t5_pc~0); 152255#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 152252#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152250#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152249#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 152245#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152242#L649-3 assume !(1 == ~M_E~0); 152240#L649-5 assume !(1 == ~T1_E~0); 152237#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152234#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152232#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152230#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152227#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 152228#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 154819#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154817#L689-3 assume !(1 == ~E_4~0); 154815#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154813#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 151970#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 151962#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 151960#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 151957#L919 assume !(0 == start_simulation_~tmp~3#1); 151958#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 155410#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 144808#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 144565#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 144566#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144615#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 144563#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 144564#L932 assume !(0 != start_simulation_~tmp___0~1#1); 144631#L900-2 [2021-11-23 14:02:36,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:36,962 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2021-11-23 14:02:36,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:36,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788687622] [2021-11-23 14:02:36,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:36,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:36,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:37,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:37,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:37,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788687622] [2021-11-23 14:02:37,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788687622] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:37,008 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:37,009 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:37,009 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009457708] [2021-11-23 14:02:37,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:37,010 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:37,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:37,011 INFO L85 PathProgramCache]: Analyzing trace with hash 20914789, now seen corresponding path program 2 times [2021-11-23 14:02:37,011 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:37,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177291132] [2021-11-23 14:02:37,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:37,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:37,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:37,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:37,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:37,062 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177291132] [2021-11-23 14:02:37,063 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177291132] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:37,063 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:37,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:37,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916327574] [2021-11-23 14:02:37,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:37,064 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:37,065 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:37,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:02:37,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:02:37,065 INFO L87 Difference]: Start difference. First operand 11243 states and 15953 transitions. cyclomatic complexity: 4718 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:37,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:37,242 INFO L93 Difference]: Finished difference Result 18761 states and 26436 transitions. [2021-11-23 14:02:37,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:02:37,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18761 states and 26436 transitions. [2021-11-23 14:02:37,344 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18573 [2021-11-23 14:02:37,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18761 states to 18761 states and 26436 transitions. [2021-11-23 14:02:37,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18761 [2021-11-23 14:02:37,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18761 [2021-11-23 14:02:37,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18761 states and 26436 transitions. [2021-11-23 14:02:37,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:37,454 INFO L681 BuchiCegarLoop]: Abstraction has 18761 states and 26436 transitions. [2021-11-23 14:02:37,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18761 states and 26436 transitions. [2021-11-23 14:02:37,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18761 to 11243. [2021-11-23 14:02:37,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4069198612469982) internal successors, (15818), 11242 states have internal predecessors, (15818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:37,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15818 transitions. [2021-11-23 14:02:37,903 INFO L704 BuchiCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2021-11-23 14:02:37,903 INFO L587 BuchiCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2021-11-23 14:02:37,904 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-23 14:02:37,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15818 transitions. [2021-11-23 14:02:37,942 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2021-11-23 14:02:37,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:37,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:37,944 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:37,944 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:37,944 INFO L791 eck$LassoCheckResult]: Stem: 174862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 174823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 174811#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174809#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174700#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 174701#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174487#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174488#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174807#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174808#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174772#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 174462#L586 assume !(0 == ~M_E~0); 174463#L586-2 assume !(0 == ~T1_E~0); 174515#L591-1 assume !(0 == ~T2_E~0); 174646#L596-1 assume !(0 == ~T3_E~0); 174647#L601-1 assume !(0 == ~T4_E~0); 174691#L606-1 assume !(0 == ~T5_E~0); 174692#L611-1 assume !(0 == ~E_1~0); 174781#L616-1 assume !(0 == ~E_2~0); 174782#L621-1 assume !(0 == ~E_3~0); 174391#L626-1 assume !(0 == ~E_4~0); 174392#L631-1 assume !(0 == ~E_5~0); 174549#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174389#L279 assume !(1 == ~m_pc~0); 174390#L279-2 is_master_triggered_~__retres1~0#1 := 0; 174712#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174622#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174623#L720 assume !(0 != activate_threads_~tmp~1#1); 174711#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174555#L298 assume !(1 == ~t1_pc~0); 174347#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174348#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174613#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174400#L728 assume !(0 != activate_threads_~tmp___0~0#1); 174401#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174521#L317 assume !(1 == ~t2_pc~0); 174522#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174729#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174819#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174571#L736 assume !(0 != activate_threads_~tmp___1~0#1); 174572#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174768#L336 assume !(1 == ~t3_pc~0); 174769#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174843#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174671#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174672#L744 assume !(0 != activate_threads_~tmp___2~0#1); 174720#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174778#L355 assume !(1 == ~t4_pc~0); 174645#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174775#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174866#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174762#L752 assume !(0 != activate_threads_~tmp___3~0#1); 174413#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174414#L374 assume !(1 == ~t5_pc~0); 174542#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174543#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174620#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174621#L760 assume !(0 != activate_threads_~tmp___4~0#1); 174676#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174677#L649 assume !(1 == ~M_E~0); 174833#L649-2 assume !(1 == ~T1_E~0); 174376#L654-1 assume !(1 == ~T2_E~0); 174377#L659-1 assume !(1 == ~T3_E~0); 174564#L664-1 assume !(1 == ~T4_E~0); 174369#L669-1 assume !(1 == ~T5_E~0); 174370#L674-1 assume !(1 == ~E_1~0); 174763#L679-1 assume !(1 == ~E_2~0); 174464#L684-1 assume !(1 == ~E_3~0); 174465#L689-1 assume !(1 == ~E_4~0); 174640#L694-1 assume !(1 == ~E_5~0); 174637#L699-1 assume { :end_inline_reset_delta_events } true; 174638#L900-2 [2021-11-23 14:02:37,945 INFO L793 eck$LassoCheckResult]: Loop: 174638#L900-2 assume !false; 181307#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 181188#L561 assume !false; 181306#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 181304#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 181299#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 181298#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 181297#L486 assume !(0 != eval_~tmp~0#1); 177439#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 177440#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 177433#L586-3 assume !(0 == ~M_E~0); 177434#L586-5 assume !(0 == ~T1_E~0); 177425#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 177426#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 177417#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 177418#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 177409#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177410#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 177401#L621-3 assume !(0 == ~E_3~0); 177402#L626-3 assume !(0 == ~E_4~0); 177393#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177394#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177379#L279-18 assume !(1 == ~m_pc~0); 177380#L279-20 is_master_triggered_~__retres1~0#1 := 0; 177369#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 177370#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 177362#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 177363#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 177353#L298-18 assume 1 == ~t1_pc~0; 177354#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 177343#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177344#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 177335#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 177336#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177326#L317-18 assume !(1 == ~t2_pc~0); 177327#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 177318#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177319#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 177310#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 177311#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177302#L336-18 assume !(1 == ~t3_pc~0); 177303#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 177295#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177296#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177287#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 177288#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 177278#L355-18 assume 1 == ~t4_pc~0; 177280#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 177265#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177266#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 177252#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 177253#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177241#L374-18 assume !(1 == ~t5_pc~0); 177242#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 177231#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 177232#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 177223#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177224#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177216#L649-3 assume !(1 == ~M_E~0); 177214#L649-5 assume !(1 == ~T1_E~0); 177207#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 177208#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177199#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177200#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177189#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 177190#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 177179#L684-3 assume !(1 == ~E_3~0); 177180#L689-3 assume !(1 == ~E_4~0); 177169#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177170#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177115#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 177104#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 177100#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 177094#L919 assume !(0 == start_simulation_~tmp~3#1); 177090#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177091#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 181313#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 181312#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 181311#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 181310#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 181309#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 181308#L932 assume !(0 != start_simulation_~tmp___0~1#1); 174638#L900-2 [2021-11-23 14:02:37,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:37,945 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2021-11-23 14:02:37,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:37,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763804100] [2021-11-23 14:02:37,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:37,946 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:37,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:37,957 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:37,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:38,009 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:38,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:38,011 INFO L85 PathProgramCache]: Analyzing trace with hash -1000153565, now seen corresponding path program 1 times [2021-11-23 14:02:38,011 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:38,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554136098] [2021-11-23 14:02:38,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:38,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:38,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:38,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:38,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:38,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554136098] [2021-11-23 14:02:38,132 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554136098] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:38,132 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:38,132 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:38,132 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97994409] [2021-11-23 14:02:38,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:38,133 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:38,133 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:38,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:38,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:38,134 INFO L87 Difference]: Start difference. First operand 11243 states and 15818 transitions. cyclomatic complexity: 4583 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:38,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:38,280 INFO L93 Difference]: Finished difference Result 19860 states and 27670 transitions. [2021-11-23 14:02:38,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:38,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19860 states and 27670 transitions. [2021-11-23 14:02:38,378 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19614 [2021-11-23 14:02:38,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19860 states to 19860 states and 27670 transitions. [2021-11-23 14:02:38,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19860 [2021-11-23 14:02:38,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19860 [2021-11-23 14:02:38,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19860 states and 27670 transitions. [2021-11-23 14:02:38,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:38,494 INFO L681 BuchiCegarLoop]: Abstraction has 19860 states and 27670 transitions. [2021-11-23 14:02:38,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19860 states and 27670 transitions. [2021-11-23 14:02:38,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19860 to 19848. [2021-11-23 14:02:38,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19848 states, 19848 states have (on average 1.393490528012898) internal successors, (27658), 19847 states have internal predecessors, (27658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:38,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19848 states to 19848 states and 27658 transitions. [2021-11-23 14:02:38,880 INFO L704 BuchiCegarLoop]: Abstraction has 19848 states and 27658 transitions. [2021-11-23 14:02:38,880 INFO L587 BuchiCegarLoop]: Abstraction has 19848 states and 27658 transitions. [2021-11-23 14:02:38,880 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-23 14:02:38,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19848 states and 27658 transitions. [2021-11-23 14:02:38,942 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19602 [2021-11-23 14:02:38,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:38,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:38,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:38,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:38,946 INFO L791 eck$LassoCheckResult]: Stem: 206025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 205973#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 205961#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 205956#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205820#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 205821#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205601#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205602#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205954#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205955#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205907#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205574#L586 assume !(0 == ~M_E~0); 205575#L586-2 assume !(0 == ~T1_E~0); 205626#L591-1 assume !(0 == ~T2_E~0); 205762#L596-1 assume !(0 == ~T3_E~0); 205763#L601-1 assume !(0 == ~T4_E~0); 205810#L606-1 assume !(0 == ~T5_E~0); 205811#L611-1 assume !(0 == ~E_1~0); 205918#L616-1 assume !(0 == ~E_2~0); 205919#L621-1 assume !(0 == ~E_3~0); 205499#L626-1 assume 0 == ~E_4~0;~E_4~0 := 1; 205500#L631-1 assume !(0 == ~E_5~0); 205659#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205660#L279 assume !(1 == ~m_pc~0); 205834#L279-2 is_master_triggered_~__retres1~0#1 := 0; 205835#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205735#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205736#L720 assume !(0 != activate_threads_~tmp~1#1); 206044#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205666#L298 assume !(1 == ~t1_pc~0); 205667#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 206003#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206004#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 206043#L728 assume !(0 != activate_threads_~tmp___0~0#1); 206042#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206041#L317 assume !(1 == ~t2_pc~0); 205857#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205858#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206040#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205683#L736 assume !(0 != activate_threads_~tmp___1~0#1); 205684#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 205982#L336 assume !(1 == ~t3_pc~0); 206000#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 206001#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206023#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205844#L744 assume !(0 != activate_threads_~tmp___2~0#1); 205845#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206037#L355 assume !(1 == ~t4_pc~0); 205909#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 205910#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206048#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206046#L752 assume !(0 != activate_threads_~tmp___3~0#1); 205524#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 205525#L374 assume !(1 == ~t5_pc~0); 205652#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205653#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205733#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 205734#L760 assume !(0 != activate_threads_~tmp___4~0#1); 205793#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205794#L649 assume !(1 == ~M_E~0); 206045#L649-2 assume !(1 == ~T1_E~0); 205484#L654-1 assume !(1 == ~T2_E~0); 205485#L659-1 assume !(1 == ~T3_E~0); 206036#L664-1 assume !(1 == ~T4_E~0); 206035#L669-1 assume !(1 == ~T5_E~0); 206034#L674-1 assume !(1 == ~E_1~0); 206033#L679-1 assume !(1 == ~E_2~0); 206032#L684-1 assume !(1 == ~E_3~0); 205755#L689-1 assume 1 == ~E_4~0;~E_4~0 := 2; 205756#L694-1 assume !(1 == ~E_5~0); 205753#L699-1 assume { :end_inline_reset_delta_events } true; 205754#L900-2 [2021-11-23 14:02:38,946 INFO L793 eck$LassoCheckResult]: Loop: 205754#L900-2 assume !false; 216056#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216047#L561 assume !false; 216042#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216010#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 215998#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 215992#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 213905#L486 assume !(0 != eval_~tmp~0#1); 213906#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216548#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216546#L586-3 assume !(0 == ~M_E~0); 216544#L586-5 assume !(0 == ~T1_E~0); 216542#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 216540#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216537#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 216535#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 216533#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 216531#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216528#L621-3 assume !(0 == ~E_3~0); 216525#L626-3 assume !(0 == ~E_4~0); 216523#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216521#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216519#L279-18 assume !(1 == ~m_pc~0); 216517#L279-20 is_master_triggered_~__retres1~0#1 := 0; 216515#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216513#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 216512#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216511#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216510#L298-18 assume 1 == ~t1_pc~0; 216507#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 216505#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216503#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216501#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216499#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216497#L317-18 assume !(1 == ~t2_pc~0); 216495#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 216494#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216493#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216491#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216489#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216487#L336-18 assume !(1 == ~t3_pc~0); 216485#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 216483#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216481#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216479#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216476#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216471#L355-18 assume !(1 == ~t4_pc~0); 216469#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 216467#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216465#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216463#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 216461#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216457#L374-18 assume !(1 == ~t5_pc~0); 216455#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 216453#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216451#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216448#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216446#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216444#L649-3 assume !(1 == ~M_E~0); 216440#L649-5 assume !(1 == ~T1_E~0); 216438#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 216415#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216411#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 216324#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216316#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 216315#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216305#L684-3 assume !(1 == ~E_3~0); 216297#L689-3 assume !(1 == ~E_4~0); 216290#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216281#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216261#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216219#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216214#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 216207#L919 assume !(0 == start_simulation_~tmp~3#1); 216204#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216085#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216079#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216077#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 216075#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216072#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216070#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 216068#L932 assume !(0 != start_simulation_~tmp___0~1#1); 205754#L900-2 [2021-11-23 14:02:38,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:38,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1583048088, now seen corresponding path program 1 times [2021-11-23 14:02:38,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:38,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065966485] [2021-11-23 14:02:38,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:38,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:38,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:38,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:38,982 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:38,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065966485] [2021-11-23 14:02:38,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065966485] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:38,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:38,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:38,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930702710] [2021-11-23 14:02:38,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:38,984 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:38,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:38,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1804756736, now seen corresponding path program 1 times [2021-11-23 14:02:38,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:38,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514762204] [2021-11-23 14:02:38,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:38,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:38,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:39,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:39,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:39,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514762204] [2021-11-23 14:02:39,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514762204] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:39,021 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:39,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:39,021 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111115334] [2021-11-23 14:02:39,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:39,022 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:39,023 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:39,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 14:02:39,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 14:02:39,024 INFO L87 Difference]: Start difference. First operand 19848 states and 27658 transitions. cyclomatic complexity: 7818 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:39,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:39,364 INFO L93 Difference]: Finished difference Result 39005 states and 54351 transitions. [2021-11-23 14:02:39,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 14:02:39,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39005 states and 54351 transitions. [2021-11-23 14:02:39,550 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35729 [2021-11-23 14:02:39,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39005 states to 39005 states and 54351 transitions. [2021-11-23 14:02:39,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39005 [2021-11-23 14:02:39,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39005 [2021-11-23 14:02:39,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39005 states and 54351 transitions. [2021-11-23 14:02:40,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:40,014 INFO L681 BuchiCegarLoop]: Abstraction has 39005 states and 54351 transitions. [2021-11-23 14:02:40,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39005 states and 54351 transitions. [2021-11-23 14:02:40,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39005 to 19815. [2021-11-23 14:02:40,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19815 states, 19815 states have (on average 1.3918748422911935) internal successors, (27580), 19814 states have internal predecessors, (27580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:40,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19815 states to 19815 states and 27580 transitions. [2021-11-23 14:02:40,604 INFO L704 BuchiCegarLoop]: Abstraction has 19815 states and 27580 transitions. [2021-11-23 14:02:40,605 INFO L587 BuchiCegarLoop]: Abstraction has 19815 states and 27580 transitions. [2021-11-23 14:02:40,605 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-23 14:02:40,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19815 states and 27580 transitions. [2021-11-23 14:02:40,683 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19602 [2021-11-23 14:02:40,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:40,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:40,685 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:40,686 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:40,686 INFO L791 eck$LassoCheckResult]: Stem: 264881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 264835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 264822#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264817#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264686#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 264687#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264463#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264464#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264815#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264816#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264767#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264433#L586 assume !(0 == ~M_E~0); 264434#L586-2 assume !(0 == ~T1_E~0); 264489#L591-1 assume !(0 == ~T2_E~0); 264630#L596-1 assume !(0 == ~T3_E~0); 264631#L601-1 assume !(0 == ~T4_E~0); 264675#L606-1 assume !(0 == ~T5_E~0); 264676#L611-1 assume !(0 == ~E_1~0); 264782#L616-1 assume !(0 == ~E_2~0); 264783#L621-1 assume !(0 == ~E_3~0); 264364#L626-1 assume !(0 == ~E_4~0); 264365#L631-1 assume !(0 == ~E_5~0); 264523#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264360#L279 assume !(1 == ~m_pc~0); 264361#L279-2 is_master_triggered_~__retres1~0#1 := 0; 264701#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264600#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 264601#L720 assume !(0 != activate_threads_~tmp~1#1); 264700#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264529#L298 assume !(1 == ~t1_pc~0); 264318#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264319#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264590#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 264373#L728 assume !(0 != activate_threads_~tmp___0~0#1); 264374#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264494#L317 assume !(1 == ~t2_pc~0); 264495#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264719#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264831#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264543#L736 assume !(0 != activate_threads_~tmp___1~0#1); 264544#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264763#L336 assume !(1 == ~t3_pc~0); 264764#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264866#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264656#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264657#L744 assume !(0 != activate_threads_~tmp___2~0#1); 264710#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264776#L355 assume !(1 == ~t4_pc~0); 264629#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264773#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264891#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264754#L752 assume !(0 != activate_threads_~tmp___3~0#1); 264755#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264805#L374 assume !(1 == ~t5_pc~0); 264806#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264818#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264819#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264847#L760 assume !(0 != activate_threads_~tmp___4~0#1); 264848#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264854#L649 assume !(1 == ~M_E~0); 264855#L649-2 assume !(1 == ~T1_E~0); 264348#L654-1 assume !(1 == ~T2_E~0); 264349#L659-1 assume !(1 == ~T3_E~0); 264537#L664-1 assume !(1 == ~T4_E~0); 264538#L669-1 assume !(1 == ~T5_E~0); 264757#L674-1 assume !(1 == ~E_1~0); 264758#L679-1 assume !(1 == ~E_2~0); 264437#L684-1 assume !(1 == ~E_3~0); 264438#L689-1 assume !(1 == ~E_4~0); 264623#L694-1 assume !(1 == ~E_5~0); 264618#L699-1 assume { :end_inline_reset_delta_events } true; 264619#L900-2 [2021-11-23 14:02:40,687 INFO L793 eck$LassoCheckResult]: Loop: 264619#L900-2 assume !false; 272811#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272783#L561 assume !false; 272784#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 272767#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 272763#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 272754#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 272755#L486 assume !(0 != eval_~tmp~0#1); 273667#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 274889#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 274888#L586-3 assume !(0 == ~M_E~0); 274886#L586-5 assume !(0 == ~T1_E~0); 274884#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 274882#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 274880#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 274877#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 274874#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 274872#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 274870#L621-3 assume !(0 == ~E_3~0); 274868#L626-3 assume !(0 == ~E_4~0); 274866#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 274864#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274863#L279-18 assume !(1 == ~m_pc~0); 274861#L279-20 is_master_triggered_~__retres1~0#1 := 0; 274859#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274857#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 274855#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 274853#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274852#L298-18 assume 1 == ~t1_pc~0; 274849#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 274847#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 274845#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 274843#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 274840#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274838#L317-18 assume !(1 == ~t2_pc~0); 274836#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 274834#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274831#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 274829#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 274827#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 274825#L336-18 assume !(1 == ~t3_pc~0); 274823#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 274821#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274819#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274817#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 274773#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274765#L355-18 assume !(1 == ~t4_pc~0); 274759#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 274752#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274746#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 274743#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 274739#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274737#L374-18 assume !(1 == ~t5_pc~0); 274736#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 274735#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274733#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 274731#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 274729#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274727#L649-3 assume !(1 == ~M_E~0); 273308#L649-5 assume !(1 == ~T1_E~0); 274724#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 274722#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 274720#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 274718#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 274716#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 274714#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 274696#L684-3 assume !(1 == ~E_3~0); 272976#L689-3 assume !(1 == ~E_4~0); 272974#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 272970#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 272971#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 272954#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 272955#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 272844#L919 assume !(0 == start_simulation_~tmp~3#1); 272845#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 272835#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 272831#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 272824#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 272825#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 272819#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272816#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 272817#L932 assume !(0 != start_simulation_~tmp___0~1#1); 264619#L900-2 [2021-11-23 14:02:40,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:40,688 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2021-11-23 14:02:40,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:40,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687583403] [2021-11-23 14:02:40,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:40,690 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:40,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:40,715 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:40,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:40,766 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:40,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:40,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1804756736, now seen corresponding path program 2 times [2021-11-23 14:02:40,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:40,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900464785] [2021-11-23 14:02:40,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:40,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:40,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:40,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:40,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:40,807 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900464785] [2021-11-23 14:02:40,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900464785] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:40,807 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:40,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:40,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407700276] [2021-11-23 14:02:40,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:40,808 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:40,808 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:40,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 14:02:40,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-23 14:02:40,809 INFO L87 Difference]: Start difference. First operand 19815 states and 27580 transitions. cyclomatic complexity: 7773 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:41,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:41,057 INFO L93 Difference]: Finished difference Result 34705 states and 47778 transitions. [2021-11-23 14:02:41,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-23 14:02:41,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34705 states and 47778 transitions. [2021-11-23 14:02:41,216 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 34372 [2021-11-23 14:02:41,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34705 states to 34705 states and 47778 transitions. [2021-11-23 14:02:41,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34705 [2021-11-23 14:02:41,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34705 [2021-11-23 14:02:41,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34705 states and 47778 transitions. [2021-11-23 14:02:41,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:41,440 INFO L681 BuchiCegarLoop]: Abstraction has 34705 states and 47778 transitions. [2021-11-23 14:02:41,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34705 states and 47778 transitions. [2021-11-23 14:02:42,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34705 to 20031. [2021-11-23 14:02:42,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20031 states, 20031 states have (on average 1.387649143827068) internal successors, (27796), 20030 states have internal predecessors, (27796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:42,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20031 states to 20031 states and 27796 transitions. [2021-11-23 14:02:42,124 INFO L704 BuchiCegarLoop]: Abstraction has 20031 states and 27796 transitions. [2021-11-23 14:02:42,125 INFO L587 BuchiCegarLoop]: Abstraction has 20031 states and 27796 transitions. [2021-11-23 14:02:42,125 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-23 14:02:42,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20031 states and 27796 transitions. [2021-11-23 14:02:42,186 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19818 [2021-11-23 14:02:42,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:42,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:42,188 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:42,188 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:42,188 INFO L791 eck$LassoCheckResult]: Stem: 319440#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 319383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 319371#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 319366#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 319235#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 319236#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 318998#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 318999#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 319364#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 319365#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 319320#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 318969#L586 assume !(0 == ~M_E~0); 318970#L586-2 assume !(0 == ~T1_E~0); 319025#L591-1 assume !(0 == ~T2_E~0); 319168#L596-1 assume !(0 == ~T3_E~0); 319169#L601-1 assume !(0 == ~T4_E~0); 319223#L606-1 assume !(0 == ~T5_E~0); 319224#L611-1 assume !(0 == ~E_1~0); 319330#L616-1 assume !(0 == ~E_2~0); 319331#L621-1 assume !(0 == ~E_3~0); 318900#L626-1 assume !(0 == ~E_4~0); 318901#L631-1 assume !(0 == ~E_5~0); 319061#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318896#L279 assume !(1 == ~m_pc~0); 318897#L279-2 is_master_triggered_~__retres1~0#1 := 0; 319251#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319141#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 319142#L720 assume !(0 != activate_threads_~tmp~1#1); 319250#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319067#L298 assume !(1 == ~t1_pc~0); 318854#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 318855#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319131#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 318909#L728 assume !(0 != activate_threads_~tmp___0~0#1); 318910#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319031#L317 assume !(1 == ~t2_pc~0); 319032#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 319269#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319377#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 319077#L736 assume !(0 != activate_threads_~tmp___1~0#1); 319078#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319315#L336 assume !(1 == ~t3_pc~0); 319316#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 319414#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 319201#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319202#L744 assume !(0 != activate_threads_~tmp___2~0#1); 319259#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319325#L355 assume !(1 == ~t4_pc~0); 319165#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 319322#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319241#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319242#L752 assume !(0 != activate_threads_~tmp___3~0#1); 318921#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 318922#L374 assume !(1 == ~t5_pc~0); 319051#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 319052#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319139#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319140#L760 assume !(0 != activate_threads_~tmp___4~0#1); 319206#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319207#L649 assume !(1 == ~M_E~0); 319449#L649-2 assume !(1 == ~T1_E~0); 318884#L654-1 assume !(1 == ~T2_E~0); 318885#L659-1 assume !(1 == ~T3_E~0); 319448#L664-1 assume !(1 == ~T4_E~0); 318877#L669-1 assume !(1 == ~T5_E~0); 318878#L674-1 assume !(1 == ~E_1~0); 319311#L679-1 assume !(1 == ~E_2~0); 318973#L684-1 assume !(1 == ~E_3~0); 318974#L689-1 assume !(1 == ~E_4~0); 319160#L694-1 assume !(1 == ~E_5~0); 319157#L699-1 assume { :end_inline_reset_delta_events } true; 319158#L900-2 [2021-11-23 14:02:42,189 INFO L793 eck$LassoCheckResult]: Loop: 319158#L900-2 assume !false; 319428#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 318833#L561 assume !false; 338721#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 338719#L439 assume !(0 == ~m_st~0); 338720#L443 assume !(0 == ~t1_st~0); 338716#L447 assume !(0 == ~t2_st~0); 338717#L451 assume !(0 == ~t3_st~0); 338718#L455 assume !(0 == ~t4_st~0); 338714#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 338715#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 319378#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 319379#L486 assume !(0 != eval_~tmp~0#1); 338711#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338710#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 338709#L586-3 assume !(0 == ~M_E~0); 338708#L586-5 assume !(0 == ~T1_E~0); 338707#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 338706#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 338704#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 338703#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 338701#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 338699#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 338697#L621-3 assume !(0 == ~E_3~0); 338695#L626-3 assume !(0 == ~E_4~0); 338623#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 338624#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 338619#L279-18 assume !(1 == ~m_pc~0); 338620#L279-20 is_master_triggered_~__retres1~0#1 := 0; 319189#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319079#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 319080#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 319333#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319203#L298-18 assume 1 == ~t1_pc~0; 319204#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 338605#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 338606#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 338601#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 338602#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 338597#L317-18 assume !(1 == ~t2_pc~0); 338598#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 338593#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 338594#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338589#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 338590#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 338585#L336-18 assume !(1 == ~t3_pc~0); 338586#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 319374#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 319375#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 338577#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 338578#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 338572#L355-18 assume !(1 == ~t4_pc~0); 338573#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 319390#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319391#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319176#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 319177#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319323#L374-18 assume !(1 == ~t5_pc~0); 319324#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 319115#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319116#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319412#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 319413#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319421#L649-3 assume !(1 == ~M_E~0); 319422#L649-5 assume !(1 == ~T1_E~0); 338646#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 338642#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 338643#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 338638#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 338639#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 338634#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 338635#L684-3 assume !(1 == ~E_3~0); 338569#L689-3 assume !(1 == ~E_4~0); 318806#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 318844#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 318845#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 338801#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 338798#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 338795#L919 assume !(0 == start_simulation_~tmp~3#1); 338793#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 319290#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 318838#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 319090#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 319091#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 319145#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319086#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 319087#L932 assume !(0 != start_simulation_~tmp___0~1#1); 319158#L900-2 [2021-11-23 14:02:42,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:42,190 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2021-11-23 14:02:42,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:42,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200712206] [2021-11-23 14:02:42,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:42,190 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:42,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:42,200 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:42,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:42,241 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:42,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:42,242 INFO L85 PathProgramCache]: Analyzing trace with hash -1085186113, now seen corresponding path program 1 times [2021-11-23 14:02:42,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:42,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582751506] [2021-11-23 14:02:42,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:42,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:42,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:42,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:42,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:42,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582751506] [2021-11-23 14:02:42,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582751506] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:42,322 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:42,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 14:02:42,322 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495682830] [2021-11-23 14:02:42,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:42,323 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:42,323 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:42,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 14:02:42,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-23 14:02:42,324 INFO L87 Difference]: Start difference. First operand 20031 states and 27796 transitions. cyclomatic complexity: 7773 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:42,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:42,591 INFO L93 Difference]: Finished difference Result 32075 states and 44605 transitions. [2021-11-23 14:02:42,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-23 14:02:42,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32075 states and 44605 transitions. [2021-11-23 14:02:42,733 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 31862 [2021-11-23 14:02:42,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32075 states to 32075 states and 44605 transitions. [2021-11-23 14:02:42,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32075 [2021-11-23 14:02:42,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32075 [2021-11-23 14:02:42,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32075 states and 44605 transitions. [2021-11-23 14:02:42,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:42,871 INFO L681 BuchiCegarLoop]: Abstraction has 32075 states and 44605 transitions. [2021-11-23 14:02:42,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32075 states and 44605 transitions. [2021-11-23 14:02:43,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32075 to 20283. [2021-11-23 14:02:43,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20283 states, 20283 states have (on average 1.3720356949169255) internal successors, (27829), 20282 states have internal predecessors, (27829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:43,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20283 states to 20283 states and 27829 transitions. [2021-11-23 14:02:43,601 INFO L704 BuchiCegarLoop]: Abstraction has 20283 states and 27829 transitions. [2021-11-23 14:02:43,601 INFO L587 BuchiCegarLoop]: Abstraction has 20283 states and 27829 transitions. [2021-11-23 14:02:43,602 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-23 14:02:43,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20283 states and 27829 transitions. [2021-11-23 14:02:43,674 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20070 [2021-11-23 14:02:43,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:43,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:43,678 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:43,678 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:43,679 INFO L791 eck$LassoCheckResult]: Stem: 371582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 371520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 371507#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 371501#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 371358#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 371359#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 371121#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 371122#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371499#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371500#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371445#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 371090#L586 assume !(0 == ~M_E~0); 371091#L586-2 assume !(0 == ~T1_E~0); 371148#L591-1 assume !(0 == ~T2_E~0); 371292#L596-1 assume !(0 == ~T3_E~0); 371293#L601-1 assume !(0 == ~T4_E~0); 371346#L606-1 assume !(0 == ~T5_E~0); 371347#L611-1 assume !(0 == ~E_1~0); 371457#L616-1 assume !(0 == ~E_2~0); 371458#L621-1 assume !(0 == ~E_3~0); 371020#L626-1 assume !(0 == ~E_4~0); 371021#L631-1 assume !(0 == ~E_5~0); 371183#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371016#L279 assume !(1 == ~m_pc~0); 371017#L279-2 is_master_triggered_~__retres1~0#1 := 0; 371374#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 371264#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 371265#L720 assume !(0 != activate_threads_~tmp~1#1); 371373#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371189#L298 assume !(1 == ~t1_pc~0); 370973#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 370974#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371255#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 371030#L728 assume !(0 != activate_threads_~tmp___0~0#1); 371031#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371153#L317 assume !(1 == ~t2_pc~0); 371154#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 371394#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371515#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 371200#L736 assume !(0 != activate_threads_~tmp___1~0#1); 371201#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371441#L336 assume !(1 == ~t3_pc~0); 371442#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 371552#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371322#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 371323#L744 assume !(0 != activate_threads_~tmp___2~0#1); 371382#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371450#L355 assume !(1 == ~t4_pc~0); 371289#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371449#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371363#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371364#L752 assume !(0 != activate_threads_~tmp___3~0#1); 371041#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371042#L374 assume !(1 == ~t5_pc~0); 371173#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 371174#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371262#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371263#L760 assume !(0 != activate_threads_~tmp___4~0#1); 371327#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371328#L649 assume !(1 == ~M_E~0); 371597#L649-2 assume !(1 == ~T1_E~0); 371005#L654-1 assume !(1 == ~T2_E~0); 371006#L659-1 assume !(1 == ~T3_E~0); 371596#L664-1 assume !(1 == ~T4_E~0); 370998#L669-1 assume !(1 == ~T5_E~0); 370999#L674-1 assume !(1 == ~E_1~0); 371437#L679-1 assume !(1 == ~E_2~0); 371094#L684-1 assume !(1 == ~E_3~0); 371095#L689-1 assume !(1 == ~E_4~0); 371285#L694-1 assume !(1 == ~E_5~0); 371282#L699-1 assume { :end_inline_reset_delta_events } true; 371283#L900-2 [2021-11-23 14:02:43,679 INFO L793 eck$LassoCheckResult]: Loop: 371283#L900-2 assume !false; 376111#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376106#L561 assume !false; 376107#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 376101#L439 assume !(0 == ~m_st~0); 376098#L443 assume !(0 == ~t1_st~0); 376096#L447 assume !(0 == ~t2_st~0); 376090#L451 assume !(0 == ~t3_st~0); 376089#L455 assume !(0 == ~t4_st~0); 376079#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 376075#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 376076#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 376069#L486 assume !(0 != eval_~tmp~0#1); 376064#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 376065#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 376054#L586-3 assume !(0 == ~M_E~0); 376055#L586-5 assume !(0 == ~T1_E~0); 376046#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 376047#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 376036#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 376037#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 376026#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 376027#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 376016#L621-3 assume !(0 == ~E_3~0); 376017#L626-3 assume !(0 == ~E_4~0); 376005#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 376006#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 375995#L279-18 assume !(1 == ~m_pc~0); 375996#L279-20 is_master_triggered_~__retres1~0#1 := 0; 375985#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 375986#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 375975#L720-18 assume !(0 != activate_threads_~tmp~1#1); 375976#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 375963#L298-18 assume !(1 == ~t1_pc~0); 375965#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 375951#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 375952#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 375941#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 375942#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 375931#L317-18 assume !(1 == ~t2_pc~0); 375932#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 375921#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 375922#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 375910#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 375911#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 375899#L336-18 assume !(1 == ~t3_pc~0); 375900#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 375890#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375891#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 375879#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 375880#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 375866#L355-18 assume 1 == ~t4_pc~0; 375868#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375854#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 375855#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 375837#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 375838#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375821#L374-18 assume !(1 == ~t5_pc~0); 375822#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 375808#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 375809#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 375793#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 375794#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 375781#L649-3 assume !(1 == ~M_E~0); 375782#L649-5 assume !(1 == ~T1_E~0); 375773#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 375774#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 375763#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 375764#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 375753#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 375754#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 375743#L684-3 assume !(1 == ~E_3~0); 375744#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 375730#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 375731#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 375542#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 375537#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 375530#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 375531#L919 assume !(0 == start_simulation_~tmp~3#1); 376131#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 376132#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 376122#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 376123#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 376118#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 376119#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 376114#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 376115#L932 assume !(0 != start_simulation_~tmp___0~1#1); 371283#L900-2 [2021-11-23 14:02:43,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:43,680 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2021-11-23 14:02:43,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:43,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162303308] [2021-11-23 14:02:43,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:43,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:43,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:43,691 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:43,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:43,731 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:43,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:43,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1828210557, now seen corresponding path program 1 times [2021-11-23 14:02:43,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:43,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564046443] [2021-11-23 14:02:43,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:43,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:43,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:43,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:43,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:43,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564046443] [2021-11-23 14:02:43,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564046443] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:43,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:43,768 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:43,768 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120666668] [2021-11-23 14:02:43,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:43,769 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 14:02:43,769 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:43,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:43,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:43,770 INFO L87 Difference]: Start difference. First operand 20283 states and 27829 transitions. cyclomatic complexity: 7554 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:43,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:43,907 INFO L93 Difference]: Finished difference Result 30540 states and 41404 transitions. [2021-11-23 14:02:43,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:43,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30540 states and 41404 transitions. [2021-11-23 14:02:44,042 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 30385 [2021-11-23 14:02:44,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30540 states to 30540 states and 41404 transitions. [2021-11-23 14:02:44,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30540 [2021-11-23 14:02:44,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30540 [2021-11-23 14:02:44,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30540 states and 41404 transitions. [2021-11-23 14:02:44,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:44,155 INFO L681 BuchiCegarLoop]: Abstraction has 30540 states and 41404 transitions. [2021-11-23 14:02:44,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30540 states and 41404 transitions. [2021-11-23 14:02:44,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30540 to 29916. [2021-11-23 14:02:44,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29916 states, 29916 states have (on average 1.3575344297365959) internal successors, (40612), 29915 states have internal predecessors, (40612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:44,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29916 states to 29916 states and 40612 transitions. [2021-11-23 14:02:44,858 INFO L704 BuchiCegarLoop]: Abstraction has 29916 states and 40612 transitions. [2021-11-23 14:02:44,859 INFO L587 BuchiCegarLoop]: Abstraction has 29916 states and 40612 transitions. [2021-11-23 14:02:44,859 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-23 14:02:44,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29916 states and 40612 transitions. [2021-11-23 14:02:44,940 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 29761 [2021-11-23 14:02:44,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:44,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:44,941 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:44,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:44,942 INFO L791 eck$LassoCheckResult]: Stem: 422369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 422316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 422304#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422297#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422167#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 422168#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421951#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421952#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 422295#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422296#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422250#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421924#L586 assume !(0 == ~M_E~0); 421925#L586-2 assume !(0 == ~T1_E~0); 421977#L591-1 assume !(0 == ~T2_E~0); 422108#L596-1 assume !(0 == ~T3_E~0); 422109#L601-1 assume !(0 == ~T4_E~0); 422156#L606-1 assume !(0 == ~T5_E~0); 422157#L611-1 assume !(0 == ~E_1~0); 422259#L616-1 assume !(0 == ~E_2~0); 422260#L621-1 assume !(0 == ~E_3~0); 421850#L626-1 assume !(0 == ~E_4~0); 421851#L631-1 assume !(0 == ~E_5~0); 422010#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421848#L279 assume !(1 == ~m_pc~0); 421849#L279-2 is_master_triggered_~__retres1~0#1 := 0; 422180#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 422081#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 422082#L720 assume !(0 != activate_threads_~tmp~1#1); 422179#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422014#L298 assume !(1 == ~t1_pc~0); 421804#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421805#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422070#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 421859#L728 assume !(0 != activate_threads_~tmp___0~0#1); 421860#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421983#L317 assume !(1 == ~t2_pc~0); 421984#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422198#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 422313#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 422030#L736 assume !(0 != activate_threads_~tmp___1~0#1); 422031#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422246#L336 assume !(1 == ~t3_pc~0); 422247#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422346#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 422136#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 422137#L744 assume !(0 != activate_threads_~tmp___2~0#1); 422189#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422255#L355 assume !(1 == ~t4_pc~0); 422107#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 421939#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421940#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 422237#L752 assume !(0 != activate_threads_~tmp___3~0#1); 422238#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422285#L374 assume !(1 == ~t5_pc~0); 422286#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422298#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422299#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422327#L760 assume !(0 != activate_threads_~tmp___4~0#1); 422328#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422332#L649 assume !(1 == ~M_E~0); 422333#L649-2 assume !(1 == ~T1_E~0); 422372#L654-1 assume !(1 == ~T2_E~0); 422177#L659-1 assume !(1 == ~T3_E~0); 422022#L664-1 assume !(1 == ~T4_E~0); 422023#L669-1 assume !(1 == ~T5_E~0); 422378#L674-1 assume !(1 == ~E_1~0); 422377#L679-1 assume !(1 == ~E_2~0); 422376#L684-1 assume !(1 == ~E_3~0); 422375#L689-1 assume !(1 == ~E_4~0); 422101#L694-1 assume !(1 == ~E_5~0); 422099#L699-1 assume { :end_inline_reset_delta_events } true; 422100#L900-2 assume !false; 441261#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 441259#L561 [2021-11-23 14:02:44,942 INFO L793 eck$LassoCheckResult]: Loop: 441259#L561 assume !false; 441257#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 441254#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 441252#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 441250#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 441248#L486 assume 0 != eval_~tmp~0#1; 441245#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 441241#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 441197#L491 assume !(0 == ~t1_st~0); 441193#L505 assume !(0 == ~t2_st~0); 438316#L519 assume !(0 == ~t3_st~0); 441266#L533 assume !(0 == ~t4_st~0); 441264#L547 assume !(0 == ~t5_st~0); 441259#L561 [2021-11-23 14:02:44,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:44,943 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2021-11-23 14:02:44,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:44,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495599199] [2021-11-23 14:02:44,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:44,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:44,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:44,953 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:44,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:44,979 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:44,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:44,980 INFO L85 PathProgramCache]: Analyzing trace with hash -519083082, now seen corresponding path program 1 times [2021-11-23 14:02:44,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:44,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892780371] [2021-11-23 14:02:44,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:44,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:44,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:44,984 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:44,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:44,989 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:44,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:44,989 INFO L85 PathProgramCache]: Analyzing trace with hash -517720007, now seen corresponding path program 1 times [2021-11-23 14:02:44,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:44,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176249051] [2021-11-23 14:02:44,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:44,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:44,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:45,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:45,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:45,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176249051] [2021-11-23 14:02:45,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176249051] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:45,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:45,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:45,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731926357] [2021-11-23 14:02:45,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:45,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:45,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:45,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:45,166 INFO L87 Difference]: Start difference. First operand 29916 states and 40612 transitions. cyclomatic complexity: 10714 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:45,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:45,461 INFO L93 Difference]: Finished difference Result 54702 states and 73437 transitions. [2021-11-23 14:02:45,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:45,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54702 states and 73437 transitions. [2021-11-23 14:02:46,074 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 54398 [2021-11-23 14:02:46,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54702 states to 54702 states and 73437 transitions. [2021-11-23 14:02:46,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54702 [2021-11-23 14:02:46,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54702 [2021-11-23 14:02:46,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54702 states and 73437 transitions. [2021-11-23 14:02:46,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:46,300 INFO L681 BuchiCegarLoop]: Abstraction has 54702 states and 73437 transitions. [2021-11-23 14:02:46,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54702 states and 73437 transitions. [2021-11-23 14:02:46,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54702 to 50770. [2021-11-23 14:02:46,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50770 states, 50770 states have (on average 1.3517628520779987) internal successors, (68629), 50769 states have internal predecessors, (68629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:47,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50770 states to 50770 states and 68629 transitions. [2021-11-23 14:02:47,093 INFO L704 BuchiCegarLoop]: Abstraction has 50770 states and 68629 transitions. [2021-11-23 14:02:47,093 INFO L587 BuchiCegarLoop]: Abstraction has 50770 states and 68629 transitions. [2021-11-23 14:02:47,093 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-23 14:02:47,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50770 states and 68629 transitions. [2021-11-23 14:02:47,268 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2021-11-23 14:02:47,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:47,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:47,269 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:47,269 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:47,270 INFO L791 eck$LassoCheckResult]: Stem: 506994#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 506942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 506930#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 506925#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 506792#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 506793#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 506890#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 530195#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 530194#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 530193#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 530192#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 530191#L586 assume !(0 == ~M_E~0); 530190#L586-2 assume !(0 == ~T1_E~0); 530189#L591-1 assume !(0 == ~T2_E~0); 530188#L596-1 assume !(0 == ~T3_E~0); 530187#L601-1 assume !(0 == ~T4_E~0); 530186#L606-1 assume !(0 == ~T5_E~0); 530185#L611-1 assume !(0 == ~E_1~0); 530184#L616-1 assume !(0 == ~E_2~0); 530183#L621-1 assume !(0 == ~E_3~0); 530182#L626-1 assume !(0 == ~E_4~0); 530181#L631-1 assume !(0 == ~E_5~0); 530180#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530179#L279 assume !(1 == ~m_pc~0); 530178#L279-2 is_master_triggered_~__retres1~0#1 := 0; 530177#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 530176#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 530175#L720 assume !(0 != activate_threads_~tmp~1#1); 530174#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 530173#L298 assume !(1 == ~t1_pc~0); 530171#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 530170#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 530169#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 530168#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 506484#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506607#L317 assume !(1 == ~t2_pc~0); 506608#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 506827#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 506936#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 506648#L736 assume !(0 != activate_threads_~tmp___1~0#1); 506649#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 506872#L336 assume !(1 == ~t3_pc~0); 506873#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 506973#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506760#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 506761#L744 assume !(0 != activate_threads_~tmp___2~0#1); 506815#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 506881#L355 assume !(1 == ~t4_pc~0); 506728#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 506879#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506797#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 506798#L752 assume !(0 != activate_threads_~tmp___3~0#1); 506494#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 506495#L374 assume !(1 == ~t5_pc~0); 506624#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 506625#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506704#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 506705#L760 assume !(0 != activate_threads_~tmp___4~0#1); 506763#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506764#L649 assume !(1 == ~M_E~0); 507007#L649-2 assume !(1 == ~T1_E~0); 506458#L654-1 assume !(1 == ~T2_E~0); 506459#L659-1 assume !(1 == ~T3_E~0); 507006#L664-1 assume !(1 == ~T4_E~0); 506451#L669-1 assume !(1 == ~T5_E~0); 506452#L674-1 assume !(1 == ~E_1~0); 506866#L679-1 assume !(1 == ~E_2~0); 506549#L684-1 assume !(1 == ~E_3~0); 506550#L689-1 assume !(1 == ~E_4~0); 506725#L694-1 assume !(1 == ~E_5~0); 506722#L699-1 assume { :end_inline_reset_delta_events } true; 506723#L900-2 assume !false; 530093#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530091#L561 [2021-11-23 14:02:47,270 INFO L793 eck$LassoCheckResult]: Loop: 530091#L561 assume !false; 530089#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 530086#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 530085#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 530084#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 530083#L486 assume 0 != eval_~tmp~0#1; 530081#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 530080#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 530079#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 528742#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 530077#L505 assume !(0 == ~t2_st~0); 530217#L519 assume !(0 == ~t3_st~0); 530098#L533 assume !(0 == ~t4_st~0); 530096#L547 assume !(0 == ~t5_st~0); 530091#L561 [2021-11-23 14:02:47,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:47,271 INFO L85 PathProgramCache]: Analyzing trace with hash -632671842, now seen corresponding path program 1 times [2021-11-23 14:02:47,271 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:47,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892767869] [2021-11-23 14:02:47,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:47,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:47,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:47,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:47,607 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:47,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892767869] [2021-11-23 14:02:47,607 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892767869] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:47,607 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:47,608 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:47,608 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538004746] [2021-11-23 14:02:47,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:47,608 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 14:02:47,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:47,609 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 1 times [2021-11-23 14:02:47,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:47,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248433760] [2021-11-23 14:02:47,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:47,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:47,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:47,612 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:47,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:47,616 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:47,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:47,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:47,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:47,742 INFO L87 Difference]: Start difference. First operand 50770 states and 68629 transitions. cyclomatic complexity: 17877 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:47,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:47,929 INFO L93 Difference]: Finished difference Result 50681 states and 68508 transitions. [2021-11-23 14:02:47,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:47,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50681 states and 68508 transitions. [2021-11-23 14:02:48,147 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2021-11-23 14:02:48,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50681 states to 50681 states and 68508 transitions. [2021-11-23 14:02:48,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50681 [2021-11-23 14:02:48,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50681 [2021-11-23 14:02:48,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50681 states and 68508 transitions. [2021-11-23 14:02:48,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:48,313 INFO L681 BuchiCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2021-11-23 14:02:48,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50681 states and 68508 transitions. [2021-11-23 14:02:48,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50681 to 50681. [2021-11-23 14:02:48,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50681 states, 50681 states have (on average 1.3517491762198852) internal successors, (68508), 50680 states have internal predecessors, (68508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:49,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50681 states to 50681 states and 68508 transitions. [2021-11-23 14:02:49,382 INFO L704 BuchiCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2021-11-23 14:02:49,383 INFO L587 BuchiCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2021-11-23 14:02:49,383 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-23 14:02:49,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50681 states and 68508 transitions. [2021-11-23 14:02:49,509 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2021-11-23 14:02:49,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:49,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:49,510 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:49,510 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:49,510 INFO L791 eck$LassoCheckResult]: Stem: 608443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 608400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 608389#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 608384#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 608252#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 608253#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 608031#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 608032#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 608382#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 608383#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 608337#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 608003#L586 assume !(0 == ~M_E~0); 608004#L586-2 assume !(0 == ~T1_E~0); 608056#L591-1 assume !(0 == ~T2_E~0); 608193#L596-1 assume !(0 == ~T3_E~0); 608194#L601-1 assume !(0 == ~T4_E~0); 608242#L606-1 assume !(0 == ~T5_E~0); 608243#L611-1 assume !(0 == ~E_1~0); 608347#L616-1 assume !(0 == ~E_2~0); 608348#L621-1 assume !(0 == ~E_3~0); 607930#L626-1 assume !(0 == ~E_4~0); 607931#L631-1 assume !(0 == ~E_5~0); 608092#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607926#L279 assume !(1 == ~m_pc~0); 607927#L279-2 is_master_triggered_~__retres1~0#1 := 0; 608266#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 608165#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 608166#L720 assume !(0 != activate_threads_~tmp~1#1); 608265#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608096#L298 assume !(1 == ~t1_pc~0); 607884#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 607885#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608154#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 607940#L728 assume !(0 != activate_threads_~tmp___0~0#1); 607941#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608062#L317 assume !(1 == ~t2_pc~0); 608063#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 608285#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608395#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 608107#L736 assume !(0 != activate_threads_~tmp___1~0#1); 608108#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 608333#L336 assume !(1 == ~t3_pc~0); 608334#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 608429#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608221#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 608222#L744 assume !(0 != activate_threads_~tmp___2~0#1); 608274#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 608342#L355 assume !(1 == ~t4_pc~0); 608190#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 608340#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608258#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 608259#L752 assume !(0 != activate_threads_~tmp___3~0#1); 607952#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607953#L374 assume !(1 == ~t5_pc~0); 608081#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 608082#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 608163#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 608164#L760 assume !(0 != activate_threads_~tmp___4~0#1); 608224#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608225#L649 assume !(1 == ~M_E~0); 608458#L649-2 assume !(1 == ~T1_E~0); 607915#L654-1 assume !(1 == ~T2_E~0); 607916#L659-1 assume !(1 == ~T3_E~0); 608457#L664-1 assume !(1 == ~T4_E~0); 607908#L669-1 assume !(1 == ~T5_E~0); 607909#L674-1 assume !(1 == ~E_1~0); 608327#L679-1 assume !(1 == ~E_2~0); 608007#L684-1 assume !(1 == ~E_3~0); 608008#L689-1 assume !(1 == ~E_4~0); 608187#L694-1 assume !(1 == ~E_5~0); 608184#L699-1 assume { :end_inline_reset_delta_events } true; 608185#L900-2 assume !false; 638277#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 638133#L561 [2021-11-23 14:02:49,511 INFO L793 eck$LassoCheckResult]: Loop: 638133#L561 assume !false; 638274#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 638271#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 638269#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 638267#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 638266#L486 assume 0 != eval_~tmp~0#1; 638261#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 638258#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 638256#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 638252#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 638248#L505 assume !(0 == ~t2_st~0); 638243#L519 assume !(0 == ~t3_st~0); 638137#L533 assume !(0 == ~t4_st~0); 638135#L547 assume !(0 == ~t5_st~0); 638133#L561 [2021-11-23 14:02:49,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:49,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2021-11-23 14:02:49,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:49,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488555167] [2021-11-23 14:02:49,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:49,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:49,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:49,520 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:49,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:49,541 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:49,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:49,542 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 2 times [2021-11-23 14:02:49,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:49,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13274296] [2021-11-23 14:02:49,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:49,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:49,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:49,546 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:49,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:49,550 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:49,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:49,550 INFO L85 PathProgramCache]: Analyzing trace with hash 182662538, now seen corresponding path program 1 times [2021-11-23 14:02:49,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:49,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025558707] [2021-11-23 14:02:49,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:49,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:49,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:49,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:49,578 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:49,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025558707] [2021-11-23 14:02:49,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025558707] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:49,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:49,579 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:49,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744230515] [2021-11-23 14:02:49,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:49,672 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:49,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:49,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:49,673 INFO L87 Difference]: Start difference. First operand 50681 states and 68508 transitions. cyclomatic complexity: 17845 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:49,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:49,882 INFO L93 Difference]: Finished difference Result 77791 states and 104450 transitions. [2021-11-23 14:02:49,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:49,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77791 states and 104450 transitions. [2021-11-23 14:02:50,144 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 77496 [2021-11-23 14:02:50,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77791 states to 77791 states and 104450 transitions. [2021-11-23 14:02:50,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77791 [2021-11-23 14:02:50,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77791 [2021-11-23 14:02:50,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77791 states and 104450 transitions. [2021-11-23 14:02:50,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:50,374 INFO L681 BuchiCegarLoop]: Abstraction has 77791 states and 104450 transitions. [2021-11-23 14:02:50,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77791 states and 104450 transitions. [2021-11-23 14:02:51,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77791 to 75559. [2021-11-23 14:02:51,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75559 states, 75559 states have (on average 1.346153337127278) internal successors, (101714), 75558 states have internal predecessors, (101714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:51,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75559 states to 75559 states and 101714 transitions. [2021-11-23 14:02:51,716 INFO L704 BuchiCegarLoop]: Abstraction has 75559 states and 101714 transitions. [2021-11-23 14:02:51,717 INFO L587 BuchiCegarLoop]: Abstraction has 75559 states and 101714 transitions. [2021-11-23 14:02:51,717 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-23 14:02:51,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75559 states and 101714 transitions. [2021-11-23 14:02:52,402 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 75264 [2021-11-23 14:02:52,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:52,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:52,403 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:52,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:52,404 INFO L791 eck$LassoCheckResult]: Stem: 736941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 736877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 736863#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 736858#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 736731#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 736732#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 736515#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 736516#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 736856#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 736857#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 736809#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 736484#L586 assume !(0 == ~M_E~0); 736485#L586-2 assume !(0 == ~T1_E~0); 736542#L591-1 assume !(0 == ~T2_E~0); 736674#L596-1 assume !(0 == ~T3_E~0); 736675#L601-1 assume !(0 == ~T4_E~0); 736720#L606-1 assume !(0 == ~T5_E~0); 736721#L611-1 assume !(0 == ~E_1~0); 736819#L616-1 assume !(0 == ~E_2~0); 736820#L621-1 assume !(0 == ~E_3~0); 736412#L626-1 assume !(0 == ~E_4~0); 736413#L631-1 assume !(0 == ~E_5~0); 736575#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 736408#L279 assume !(1 == ~m_pc~0); 736409#L279-2 is_master_triggered_~__retres1~0#1 := 0; 736746#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 736649#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 736650#L720 assume !(0 != activate_threads_~tmp~1#1); 736745#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 736579#L298 assume !(1 == ~t1_pc~0); 736365#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 736366#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 736638#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 736422#L728 assume !(0 != activate_threads_~tmp___0~0#1); 736423#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 736548#L317 assume !(1 == ~t2_pc~0); 736549#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 736765#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 736872#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 736589#L736 assume !(0 != activate_threads_~tmp___1~0#1); 736590#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 736805#L336 assume !(1 == ~t3_pc~0); 736806#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 736912#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 736702#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 736703#L744 assume !(0 != activate_threads_~tmp___2~0#1); 736754#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 736814#L355 assume !(1 == ~t4_pc~0); 736671#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 736812#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 736736#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 736737#L752 assume !(0 != activate_threads_~tmp___3~0#1); 736432#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 736433#L374 assume !(1 == ~t5_pc~0); 736566#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 736567#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 736647#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 736648#L760 assume !(0 != activate_threads_~tmp___4~0#1); 736705#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 736706#L649 assume !(1 == ~M_E~0); 736951#L649-2 assume !(1 == ~T1_E~0); 736397#L654-1 assume !(1 == ~T2_E~0); 736398#L659-1 assume !(1 == ~T3_E~0); 736950#L664-1 assume !(1 == ~T4_E~0); 736390#L669-1 assume !(1 == ~T5_E~0); 736391#L674-1 assume !(1 == ~E_1~0); 736801#L679-1 assume !(1 == ~E_2~0); 736488#L684-1 assume !(1 == ~E_3~0); 736489#L689-1 assume !(1 == ~E_4~0); 736668#L694-1 assume !(1 == ~E_5~0); 736665#L699-1 assume { :end_inline_reset_delta_events } true; 736666#L900-2 assume !false; 750849#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 750847#L561 [2021-11-23 14:02:52,404 INFO L793 eck$LassoCheckResult]: Loop: 750847#L561 assume !false; 750845#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 750834#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 750827#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 750819#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 750814#L486 assume 0 != eval_~tmp~0#1; 750807#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 750779#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 748839#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 748836#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 748834#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 743084#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 743085#L519 assume !(0 == ~t3_st~0); 750853#L533 assume !(0 == ~t4_st~0); 750852#L547 assume !(0 == ~t5_st~0); 750847#L561 [2021-11-23 14:02:52,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:52,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2021-11-23 14:02:52,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:52,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55550394] [2021-11-23 14:02:52,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:52,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:52,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:52,414 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:52,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:52,438 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:52,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:52,439 INFO L85 PathProgramCache]: Analyzing trace with hash -111462417, now seen corresponding path program 1 times [2021-11-23 14:02:52,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:52,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66439691] [2021-11-23 14:02:52,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:52,440 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:52,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:52,443 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:52,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:52,448 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:52,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:52,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1198452658, now seen corresponding path program 1 times [2021-11-23 14:02:52,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:52,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608820147] [2021-11-23 14:02:52,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:52,450 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:52,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:52,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:52,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:52,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608820147] [2021-11-23 14:02:52,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608820147] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:52,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:52,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:52,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949582175] [2021-11-23 14:02:52,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:52,679 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:52,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:52,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:52,680 INFO L87 Difference]: Start difference. First operand 75559 states and 101714 transitions. cyclomatic complexity: 26175 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:53,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:53,194 INFO L93 Difference]: Finished difference Result 120051 states and 161118 transitions. [2021-11-23 14:02:53,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:53,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120051 states and 161118 transitions. [2021-11-23 14:02:53,754 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 119676 [2021-11-23 14:02:54,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120051 states to 120051 states and 161118 transitions. [2021-11-23 14:02:54,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120051 [2021-11-23 14:02:54,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120051 [2021-11-23 14:02:54,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120051 states and 161118 transitions. [2021-11-23 14:02:54,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:54,160 INFO L681 BuchiCegarLoop]: Abstraction has 120051 states and 161118 transitions. [2021-11-23 14:02:54,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120051 states and 161118 transitions. [2021-11-23 14:02:55,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120051 to 118575. [2021-11-23 14:02:55,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118575 states, 118575 states have (on average 1.3439089184060722) internal successors, (159354), 118574 states have internal predecessors, (159354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:56,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118575 states to 118575 states and 159354 transitions. [2021-11-23 14:02:56,053 INFO L704 BuchiCegarLoop]: Abstraction has 118575 states and 159354 transitions. [2021-11-23 14:02:56,053 INFO L587 BuchiCegarLoop]: Abstraction has 118575 states and 159354 transitions. [2021-11-23 14:02:56,053 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-23 14:02:56,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118575 states and 159354 transitions. [2021-11-23 14:02:57,134 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 118200 [2021-11-23 14:02:57,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:02:57,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:02:57,135 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:57,135 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:02:57,136 INFO L791 eck$LassoCheckResult]: Stem: 932573#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 932517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 932499#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 932492#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 932361#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 932362#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932130#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 932131#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 932490#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 932491#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 932442#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 932101#L586 assume !(0 == ~M_E~0); 932102#L586-2 assume !(0 == ~T1_E~0); 932158#L591-1 assume !(0 == ~T2_E~0); 932300#L596-1 assume !(0 == ~T3_E~0); 932301#L601-1 assume !(0 == ~T4_E~0); 932348#L606-1 assume !(0 == ~T5_E~0); 932349#L611-1 assume !(0 == ~E_1~0); 932455#L616-1 assume !(0 == ~E_2~0); 932456#L621-1 assume !(0 == ~E_3~0); 932028#L626-1 assume !(0 == ~E_4~0); 932029#L631-1 assume !(0 == ~E_5~0); 932191#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 932024#L279 assume !(1 == ~m_pc~0); 932025#L279-2 is_master_triggered_~__retres1~0#1 := 0; 932376#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 932274#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 932275#L720 assume !(0 != activate_threads_~tmp~1#1); 932375#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932197#L298 assume !(1 == ~t1_pc~0); 931982#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 931983#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 932263#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 932038#L728 assume !(0 != activate_threads_~tmp___0~0#1); 932039#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 932163#L317 assume !(1 == ~t2_pc~0); 932164#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 932396#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 932511#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 932208#L736 assume !(0 != activate_threads_~tmp___1~0#1); 932209#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 932438#L336 assume !(1 == ~t3_pc~0); 932439#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 932551#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 932330#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 932331#L744 assume !(0 != activate_threads_~tmp___2~0#1); 932384#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 932449#L355 assume !(1 == ~t4_pc~0); 932297#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 932447#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 932366#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 932367#L752 assume !(0 != activate_threads_~tmp___3~0#1); 932050#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 932051#L374 assume !(1 == ~t5_pc~0); 932180#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 932181#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932272#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 932273#L760 assume !(0 != activate_threads_~tmp___4~0#1); 932333#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932334#L649 assume !(1 == ~M_E~0); 932588#L649-2 assume !(1 == ~T1_E~0); 932013#L654-1 assume !(1 == ~T2_E~0); 932014#L659-1 assume !(1 == ~T3_E~0); 932587#L664-1 assume !(1 == ~T4_E~0); 932006#L669-1 assume !(1 == ~T5_E~0); 932007#L674-1 assume !(1 == ~E_1~0); 932432#L679-1 assume !(1 == ~E_2~0); 932105#L684-1 assume !(1 == ~E_3~0); 932106#L689-1 assume !(1 == ~E_4~0); 932293#L694-1 assume !(1 == ~E_5~0); 932290#L699-1 assume { :end_inline_reset_delta_events } true; 932291#L900-2 assume !false; 1005436#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1005433#L561 [2021-11-23 14:02:57,136 INFO L793 eck$LassoCheckResult]: Loop: 1005433#L561 assume !false; 1005430#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1005427#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1005424#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1005421#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1005417#L486 assume 0 != eval_~tmp~0#1; 1005413#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1005409#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1005405#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1005388#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1005402#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1006939#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1001603#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1001604#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1005442#L533 assume !(0 == ~t4_st~0); 1005439#L547 assume !(0 == ~t5_st~0); 1005433#L561 [2021-11-23 14:02:57,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:57,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2021-11-23 14:02:57,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:57,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969435510] [2021-11-23 14:02:57,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:57,138 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:57,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:57,146 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:57,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:57,168 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:57,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:57,169 INFO L85 PathProgramCache]: Analyzing trace with hash 834182516, now seen corresponding path program 1 times [2021-11-23 14:02:57,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:57,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276808648] [2021-11-23 14:02:57,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:57,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:57,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:57,173 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:02:57,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:02:57,177 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:02:57,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:02:57,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1508123119, now seen corresponding path program 1 times [2021-11-23 14:02:57,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:02:57,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330732746] [2021-11-23 14:02:57,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:02:57,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:02:57,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:02:57,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:02:57,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:02:57,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330732746] [2021-11-23 14:02:57,206 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330732746] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:02:57,207 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:02:57,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 14:02:57,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375956282] [2021-11-23 14:02:57,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:02:57,362 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:02:57,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:02:57,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:02:57,363 INFO L87 Difference]: Start difference. First operand 118575 states and 159354 transitions. cyclomatic complexity: 40801 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:02:57,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:02:57,950 INFO L93 Difference]: Finished difference Result 196899 states and 264506 transitions. [2021-11-23 14:02:57,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:02:57,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196899 states and 264506 transitions. [2021-11-23 14:02:59,334 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 196244 [2021-11-23 14:02:59,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196899 states to 196899 states and 264506 transitions. [2021-11-23 14:02:59,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196899 [2021-11-23 14:02:59,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196899 [2021-11-23 14:02:59,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196899 states and 264506 transitions. [2021-11-23 14:02:59,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:02:59,874 INFO L681 BuchiCegarLoop]: Abstraction has 196899 states and 264506 transitions. [2021-11-23 14:02:59,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196899 states and 264506 transitions. [2021-11-23 14:03:01,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196899 to 193455. [2021-11-23 14:03:01,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193455 states, 193455 states have (on average 1.3460804838334497) internal successors, (260406), 193454 states have internal predecessors, (260406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:03:03,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193455 states to 193455 states and 260406 transitions. [2021-11-23 14:03:03,179 INFO L704 BuchiCegarLoop]: Abstraction has 193455 states and 260406 transitions. [2021-11-23 14:03:03,179 INFO L587 BuchiCegarLoop]: Abstraction has 193455 states and 260406 transitions. [2021-11-23 14:03:03,179 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-23 14:03:03,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193455 states and 260406 transitions. [2021-11-23 14:03:03,705 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 192800 [2021-11-23 14:03:03,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 14:03:03,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 14:03:03,706 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:03:03,706 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 14:03:03,707 INFO L791 eck$LassoCheckResult]: Stem: 1248076#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1248007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1247990#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1247984#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1247849#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1247850#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1247612#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1247613#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1247982#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1247983#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1247932#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1247582#L586 assume !(0 == ~M_E~0); 1247583#L586-2 assume !(0 == ~T1_E~0); 1247641#L591-1 assume !(0 == ~T2_E~0); 1247787#L596-1 assume !(0 == ~T3_E~0); 1247788#L601-1 assume !(0 == ~T4_E~0); 1247837#L606-1 assume !(0 == ~T5_E~0); 1247838#L611-1 assume !(0 == ~E_1~0); 1247943#L616-1 assume !(0 == ~E_2~0); 1247944#L621-1 assume !(0 == ~E_3~0); 1247509#L626-1 assume !(0 == ~E_4~0); 1247510#L631-1 assume !(0 == ~E_5~0); 1247673#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1247505#L279 assume !(1 == ~m_pc~0); 1247506#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1247865#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1247754#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1247755#L720 assume !(0 != activate_threads_~tmp~1#1); 1247864#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1247677#L298 assume !(1 == ~t1_pc~0); 1247463#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1247464#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1247742#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1247519#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1247520#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1247646#L317 assume !(1 == ~t2_pc~0); 1247647#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1247881#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1248000#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1247688#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1247689#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1247928#L336 assume !(1 == ~t3_pc~0); 1247929#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1248048#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1247818#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1247819#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1247873#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247936#L355 assume !(1 == ~t4_pc~0); 1247784#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1247935#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1247854#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247855#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1247532#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1247533#L374 assume !(1 == ~t5_pc~0); 1247664#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1247665#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1247752#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1247753#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1247821#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1247822#L649 assume !(1 == ~M_E~0); 1248090#L649-2 assume !(1 == ~T1_E~0); 1247494#L654-1 assume !(1 == ~T2_E~0); 1247495#L659-1 assume !(1 == ~T3_E~0); 1248089#L664-1 assume !(1 == ~T4_E~0); 1247486#L669-1 assume !(1 == ~T5_E~0); 1247487#L674-1 assume !(1 == ~E_1~0); 1247924#L679-1 assume !(1 == ~E_2~0); 1247586#L684-1 assume !(1 == ~E_3~0); 1247587#L689-1 assume !(1 == ~E_4~0); 1247777#L694-1 assume !(1 == ~E_5~0); 1247774#L699-1 assume { :end_inline_reset_delta_events } true; 1247775#L900-2 assume !false; 1374167#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1374165#L561 [2021-11-23 14:03:03,707 INFO L793 eck$LassoCheckResult]: Loop: 1374165#L561 assume !false; 1374163#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1374160#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1374158#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1374156#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1374154#L486 assume 0 != eval_~tmp~0#1; 1374151#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1374148#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1374146#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1374132#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1374144#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1363365#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1363366#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1368649#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1368650#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1374174#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1374170#L547 assume !(0 == ~t5_st~0); 1374165#L561 [2021-11-23 14:03:03,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:03:03,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2021-11-23 14:03:03,707 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:03:03,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837055615] [2021-11-23 14:03:03,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:03:03,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:03:03,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:03:03,715 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:03:03,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:03:03,737 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:03:03,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:03:03,738 INFO L85 PathProgramCache]: Analyzing trace with hash 89684008, now seen corresponding path program 1 times [2021-11-23 14:03:03,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:03:03,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136572704] [2021-11-23 14:03:03,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:03:03,739 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:03:03,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:03:03,742 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 14:03:03,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 14:03:03,747 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-23 14:03:03,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 14:03:03,747 INFO L85 PathProgramCache]: Analyzing trace with hash 492653355, now seen corresponding path program 1 times [2021-11-23 14:03:03,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 14:03:03,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767682586] [2021-11-23 14:03:03,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 14:03:03,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 14:03:03,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 14:03:03,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 14:03:03,774 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 14:03:03,774 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767682586] [2021-11-23 14:03:03,774 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767682586] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 14:03:03,774 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 14:03:03,774 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 14:03:03,774 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239665571] [2021-11-23 14:03:03,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 14:03:03,952 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 14:03:03,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 14:03:03,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 14:03:03,953 INFO L87 Difference]: Start difference. First operand 193455 states and 260406 transitions. cyclomatic complexity: 66973 Second operand has 3 states, 2 states have (on average 45.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:03:05,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 14:03:05,512 INFO L93 Difference]: Finished difference Result 228139 states and 306350 transitions. [2021-11-23 14:03:05,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 14:03:05,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228139 states and 306350 transitions. [2021-11-23 14:03:06,367 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 220868 [2021-11-23 14:03:06,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228139 states to 228139 states and 306350 transitions. [2021-11-23 14:03:06,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228139 [2021-11-23 14:03:06,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228139 [2021-11-23 14:03:06,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228139 states and 306350 transitions. [2021-11-23 14:03:07,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 14:03:07,776 INFO L681 BuchiCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2021-11-23 14:03:07,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228139 states and 306350 transitions. [2021-11-23 14:03:10,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228139 to 228139. [2021-11-23 14:03:10,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228139 states, 228139 states have (on average 1.3428217008052108) internal successors, (306350), 228138 states have internal predecessors, (306350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 14:03:10,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228139 states to 228139 states and 306350 transitions. [2021-11-23 14:03:10,872 INFO L704 BuchiCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2021-11-23 14:03:10,872 INFO L587 BuchiCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2021-11-23 14:03:10,872 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-23 14:03:10,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228139 states and 306350 transitions.