./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 7e70badd Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-7e70bad [2021-11-23 12:40:12,584 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-23 12:40:12,587 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-23 12:40:12,656 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-23 12:40:12,657 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-23 12:40:12,663 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-23 12:40:12,665 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-23 12:40:12,669 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-23 12:40:12,672 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-23 12:40:12,678 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-23 12:40:12,679 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-23 12:40:12,681 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-23 12:40:12,682 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-23 12:40:12,685 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-23 12:40:12,687 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-23 12:40:12,693 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-23 12:40:12,695 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-23 12:40:12,696 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-23 12:40:12,699 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-23 12:40:12,709 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-23 12:40:12,711 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-23 12:40:12,713 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-23 12:40:12,717 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-23 12:40:12,718 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-23 12:40:12,722 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-23 12:40:12,722 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-23 12:40:12,723 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-23 12:40:12,725 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-23 12:40:12,726 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-23 12:40:12,727 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-23 12:40:12,728 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-23 12:40:12,728 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-23 12:40:12,730 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-23 12:40:12,732 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-23 12:40:12,733 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-23 12:40:12,734 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-23 12:40:12,734 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-23 12:40:12,735 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-23 12:40:12,735 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-23 12:40:12,736 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-23 12:40:12,737 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-23 12:40:12,738 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-23 12:40:12,779 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-23 12:40:12,785 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-23 12:40:12,785 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-23 12:40:12,786 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-23 12:40:12,787 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-23 12:40:12,788 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-23 12:40:12,788 INFO L138 SettingsManager]: * Use SBE=true [2021-11-23 12:40:12,788 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-23 12:40:12,788 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-23 12:40:12,789 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-23 12:40:12,790 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-23 12:40:12,790 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-23 12:40:12,790 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-23 12:40:12,790 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-23 12:40:12,791 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-23 12:40:12,791 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-23 12:40:12,791 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-23 12:40:12,791 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-23 12:40:12,791 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-23 12:40:12,792 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-23 12:40:12,792 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-23 12:40:12,792 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-23 12:40:12,792 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-23 12:40:12,793 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-23 12:40:12,793 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-23 12:40:12,793 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-23 12:40:12,795 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-23 12:40:12,795 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-23 12:40:12,795 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-23 12:40:12,796 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-23 12:40:12,796 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-23 12:40:12,796 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-23 12:40:12,797 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-23 12:40:12,797 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2021-11-23 12:40:13,120 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-23 12:40:13,143 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-23 12:40:13,146 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-23 12:40:13,147 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-23 12:40:13,148 INFO L275 PluginConnector]: CDTParser initialized [2021-11-23 12:40:13,150 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/../../sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-11-23 12:40:13,226 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/data/d4758cd0c/ae50abc0de474b7aa78659ef7c40feb5/FLAG07f278b5f [2021-11-23 12:40:13,800 INFO L306 CDTParser]: Found 1 translation units. [2021-11-23 12:40:13,801 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-11-23 12:40:13,834 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/data/d4758cd0c/ae50abc0de474b7aa78659ef7c40feb5/FLAG07f278b5f [2021-11-23 12:40:14,109 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/data/d4758cd0c/ae50abc0de474b7aa78659ef7c40feb5 [2021-11-23 12:40:14,111 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-23 12:40:14,112 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-23 12:40:14,114 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-23 12:40:14,115 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-23 12:40:14,118 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-23 12:40:14,120 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,123 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@759b1e0a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14, skipping insertion in model container [2021-11-23 12:40:14,123 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,131 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-23 12:40:14,195 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-23 12:40:14,411 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-11-23 12:40:14,531 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 12:40:14,550 INFO L203 MainTranslator]: Completed pre-run [2021-11-23 12:40:14,562 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-11-23 12:40:14,630 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 12:40:14,652 INFO L208 MainTranslator]: Completed translation [2021-11-23 12:40:14,652 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14 WrapperNode [2021-11-23 12:40:14,652 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-23 12:40:14,654 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-23 12:40:14,654 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-23 12:40:14,654 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-23 12:40:14,661 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,690 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,818 INFO L137 Inliner]: procedures = 52, calls = 66, calls flagged for inlining = 61, calls inlined = 254, statements flattened = 3910 [2021-11-23 12:40:14,819 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-23 12:40:14,820 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-23 12:40:14,820 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-23 12:40:14,820 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-23 12:40:14,829 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,829 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,839 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,840 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,889 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,941 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,949 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,963 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-23 12:40:14,964 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-23 12:40:14,964 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-23 12:40:14,964 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-23 12:40:14,965 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (1/1) ... [2021-11-23 12:40:14,973 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-23 12:40:14,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/z3 [2021-11-23 12:40:14,997 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-23 12:40:15,032 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f25d6083-652b-4623-8748-fbf46802387c/bin/uautomizer-wIGwrQj20G/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-23 12:40:15,052 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-23 12:40:15,052 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-23 12:40:15,052 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-23 12:40:15,052 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-23 12:40:15,221 INFO L236 CfgBuilder]: Building ICFG [2021-11-23 12:40:15,223 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-23 12:40:17,436 INFO L277 CfgBuilder]: Performing block encoding [2021-11-23 12:40:17,466 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-23 12:40:17,466 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-11-23 12:40:17,471 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:40:17 BoogieIcfgContainer [2021-11-23 12:40:17,471 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-23 12:40:17,473 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-23 12:40:17,473 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-23 12:40:17,476 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-23 12:40:17,477 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 12:40:17,477 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 12:40:14" (1/3) ... [2021-11-23 12:40:17,479 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4d3548c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:40:17, skipping insertion in model container [2021-11-23 12:40:17,479 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 12:40:17,479 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:40:14" (2/3) ... [2021-11-23 12:40:17,479 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4d3548c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:40:17, skipping insertion in model container [2021-11-23 12:40:17,479 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-23 12:40:17,480 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:40:17" (3/3) ... [2021-11-23 12:40:17,481 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2021-11-23 12:40:17,541 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-23 12:40:17,542 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-23 12:40:17,542 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-23 12:40:17,542 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-23 12:40:17,542 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-23 12:40:17,542 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-23 12:40:17,542 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-23 12:40:17,542 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-23 12:40:17,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:17,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-11-23 12:40:17,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:17,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:17,742 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:17,742 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:17,743 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-23 12:40:17,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:17,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-11-23 12:40:17,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:17,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:17,792 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:17,792 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:17,809 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1609#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1450#L1731true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 696#L814true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 529#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 598#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1031#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1624#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 945#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 451#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 481#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 700#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 693#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244#L1174true assume !(0 == ~M_E~0); 1354#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 167#L1179-1true assume !(0 == ~T2_E~0); 119#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 188#L1194-1true assume !(0 == ~T5_E~0); 819#L1199-1true assume !(0 == ~T6_E~0); 979#L1204-1true assume !(0 == ~T7_E~0); 742#L1209-1true assume !(0 == ~T8_E~0); 1244#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1637#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 307#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 491#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1336#L1249-1true assume !(0 == ~E_4~0); 468#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 51#L1259-1true assume !(0 == ~E_6~0); 31#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1612#L1274-1true assume !(0 == ~E_9~0); 1325#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1466#L1289-1true assume !(0 == ~E_12~0); 508#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341#L566true assume 1 == ~m_pc~0; 39#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 972#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767#L578true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1189#L1455true assume !(0 != activate_threads_~tmp~1#1); 256#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1616#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714#L597true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1535#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1404#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397#L604true assume !(1 == ~t2_pc~0); 783#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1363#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413#L616true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1198#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 986#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465#L623true assume 1 == ~t3_pc~0; 359#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454#L635true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1025#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1242#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38#L642true assume !(1 == ~t4_pc~0); 663#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 265#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521#L654true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 796#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1123#L661true assume 1 == ~t5_pc~0; 149#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 708#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130#L673true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1100#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 827#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1490#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562#L692true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1115#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1401#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393#L699true assume 1 == ~t7_pc~0; 674#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 894#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144#L711true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 589#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 804#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L718true assume !(1 == ~t8_pc~0); 1250#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#L730true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 226#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 857#L737true assume 1 == ~t9_pc~0; 1502#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1284#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 735#L749true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1638#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 404#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1094#L756true assume 1 == ~t10_pc~0; 887#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 814#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5#L768true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 536#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 290#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 754#L775true assume !(1 == ~t11_pc~0); 445#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1262#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 223#L787true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 849#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L794true assume 1 == ~t12_pc~0; 117#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1101#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 975#L806true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 690#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L1307true assume !(1 == ~M_E~0); 541#L1307-2true assume !(1 == ~T1_E~0); 1445#L1312-1true assume !(1 == ~T2_E~0); 479#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 640#L1322-1true assume !(1 == ~T4_E~0); 295#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1414#L1337-1true assume !(1 == ~T7_E~0); 636#L1342-1true assume !(1 == ~T8_E~0); 1322#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 895#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1136#L1367-1true assume !(1 == ~E_1~0); 189#L1372-1true assume !(1 == ~E_2~0); 488#L1377-1true assume !(1 == ~E_3~0); 351#L1382-1true assume !(1 == ~E_4~0); 784#L1387-1true assume !(1 == ~E_5~0); 1258#L1392-1true assume !(1 == ~E_6~0); 363#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1389#L1402-1true assume !(1 == ~E_8~0); 195#L1407-1true assume !(1 == ~E_9~0); 1520#L1412-1true assume !(1 == ~E_10~0); 974#L1417-1true assume !(1 == ~E_11~0); 1696#L1422-1true assume !(1 == ~E_12~0); 1385#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2021-11-23 12:40:17,821 INFO L793 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 522#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 844#L1149true assume false; 1434#L1164true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419#L814-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999#L1174-3true assume !(0 == ~M_E~0); 992#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 717#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 896#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 577#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume !(0 == ~T8_E~0); 14#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 412#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 100#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1249-3true assume !(0 == ~E_4~0); 1446#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1237#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 765#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1504#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1321#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 411#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1379#L1289-3true assume !(0 == ~E_12~0); 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218#L566-39true assume !(1 == ~m_pc~0); 654#L566-41true is_master_triggered_~__retres1~0#1 := 0; 606#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396#L578-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 836#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298#L585-39true assume 1 == ~t1_pc~0; 968#L586-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L597-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1225#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 871#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L604-39true assume !(1 == ~t2_pc~0); 1222#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 339#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134#L616-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L623-39true assume !(1 == ~t3_pc~0); 650#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 853#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486#L635-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 803#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304#L642-39true assume 1 == ~t4_pc~0; 448#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 753#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#L654-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1184#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204#L661-39true assume !(1 == ~t5_pc~0); 25#L661-41true is_transmit5_triggered_~__retres1~5#1 := 0; 1627#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961#L673-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 977#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1145#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785#L692-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 289#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1491#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1248#L699-39true assume 1 == ~t7_pc~0; 579#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 381#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982#L711-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1269#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 511#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1388#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461#L730-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1153#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 707#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume 1 == ~t9_pc~0; 276#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 452#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1323#L749-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1449#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027#L756-39true assume 1 == ~t10_pc~0; 1376#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1515#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352#L768-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 460#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 431#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1694#L787-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1546#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 759#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467#L794-39true assume 1 == ~t12_pc~0; 277#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 914#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1347#L806-13true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 810#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1307#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1199#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610#L1312-3true assume !(1 == ~T2_E~0); 1604#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 828#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1672#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 533#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 957#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 632#L1352-3true assume !(1 == ~T10_E~0); 1112#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1508#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 20#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 343#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 927#L1392-3true assume !(1 == ~E_6~0); 1595#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1373#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 605#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 156#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1149#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 547#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1105#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1651#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 739#L962-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1433#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1215#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 647#L962-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1318#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 331#L1750true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1590#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2021-11-23 12:40:17,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:17,829 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2021-11-23 12:40:17,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:17,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914739094] [2021-11-23 12:40:17,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:17,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:17,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:18,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:18,097 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:18,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914739094] [2021-11-23 12:40:18,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914739094] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:18,098 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:18,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:18,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506422621] [2021-11-23 12:40:18,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:18,106 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:18,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:18,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1819192778, now seen corresponding path program 1 times [2021-11-23 12:40:18,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:18,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996666512] [2021-11-23 12:40:18,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:18,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:18,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:18,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:18,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:18,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996666512] [2021-11-23 12:40:18,209 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996666512] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:18,210 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:18,210 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 12:40:18,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500645159] [2021-11-23 12:40:18,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:18,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:18,213 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:18,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-23 12:40:18,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-23 12:40:18,276 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:18,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:18,376 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2021-11-23 12:40:18,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-23 12:40:18,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2021-11-23 12:40:18,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:18,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2021-11-23 12:40:18,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:18,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:18,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2021-11-23 12:40:18,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:18,444 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-23 12:40:18,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2021-11-23 12:40:18,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:18,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:18,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2021-11-23 12:40:18,553 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-23 12:40:18,553 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-23 12:40:18,553 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-23 12:40:18,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2021-11-23 12:40:18,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:18,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:18,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:18,600 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:18,600 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:18,601 INFO L791 eck$LassoCheckResult]: Stem: 4201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5055#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4547#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4354#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4355#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4440#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4741#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4863#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4864#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3652#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3653#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4801#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4247#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4248#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4154#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4155#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4543#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3896#L1174 assume !(0 == ~M_E~0); 3897#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3748#L1179-1 assume !(0 == ~T2_E~0); 3650#L1184-1 assume !(0 == ~T3_E~0); 3651#L1189-1 assume !(0 == ~T4_E~0); 3689#L1194-1 assume !(0 == ~T5_E~0); 3789#L1199-1 assume !(0 == ~T6_E~0); 4684#L1204-1 assume !(0 == ~T7_E~0); 4603#L1209-1 assume !(0 == ~T8_E~0); 4604#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4992#L1219-1 assume !(0 == ~T10_E~0); 5077#L1224-1 assume !(0 == ~T11_E~0); 4014#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3609#L1244-1 assume !(0 == ~E_3~0); 3610#L1249-1 assume !(0 == ~E_4~0); 4271#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3460#L1264-1 assume !(0 == ~E_7~0); 3461#L1269-1 assume !(0 == ~E_8~0); 5082#L1274-1 assume !(0 == ~E_9~0); 5017#L1279-1 assume !(0 == ~E_10~0); 3693#L1284-1 assume !(0 == ~E_11~0); 3694#L1289-1 assume !(0 == ~E_12~0); 4323#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324#L566 assume 1 == ~m_pc~0; 3477#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4632#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4633#L1455 assume !(0 != activate_threads_~tmp~1#1); 3923#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3924#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4573#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4574#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5042#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5040#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4186#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4187#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4824#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4825#L623 assume 1 == ~t3_pc~0; 4101#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3441#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4252#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4859#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3474#L642 assume !(1 == ~t4_pc~0); 3475#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3940#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3941#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3546#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3547#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4664#L661 assume 1 == ~t5_pc~0; 3711#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3712#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3673#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4693#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4694#L680 assume !(1 == ~t6_pc~0); 4134#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4396#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4397#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5038#L699 assume 1 == ~t7_pc~0; 4524#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4525#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3701#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3702#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4426#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325#L718 assume !(1 == ~t8_pc~0); 4326#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3687#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3688#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3729#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3730#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3863#L737 assume 1 == ~t9_pc~0; 4728#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3998#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4599#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4600#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4172#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4173#L756 assume 1 == ~t10_pc~0; 4752#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4418#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3404#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3405#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3980#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3981#L775 assume !(1 == ~t11_pc~0); 4235#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4236#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3857#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3621#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3622#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3808#L794 assume 1 == ~t12_pc~0; 3648#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3626#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4819#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3774#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3775#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L1307 assume !(1 == ~M_E~0); 4255#L1307-2 assume !(1 == ~T1_E~0); 4366#L1312-1 assume !(1 == ~T2_E~0); 4285#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4286#L1322-1 assume !(1 == ~T4_E~0); 3989#L1327-1 assume !(1 == ~T5_E~0); 3990#L1332-1 assume !(1 == ~T6_E~0); 4528#L1337-1 assume !(1 == ~T7_E~0); 4490#L1342-1 assume !(1 == ~T8_E~0); 4491#L1347-1 assume !(1 == ~T9_E~0); 4888#L1352-1 assume !(1 == ~T10_E~0); 4761#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4152#L1362-1 assume !(1 == ~T12_E~0); 4153#L1367-1 assume !(1 == ~E_1~0); 3790#L1372-1 assume !(1 == ~E_2~0); 3791#L1377-1 assume !(1 == ~E_3~0); 4084#L1382-1 assume !(1 == ~E_4~0); 4085#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4104#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4105#L1402-1 assume !(1 == ~E_8~0); 3801#L1407-1 assume !(1 == ~E_9~0); 3802#L1412-1 assume !(1 == ~E_10~0); 4817#L1417-1 assume !(1 == ~E_11~0); 4818#L1422-1 assume !(1 == ~E_12~0); 5036#L1427-1 assume { :end_inline_reset_delta_events } true; 3605#L1768-2 [2021-11-23 12:40:18,602 INFO L793 eck$LassoCheckResult]: Loop: 3605#L1768-2 assume !false; 3606#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4344#L1149 assume !false; 4716#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4869#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3995#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3901#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3902#L976 assume !(0 != eval_~tmp~0#1); 5035#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4836#L1174-3 assume !(0 == ~M_E~0); 4829#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4578#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4579#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4762#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4413#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3764#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4005#L1209-3 assume !(0 == ~T8_E~0); 3425#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3426#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4184#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4185#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4203#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3613#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3614#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4057#L1249-3 assume !(0 == ~E_4~0); 4516#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4630#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3619#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3620#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5015#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4182#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4183#L1289-3 assume !(0 == ~E_12~0); 4171#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3847#L566-39 assume 1 == ~m_pc~0; 3848#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4450#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4162#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4163#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4705#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4706#L585-39 assume 1 == ~t1_pc~0; 4816#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3856#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3931#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3932#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4738#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4431#L604-39 assume 1 == ~t2_pc~0; 4432#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4063#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4064#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4481#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4482#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4046#L623-39 assume 1 == ~t3_pc~0; 3442#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3444#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4722#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3898#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3899#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4670#L642-39 assume 1 == ~t4_pc~0; 4241#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4242#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3770#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3771#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4868#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3819#L661-39 assume !(1 == ~t5_pc~0); 3450#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3451#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4811#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4812#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4725#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4726#L680-39 assume 1 == ~t6_pc~0; 3512#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3513#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4655#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3978#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3979#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4993#L699-39 assume !(1 == ~t7_pc~0); 4416#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4137#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4821#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4942#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4940#L718-39 assume 1 == ~t8_pc~0; 4329#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4330#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4262#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4263#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4565#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4534#L737-39 assume 1 == ~t9_pc~0; 3959#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3960#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4249#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5016#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4917#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4860#L756-39 assume !(1 == ~t10_pc~0); 4341#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4342#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4086#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4087#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4219#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4212#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4213#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5075#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L794-39 assume !(1 == ~t12_pc~0); 3955#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3956#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4776#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4677#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4970#L1312-3 assume !(1 == ~T2_E~0); 5081#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4695#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4696#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3640#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3611#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3612#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4358#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4483#L1352-3 assume !(1 == ~T10_E~0); 4484#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4923#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5074#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4070#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4071#L1392-3 assume !(1 == ~E_6~0); 4786#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4449#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3725#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3726#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4374#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4375#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3735#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4602#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4454#L1787 assume !(0 == start_simulation_~tmp~3#1); 4455#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4978#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3706#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4501#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4502#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4053#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4054#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4055#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3605#L1768-2 [2021-11-23 12:40:18,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:18,603 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2021-11-23 12:40:18,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:18,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959469213] [2021-11-23 12:40:18,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:18,604 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:18,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:18,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:18,743 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:18,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959469213] [2021-11-23 12:40:18,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959469213] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:18,743 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:18,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:18,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933161560] [2021-11-23 12:40:18,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:18,745 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:18,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:18,746 INFO L85 PathProgramCache]: Analyzing trace with hash -1764555615, now seen corresponding path program 1 times [2021-11-23 12:40:18,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:18,746 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728186899] [2021-11-23 12:40:18,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:18,747 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:18,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:18,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:18,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:18,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728186899] [2021-11-23 12:40:18,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728186899] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:18,950 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:18,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:18,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008870381] [2021-11-23 12:40:18,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:18,951 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:18,952 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:18,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:18,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:18,956 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:19,022 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2021-11-23 12:40:19,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:19,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2021-11-23 12:40:19,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-11-23 12:40:19,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:19,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:19,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2021-11-23 12:40:19,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:19,066 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-23 12:40:19,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2021-11-23 12:40:19,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:19,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-11-23 12:40:19,111 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-23 12:40:19,111 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-23 12:40:19,111 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-23 12:40:19,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2021-11-23 12:40:19,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:19,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:19,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,131 INFO L791 eck$LassoCheckResult]: Stem: 7584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8438#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7930#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7737#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7738#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7823#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8124#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8246#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8247#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7035#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7036#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8184#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7630#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7631#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7537#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7538#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7926#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7279#L1174 assume !(0 == ~M_E~0); 7280#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7131#L1179-1 assume !(0 == ~T2_E~0); 7033#L1184-1 assume !(0 == ~T3_E~0); 7034#L1189-1 assume !(0 == ~T4_E~0); 7072#L1194-1 assume !(0 == ~T5_E~0); 7172#L1199-1 assume !(0 == ~T6_E~0); 8067#L1204-1 assume !(0 == ~T7_E~0); 7986#L1209-1 assume !(0 == ~T8_E~0); 7987#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8375#L1219-1 assume !(0 == ~T10_E~0); 8460#L1224-1 assume !(0 == ~T11_E~0); 7397#L1229-1 assume !(0 == ~T12_E~0); 6958#L1234-1 assume !(0 == ~E_1~0); 6959#L1239-1 assume !(0 == ~E_2~0); 6992#L1244-1 assume !(0 == ~E_3~0); 6993#L1249-1 assume !(0 == ~E_4~0); 7654#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6888#L1259-1 assume !(0 == ~E_6~0); 6843#L1264-1 assume !(0 == ~E_7~0); 6844#L1269-1 assume !(0 == ~E_8~0); 8465#L1274-1 assume !(0 == ~E_9~0); 8400#L1279-1 assume !(0 == ~E_10~0); 7076#L1284-1 assume !(0 == ~E_11~0); 7077#L1289-1 assume !(0 == ~E_12~0); 7706#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7707#L566 assume 1 == ~m_pc~0; 6860#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6861#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8015#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8016#L1455 assume !(0 != activate_threads_~tmp~1#1); 7306#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7307#L585 assume 1 == ~t1_pc~0; 6955#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6956#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7956#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7957#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8425#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L604 assume !(1 == ~t2_pc~0); 8035#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8036#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7569#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7570#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8207#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8208#L623 assume 1 == ~t3_pc~0; 7484#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6824#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7634#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8242#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6857#L642 assume !(1 == ~t4_pc~0); 6858#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7323#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7324#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6929#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6930#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8047#L661 assume 1 == ~t5_pc~0; 7094#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7095#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7056#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7057#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8076#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8077#L680 assume !(1 == ~t6_pc~0); 7517#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7518#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7779#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7780#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8308#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8421#L699 assume 1 == ~t7_pc~0; 7907#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7908#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7084#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7085#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7809#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7708#L718 assume !(1 == ~t8_pc~0); 7709#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7070#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7071#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7112#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7113#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7246#L737 assume 1 == ~t9_pc~0; 8111#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7381#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7982#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7983#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L756 assume 1 == ~t10_pc~0; 8135#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7801#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6787#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6788#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7363#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7364#L775 assume !(1 == ~t11_pc~0); 7618#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7619#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7240#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7004#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7005#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7191#L794 assume 1 == ~t12_pc~0; 7031#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7009#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8202#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7157#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7158#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7637#L1307 assume !(1 == ~M_E~0); 7638#L1307-2 assume !(1 == ~T1_E~0); 7749#L1312-1 assume !(1 == ~T2_E~0); 7668#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7669#L1322-1 assume !(1 == ~T4_E~0); 7372#L1327-1 assume !(1 == ~T5_E~0); 7373#L1332-1 assume !(1 == ~T6_E~0); 7911#L1337-1 assume !(1 == ~T7_E~0); 7873#L1342-1 assume !(1 == ~T8_E~0); 7874#L1347-1 assume !(1 == ~T9_E~0); 8271#L1352-1 assume !(1 == ~T10_E~0); 8144#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7535#L1362-1 assume !(1 == ~T12_E~0); 7536#L1367-1 assume !(1 == ~E_1~0); 7173#L1372-1 assume !(1 == ~E_2~0); 7174#L1377-1 assume !(1 == ~E_3~0); 7467#L1382-1 assume !(1 == ~E_4~0); 7468#L1387-1 assume !(1 == ~E_5~0); 8037#L1392-1 assume !(1 == ~E_6~0); 7487#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7488#L1402-1 assume !(1 == ~E_8~0); 7184#L1407-1 assume !(1 == ~E_9~0); 7185#L1412-1 assume !(1 == ~E_10~0); 8200#L1417-1 assume !(1 == ~E_11~0); 8201#L1422-1 assume !(1 == ~E_12~0); 8419#L1427-1 assume { :end_inline_reset_delta_events } true; 6988#L1768-2 [2021-11-23 12:40:19,132 INFO L793 eck$LassoCheckResult]: Loop: 6988#L1768-2 assume !false; 6989#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7727#L1149 assume !false; 8099#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8252#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7378#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7284#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7285#L976 assume !(0 != eval_~tmp~0#1); 8418#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8428#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8219#L1174-3 assume !(0 == ~M_E~0); 8212#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8145#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7796#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7146#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7147#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7388#L1209-3 assume !(0 == ~T8_E~0); 6808#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6809#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7567#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7586#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6996#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6997#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7440#L1249-3 assume !(0 == ~E_4~0); 7899#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8371#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8013#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7002#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7003#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8398#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7565#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7566#L1289-3 assume !(0 == ~E_12~0); 7554#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7230#L566-39 assume !(1 == ~m_pc~0); 7232#L566-41 is_master_triggered_~__retres1~0#1 := 0; 7833#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7545#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7546#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8088#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8089#L585-39 assume !(1 == ~t1_pc~0); 7238#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7239#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7314#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7315#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8121#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7814#L604-39 assume 1 == ~t2_pc~0; 7815#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7446#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7447#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7864#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7865#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7429#L623-39 assume 1 == ~t3_pc~0; 6825#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6827#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8105#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7281#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7282#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8053#L642-39 assume 1 == ~t4_pc~0; 7624#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7625#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7153#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7154#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8251#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7202#L661-39 assume !(1 == ~t5_pc~0); 6833#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6834#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8194#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8195#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8108#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8109#L680-39 assume !(1 == ~t6_pc~0); 6897#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6896#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8038#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7361#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7362#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8376#L699-39 assume 1 == ~t7_pc~0; 7798#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7520#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7521#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8204#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8325#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8323#L718-39 assume 1 == ~t8_pc~0; 7712#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7713#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7645#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7646#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 7948#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7917#L737-39 assume !(1 == ~t9_pc~0); 7344#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 7343#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7632#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8399#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8300#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8243#L756-39 assume 1 == ~t10_pc~0; 8244#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7725#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7469#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7470#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7602#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6942#L775-39 assume !(1 == ~t11_pc~0); 6944#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 7595#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7596#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8458#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8006#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7653#L794-39 assume 1 == ~t12_pc~0; 7345#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7339#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8159#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8060#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8352#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8353#L1312-3 assume !(1 == ~T2_E~0); 8464#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8078#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8079#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7023#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6994#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6995#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7741#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7866#L1352-3 assume !(1 == ~T10_E~0); 7867#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8306#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8457#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8448#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6821#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6822#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7453#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7454#L1392-3 assume !(1 == ~E_6~0); 8169#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8415#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7108#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7109#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7757#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7758#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7118#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7119#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7985#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7837#L1787 assume !(0 == start_simulation_~tmp~3#1); 7838#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8361#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7089#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7884#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 7885#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7436#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7437#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1768-2 [2021-11-23 12:40:19,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,136 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2021-11-23 12:40:19,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633902284] [2021-11-23 12:40:19,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,138 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,219 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633902284] [2021-11-23 12:40:19,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633902284] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,220 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,220 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,221 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563264600] [2021-11-23 12:40:19,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,221 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:19,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1578992735, now seen corresponding path program 1 times [2021-11-23 12:40:19,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134065715] [2021-11-23 12:40:19,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,290 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134065715] [2021-11-23 12:40:19,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134065715] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,291 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,291 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,292 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315257009] [2021-11-23 12:40:19,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,292 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:19,293 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:19,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:19,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:19,294 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:19,340 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2021-11-23 12:40:19,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:19,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2021-11-23 12:40:19,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-11-23 12:40:19,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:19,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:19,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2021-11-23 12:40:19,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:19,381 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-23 12:40:19,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2021-11-23 12:40:19,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:19,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-11-23 12:40:19,485 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-23 12:40:19,485 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-23 12:40:19,485 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-23 12:40:19,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2021-11-23 12:40:19,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:19,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:19,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,500 INFO L791 eck$LassoCheckResult]: Stem: 10967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11821#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11313#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11120#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11121#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11206#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11507#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11629#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11630#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10418#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10419#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11567#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11013#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11014#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10920#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10921#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11309#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10662#L1174 assume !(0 == ~M_E~0); 10663#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10514#L1179-1 assume !(0 == ~T2_E~0); 10416#L1184-1 assume !(0 == ~T3_E~0); 10417#L1189-1 assume !(0 == ~T4_E~0); 10455#L1194-1 assume !(0 == ~T5_E~0); 10555#L1199-1 assume !(0 == ~T6_E~0); 11450#L1204-1 assume !(0 == ~T7_E~0); 11369#L1209-1 assume !(0 == ~T8_E~0); 11370#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11758#L1219-1 assume !(0 == ~T10_E~0); 11843#L1224-1 assume !(0 == ~T11_E~0); 10780#L1229-1 assume !(0 == ~T12_E~0); 10341#L1234-1 assume !(0 == ~E_1~0); 10342#L1239-1 assume !(0 == ~E_2~0); 10375#L1244-1 assume !(0 == ~E_3~0); 10376#L1249-1 assume !(0 == ~E_4~0); 11037#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10271#L1259-1 assume !(0 == ~E_6~0); 10226#L1264-1 assume !(0 == ~E_7~0); 10227#L1269-1 assume !(0 == ~E_8~0); 11848#L1274-1 assume !(0 == ~E_9~0); 11783#L1279-1 assume !(0 == ~E_10~0); 10459#L1284-1 assume !(0 == ~E_11~0); 10460#L1289-1 assume !(0 == ~E_12~0); 11089#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11090#L566 assume 1 == ~m_pc~0; 10243#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10244#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11398#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11399#L1455 assume !(0 != activate_threads_~tmp~1#1); 10689#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10690#L585 assume 1 == ~t1_pc~0; 10338#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10339#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11339#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11340#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11806#L604 assume !(1 == ~t2_pc~0); 11418#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11419#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10952#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10953#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11590#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11591#L623 assume 1 == ~t3_pc~0; 10867#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10207#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11017#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11018#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11625#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10240#L642 assume !(1 == ~t4_pc~0); 10241#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10706#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10707#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10312#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10313#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11430#L661 assume 1 == ~t5_pc~0; 10477#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10478#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10439#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10440#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11459#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11460#L680 assume !(1 == ~t6_pc~0); 10900#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10901#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11162#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11163#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11691#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11804#L699 assume 1 == ~t7_pc~0; 11290#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11291#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10467#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10468#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11192#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11091#L718 assume !(1 == ~t8_pc~0); 11092#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10453#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10454#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10495#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10496#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10629#L737 assume 1 == ~t9_pc~0; 11494#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10764#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11365#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11366#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10938#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10939#L756 assume 1 == ~t10_pc~0; 11518#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11184#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10170#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10171#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10746#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10747#L775 assume !(1 == ~t11_pc~0); 11001#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11002#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10623#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10387#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10388#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10574#L794 assume 1 == ~t12_pc~0; 10414#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10392#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11585#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10540#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10541#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11020#L1307 assume !(1 == ~M_E~0); 11021#L1307-2 assume !(1 == ~T1_E~0); 11132#L1312-1 assume !(1 == ~T2_E~0); 11051#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11052#L1322-1 assume !(1 == ~T4_E~0); 10755#L1327-1 assume !(1 == ~T5_E~0); 10756#L1332-1 assume !(1 == ~T6_E~0); 11294#L1337-1 assume !(1 == ~T7_E~0); 11256#L1342-1 assume !(1 == ~T8_E~0); 11257#L1347-1 assume !(1 == ~T9_E~0); 11654#L1352-1 assume !(1 == ~T10_E~0); 11527#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10918#L1362-1 assume !(1 == ~T12_E~0); 10919#L1367-1 assume !(1 == ~E_1~0); 10556#L1372-1 assume !(1 == ~E_2~0); 10557#L1377-1 assume !(1 == ~E_3~0); 10850#L1382-1 assume !(1 == ~E_4~0); 10851#L1387-1 assume !(1 == ~E_5~0); 11420#L1392-1 assume !(1 == ~E_6~0); 10870#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10871#L1402-1 assume !(1 == ~E_8~0); 10567#L1407-1 assume !(1 == ~E_9~0); 10568#L1412-1 assume !(1 == ~E_10~0); 11583#L1417-1 assume !(1 == ~E_11~0); 11584#L1422-1 assume !(1 == ~E_12~0); 11802#L1427-1 assume { :end_inline_reset_delta_events } true; 10371#L1768-2 [2021-11-23 12:40:19,500 INFO L793 eck$LassoCheckResult]: Loop: 10371#L1768-2 assume !false; 10372#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11110#L1149 assume !false; 11482#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11635#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10761#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10667#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10668#L976 assume !(0 != eval_~tmp~0#1); 11801#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11811#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11602#L1174-3 assume !(0 == ~M_E~0); 11595#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11344#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11345#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11528#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11179#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10529#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10530#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10771#L1209-3 assume !(0 == ~T8_E~0); 10191#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10192#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10950#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10951#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10969#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10379#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10380#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10823#L1249-3 assume !(0 == ~E_4~0); 11282#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11754#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11396#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10385#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10386#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11781#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10948#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10949#L1289-3 assume !(0 == ~E_12~0); 10937#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10613#L566-39 assume 1 == ~m_pc~0; 10614#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11216#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10928#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10929#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11471#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11472#L585-39 assume !(1 == ~t1_pc~0); 10621#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10622#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10697#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10698#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11504#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11197#L604-39 assume 1 == ~t2_pc~0; 11198#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10829#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10830#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11247#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11248#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10812#L623-39 assume 1 == ~t3_pc~0; 10208#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10210#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11488#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10664#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10665#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11436#L642-39 assume !(1 == ~t4_pc~0); 11009#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 11008#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10536#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10537#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11634#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10585#L661-39 assume !(1 == ~t5_pc~0); 10216#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10217#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11578#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11491#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11492#L680-39 assume 1 == ~t6_pc~0; 10278#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11421#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10744#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10745#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11759#L699-39 assume 1 == ~t7_pc~0; 11181#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10903#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10904#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11587#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11708#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11706#L718-39 assume 1 == ~t8_pc~0; 11095#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11096#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11028#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11029#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11331#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11300#L737-39 assume 1 == ~t9_pc~0; 10725#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10726#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11015#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11782#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11683#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11626#L756-39 assume !(1 == ~t10_pc~0); 11107#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11108#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10852#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10853#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10985#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10325#L775-39 assume 1 == ~t11_pc~0; 10326#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10978#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10979#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11841#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11389#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11036#L794-39 assume !(1 == ~t12_pc~0); 10721#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10722#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11542#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11443#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10267#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10268#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11735#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11736#L1312-3 assume !(1 == ~T2_E~0); 11847#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11461#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11462#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10406#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10377#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10378#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11124#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11249#L1352-3 assume !(1 == ~T10_E~0); 11250#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11689#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11840#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11831#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10204#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10205#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10836#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10837#L1392-3 assume !(1 == ~E_6~0); 11552#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11798#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11215#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10491#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10492#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11140#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11141#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10501#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10502#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11368#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 11220#L1787 assume !(0 == start_simulation_~tmp~3#1); 11221#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11744#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10472#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11267#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 11268#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10819#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10820#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10821#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10371#L1768-2 [2021-11-23 12:40:19,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2021-11-23 12:40:19,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940975439] [2021-11-23 12:40:19,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,503 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,547 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940975439] [2021-11-23 12:40:19,548 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940975439] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,548 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903649718] [2021-11-23 12:40:19,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,553 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:19,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,554 INFO L85 PathProgramCache]: Analyzing trace with hash -601300672, now seen corresponding path program 1 times [2021-11-23 12:40:19,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86432460] [2021-11-23 12:40:19,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,642 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86432460] [2021-11-23 12:40:19,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86432460] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,643 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,643 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539652890] [2021-11-23 12:40:19,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,644 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:19,644 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:19,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:19,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:19,646 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:19,692 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2021-11-23 12:40:19,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:19,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2021-11-23 12:40:19,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-11-23 12:40:19,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:19,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:19,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2021-11-23 12:40:19,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:19,730 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-23 12:40:19,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2021-11-23 12:40:19,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:19,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-11-23 12:40:19,770 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-23 12:40:19,770 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-23 12:40:19,770 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-23 12:40:19,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2021-11-23 12:40:19,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:19,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:19,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:19,785 INFO L791 eck$LassoCheckResult]: Stem: 14351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 14352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15204#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14698#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14503#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14504#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14589#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14891#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15012#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15013#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13801#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13802#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14950#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14396#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14397#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14303#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14304#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14693#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14045#L1174 assume !(0 == ~M_E~0); 14046#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13897#L1179-1 assume !(0 == ~T2_E~0); 13799#L1184-1 assume !(0 == ~T3_E~0); 13800#L1189-1 assume !(0 == ~T4_E~0); 13838#L1194-1 assume !(0 == ~T5_E~0); 13938#L1199-1 assume !(0 == ~T6_E~0); 14833#L1204-1 assume !(0 == ~T7_E~0); 14752#L1209-1 assume !(0 == ~T8_E~0); 14753#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15141#L1219-1 assume !(0 == ~T10_E~0); 15226#L1224-1 assume !(0 == ~T11_E~0); 14164#L1229-1 assume !(0 == ~T12_E~0); 13726#L1234-1 assume !(0 == ~E_1~0); 13727#L1239-1 assume !(0 == ~E_2~0); 13760#L1244-1 assume !(0 == ~E_3~0); 13761#L1249-1 assume !(0 == ~E_4~0); 14420#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13654#L1259-1 assume !(0 == ~E_6~0); 13609#L1264-1 assume !(0 == ~E_7~0); 13610#L1269-1 assume !(0 == ~E_8~0); 15231#L1274-1 assume !(0 == ~E_9~0); 15166#L1279-1 assume !(0 == ~E_10~0); 13842#L1284-1 assume !(0 == ~E_11~0); 13843#L1289-1 assume !(0 == ~E_12~0); 14472#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14473#L566 assume 1 == ~m_pc~0; 13626#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13627#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14781#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14782#L1455 assume !(0 != activate_threads_~tmp~1#1); 14072#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14073#L585 assume 1 == ~t1_pc~0; 13721#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13722#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14722#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14723#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15191#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15189#L604 assume !(1 == ~t2_pc~0); 14801#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14802#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14335#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14336#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14975#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14976#L623 assume 1 == ~t3_pc~0; 14250#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13590#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14400#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14401#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15008#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13623#L642 assume !(1 == ~t4_pc~0); 13624#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14089#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14090#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13697#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13698#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14813#L661 assume 1 == ~t5_pc~0; 13860#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13861#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13823#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14844#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14845#L680 assume !(1 == ~t6_pc~0); 14283#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14284#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14545#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14546#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15074#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15187#L699 assume 1 == ~t7_pc~0; 14673#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14674#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13850#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13851#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14575#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14474#L718 assume !(1 == ~t8_pc~0); 14475#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13836#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13837#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13878#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13879#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14012#L737 assume 1 == ~t9_pc~0; 14878#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14148#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14748#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14749#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14321#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14322#L756 assume 1 == ~t10_pc~0; 14901#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14567#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13553#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13554#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14129#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14130#L775 assume !(1 == ~t11_pc~0); 14384#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14385#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14009#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13770#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13771#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13957#L794 assume 1 == ~t12_pc~0; 13798#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13775#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14968#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13925#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 13926#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14403#L1307 assume !(1 == ~M_E~0); 14404#L1307-2 assume !(1 == ~T1_E~0); 14515#L1312-1 assume !(1 == ~T2_E~0); 14434#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14435#L1322-1 assume !(1 == ~T4_E~0); 14138#L1327-1 assume !(1 == ~T5_E~0); 14139#L1332-1 assume !(1 == ~T6_E~0); 14677#L1337-1 assume !(1 == ~T7_E~0); 14639#L1342-1 assume !(1 == ~T8_E~0); 14640#L1347-1 assume !(1 == ~T9_E~0); 15037#L1352-1 assume !(1 == ~T10_E~0); 14910#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14301#L1362-1 assume !(1 == ~T12_E~0); 14302#L1367-1 assume !(1 == ~E_1~0); 13939#L1372-1 assume !(1 == ~E_2~0); 13940#L1377-1 assume !(1 == ~E_3~0); 14233#L1382-1 assume !(1 == ~E_4~0); 14234#L1387-1 assume !(1 == ~E_5~0); 14803#L1392-1 assume !(1 == ~E_6~0); 14255#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14256#L1402-1 assume !(1 == ~E_8~0); 13955#L1407-1 assume !(1 == ~E_9~0); 13956#L1412-1 assume !(1 == ~E_10~0); 14966#L1417-1 assume !(1 == ~E_11~0); 14967#L1422-1 assume !(1 == ~E_12~0); 15185#L1427-1 assume { :end_inline_reset_delta_events } true; 13754#L1768-2 [2021-11-23 12:40:19,785 INFO L793 eck$LassoCheckResult]: Loop: 13754#L1768-2 assume !false; 13755#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14495#L1149 assume !false; 14866#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15018#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14144#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14056#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14057#L976 assume !(0 != eval_~tmp~0#1); 15184#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15194#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14985#L1174-3 assume !(0 == ~M_E~0); 14978#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14727#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14728#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14912#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14562#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13915#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13916#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14154#L1209-3 assume !(0 == ~T8_E~0); 13574#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13575#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14333#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14334#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14353#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13762#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13763#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14209#L1249-3 assume !(0 == ~E_4~0); 14665#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15137#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14779#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13768#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13769#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15164#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14331#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14332#L1289-3 assume !(0 == ~E_12~0); 14320#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13993#L566-39 assume 1 == ~m_pc~0; 13994#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14599#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14311#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14312#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14854#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14855#L585-39 assume !(1 == ~t1_pc~0); 14004#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14005#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14080#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14081#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14580#L604-39 assume 1 == ~t2_pc~0; 14581#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14212#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14213#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14630#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14631#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14195#L623-39 assume 1 == ~t3_pc~0; 13591#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13593#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14871#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14047#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14048#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14819#L642-39 assume 1 == ~t4_pc~0; 14390#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14391#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13919#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13968#L661-39 assume 1 == ~t5_pc~0; 13969#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13600#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14960#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14961#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14874#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14875#L680-39 assume 1 == ~t6_pc~0; 13661#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13662#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14804#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14127#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14128#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15142#L699-39 assume 1 == ~t7_pc~0; 14564#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14286#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14287#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14970#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15091#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15089#L718-39 assume !(1 == ~t8_pc~0); 14480#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 14479#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14411#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14412#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 14713#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14683#L737-39 assume 1 == ~t9_pc~0; 14108#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14109#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14398#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15165#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15066#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15009#L756-39 assume 1 == ~t10_pc~0; 15010#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14491#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14235#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14236#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14368#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13708#L775-39 assume 1 == ~t11_pc~0; 13709#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14361#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14362#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15224#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14772#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14419#L794-39 assume !(1 == ~t12_pc~0); 14104#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14105#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14925#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14826#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13650#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13651#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15118#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15119#L1312-3 assume !(1 == ~T2_E~0); 15230#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14843#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13789#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13758#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13759#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14507#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14632#L1352-3 assume !(1 == ~T10_E~0); 14633#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15072#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15223#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15214#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13584#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13585#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14219#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14220#L1392-3 assume !(1 == ~E_6~0); 14935#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15181#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14598#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13874#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13875#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14523#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14524#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13884#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13885#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14751#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14602#L1787 assume !(0 == start_simulation_~tmp~3#1); 14603#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15127#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13855#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14650#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 14651#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14202#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14203#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14204#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13754#L1768-2 [2021-11-23 12:40:19,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2021-11-23 12:40:19,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126405539] [2021-11-23 12:40:19,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,830 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126405539] [2021-11-23 12:40:19,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126405539] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,830 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,831 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934485424] [2021-11-23 12:40:19,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,831 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:19,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:19,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371202, now seen corresponding path program 1 times [2021-11-23 12:40:19,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:19,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5166996] [2021-11-23 12:40:19,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:19,832 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:19,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:19,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:19,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:19,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5166996] [2021-11-23 12:40:19,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5166996] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:19,891 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:19,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:19,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084958551] [2021-11-23 12:40:19,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:19,892 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:19,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:19,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:19,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:19,893 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:19,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:19,932 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2021-11-23 12:40:19,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:19,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2021-11-23 12:40:19,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:19,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-11-23 12:40:19,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:19,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:19,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2021-11-23 12:40:19,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:19,971 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-23 12:40:19,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2021-11-23 12:40:20,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:20,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-11-23 12:40:20,013 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-23 12:40:20,013 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-23 12:40:20,014 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-23 12:40:20,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2021-11-23 12:40:20,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:20,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:20,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,026 INFO L791 eck$LassoCheckResult]: Stem: 17733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18587#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18081#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17886#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17887#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17972#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18273#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18395#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18396#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17184#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17185#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18333#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17779#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17780#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17686#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17687#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17428#L1174 assume !(0 == ~M_E~0); 17429#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17280#L1179-1 assume !(0 == ~T2_E~0); 17182#L1184-1 assume !(0 == ~T3_E~0); 17183#L1189-1 assume !(0 == ~T4_E~0); 17221#L1194-1 assume !(0 == ~T5_E~0); 17321#L1199-1 assume !(0 == ~T6_E~0); 18216#L1204-1 assume !(0 == ~T7_E~0); 18135#L1209-1 assume !(0 == ~T8_E~0); 18136#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18524#L1219-1 assume !(0 == ~T10_E~0); 18609#L1224-1 assume !(0 == ~T11_E~0); 17546#L1229-1 assume !(0 == ~T12_E~0); 17107#L1234-1 assume !(0 == ~E_1~0); 17108#L1239-1 assume !(0 == ~E_2~0); 17143#L1244-1 assume !(0 == ~E_3~0); 17144#L1249-1 assume !(0 == ~E_4~0); 17803#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17037#L1259-1 assume !(0 == ~E_6~0); 16992#L1264-1 assume !(0 == ~E_7~0); 16993#L1269-1 assume !(0 == ~E_8~0); 18614#L1274-1 assume !(0 == ~E_9~0); 18549#L1279-1 assume !(0 == ~E_10~0); 17225#L1284-1 assume !(0 == ~E_11~0); 17226#L1289-1 assume !(0 == ~E_12~0); 17855#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17856#L566 assume 1 == ~m_pc~0; 17009#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17010#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18164#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18165#L1455 assume !(0 != activate_threads_~tmp~1#1); 17455#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17456#L585 assume 1 == ~t1_pc~0; 17104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18105#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18106#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18574#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18572#L604 assume !(1 == ~t2_pc~0); 18184#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18185#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17718#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17719#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18358#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18359#L623 assume 1 == ~t3_pc~0; 17633#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16973#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17783#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17784#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18391#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17006#L642 assume !(1 == ~t4_pc~0); 17007#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17472#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17473#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17078#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17079#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18196#L661 assume 1 == ~t5_pc~0; 17243#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17244#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17205#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17206#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18227#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18228#L680 assume !(1 == ~t6_pc~0); 17666#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17667#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17928#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17929#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18457#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18570#L699 assume 1 == ~t7_pc~0; 18056#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18057#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17233#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17234#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17958#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17857#L718 assume !(1 == ~t8_pc~0); 17858#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17219#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17220#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17261#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17262#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17395#L737 assume 1 == ~t9_pc~0; 18261#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17530#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18131#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18132#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17704#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17705#L756 assume 1 == ~t10_pc~0; 18284#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17950#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16936#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16937#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17512#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17513#L775 assume !(1 == ~t11_pc~0); 17767#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17768#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17389#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17153#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17154#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17340#L794 assume 1 == ~t12_pc~0; 17181#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17158#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18351#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17308#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17309#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17786#L1307 assume !(1 == ~M_E~0); 17787#L1307-2 assume !(1 == ~T1_E~0); 17898#L1312-1 assume !(1 == ~T2_E~0); 17817#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17818#L1322-1 assume !(1 == ~T4_E~0); 17521#L1327-1 assume !(1 == ~T5_E~0); 17522#L1332-1 assume !(1 == ~T6_E~0); 18060#L1337-1 assume !(1 == ~T7_E~0); 18022#L1342-1 assume !(1 == ~T8_E~0); 18023#L1347-1 assume !(1 == ~T9_E~0); 18420#L1352-1 assume !(1 == ~T10_E~0); 18293#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17684#L1362-1 assume !(1 == ~T12_E~0); 17685#L1367-1 assume !(1 == ~E_1~0); 17322#L1372-1 assume !(1 == ~E_2~0); 17323#L1377-1 assume !(1 == ~E_3~0); 17616#L1382-1 assume !(1 == ~E_4~0); 17617#L1387-1 assume !(1 == ~E_5~0); 18186#L1392-1 assume !(1 == ~E_6~0); 17638#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17639#L1402-1 assume !(1 == ~E_8~0); 17335#L1407-1 assume !(1 == ~E_9~0); 17336#L1412-1 assume !(1 == ~E_10~0); 18349#L1417-1 assume !(1 == ~E_11~0); 18350#L1422-1 assume !(1 == ~E_12~0); 18568#L1427-1 assume { :end_inline_reset_delta_events } true; 17137#L1768-2 [2021-11-23 12:40:20,026 INFO L793 eck$LassoCheckResult]: Loop: 17137#L1768-2 assume !false; 17138#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17876#L1149 assume !false; 18248#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18401#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17527#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17433#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17434#L976 assume !(0 != eval_~tmp~0#1); 18567#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18577#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18368#L1174-3 assume !(0 == ~M_E~0); 18361#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18110#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18111#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18295#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17945#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17298#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17299#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17537#L1209-3 assume !(0 == ~T8_E~0); 16957#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16958#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17716#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17717#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17735#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17145#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17146#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17589#L1249-3 assume !(0 == ~E_4~0); 18048#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18520#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18162#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17151#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17152#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18547#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17714#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17715#L1289-3 assume !(0 == ~E_12~0); 17703#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17379#L566-39 assume 1 == ~m_pc~0; 17380#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17982#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17694#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17695#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18237#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18238#L585-39 assume !(1 == ~t1_pc~0); 17387#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17388#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17463#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17464#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18270#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17963#L604-39 assume 1 == ~t2_pc~0; 17964#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17595#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17596#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18015#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18016#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17578#L623-39 assume 1 == ~t3_pc~0; 16976#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16978#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18254#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17430#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18202#L642-39 assume !(1 == ~t4_pc~0); 17777#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 17776#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17302#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17303#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18400#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17353#L661-39 assume !(1 == ~t5_pc~0); 16982#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16983#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18343#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18344#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18258#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18259#L680-39 assume 1 == ~t6_pc~0; 17046#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17047#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18187#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17510#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17511#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18525#L699-39 assume 1 == ~t7_pc~0; 17947#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17669#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17670#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18353#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18473#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18471#L718-39 assume 1 == ~t8_pc~0; 17861#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17862#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17794#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17795#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18096#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18066#L737-39 assume 1 == ~t9_pc~0; 17491#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17492#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18548#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18449#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18392#L756-39 assume !(1 == ~t10_pc~0); 17873#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17874#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17618#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17619#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17751#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17091#L775-39 assume 1 == ~t11_pc~0; 17092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17744#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17745#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18607#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18155#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17802#L794-39 assume 1 == ~t12_pc~0; 17494#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17488#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18308#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18209#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17033#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17034#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18501#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18502#L1312-3 assume !(1 == ~T2_E~0); 18613#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18225#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18226#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17170#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17141#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17142#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17890#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18013#L1352-3 assume !(1 == ~T10_E~0); 18014#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18454#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18606#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18597#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16967#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16968#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17602#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17603#L1392-3 assume !(1 == ~E_6~0); 18318#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18564#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17981#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17257#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17258#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17904#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17905#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17267#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17268#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18134#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17985#L1787 assume !(0 == start_simulation_~tmp~3#1); 17986#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18510#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17238#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18033#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 18034#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17585#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17586#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17587#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17137#L1768-2 [2021-11-23 12:40:20,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2021-11-23 12:40:20,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202051690] [2021-11-23 12:40:20,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202051690] [2021-11-23 12:40:20,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202051690] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,065 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,065 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,065 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989175568] [2021-11-23 12:40:20,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,067 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:20,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,070 INFO L85 PathProgramCache]: Analyzing trace with hash 673802017, now seen corresponding path program 1 times [2021-11-23 12:40:20,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091391685] [2021-11-23 12:40:20,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2091391685] [2021-11-23 12:40:20,126 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2091391685] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,126 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,127 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,127 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102735064] [2021-11-23 12:40:20,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,128 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:20,128 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:20,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:20,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:20,129 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:20,169 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2021-11-23 12:40:20,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:20,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2021-11-23 12:40:20,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-11-23 12:40:20,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:20,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:20,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2021-11-23 12:40:20,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:20,248 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-23 12:40:20,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2021-11-23 12:40:20,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:20,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-11-23 12:40:20,295 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-23 12:40:20,295 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-23 12:40:20,295 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-23 12:40:20,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2021-11-23 12:40:20,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:20,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:20,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,310 INFO L791 eck$LassoCheckResult]: Stem: 21116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 21117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21970#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21462#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21269#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21270#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21355#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21656#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21778#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21779#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20567#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20568#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21716#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21162#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21163#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21069#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21070#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21458#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20811#L1174 assume !(0 == ~M_E~0); 20812#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20663#L1179-1 assume !(0 == ~T2_E~0); 20565#L1184-1 assume !(0 == ~T3_E~0); 20566#L1189-1 assume !(0 == ~T4_E~0); 20604#L1194-1 assume !(0 == ~T5_E~0); 20704#L1199-1 assume !(0 == ~T6_E~0); 21599#L1204-1 assume !(0 == ~T7_E~0); 21518#L1209-1 assume !(0 == ~T8_E~0); 21519#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21907#L1219-1 assume !(0 == ~T10_E~0); 21992#L1224-1 assume !(0 == ~T11_E~0); 20929#L1229-1 assume !(0 == ~T12_E~0); 20490#L1234-1 assume !(0 == ~E_1~0); 20491#L1239-1 assume !(0 == ~E_2~0); 20524#L1244-1 assume !(0 == ~E_3~0); 20525#L1249-1 assume !(0 == ~E_4~0); 21186#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20420#L1259-1 assume !(0 == ~E_6~0); 20375#L1264-1 assume !(0 == ~E_7~0); 20376#L1269-1 assume !(0 == ~E_8~0); 21997#L1274-1 assume !(0 == ~E_9~0); 21932#L1279-1 assume !(0 == ~E_10~0); 20608#L1284-1 assume !(0 == ~E_11~0); 20609#L1289-1 assume !(0 == ~E_12~0); 21238#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21239#L566 assume 1 == ~m_pc~0; 20392#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20393#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21547#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21548#L1455 assume !(0 != activate_threads_~tmp~1#1); 20838#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20839#L585 assume 1 == ~t1_pc~0; 20487#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20488#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21488#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21489#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 21957#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21955#L604 assume !(1 == ~t2_pc~0); 21567#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21568#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21101#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21102#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21739#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21740#L623 assume 1 == ~t3_pc~0; 21016#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20356#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21166#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21167#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21774#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20389#L642 assume !(1 == ~t4_pc~0); 20390#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20855#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20856#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20461#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20462#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21579#L661 assume 1 == ~t5_pc~0; 20626#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20627#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20588#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20589#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21608#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21609#L680 assume !(1 == ~t6_pc~0); 21049#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21050#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21311#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21312#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 21840#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21953#L699 assume 1 == ~t7_pc~0; 21439#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21440#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20616#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20617#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21240#L718 assume !(1 == ~t8_pc~0); 21241#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20602#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20603#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20644#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20645#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20778#L737 assume 1 == ~t9_pc~0; 21643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20913#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21514#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21515#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21087#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21088#L756 assume 1 == ~t10_pc~0; 21667#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21333#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20319#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20320#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 20895#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20896#L775 assume !(1 == ~t11_pc~0); 21150#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21151#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20772#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20536#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20537#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20723#L794 assume 1 == ~t12_pc~0; 20563#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20541#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21734#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20689#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20690#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21169#L1307 assume !(1 == ~M_E~0); 21170#L1307-2 assume !(1 == ~T1_E~0); 21281#L1312-1 assume !(1 == ~T2_E~0); 21200#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21201#L1322-1 assume !(1 == ~T4_E~0); 20904#L1327-1 assume !(1 == ~T5_E~0); 20905#L1332-1 assume !(1 == ~T6_E~0); 21443#L1337-1 assume !(1 == ~T7_E~0); 21405#L1342-1 assume !(1 == ~T8_E~0); 21406#L1347-1 assume !(1 == ~T9_E~0); 21803#L1352-1 assume !(1 == ~T10_E~0); 21676#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21067#L1362-1 assume !(1 == ~T12_E~0); 21068#L1367-1 assume !(1 == ~E_1~0); 20705#L1372-1 assume !(1 == ~E_2~0); 20706#L1377-1 assume !(1 == ~E_3~0); 20999#L1382-1 assume !(1 == ~E_4~0); 21000#L1387-1 assume !(1 == ~E_5~0); 21569#L1392-1 assume !(1 == ~E_6~0); 21019#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21020#L1402-1 assume !(1 == ~E_8~0); 20716#L1407-1 assume !(1 == ~E_9~0); 20717#L1412-1 assume !(1 == ~E_10~0); 21732#L1417-1 assume !(1 == ~E_11~0); 21733#L1422-1 assume !(1 == ~E_12~0); 21951#L1427-1 assume { :end_inline_reset_delta_events } true; 20520#L1768-2 [2021-11-23 12:40:20,310 INFO L793 eck$LassoCheckResult]: Loop: 20520#L1768-2 assume !false; 20521#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21259#L1149 assume !false; 21631#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21784#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20910#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20816#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20817#L976 assume !(0 != eval_~tmp~0#1); 21950#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21960#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21751#L1174-3 assume !(0 == ~M_E~0); 21744#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21493#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21494#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21677#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21328#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20678#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20679#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20920#L1209-3 assume !(0 == ~T8_E~0); 20340#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20341#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21099#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21100#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21118#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20528#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20529#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20972#L1249-3 assume !(0 == ~E_4~0); 21431#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21903#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21545#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20534#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20535#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21930#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21097#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21098#L1289-3 assume !(0 == ~E_12~0); 21086#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20762#L566-39 assume 1 == ~m_pc~0; 20763#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21365#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21077#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21078#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21621#L585-39 assume !(1 == ~t1_pc~0); 20770#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20771#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20846#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20847#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21653#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21346#L604-39 assume 1 == ~t2_pc~0; 21347#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20978#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20979#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21396#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21397#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20961#L623-39 assume 1 == ~t3_pc~0; 20357#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20359#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21637#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20813#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20814#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21585#L642-39 assume 1 == ~t4_pc~0; 21156#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21157#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20685#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20686#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21783#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20734#L661-39 assume !(1 == ~t5_pc~0); 20365#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 20366#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21726#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21727#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21641#L680-39 assume 1 == ~t6_pc~0; 20427#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20428#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21570#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20893#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20894#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21908#L699-39 assume 1 == ~t7_pc~0; 21330#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21052#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21053#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21736#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21857#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21855#L718-39 assume 1 == ~t8_pc~0; 21244#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21245#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21177#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21178#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 21480#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21449#L737-39 assume 1 == ~t9_pc~0; 20874#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20875#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21164#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21931#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21832#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21775#L756-39 assume 1 == ~t10_pc~0; 21776#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21257#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21001#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21002#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21134#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20474#L775-39 assume 1 == ~t11_pc~0; 20475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21127#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21128#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21990#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21185#L794-39 assume !(1 == ~t12_pc~0); 20870#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 20871#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21691#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21592#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20416#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20417#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21884#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21885#L1312-3 assume !(1 == ~T2_E~0); 21996#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21610#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21611#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20555#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20526#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20527#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21273#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21398#L1352-3 assume !(1 == ~T10_E~0); 21399#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21838#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21989#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21980#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20353#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20354#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20985#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20986#L1392-3 assume !(1 == ~E_6~0); 21701#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21947#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21364#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20640#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20641#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21289#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21290#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20650#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20651#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21517#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 21369#L1787 assume !(0 == start_simulation_~tmp~3#1); 21370#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21893#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20621#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21416#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 21417#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20968#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20969#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20970#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20520#L1768-2 [2021-11-23 12:40:20,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,311 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2021-11-23 12:40:20,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055757280] [2021-11-23 12:40:20,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,349 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055757280] [2021-11-23 12:40:20,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055757280] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540026237] [2021-11-23 12:40:20,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,350 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:20,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1017478530, now seen corresponding path program 1 times [2021-11-23 12:40:20,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686377881] [2021-11-23 12:40:20,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686377881] [2021-11-23 12:40:20,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686377881] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734882725] [2021-11-23 12:40:20,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:20,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:20,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:20,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:20,403 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:20,444 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2021-11-23 12:40:20,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:20,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2021-11-23 12:40:20,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-11-23 12:40:20,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:20,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:20,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2021-11-23 12:40:20,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:20,481 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-23 12:40:20,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2021-11-23 12:40:20,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:20,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-11-23 12:40:20,529 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-23 12:40:20,529 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-23 12:40:20,529 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-23 12:40:20,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2021-11-23 12:40:20,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:20,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:20,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,542 INFO L791 eck$LassoCheckResult]: Stem: 24499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25353#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24845#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24652#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24653#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24738#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25039#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25161#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25162#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23951#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25099#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24545#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24546#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24452#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24453#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24841#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24194#L1174 assume !(0 == ~M_E~0); 24195#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24046#L1179-1 assume !(0 == ~T2_E~0); 23948#L1184-1 assume !(0 == ~T3_E~0); 23949#L1189-1 assume !(0 == ~T4_E~0); 23987#L1194-1 assume !(0 == ~T5_E~0); 24087#L1199-1 assume !(0 == ~T6_E~0); 24982#L1204-1 assume !(0 == ~T7_E~0); 24901#L1209-1 assume !(0 == ~T8_E~0); 24902#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25290#L1219-1 assume !(0 == ~T10_E~0); 25375#L1224-1 assume !(0 == ~T11_E~0); 24312#L1229-1 assume !(0 == ~T12_E~0); 23873#L1234-1 assume !(0 == ~E_1~0); 23874#L1239-1 assume !(0 == ~E_2~0); 23907#L1244-1 assume !(0 == ~E_3~0); 23908#L1249-1 assume !(0 == ~E_4~0); 24569#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23803#L1259-1 assume !(0 == ~E_6~0); 23758#L1264-1 assume !(0 == ~E_7~0); 23759#L1269-1 assume !(0 == ~E_8~0); 25380#L1274-1 assume !(0 == ~E_9~0); 25315#L1279-1 assume !(0 == ~E_10~0); 23991#L1284-1 assume !(0 == ~E_11~0); 23992#L1289-1 assume !(0 == ~E_12~0); 24621#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L566 assume 1 == ~m_pc~0; 23775#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23776#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24930#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24931#L1455 assume !(0 != activate_threads_~tmp~1#1); 24221#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24222#L585 assume 1 == ~t1_pc~0; 23870#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23871#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24872#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25340#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25338#L604 assume !(1 == ~t2_pc~0); 24950#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24951#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24484#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24485#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25122#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25123#L623 assume 1 == ~t3_pc~0; 24399#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23739#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24549#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24550#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23772#L642 assume !(1 == ~t4_pc~0); 23773#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24238#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24239#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23844#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23845#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24962#L661 assume 1 == ~t5_pc~0; 24009#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24010#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23971#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23972#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24991#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24992#L680 assume !(1 == ~t6_pc~0); 24432#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24433#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24694#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24695#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25223#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25336#L699 assume 1 == ~t7_pc~0; 24822#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24823#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23999#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24000#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24724#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24623#L718 assume !(1 == ~t8_pc~0); 24624#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23985#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23986#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24027#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24028#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24161#L737 assume 1 == ~t9_pc~0; 25026#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24296#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24897#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24898#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24470#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24471#L756 assume 1 == ~t10_pc~0; 25050#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24716#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23702#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23703#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24278#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24279#L775 assume !(1 == ~t11_pc~0); 24533#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24534#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24155#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23919#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23920#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24106#L794 assume 1 == ~t12_pc~0; 23946#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23924#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25117#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24072#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24073#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24552#L1307 assume !(1 == ~M_E~0); 24553#L1307-2 assume !(1 == ~T1_E~0); 24664#L1312-1 assume !(1 == ~T2_E~0); 24583#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24584#L1322-1 assume !(1 == ~T4_E~0); 24287#L1327-1 assume !(1 == ~T5_E~0); 24288#L1332-1 assume !(1 == ~T6_E~0); 24826#L1337-1 assume !(1 == ~T7_E~0); 24788#L1342-1 assume !(1 == ~T8_E~0); 24789#L1347-1 assume !(1 == ~T9_E~0); 25186#L1352-1 assume !(1 == ~T10_E~0); 25059#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24450#L1362-1 assume !(1 == ~T12_E~0); 24451#L1367-1 assume !(1 == ~E_1~0); 24088#L1372-1 assume !(1 == ~E_2~0); 24089#L1377-1 assume !(1 == ~E_3~0); 24382#L1382-1 assume !(1 == ~E_4~0); 24383#L1387-1 assume !(1 == ~E_5~0); 24952#L1392-1 assume !(1 == ~E_6~0); 24402#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24403#L1402-1 assume !(1 == ~E_8~0); 24099#L1407-1 assume !(1 == ~E_9~0); 24100#L1412-1 assume !(1 == ~E_10~0); 25115#L1417-1 assume !(1 == ~E_11~0); 25116#L1422-1 assume !(1 == ~E_12~0); 25334#L1427-1 assume { :end_inline_reset_delta_events } true; 23903#L1768-2 [2021-11-23 12:40:20,542 INFO L793 eck$LassoCheckResult]: Loop: 23903#L1768-2 assume !false; 23904#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24642#L1149 assume !false; 25014#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25167#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24293#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24199#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24200#L976 assume !(0 != eval_~tmp~0#1); 25333#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25343#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25134#L1174-3 assume !(0 == ~M_E~0); 25127#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24876#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24877#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25060#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24711#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24061#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24062#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24303#L1209-3 assume !(0 == ~T8_E~0); 23723#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23724#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24482#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24483#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24501#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23911#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23912#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24355#L1249-3 assume !(0 == ~E_4~0); 24814#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25286#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24928#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23917#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23918#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25313#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24480#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24481#L1289-3 assume !(0 == ~E_12~0); 24469#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24145#L566-39 assume 1 == ~m_pc~0; 24146#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24748#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24460#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24461#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25003#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25004#L585-39 assume !(1 == ~t1_pc~0); 24153#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24154#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24229#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24230#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25036#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24729#L604-39 assume 1 == ~t2_pc~0; 24730#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24361#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24362#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24779#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24780#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24344#L623-39 assume 1 == ~t3_pc~0; 23740#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23742#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25020#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24196#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24197#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24968#L642-39 assume 1 == ~t4_pc~0; 24539#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24540#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24068#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24069#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25166#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24117#L661-39 assume !(1 == ~t5_pc~0); 23748#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23749#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25109#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25110#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25023#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25024#L680-39 assume 1 == ~t6_pc~0; 23810#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23811#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24953#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24276#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24277#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25291#L699-39 assume 1 == ~t7_pc~0; 24713#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24435#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24436#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25119#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25240#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25238#L718-39 assume 1 == ~t8_pc~0; 24627#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24628#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24560#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24561#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24863#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24832#L737-39 assume 1 == ~t9_pc~0; 24257#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24258#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25314#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25215#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25158#L756-39 assume 1 == ~t10_pc~0; 25159#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24640#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24384#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24385#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24517#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23857#L775-39 assume 1 == ~t11_pc~0; 23858#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24510#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24511#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25373#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24921#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24568#L794-39 assume 1 == ~t12_pc~0; 24260#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24254#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25074#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24975#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23799#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23800#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25268#L1312-3 assume !(1 == ~T2_E~0); 25379#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24993#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24994#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23938#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23909#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23910#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24656#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24781#L1352-3 assume !(1 == ~T10_E~0); 24782#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25221#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25372#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25363#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23736#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23737#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24368#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24369#L1392-3 assume !(1 == ~E_6~0); 25084#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25330#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24747#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24023#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24024#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24672#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24673#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24033#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24034#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24900#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24752#L1787 assume !(0 == start_simulation_~tmp~3#1); 24753#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25276#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24799#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 24800#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24351#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24352#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 24353#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23903#L1768-2 [2021-11-23 12:40:20,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2021-11-23 12:40:20,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408804019] [2021-11-23 12:40:20,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,544 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,586 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408804019] [2021-11-23 12:40:20,586 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408804019] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,588 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879428988] [2021-11-23 12:40:20,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:20,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,589 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 1 times [2021-11-23 12:40:20,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787612937] [2021-11-23 12:40:20,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787612937] [2021-11-23 12:40:20,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787612937] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,660 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,660 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412661315] [2021-11-23 12:40:20,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,661 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:20,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:20,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:20,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:20,662 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:20,705 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2021-11-23 12:40:20,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:20,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2021-11-23 12:40:20,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-11-23 12:40:20,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:20,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:20,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2021-11-23 12:40:20,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:20,740 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-23 12:40:20,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2021-11-23 12:40:20,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:20,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-11-23 12:40:20,780 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-23 12:40:20,780 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-23 12:40:20,780 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-23 12:40:20,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2021-11-23 12:40:20,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:20,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:20,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:20,791 INFO L791 eck$LassoCheckResult]: Stem: 27882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28736#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28228#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28035#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28036#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28121#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28422#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28544#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28545#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27333#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27334#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28482#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27928#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27929#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27835#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27836#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28224#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27577#L1174 assume !(0 == ~M_E~0); 27578#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27429#L1179-1 assume !(0 == ~T2_E~0); 27331#L1184-1 assume !(0 == ~T3_E~0); 27332#L1189-1 assume !(0 == ~T4_E~0); 27370#L1194-1 assume !(0 == ~T5_E~0); 27470#L1199-1 assume !(0 == ~T6_E~0); 28365#L1204-1 assume !(0 == ~T7_E~0); 28284#L1209-1 assume !(0 == ~T8_E~0); 28285#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28673#L1219-1 assume !(0 == ~T10_E~0); 28758#L1224-1 assume !(0 == ~T11_E~0); 27695#L1229-1 assume !(0 == ~T12_E~0); 27256#L1234-1 assume !(0 == ~E_1~0); 27257#L1239-1 assume !(0 == ~E_2~0); 27290#L1244-1 assume !(0 == ~E_3~0); 27291#L1249-1 assume !(0 == ~E_4~0); 27952#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27186#L1259-1 assume !(0 == ~E_6~0); 27141#L1264-1 assume !(0 == ~E_7~0); 27142#L1269-1 assume !(0 == ~E_8~0); 28763#L1274-1 assume !(0 == ~E_9~0); 28698#L1279-1 assume !(0 == ~E_10~0); 27374#L1284-1 assume !(0 == ~E_11~0); 27375#L1289-1 assume !(0 == ~E_12~0); 28004#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28005#L566 assume 1 == ~m_pc~0; 27158#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27159#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28313#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28314#L1455 assume !(0 != activate_threads_~tmp~1#1); 27604#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27605#L585 assume 1 == ~t1_pc~0; 27253#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27254#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28254#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28255#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28723#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28721#L604 assume !(1 == ~t2_pc~0); 28333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27867#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27868#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28505#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28506#L623 assume 1 == ~t3_pc~0; 27782#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27122#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27932#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27933#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28540#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27155#L642 assume !(1 == ~t4_pc~0); 27156#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27621#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27622#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27227#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27228#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28345#L661 assume 1 == ~t5_pc~0; 27392#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27393#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27354#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27355#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28375#L680 assume !(1 == ~t6_pc~0); 27815#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27816#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28077#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28078#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28606#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28719#L699 assume 1 == ~t7_pc~0; 28205#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28206#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27382#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27383#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28107#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28006#L718 assume !(1 == ~t8_pc~0); 28007#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27368#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27369#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27410#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27411#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27544#L737 assume 1 == ~t9_pc~0; 28409#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27679#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28280#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28281#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 27853#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27854#L756 assume 1 == ~t10_pc~0; 28433#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28099#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27085#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27086#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27661#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27662#L775 assume !(1 == ~t11_pc~0); 27916#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27917#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27538#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27302#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27303#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27489#L794 assume 1 == ~t12_pc~0; 27329#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27307#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28500#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27455#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27456#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27935#L1307 assume !(1 == ~M_E~0); 27936#L1307-2 assume !(1 == ~T1_E~0); 28047#L1312-1 assume !(1 == ~T2_E~0); 27966#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27967#L1322-1 assume !(1 == ~T4_E~0); 27670#L1327-1 assume !(1 == ~T5_E~0); 27671#L1332-1 assume !(1 == ~T6_E~0); 28209#L1337-1 assume !(1 == ~T7_E~0); 28171#L1342-1 assume !(1 == ~T8_E~0); 28172#L1347-1 assume !(1 == ~T9_E~0); 28569#L1352-1 assume !(1 == ~T10_E~0); 28442#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27833#L1362-1 assume !(1 == ~T12_E~0); 27834#L1367-1 assume !(1 == ~E_1~0); 27471#L1372-1 assume !(1 == ~E_2~0); 27472#L1377-1 assume !(1 == ~E_3~0); 27765#L1382-1 assume !(1 == ~E_4~0); 27766#L1387-1 assume !(1 == ~E_5~0); 28335#L1392-1 assume !(1 == ~E_6~0); 27785#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27786#L1402-1 assume !(1 == ~E_8~0); 27482#L1407-1 assume !(1 == ~E_9~0); 27483#L1412-1 assume !(1 == ~E_10~0); 28498#L1417-1 assume !(1 == ~E_11~0); 28499#L1422-1 assume !(1 == ~E_12~0); 28717#L1427-1 assume { :end_inline_reset_delta_events } true; 27286#L1768-2 [2021-11-23 12:40:20,792 INFO L793 eck$LassoCheckResult]: Loop: 27286#L1768-2 assume !false; 27287#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28025#L1149 assume !false; 28397#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28550#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27676#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27582#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27583#L976 assume !(0 != eval_~tmp~0#1); 28716#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28726#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28517#L1174-3 assume !(0 == ~M_E~0); 28510#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28259#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28260#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28443#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28094#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27444#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27445#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27686#L1209-3 assume !(0 == ~T8_E~0); 27106#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27107#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27865#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27866#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27884#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27294#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27295#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27738#L1249-3 assume !(0 == ~E_4~0); 28197#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28669#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28311#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27300#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27301#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28696#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27863#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27864#L1289-3 assume !(0 == ~E_12~0); 27852#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27528#L566-39 assume 1 == ~m_pc~0; 27529#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28131#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27843#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27844#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28386#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28387#L585-39 assume !(1 == ~t1_pc~0); 27536#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 27537#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27612#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27613#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28419#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28112#L604-39 assume 1 == ~t2_pc~0; 28113#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27744#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27745#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28162#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28163#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27727#L623-39 assume 1 == ~t3_pc~0; 27123#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27125#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28403#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27579#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27580#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28351#L642-39 assume 1 == ~t4_pc~0; 27922#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27923#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27451#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27452#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28549#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27500#L661-39 assume !(1 == ~t5_pc~0); 27131#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 27132#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28492#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28493#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28406#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28407#L680-39 assume 1 == ~t6_pc~0; 27193#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27194#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28336#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27659#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27660#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28674#L699-39 assume 1 == ~t7_pc~0; 28096#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27818#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27819#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28502#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28623#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28621#L718-39 assume 1 == ~t8_pc~0; 28010#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28011#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27943#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27944#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 28246#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28215#L737-39 assume 1 == ~t9_pc~0; 27640#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27641#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27930#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28697#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28598#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28541#L756-39 assume !(1 == ~t10_pc~0); 28022#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28023#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27768#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27900#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27240#L775-39 assume 1 == ~t11_pc~0; 27241#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27893#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27894#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28756#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28304#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27951#L794-39 assume !(1 == ~t12_pc~0); 27636#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27637#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28457#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28358#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27182#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27183#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28650#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28651#L1312-3 assume !(1 == ~T2_E~0); 28762#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28376#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28377#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27321#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27292#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27293#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28039#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28164#L1352-3 assume !(1 == ~T10_E~0); 28165#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28604#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28755#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28746#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27119#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27120#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27751#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27752#L1392-3 assume !(1 == ~E_6~0); 28467#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28713#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28130#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27406#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27407#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28055#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28056#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27416#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27417#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28283#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28135#L1787 assume !(0 == start_simulation_~tmp~3#1); 28136#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28659#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27387#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28182#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28183#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27734#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27735#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 27736#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27286#L1768-2 [2021-11-23 12:40:20,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,792 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2021-11-23 12:40:20,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469134320] [2021-11-23 12:40:20,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469134320] [2021-11-23 12:40:20,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469134320] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,824 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,824 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,824 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788832538] [2021-11-23 12:40:20,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,825 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:20,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:20,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 1 times [2021-11-23 12:40:20,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:20,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599354462] [2021-11-23 12:40:20,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:20,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:20,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:20,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:20,868 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:20,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599354462] [2021-11-23 12:40:20,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599354462] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:20,869 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:20,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:20,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809497783] [2021-11-23 12:40:20,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:20,870 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:20,870 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:20,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:20,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:20,870 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:20,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:20,938 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2021-11-23 12:40:20,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:20,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2021-11-23 12:40:20,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:20,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-11-23 12:40:20,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:20,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:20,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2021-11-23 12:40:20,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:20,974 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-23 12:40:20,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2021-11-23 12:40:20,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:21,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-11-23 12:40:21,009 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-23 12:40:21,009 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-23 12:40:21,009 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-23 12:40:21,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2021-11-23 12:40:21,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:21,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:21,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,019 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,019 INFO L791 eck$LassoCheckResult]: Stem: 31265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 31266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32119#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31611#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31418#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31419#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31504#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31805#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31927#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31928#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30716#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30717#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31865#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31311#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31312#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31218#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31219#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31607#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30960#L1174 assume !(0 == ~M_E~0); 30961#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30812#L1179-1 assume !(0 == ~T2_E~0); 30714#L1184-1 assume !(0 == ~T3_E~0); 30715#L1189-1 assume !(0 == ~T4_E~0); 30753#L1194-1 assume !(0 == ~T5_E~0); 30853#L1199-1 assume !(0 == ~T6_E~0); 31748#L1204-1 assume !(0 == ~T7_E~0); 31667#L1209-1 assume !(0 == ~T8_E~0); 31668#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32056#L1219-1 assume !(0 == ~T10_E~0); 32141#L1224-1 assume !(0 == ~T11_E~0); 31078#L1229-1 assume !(0 == ~T12_E~0); 30639#L1234-1 assume !(0 == ~E_1~0); 30640#L1239-1 assume !(0 == ~E_2~0); 30673#L1244-1 assume !(0 == ~E_3~0); 30674#L1249-1 assume !(0 == ~E_4~0); 31335#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30569#L1259-1 assume !(0 == ~E_6~0); 30524#L1264-1 assume !(0 == ~E_7~0); 30525#L1269-1 assume !(0 == ~E_8~0); 32146#L1274-1 assume !(0 == ~E_9~0); 32081#L1279-1 assume !(0 == ~E_10~0); 30757#L1284-1 assume !(0 == ~E_11~0); 30758#L1289-1 assume !(0 == ~E_12~0); 31387#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31388#L566 assume 1 == ~m_pc~0; 30541#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30542#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31696#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31697#L1455 assume !(0 != activate_threads_~tmp~1#1); 30987#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30988#L585 assume 1 == ~t1_pc~0; 30636#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30637#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31637#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31638#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32106#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32104#L604 assume !(1 == ~t2_pc~0); 31716#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31717#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31250#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31251#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31888#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31889#L623 assume 1 == ~t3_pc~0; 31165#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30505#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31315#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31316#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31923#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30538#L642 assume !(1 == ~t4_pc~0); 30539#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31004#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31005#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30610#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30611#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31728#L661 assume 1 == ~t5_pc~0; 30775#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30776#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30737#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30738#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31757#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31758#L680 assume !(1 == ~t6_pc~0); 31198#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31199#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31460#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31461#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31989#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32102#L699 assume 1 == ~t7_pc~0; 31588#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31589#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30765#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30766#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31490#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31389#L718 assume !(1 == ~t8_pc~0); 31390#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30751#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30752#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30793#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30794#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30927#L737 assume 1 == ~t9_pc~0; 31792#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31062#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31663#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31664#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31236#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31237#L756 assume 1 == ~t10_pc~0; 31816#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31482#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30468#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30469#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31044#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31045#L775 assume !(1 == ~t11_pc~0); 31299#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31300#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30921#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30685#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30686#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30872#L794 assume 1 == ~t12_pc~0; 30712#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30690#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31883#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30838#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30839#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31318#L1307 assume !(1 == ~M_E~0); 31319#L1307-2 assume !(1 == ~T1_E~0); 31430#L1312-1 assume !(1 == ~T2_E~0); 31349#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31350#L1322-1 assume !(1 == ~T4_E~0); 31053#L1327-1 assume !(1 == ~T5_E~0); 31054#L1332-1 assume !(1 == ~T6_E~0); 31592#L1337-1 assume !(1 == ~T7_E~0); 31554#L1342-1 assume !(1 == ~T8_E~0); 31555#L1347-1 assume !(1 == ~T9_E~0); 31952#L1352-1 assume !(1 == ~T10_E~0); 31825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31216#L1362-1 assume !(1 == ~T12_E~0); 31217#L1367-1 assume !(1 == ~E_1~0); 30854#L1372-1 assume !(1 == ~E_2~0); 30855#L1377-1 assume !(1 == ~E_3~0); 31148#L1382-1 assume !(1 == ~E_4~0); 31149#L1387-1 assume !(1 == ~E_5~0); 31718#L1392-1 assume !(1 == ~E_6~0); 31168#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31169#L1402-1 assume !(1 == ~E_8~0); 30865#L1407-1 assume !(1 == ~E_9~0); 30866#L1412-1 assume !(1 == ~E_10~0); 31881#L1417-1 assume !(1 == ~E_11~0); 31882#L1422-1 assume !(1 == ~E_12~0); 32100#L1427-1 assume { :end_inline_reset_delta_events } true; 30669#L1768-2 [2021-11-23 12:40:21,020 INFO L793 eck$LassoCheckResult]: Loop: 30669#L1768-2 assume !false; 30670#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31408#L1149 assume !false; 31780#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31933#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31059#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30965#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30966#L976 assume !(0 != eval_~tmp~0#1); 32099#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32109#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31900#L1174-3 assume !(0 == ~M_E~0); 31893#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31642#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31643#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31477#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30827#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30828#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31069#L1209-3 assume !(0 == ~T8_E~0); 30489#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30490#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31248#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31249#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31267#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30677#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30678#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31121#L1249-3 assume !(0 == ~E_4~0); 31580#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32052#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31694#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30683#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30684#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32079#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31247#L1289-3 assume !(0 == ~E_12~0); 31235#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30911#L566-39 assume 1 == ~m_pc~0; 30912#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31514#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31226#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31227#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31769#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31770#L585-39 assume !(1 == ~t1_pc~0); 30919#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30920#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30995#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30996#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31802#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31495#L604-39 assume 1 == ~t2_pc~0; 31496#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31127#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31128#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31545#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31546#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31110#L623-39 assume 1 == ~t3_pc~0; 30506#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30508#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31786#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30962#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30963#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31734#L642-39 assume 1 == ~t4_pc~0; 31305#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31306#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30834#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30835#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31932#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30883#L661-39 assume !(1 == ~t5_pc~0); 30514#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 30515#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31875#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31876#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31789#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31790#L680-39 assume 1 == ~t6_pc~0; 30576#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30577#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31719#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31042#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31043#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32057#L699-39 assume 1 == ~t7_pc~0; 31479#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31201#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31202#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31885#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32006#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32004#L718-39 assume 1 == ~t8_pc~0; 31393#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31394#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31326#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31327#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31629#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31598#L737-39 assume !(1 == ~t9_pc~0); 31025#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31024#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31313#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32080#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31981#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31924#L756-39 assume 1 == ~t10_pc~0; 31925#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31406#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31150#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31151#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31283#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30623#L775-39 assume 1 == ~t11_pc~0; 30624#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31276#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31277#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32139#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31687#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L794-39 assume 1 == ~t12_pc~0; 31026#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31020#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31840#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31741#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30565#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30566#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32033#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32034#L1312-3 assume !(1 == ~T2_E~0); 32145#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31759#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31760#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30704#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30675#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30676#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31422#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31547#L1352-3 assume !(1 == ~T10_E~0); 31548#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31987#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32138#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32129#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30502#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30503#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31134#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31135#L1392-3 assume !(1 == ~E_6~0); 31850#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32096#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31513#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30789#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30790#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31438#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31439#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30799#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30800#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31666#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31518#L1787 assume !(0 == start_simulation_~tmp~3#1); 31519#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32042#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30770#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31565#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31566#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31117#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31118#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 31119#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30669#L1768-2 [2021-11-23 12:40:21,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2021-11-23 12:40:21,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349096016] [2021-11-23 12:40:21,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,021 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,055 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349096016] [2021-11-23 12:40:21,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349096016] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,056 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,056 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,056 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426290852] [2021-11-23 12:40:21,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,058 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:21,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,058 INFO L85 PathProgramCache]: Analyzing trace with hash -182660158, now seen corresponding path program 1 times [2021-11-23 12:40:21,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035681478] [2021-11-23 12:40:21,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,118 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1035681478] [2021-11-23 12:40:21,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1035681478] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,118 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,119 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797076877] [2021-11-23 12:40:21,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,119 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:21,119 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:21,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:21,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:21,121 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:21,156 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2021-11-23 12:40:21,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:21,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2021-11-23 12:40:21,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-11-23 12:40:21,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:21,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:21,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2021-11-23 12:40:21,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:21,184 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-23 12:40:21,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2021-11-23 12:40:21,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:21,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-11-23 12:40:21,226 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-23 12:40:21,226 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-23 12:40:21,226 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-23 12:40:21,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2021-11-23 12:40:21,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:21,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:21,236 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,236 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,236 INFO L791 eck$LassoCheckResult]: Stem: 34648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35502#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34996#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34801#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 34802#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34887#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35189#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35310#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35311#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34099#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34100#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35248#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34694#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34695#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34601#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34602#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34991#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34343#L1174 assume !(0 == ~M_E~0); 34344#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34195#L1179-1 assume !(0 == ~T2_E~0); 34097#L1184-1 assume !(0 == ~T3_E~0); 34098#L1189-1 assume !(0 == ~T4_E~0); 34136#L1194-1 assume !(0 == ~T5_E~0); 34236#L1199-1 assume !(0 == ~T6_E~0); 35131#L1204-1 assume !(0 == ~T7_E~0); 35050#L1209-1 assume !(0 == ~T8_E~0); 35051#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35439#L1219-1 assume !(0 == ~T10_E~0); 35524#L1224-1 assume !(0 == ~T11_E~0); 34462#L1229-1 assume !(0 == ~T12_E~0); 34024#L1234-1 assume !(0 == ~E_1~0); 34025#L1239-1 assume !(0 == ~E_2~0); 34058#L1244-1 assume !(0 == ~E_3~0); 34059#L1249-1 assume !(0 == ~E_4~0); 34718#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33952#L1259-1 assume !(0 == ~E_6~0); 33907#L1264-1 assume !(0 == ~E_7~0); 33908#L1269-1 assume !(0 == ~E_8~0); 35529#L1274-1 assume !(0 == ~E_9~0); 35464#L1279-1 assume !(0 == ~E_10~0); 34140#L1284-1 assume !(0 == ~E_11~0); 34141#L1289-1 assume !(0 == ~E_12~0); 34770#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34771#L566 assume 1 == ~m_pc~0; 33924#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33925#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35079#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35080#L1455 assume !(0 != activate_threads_~tmp~1#1); 34370#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34371#L585 assume 1 == ~t1_pc~0; 34019#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34020#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35020#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35021#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35489#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35487#L604 assume !(1 == ~t2_pc~0); 35099#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35100#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34633#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34634#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35273#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35274#L623 assume 1 == ~t3_pc~0; 34548#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33888#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34698#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34699#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35306#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33921#L642 assume !(1 == ~t4_pc~0); 33922#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34387#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34388#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33995#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 33996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35111#L661 assume 1 == ~t5_pc~0; 34158#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34159#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34120#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34121#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35142#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35143#L680 assume !(1 == ~t6_pc~0); 34581#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34582#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34844#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35372#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35485#L699 assume 1 == ~t7_pc~0; 34971#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34972#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34148#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34149#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 34873#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34772#L718 assume !(1 == ~t8_pc~0); 34773#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34134#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34135#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34176#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34177#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34310#L737 assume 1 == ~t9_pc~0; 35176#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34445#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35046#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35047#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34619#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34620#L756 assume 1 == ~t10_pc~0; 35199#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34865#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33851#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33852#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34427#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34428#L775 assume !(1 == ~t11_pc~0); 34682#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34683#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34304#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34068#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34069#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34255#L794 assume 1 == ~t12_pc~0; 34096#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34073#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35266#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34223#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34224#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34701#L1307 assume !(1 == ~M_E~0); 34702#L1307-2 assume !(1 == ~T1_E~0); 34813#L1312-1 assume !(1 == ~T2_E~0); 34732#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34733#L1322-1 assume !(1 == ~T4_E~0); 34436#L1327-1 assume !(1 == ~T5_E~0); 34437#L1332-1 assume !(1 == ~T6_E~0); 34975#L1337-1 assume !(1 == ~T7_E~0); 34937#L1342-1 assume !(1 == ~T8_E~0); 34938#L1347-1 assume !(1 == ~T9_E~0); 35335#L1352-1 assume !(1 == ~T10_E~0); 35208#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34599#L1362-1 assume !(1 == ~T12_E~0); 34600#L1367-1 assume !(1 == ~E_1~0); 34237#L1372-1 assume !(1 == ~E_2~0); 34238#L1377-1 assume !(1 == ~E_3~0); 34531#L1382-1 assume !(1 == ~E_4~0); 34532#L1387-1 assume !(1 == ~E_5~0); 35101#L1392-1 assume !(1 == ~E_6~0); 34553#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34554#L1402-1 assume !(1 == ~E_8~0); 34250#L1407-1 assume !(1 == ~E_9~0); 34251#L1412-1 assume !(1 == ~E_10~0); 35264#L1417-1 assume !(1 == ~E_11~0); 35265#L1422-1 assume !(1 == ~E_12~0); 35483#L1427-1 assume { :end_inline_reset_delta_events } true; 34052#L1768-2 [2021-11-23 12:40:21,237 INFO L793 eck$LassoCheckResult]: Loop: 34052#L1768-2 assume !false; 34053#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34793#L1149 assume !false; 35164#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35316#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34442#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34354#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34355#L976 assume !(0 != eval_~tmp~0#1); 35482#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35492#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35283#L1174-3 assume !(0 == ~M_E~0); 35276#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35025#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35026#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35210#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34860#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34213#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34214#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34452#L1209-3 assume !(0 == ~T8_E~0); 33872#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33873#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34631#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34632#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34650#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34060#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34061#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34504#L1249-3 assume !(0 == ~E_4~0); 34963#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35435#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35077#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34066#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34067#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35462#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34629#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34630#L1289-3 assume !(0 == ~E_12~0); 34618#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34294#L566-39 assume 1 == ~m_pc~0; 34295#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34897#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34609#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34610#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35152#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35153#L585-39 assume !(1 == ~t1_pc~0); 34301#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34302#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34378#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34379#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35185#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34877#L604-39 assume 1 == ~t2_pc~0; 34878#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34510#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34511#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34928#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34929#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34493#L623-39 assume 1 == ~t3_pc~0; 33889#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33891#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35169#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34345#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34346#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35117#L642-39 assume 1 == ~t4_pc~0; 34688#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34689#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34217#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34218#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35315#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34264#L661-39 assume !(1 == ~t5_pc~0); 33897#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 33898#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35258#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35259#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35172#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35173#L680-39 assume 1 == ~t6_pc~0; 33959#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33960#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35102#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34425#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34426#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35440#L699-39 assume 1 == ~t7_pc~0; 34862#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34584#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34585#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35268#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35389#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35387#L718-39 assume 1 == ~t8_pc~0; 34776#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34777#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34709#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34710#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 35011#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34981#L737-39 assume 1 == ~t9_pc~0; 34406#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34407#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34696#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35463#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35364#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35307#L756-39 assume !(1 == ~t10_pc~0); 34788#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 34789#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34533#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34534#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34666#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34006#L775-39 assume 1 == ~t11_pc~0; 34007#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34659#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34660#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35522#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35070#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34717#L794-39 assume !(1 == ~t12_pc~0); 34402#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 34403#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35223#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35124#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33948#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35416#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35417#L1312-3 assume !(1 == ~T2_E~0); 35528#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35140#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35141#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34087#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34056#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34057#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34805#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34930#L1352-3 assume !(1 == ~T10_E~0); 34931#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35370#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35521#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35512#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33882#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33883#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34517#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34518#L1392-3 assume !(1 == ~E_6~0); 35233#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35479#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34896#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34172#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34173#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 34819#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34820#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34182#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34183#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35049#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34900#L1787 assume !(0 == start_simulation_~tmp~3#1); 34901#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35425#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34153#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34948#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34949#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34500#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34501#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 34502#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34052#L1768-2 [2021-11-23 12:40:21,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,238 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2021-11-23 12:40:21,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402855164] [2021-11-23 12:40:21,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,239 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402855164] [2021-11-23 12:40:21,277 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402855164] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,277 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,277 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299259468] [2021-11-23 12:40:21,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,278 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:21,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 2 times [2021-11-23 12:40:21,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822604303] [2021-11-23 12:40:21,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822604303] [2021-11-23 12:40:21,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822604303] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,326 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728942359] [2021-11-23 12:40:21,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,327 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:21,328 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:21,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:21,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:21,329 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:21,366 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2021-11-23 12:40:21,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:21,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2021-11-23 12:40:21,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-11-23 12:40:21,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:21,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:21,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2021-11-23 12:40:21,404 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:21,405 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-23 12:40:21,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2021-11-23 12:40:21,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:21,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-11-23 12:40:21,460 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-23 12:40:21,460 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-23 12:40:21,460 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-23 12:40:21,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2021-11-23 12:40:21,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:21,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:21,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,472 INFO L791 eck$LassoCheckResult]: Stem: 38031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 38032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38885#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38379#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38184#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38185#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38270#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38571#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38693#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38694#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37482#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37483#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38631#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38077#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38078#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37984#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37985#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38374#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37726#L1174 assume !(0 == ~M_E~0); 37727#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37578#L1179-1 assume !(0 == ~T2_E~0); 37480#L1184-1 assume !(0 == ~T3_E~0); 37481#L1189-1 assume !(0 == ~T4_E~0); 37519#L1194-1 assume !(0 == ~T5_E~0); 37619#L1199-1 assume !(0 == ~T6_E~0); 38514#L1204-1 assume !(0 == ~T7_E~0); 38433#L1209-1 assume !(0 == ~T8_E~0); 38434#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38822#L1219-1 assume !(0 == ~T10_E~0); 38907#L1224-1 assume !(0 == ~T11_E~0); 37844#L1229-1 assume !(0 == ~T12_E~0); 37405#L1234-1 assume !(0 == ~E_1~0); 37406#L1239-1 assume !(0 == ~E_2~0); 37441#L1244-1 assume !(0 == ~E_3~0); 37442#L1249-1 assume !(0 == ~E_4~0); 38101#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37335#L1259-1 assume !(0 == ~E_6~0); 37290#L1264-1 assume !(0 == ~E_7~0); 37291#L1269-1 assume !(0 == ~E_8~0); 38912#L1274-1 assume !(0 == ~E_9~0); 38847#L1279-1 assume !(0 == ~E_10~0); 37523#L1284-1 assume !(0 == ~E_11~0); 37524#L1289-1 assume !(0 == ~E_12~0); 38153#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38154#L566 assume 1 == ~m_pc~0; 37307#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37308#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38462#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38463#L1455 assume !(0 != activate_threads_~tmp~1#1); 37753#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37754#L585 assume 1 == ~t1_pc~0; 37402#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37403#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38403#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38404#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38872#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38870#L604 assume !(1 == ~t2_pc~0); 38482#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38483#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38016#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38017#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38654#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38655#L623 assume 1 == ~t3_pc~0; 37931#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37271#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38081#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38082#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38689#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37304#L642 assume !(1 == ~t4_pc~0); 37305#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37770#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37771#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37377#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38494#L661 assume 1 == ~t5_pc~0; 37541#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37542#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37503#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37504#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38525#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38526#L680 assume !(1 == ~t6_pc~0); 37964#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37965#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38226#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38227#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38755#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38868#L699 assume 1 == ~t7_pc~0; 38354#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38355#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37531#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37532#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38256#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38155#L718 assume !(1 == ~t8_pc~0); 38156#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37517#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37518#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37559#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37560#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37693#L737 assume 1 == ~t9_pc~0; 38558#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37828#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38429#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38430#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38002#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38003#L756 assume 1 == ~t10_pc~0; 38582#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37234#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37235#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37810#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37811#L775 assume !(1 == ~t11_pc~0); 38065#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38066#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37687#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37451#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37452#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37638#L794 assume 1 == ~t12_pc~0; 37479#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37456#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38649#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37604#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37605#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38084#L1307 assume !(1 == ~M_E~0); 38085#L1307-2 assume !(1 == ~T1_E~0); 38196#L1312-1 assume !(1 == ~T2_E~0); 38115#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38116#L1322-1 assume !(1 == ~T4_E~0); 37819#L1327-1 assume !(1 == ~T5_E~0); 37820#L1332-1 assume !(1 == ~T6_E~0); 38358#L1337-1 assume !(1 == ~T7_E~0); 38320#L1342-1 assume !(1 == ~T8_E~0); 38321#L1347-1 assume !(1 == ~T9_E~0); 38718#L1352-1 assume !(1 == ~T10_E~0); 38591#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37982#L1362-1 assume !(1 == ~T12_E~0); 37983#L1367-1 assume !(1 == ~E_1~0); 37620#L1372-1 assume !(1 == ~E_2~0); 37621#L1377-1 assume !(1 == ~E_3~0); 37914#L1382-1 assume !(1 == ~E_4~0); 37915#L1387-1 assume !(1 == ~E_5~0); 38484#L1392-1 assume !(1 == ~E_6~0); 37934#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37935#L1402-1 assume !(1 == ~E_8~0); 37631#L1407-1 assume !(1 == ~E_9~0); 37632#L1412-1 assume !(1 == ~E_10~0); 38647#L1417-1 assume !(1 == ~E_11~0); 38648#L1422-1 assume !(1 == ~E_12~0); 38866#L1427-1 assume { :end_inline_reset_delta_events } true; 37435#L1768-2 [2021-11-23 12:40:21,473 INFO L793 eck$LassoCheckResult]: Loop: 37435#L1768-2 assume !false; 37436#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38174#L1149 assume !false; 38546#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38699#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37825#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37731#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37732#L976 assume !(0 != eval_~tmp~0#1); 38865#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38875#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38666#L1174-3 assume !(0 == ~M_E~0); 38659#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38408#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38409#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38593#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37596#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37597#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37835#L1209-3 assume !(0 == ~T8_E~0); 37255#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37256#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38014#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38015#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38033#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37443#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37444#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37887#L1249-3 assume !(0 == ~E_4~0); 38346#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38818#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38460#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37449#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37450#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38845#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38012#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38013#L1289-3 assume !(0 == ~E_12~0); 38001#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37677#L566-39 assume 1 == ~m_pc~0; 37678#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38280#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37992#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37993#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38535#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38536#L585-39 assume !(1 == ~t1_pc~0); 37685#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37686#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37761#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37762#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38261#L604-39 assume 1 == ~t2_pc~0; 38262#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37893#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37894#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38313#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38314#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37876#L623-39 assume 1 == ~t3_pc~0; 37274#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37276#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38552#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37729#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38500#L642-39 assume 1 == ~t4_pc~0; 38073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37600#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37601#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38698#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37651#L661-39 assume !(1 == ~t5_pc~0); 37280#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37281#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38641#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38642#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38555#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38556#L680-39 assume 1 == ~t6_pc~0; 37344#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37345#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38485#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37808#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37809#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38823#L699-39 assume 1 == ~t7_pc~0; 38245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37967#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37968#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38651#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38772#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38770#L718-39 assume 1 == ~t8_pc~0; 38160#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38161#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38093#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38394#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38363#L737-39 assume 1 == ~t9_pc~0; 37789#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37790#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38079#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38846#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38747#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38690#L756-39 assume 1 == ~t10_pc~0; 38691#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38169#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37916#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37917#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38049#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37389#L775-39 assume 1 == ~t11_pc~0; 37390#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38042#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38043#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38905#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38453#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38100#L794-39 assume 1 == ~t12_pc~0; 37792#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37786#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38606#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38507#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37331#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37332#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38799#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38800#L1312-3 assume !(1 == ~T2_E~0); 38911#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38523#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38524#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37468#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37439#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37440#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38188#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38311#L1352-3 assume !(1 == ~T10_E~0); 38312#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38752#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38904#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38895#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37265#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37266#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37900#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37901#L1392-3 assume !(1 == ~E_6~0); 38616#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38862#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38279#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37555#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37556#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38202#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38203#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37565#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37566#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38432#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 38283#L1787 assume !(0 == start_simulation_~tmp~3#1); 38284#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38808#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37536#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38331#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 38332#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37883#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37884#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 37885#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37435#L1768-2 [2021-11-23 12:40:21,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2021-11-23 12:40:21,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107935963] [2021-11-23 12:40:21,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107935963] [2021-11-23 12:40:21,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107935963] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,509 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,511 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111901653] [2021-11-23 12:40:21,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:21,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,513 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 2 times [2021-11-23 12:40:21,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929854399] [2021-11-23 12:40:21,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929854399] [2021-11-23 12:40:21,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1929854399] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,595 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946790222] [2021-11-23 12:40:21,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,596 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:21,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:21,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:21,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:21,598 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:21,636 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2021-11-23 12:40:21,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:21,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2021-11-23 12:40:21,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-11-23 12:40:21,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:21,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:21,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2021-11-23 12:40:21,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:21,664 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-23 12:40:21,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2021-11-23 12:40:21,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:21,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-11-23 12:40:21,706 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-23 12:40:21,706 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-23 12:40:21,706 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-23 12:40:21,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2021-11-23 12:40:21,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:21,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:21,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,718 INFO L791 eck$LassoCheckResult]: Stem: 41414#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 42268#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41760#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41567#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41568#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41653#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41954#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42076#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42077#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40865#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40866#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42014#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41460#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41461#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41367#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41368#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 41756#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41109#L1174 assume !(0 == ~M_E~0); 41110#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40961#L1179-1 assume !(0 == ~T2_E~0); 40863#L1184-1 assume !(0 == ~T3_E~0); 40864#L1189-1 assume !(0 == ~T4_E~0); 40902#L1194-1 assume !(0 == ~T5_E~0); 41002#L1199-1 assume !(0 == ~T6_E~0); 41897#L1204-1 assume !(0 == ~T7_E~0); 41816#L1209-1 assume !(0 == ~T8_E~0); 41817#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42205#L1219-1 assume !(0 == ~T10_E~0); 42290#L1224-1 assume !(0 == ~T11_E~0); 41227#L1229-1 assume !(0 == ~T12_E~0); 40788#L1234-1 assume !(0 == ~E_1~0); 40789#L1239-1 assume !(0 == ~E_2~0); 40822#L1244-1 assume !(0 == ~E_3~0); 40823#L1249-1 assume !(0 == ~E_4~0); 41484#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40718#L1259-1 assume !(0 == ~E_6~0); 40673#L1264-1 assume !(0 == ~E_7~0); 40674#L1269-1 assume !(0 == ~E_8~0); 42295#L1274-1 assume !(0 == ~E_9~0); 42230#L1279-1 assume !(0 == ~E_10~0); 40906#L1284-1 assume !(0 == ~E_11~0); 40907#L1289-1 assume !(0 == ~E_12~0); 41536#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41537#L566 assume 1 == ~m_pc~0; 40690#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 40691#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41845#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41846#L1455 assume !(0 != activate_threads_~tmp~1#1); 41136#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41137#L585 assume 1 == ~t1_pc~0; 40785#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40786#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41786#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41787#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42255#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42253#L604 assume !(1 == ~t2_pc~0); 41865#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41866#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41399#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41400#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42037#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42038#L623 assume 1 == ~t3_pc~0; 41314#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40654#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41464#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41465#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42072#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40687#L642 assume !(1 == ~t4_pc~0); 40688#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41153#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41154#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40759#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 40760#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41877#L661 assume 1 == ~t5_pc~0; 40924#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40925#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40886#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40887#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 41906#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41907#L680 assume !(1 == ~t6_pc~0); 41347#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41348#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41609#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41610#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42138#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42251#L699 assume 1 == ~t7_pc~0; 41737#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41738#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40914#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40915#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41639#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41538#L718 assume !(1 == ~t8_pc~0); 41539#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40900#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40901#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40942#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 40943#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41076#L737 assume 1 == ~t9_pc~0; 41941#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41211#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41812#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41813#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41385#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41386#L756 assume 1 == ~t10_pc~0; 41965#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41631#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40617#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40618#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41193#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41194#L775 assume !(1 == ~t11_pc~0); 41448#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41449#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41070#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40834#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40835#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41021#L794 assume 1 == ~t12_pc~0; 40861#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40839#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42032#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40987#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 40988#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41467#L1307 assume !(1 == ~M_E~0); 41468#L1307-2 assume !(1 == ~T1_E~0); 41579#L1312-1 assume !(1 == ~T2_E~0); 41498#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41499#L1322-1 assume !(1 == ~T4_E~0); 41202#L1327-1 assume !(1 == ~T5_E~0); 41203#L1332-1 assume !(1 == ~T6_E~0); 41741#L1337-1 assume !(1 == ~T7_E~0); 41703#L1342-1 assume !(1 == ~T8_E~0); 41704#L1347-1 assume !(1 == ~T9_E~0); 42101#L1352-1 assume !(1 == ~T10_E~0); 41974#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41365#L1362-1 assume !(1 == ~T12_E~0); 41366#L1367-1 assume !(1 == ~E_1~0); 41003#L1372-1 assume !(1 == ~E_2~0); 41004#L1377-1 assume !(1 == ~E_3~0); 41297#L1382-1 assume !(1 == ~E_4~0); 41298#L1387-1 assume !(1 == ~E_5~0); 41867#L1392-1 assume !(1 == ~E_6~0); 41317#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41318#L1402-1 assume !(1 == ~E_8~0); 41014#L1407-1 assume !(1 == ~E_9~0); 41015#L1412-1 assume !(1 == ~E_10~0); 42030#L1417-1 assume !(1 == ~E_11~0); 42031#L1422-1 assume !(1 == ~E_12~0); 42249#L1427-1 assume { :end_inline_reset_delta_events } true; 40818#L1768-2 [2021-11-23 12:40:21,718 INFO L793 eck$LassoCheckResult]: Loop: 40818#L1768-2 assume !false; 40819#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41557#L1149 assume !false; 41929#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42082#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41208#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41114#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41115#L976 assume !(0 != eval_~tmp~0#1); 42248#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42258#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42049#L1174-3 assume !(0 == ~M_E~0); 42042#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41791#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41792#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41975#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41626#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40976#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40977#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41218#L1209-3 assume !(0 == ~T8_E~0); 40638#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40639#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41397#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41398#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41416#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40826#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40827#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41270#L1249-3 assume !(0 == ~E_4~0); 41729#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42201#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41843#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40832#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40833#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42228#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41395#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41396#L1289-3 assume !(0 == ~E_12~0); 41384#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41060#L566-39 assume 1 == ~m_pc~0; 41061#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41663#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41375#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41376#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41918#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41919#L585-39 assume !(1 == ~t1_pc~0); 41068#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 41069#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41144#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41145#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41951#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41644#L604-39 assume 1 == ~t2_pc~0; 41645#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41276#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41277#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41694#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41695#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41259#L623-39 assume !(1 == ~t3_pc~0); 40656#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 40657#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41935#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41111#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41112#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41883#L642-39 assume !(1 == ~t4_pc~0); 41456#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41455#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40983#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40984#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42081#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41032#L661-39 assume !(1 == ~t5_pc~0); 40663#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 40664#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42024#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42025#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41938#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41939#L680-39 assume 1 == ~t6_pc~0; 40725#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40726#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41868#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41191#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41192#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42206#L699-39 assume 1 == ~t7_pc~0; 41628#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41350#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41351#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42034#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42155#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42153#L718-39 assume 1 == ~t8_pc~0; 41542#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41543#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41475#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41476#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 41778#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41747#L737-39 assume 1 == ~t9_pc~0; 41172#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41173#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41462#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42229#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42130#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42073#L756-39 assume !(1 == ~t10_pc~0); 41554#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41555#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41299#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41300#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41432#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40772#L775-39 assume 1 == ~t11_pc~0; 40773#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41425#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41426#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42288#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41836#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41483#L794-39 assume !(1 == ~t12_pc~0); 41168#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 41169#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41989#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41890#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40714#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42182#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42183#L1312-3 assume !(1 == ~T2_E~0); 42294#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41908#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41909#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40853#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40824#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40825#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41571#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41696#L1352-3 assume !(1 == ~T10_E~0); 41697#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42136#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42287#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42278#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40651#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40652#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41283#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41284#L1392-3 assume !(1 == ~E_6~0); 41999#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42245#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41662#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40938#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40939#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41587#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41588#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40948#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40949#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41815#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41667#L1787 assume !(0 == start_simulation_~tmp~3#1); 41668#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42191#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40919#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41714#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 41715#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41266#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41267#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 41268#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 40818#L1768-2 [2021-11-23 12:40:21,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2021-11-23 12:40:21,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278079905] [2021-11-23 12:40:21,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,721 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278079905] [2021-11-23 12:40:21,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278079905] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,763 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 12:40:21,763 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421260216] [2021-11-23 12:40:21,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,763 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:21,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,764 INFO L85 PathProgramCache]: Analyzing trace with hash 1824468511, now seen corresponding path program 1 times [2021-11-23 12:40:21,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865996460] [2021-11-23 12:40:21,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865996460] [2021-11-23 12:40:21,810 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865996460] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,810 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,810 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1261426219] [2021-11-23 12:40:21,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,811 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:21,812 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:21,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:21,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:21,812 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:21,855 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2021-11-23 12:40:21,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:21,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2488 transitions. [2021-11-23 12:40:21,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-11-23 12:40:21,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-23 12:40:21,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-23 12:40:21,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2488 transitions. [2021-11-23 12:40:21,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:21,883 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-23 12:40:21,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2488 transitions. [2021-11-23 12:40:21,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-23 12:40:21,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:21,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-11-23 12:40:21,924 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-23 12:40:21,924 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-23 12:40:21,924 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-23 12:40:21,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2488 transitions. [2021-11-23 12:40:21,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:21,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:21,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:21,937 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,937 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:21,938 INFO L791 eck$LassoCheckResult]: Stem: 44797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45651#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45143#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44950#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 44951#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45036#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45337#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45459#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45460#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44248#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44249#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45397#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44843#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44844#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44750#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44751#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45139#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44492#L1174 assume !(0 == ~M_E~0); 44493#L1174-2 assume !(0 == ~T1_E~0); 44344#L1179-1 assume !(0 == ~T2_E~0); 44246#L1184-1 assume !(0 == ~T3_E~0); 44247#L1189-1 assume !(0 == ~T4_E~0); 44285#L1194-1 assume !(0 == ~T5_E~0); 44385#L1199-1 assume !(0 == ~T6_E~0); 45280#L1204-1 assume !(0 == ~T7_E~0); 45199#L1209-1 assume !(0 == ~T8_E~0); 45200#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45588#L1219-1 assume !(0 == ~T10_E~0); 45673#L1224-1 assume !(0 == ~T11_E~0); 44610#L1229-1 assume !(0 == ~T12_E~0); 44171#L1234-1 assume !(0 == ~E_1~0); 44172#L1239-1 assume !(0 == ~E_2~0); 44205#L1244-1 assume !(0 == ~E_3~0); 44206#L1249-1 assume !(0 == ~E_4~0); 44867#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44101#L1259-1 assume !(0 == ~E_6~0); 44056#L1264-1 assume !(0 == ~E_7~0); 44057#L1269-1 assume !(0 == ~E_8~0); 45678#L1274-1 assume !(0 == ~E_9~0); 45613#L1279-1 assume !(0 == ~E_10~0); 44289#L1284-1 assume !(0 == ~E_11~0); 44290#L1289-1 assume !(0 == ~E_12~0); 44919#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44920#L566 assume 1 == ~m_pc~0; 44073#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44074#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45228#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45229#L1455 assume !(0 != activate_threads_~tmp~1#1); 44519#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44520#L585 assume 1 == ~t1_pc~0; 44168#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44169#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45169#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45170#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45638#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45636#L604 assume !(1 == ~t2_pc~0); 45248#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45249#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44782#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44783#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45420#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45421#L623 assume 1 == ~t3_pc~0; 44697#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44037#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44847#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44848#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45455#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44070#L642 assume !(1 == ~t4_pc~0); 44071#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44536#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44537#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44142#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44143#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45260#L661 assume 1 == ~t5_pc~0; 44307#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44308#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44269#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44270#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45289#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45290#L680 assume !(1 == ~t6_pc~0); 44730#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44731#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44992#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44993#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45521#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45634#L699 assume 1 == ~t7_pc~0; 45120#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45121#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44297#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44298#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45022#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44921#L718 assume !(1 == ~t8_pc~0); 44922#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44283#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44284#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44325#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44326#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44459#L737 assume 1 == ~t9_pc~0; 45324#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44594#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45195#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45196#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 44768#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44769#L756 assume 1 == ~t10_pc~0; 45348#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45014#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44000#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44001#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44576#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44577#L775 assume !(1 == ~t11_pc~0); 44831#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 44832#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44453#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44217#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44218#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44404#L794 assume 1 == ~t12_pc~0; 44244#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44222#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45415#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44370#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44371#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44850#L1307 assume !(1 == ~M_E~0); 44851#L1307-2 assume !(1 == ~T1_E~0); 44962#L1312-1 assume !(1 == ~T2_E~0); 44881#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44882#L1322-1 assume !(1 == ~T4_E~0); 44585#L1327-1 assume !(1 == ~T5_E~0); 44586#L1332-1 assume !(1 == ~T6_E~0); 45124#L1337-1 assume !(1 == ~T7_E~0); 45086#L1342-1 assume !(1 == ~T8_E~0); 45087#L1347-1 assume !(1 == ~T9_E~0); 45484#L1352-1 assume !(1 == ~T10_E~0); 45357#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44748#L1362-1 assume !(1 == ~T12_E~0); 44749#L1367-1 assume !(1 == ~E_1~0); 44386#L1372-1 assume !(1 == ~E_2~0); 44387#L1377-1 assume !(1 == ~E_3~0); 44680#L1382-1 assume !(1 == ~E_4~0); 44681#L1387-1 assume !(1 == ~E_5~0); 45250#L1392-1 assume !(1 == ~E_6~0); 44700#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44701#L1402-1 assume !(1 == ~E_8~0); 44397#L1407-1 assume !(1 == ~E_9~0); 44398#L1412-1 assume !(1 == ~E_10~0); 45413#L1417-1 assume !(1 == ~E_11~0); 45414#L1422-1 assume !(1 == ~E_12~0); 45632#L1427-1 assume { :end_inline_reset_delta_events } true; 44201#L1768-2 [2021-11-23 12:40:21,939 INFO L793 eck$LassoCheckResult]: Loop: 44201#L1768-2 assume !false; 44202#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44940#L1149 assume !false; 45312#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45465#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44591#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44497#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44498#L976 assume !(0 != eval_~tmp~0#1); 45631#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45641#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45432#L1174-3 assume !(0 == ~M_E~0); 45425#L1174-5 assume !(0 == ~T1_E~0); 45174#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45175#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45358#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45009#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44359#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44360#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44601#L1209-3 assume !(0 == ~T8_E~0); 44021#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44022#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44780#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44781#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44799#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44209#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44210#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44653#L1249-3 assume !(0 == ~E_4~0); 45112#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45584#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45226#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44215#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44216#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45611#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44778#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44779#L1289-3 assume !(0 == ~E_12~0); 44767#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44443#L566-39 assume 1 == ~m_pc~0; 44444#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45046#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44758#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44759#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45301#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45302#L585-39 assume !(1 == ~t1_pc~0); 44451#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44452#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44527#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44528#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45334#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45027#L604-39 assume 1 == ~t2_pc~0; 45028#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44659#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44660#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45077#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45078#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44642#L623-39 assume 1 == ~t3_pc~0; 44038#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44040#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45318#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44494#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44495#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45266#L642-39 assume 1 == ~t4_pc~0; 44837#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44838#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44366#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44367#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45464#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44415#L661-39 assume 1 == ~t5_pc~0; 44416#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44047#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45407#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45408#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45321#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45322#L680-39 assume 1 == ~t6_pc~0; 44108#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44109#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45251#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44574#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44575#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45589#L699-39 assume 1 == ~t7_pc~0; 45011#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44733#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44734#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45538#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45536#L718-39 assume 1 == ~t8_pc~0; 44925#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44926#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44858#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44859#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 45161#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45130#L737-39 assume 1 == ~t9_pc~0; 44555#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44556#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44845#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45612#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45513#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45456#L756-39 assume 1 == ~t10_pc~0; 45457#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44938#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44682#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44683#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44815#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44155#L775-39 assume 1 == ~t11_pc~0; 44156#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44808#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44809#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45671#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45219#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44866#L794-39 assume !(1 == ~t12_pc~0); 44551#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 44552#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45372#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45273#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44097#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44098#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45565#L1307-5 assume !(1 == ~T1_E~0); 45566#L1312-3 assume !(1 == ~T2_E~0); 45677#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45291#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45292#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44236#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44207#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44208#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44954#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45079#L1352-3 assume !(1 == ~T10_E~0); 45080#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45519#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45670#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45661#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44034#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44035#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44666#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44667#L1392-3 assume !(1 == ~E_6~0); 45382#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45628#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45045#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44321#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44322#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44970#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44971#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44331#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44332#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45198#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 45050#L1787 assume !(0 == start_simulation_~tmp~3#1); 45051#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45574#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44302#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45097#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 45098#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44649#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44650#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 44651#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44201#L1768-2 [2021-11-23 12:40:21,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2021-11-23 12:40:21,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047993918] [2021-11-23 12:40:21,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:21,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:21,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:21,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047993918] [2021-11-23 12:40:21,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047993918] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:21,980 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:21,980 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:21,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825279237] [2021-11-23 12:40:21,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:21,981 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:21,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:21,982 INFO L85 PathProgramCache]: Analyzing trace with hash 599109159, now seen corresponding path program 1 times [2021-11-23 12:40:21,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:21,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53999760] [2021-11-23 12:40:21,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:21,983 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:21,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:22,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:22,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:22,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53999760] [2021-11-23 12:40:22,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53999760] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:22,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:22,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:22,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39080166] [2021-11-23 12:40:22,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:22,028 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:22,029 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:22,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:22,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:22,029 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:22,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:22,179 INFO L93 Difference]: Finished difference Result 3231 states and 4754 transitions. [2021-11-23 12:40:22,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:22,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3231 states and 4754 transitions. [2021-11-23 12:40:22,205 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2021-11-23 12:40:22,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3231 states to 3231 states and 4754 transitions. [2021-11-23 12:40:22,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3231 [2021-11-23 12:40:22,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3231 [2021-11-23 12:40:22,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3231 states and 4754 transitions. [2021-11-23 12:40:22,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:22,237 INFO L681 BuchiCegarLoop]: Abstraction has 3231 states and 4754 transitions. [2021-11-23 12:40:22,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3231 states and 4754 transitions. [2021-11-23 12:40:22,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3231 to 1688. [2021-11-23 12:40:22,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4727488151658767) internal successors, (2486), 1687 states have internal predecessors, (2486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:22,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2486 transitions. [2021-11-23 12:40:22,293 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2486 transitions. [2021-11-23 12:40:22,293 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2486 transitions. [2021-11-23 12:40:22,293 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-23 12:40:22,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2486 transitions. [2021-11-23 12:40:22,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:22,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:22,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:22,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:22,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:22,308 INFO L791 eck$LassoCheckResult]: Stem: 49726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50580#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50072#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49879#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 49880#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49965#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50266#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50388#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50389#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49177#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49178#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50326#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49772#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49773#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49679#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49680#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50068#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49421#L1174 assume !(0 == ~M_E~0); 49422#L1174-2 assume !(0 == ~T1_E~0); 49273#L1179-1 assume !(0 == ~T2_E~0); 49175#L1184-1 assume !(0 == ~T3_E~0); 49176#L1189-1 assume !(0 == ~T4_E~0); 49214#L1194-1 assume !(0 == ~T5_E~0); 49314#L1199-1 assume !(0 == ~T6_E~0); 50209#L1204-1 assume !(0 == ~T7_E~0); 50128#L1209-1 assume !(0 == ~T8_E~0); 50129#L1214-1 assume !(0 == ~T9_E~0); 50517#L1219-1 assume !(0 == ~T10_E~0); 50602#L1224-1 assume !(0 == ~T11_E~0); 49539#L1229-1 assume !(0 == ~T12_E~0); 49100#L1234-1 assume !(0 == ~E_1~0); 49101#L1239-1 assume !(0 == ~E_2~0); 49134#L1244-1 assume !(0 == ~E_3~0); 49135#L1249-1 assume !(0 == ~E_4~0); 49796#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49030#L1259-1 assume !(0 == ~E_6~0); 48985#L1264-1 assume !(0 == ~E_7~0); 48986#L1269-1 assume !(0 == ~E_8~0); 50607#L1274-1 assume !(0 == ~E_9~0); 50542#L1279-1 assume !(0 == ~E_10~0); 49218#L1284-1 assume !(0 == ~E_11~0); 49219#L1289-1 assume !(0 == ~E_12~0); 49848#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49849#L566 assume 1 == ~m_pc~0; 49002#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49003#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50157#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50158#L1455 assume !(0 != activate_threads_~tmp~1#1); 49448#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49449#L585 assume 1 == ~t1_pc~0; 49097#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49098#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50098#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50099#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 50567#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50565#L604 assume !(1 == ~t2_pc~0); 50177#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50178#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49711#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49712#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50349#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50350#L623 assume 1 == ~t3_pc~0; 49626#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48966#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49776#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49777#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50384#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48999#L642 assume !(1 == ~t4_pc~0); 49000#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49465#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49466#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49071#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49072#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50189#L661 assume 1 == ~t5_pc~0; 49236#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49237#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49198#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49199#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50218#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50219#L680 assume !(1 == ~t6_pc~0); 49659#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49660#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49921#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49922#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50450#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50563#L699 assume 1 == ~t7_pc~0; 50049#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50050#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49226#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49227#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 49951#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49850#L718 assume !(1 == ~t8_pc~0); 49851#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49212#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49213#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49254#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49255#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49388#L737 assume 1 == ~t9_pc~0; 50253#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49523#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50124#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50125#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 49697#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49698#L756 assume 1 == ~t10_pc~0; 50277#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49943#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48929#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48930#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49505#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49506#L775 assume !(1 == ~t11_pc~0); 49760#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49761#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49382#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49146#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49147#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49333#L794 assume 1 == ~t12_pc~0; 49173#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49151#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50344#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49299#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49300#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49779#L1307 assume !(1 == ~M_E~0); 49780#L1307-2 assume !(1 == ~T1_E~0); 49891#L1312-1 assume !(1 == ~T2_E~0); 49810#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49811#L1322-1 assume !(1 == ~T4_E~0); 49514#L1327-1 assume !(1 == ~T5_E~0); 49515#L1332-1 assume !(1 == ~T6_E~0); 50053#L1337-1 assume !(1 == ~T7_E~0); 50015#L1342-1 assume !(1 == ~T8_E~0); 50016#L1347-1 assume !(1 == ~T9_E~0); 50413#L1352-1 assume !(1 == ~T10_E~0); 50286#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49677#L1362-1 assume !(1 == ~T12_E~0); 49678#L1367-1 assume !(1 == ~E_1~0); 49315#L1372-1 assume !(1 == ~E_2~0); 49316#L1377-1 assume !(1 == ~E_3~0); 49609#L1382-1 assume !(1 == ~E_4~0); 49610#L1387-1 assume !(1 == ~E_5~0); 50179#L1392-1 assume !(1 == ~E_6~0); 49629#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49630#L1402-1 assume !(1 == ~E_8~0); 49326#L1407-1 assume !(1 == ~E_9~0); 49327#L1412-1 assume !(1 == ~E_10~0); 50342#L1417-1 assume !(1 == ~E_11~0); 50343#L1422-1 assume !(1 == ~E_12~0); 50561#L1427-1 assume { :end_inline_reset_delta_events } true; 49130#L1768-2 [2021-11-23 12:40:22,309 INFO L793 eck$LassoCheckResult]: Loop: 49130#L1768-2 assume !false; 49131#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49869#L1149 assume !false; 50241#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50394#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49520#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49426#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49427#L976 assume !(0 != eval_~tmp~0#1); 50560#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50570#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50361#L1174-3 assume !(0 == ~M_E~0); 50354#L1174-5 assume !(0 == ~T1_E~0); 50103#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50104#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50287#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49938#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49288#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49289#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49530#L1209-3 assume !(0 == ~T8_E~0); 48950#L1214-3 assume !(0 == ~T9_E~0); 48951#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49709#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49710#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49728#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49138#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49139#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49582#L1249-3 assume !(0 == ~E_4~0); 50041#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50513#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50155#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49144#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49145#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50540#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49707#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49708#L1289-3 assume !(0 == ~E_12~0); 49696#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49372#L566-39 assume 1 == ~m_pc~0; 49373#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49975#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49687#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49688#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50230#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50231#L585-39 assume !(1 == ~t1_pc~0); 49380#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 49381#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49456#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49457#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50263#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49956#L604-39 assume 1 == ~t2_pc~0; 49957#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49588#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49589#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50006#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50007#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49571#L623-39 assume 1 == ~t3_pc~0; 48967#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48969#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50247#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49423#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49424#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50195#L642-39 assume 1 == ~t4_pc~0; 49766#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49767#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49295#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49296#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50393#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49344#L661-39 assume 1 == ~t5_pc~0; 49345#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48976#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50336#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50337#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50250#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50251#L680-39 assume 1 == ~t6_pc~0; 49037#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49038#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50180#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49503#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49504#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50518#L699-39 assume 1 == ~t7_pc~0; 49940#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49662#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49663#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50346#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50467#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50465#L718-39 assume !(1 == ~t8_pc~0); 49856#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 49855#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49787#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49788#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 50090#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50059#L737-39 assume 1 == ~t9_pc~0; 49484#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49485#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49774#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50541#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50442#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50385#L756-39 assume 1 == ~t10_pc~0; 50386#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49867#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49611#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49612#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49744#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49084#L775-39 assume 1 == ~t11_pc~0; 49085#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49737#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49738#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50600#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50148#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49795#L794-39 assume !(1 == ~t12_pc~0); 49480#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 49481#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50301#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50202#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49026#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49027#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50494#L1307-5 assume !(1 == ~T1_E~0); 50495#L1312-3 assume !(1 == ~T2_E~0); 50606#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50220#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50221#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49165#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49136#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49137#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49883#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50008#L1352-3 assume !(1 == ~T10_E~0); 50009#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50448#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50599#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50590#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48963#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48964#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49595#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49596#L1392-3 assume !(1 == ~E_6~0); 50311#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50557#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49974#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49250#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49251#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49899#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49900#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49260#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49261#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50127#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49979#L1787 assume !(0 == start_simulation_~tmp~3#1); 49980#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50503#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49231#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50026#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 50027#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49578#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49579#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 49580#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 49130#L1768-2 [2021-11-23 12:40:22,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:22,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1828387561, now seen corresponding path program 1 times [2021-11-23 12:40:22,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:22,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459845430] [2021-11-23 12:40:22,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:22,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:22,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:22,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:22,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:22,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459845430] [2021-11-23 12:40:22,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459845430] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:22,353 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:22,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:22,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847740522] [2021-11-23 12:40:22,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:22,354 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:22,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:22,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1494578616, now seen corresponding path program 1 times [2021-11-23 12:40:22,355 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:22,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836257337] [2021-11-23 12:40:22,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:22,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:22,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:22,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:22,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:22,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836257337] [2021-11-23 12:40:22,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1836257337] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:22,398 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:22,398 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:22,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822886198] [2021-11-23 12:40:22,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:22,399 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:22,400 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:22,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:22,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:22,400 INFO L87 Difference]: Start difference. First operand 1688 states and 2486 transitions. cyclomatic complexity: 799 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:22,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:22,599 INFO L93 Difference]: Finished difference Result 3131 states and 4604 transitions. [2021-11-23 12:40:22,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:22,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3131 states and 4604 transitions. [2021-11-23 12:40:22,618 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2961 [2021-11-23 12:40:22,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3131 states to 3131 states and 4604 transitions. [2021-11-23 12:40:22,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3131 [2021-11-23 12:40:22,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3131 [2021-11-23 12:40:22,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3131 states and 4604 transitions. [2021-11-23 12:40:22,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:22,640 INFO L681 BuchiCegarLoop]: Abstraction has 3131 states and 4604 transitions. [2021-11-23 12:40:22,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3131 states and 4604 transitions. [2021-11-23 12:40:22,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3131 to 1688. [2021-11-23 12:40:22,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.471563981042654) internal successors, (2484), 1687 states have internal predecessors, (2484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:22,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2484 transitions. [2021-11-23 12:40:22,684 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2484 transitions. [2021-11-23 12:40:22,684 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2484 transitions. [2021-11-23 12:40:22,684 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-23 12:40:22,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2484 transitions. [2021-11-23 12:40:22,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-23 12:40:22,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:22,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:22,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:22,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:22,696 INFO L791 eck$LassoCheckResult]: Stem: 54555#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 54556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 55409#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54901#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54708#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 54709#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54794#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55095#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55217#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55218#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54006#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54007#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55155#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54601#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54602#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54508#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54509#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54897#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54250#L1174 assume !(0 == ~M_E~0); 54251#L1174-2 assume !(0 == ~T1_E~0); 54102#L1179-1 assume !(0 == ~T2_E~0); 54004#L1184-1 assume !(0 == ~T3_E~0); 54005#L1189-1 assume !(0 == ~T4_E~0); 54043#L1194-1 assume !(0 == ~T5_E~0); 54143#L1199-1 assume !(0 == ~T6_E~0); 55038#L1204-1 assume !(0 == ~T7_E~0); 54957#L1209-1 assume !(0 == ~T8_E~0); 54958#L1214-1 assume !(0 == ~T9_E~0); 55346#L1219-1 assume !(0 == ~T10_E~0); 55431#L1224-1 assume !(0 == ~T11_E~0); 54368#L1229-1 assume !(0 == ~T12_E~0); 53929#L1234-1 assume !(0 == ~E_1~0); 53930#L1239-1 assume !(0 == ~E_2~0); 53963#L1244-1 assume !(0 == ~E_3~0); 53964#L1249-1 assume !(0 == ~E_4~0); 54625#L1254-1 assume !(0 == ~E_5~0); 53859#L1259-1 assume !(0 == ~E_6~0); 53814#L1264-1 assume !(0 == ~E_7~0); 53815#L1269-1 assume !(0 == ~E_8~0); 55436#L1274-1 assume !(0 == ~E_9~0); 55371#L1279-1 assume !(0 == ~E_10~0); 54047#L1284-1 assume !(0 == ~E_11~0); 54048#L1289-1 assume !(0 == ~E_12~0); 54677#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54678#L566 assume 1 == ~m_pc~0; 53831#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 53832#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54986#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54987#L1455 assume !(0 != activate_threads_~tmp~1#1); 54277#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54278#L585 assume 1 == ~t1_pc~0; 53926#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53927#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54927#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54928#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 55396#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55394#L604 assume !(1 == ~t2_pc~0); 55006#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55007#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54540#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54541#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55178#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55179#L623 assume 1 == ~t3_pc~0; 54455#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53795#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54605#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54606#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 55213#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53828#L642 assume !(1 == ~t4_pc~0); 53829#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54294#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54295#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53900#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 53901#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55018#L661 assume 1 == ~t5_pc~0; 54065#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54066#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54027#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54028#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 55047#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55048#L680 assume !(1 == ~t6_pc~0); 54488#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54489#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54750#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54751#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 55279#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55392#L699 assume 1 == ~t7_pc~0; 54878#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54879#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54055#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54056#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 54780#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54679#L718 assume !(1 == ~t8_pc~0); 54680#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 54041#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54042#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54083#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 54084#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54217#L737 assume 1 == ~t9_pc~0; 55082#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54352#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54953#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54954#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 54526#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54527#L756 assume 1 == ~t10_pc~0; 55106#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54772#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53758#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53759#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 54334#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54335#L775 assume !(1 == ~t11_pc~0); 54589#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 54590#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54211#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53975#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53976#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54162#L794 assume 1 == ~t12_pc~0; 54002#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53980#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55173#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54128#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 54129#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54608#L1307 assume !(1 == ~M_E~0); 54609#L1307-2 assume !(1 == ~T1_E~0); 54720#L1312-1 assume !(1 == ~T2_E~0); 54639#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54640#L1322-1 assume !(1 == ~T4_E~0); 54343#L1327-1 assume !(1 == ~T5_E~0); 54344#L1332-1 assume !(1 == ~T6_E~0); 54882#L1337-1 assume !(1 == ~T7_E~0); 54844#L1342-1 assume !(1 == ~T8_E~0); 54845#L1347-1 assume !(1 == ~T9_E~0); 55242#L1352-1 assume !(1 == ~T10_E~0); 55115#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54506#L1362-1 assume !(1 == ~T12_E~0); 54507#L1367-1 assume !(1 == ~E_1~0); 54144#L1372-1 assume !(1 == ~E_2~0); 54145#L1377-1 assume !(1 == ~E_3~0); 54438#L1382-1 assume !(1 == ~E_4~0); 54439#L1387-1 assume !(1 == ~E_5~0); 55008#L1392-1 assume !(1 == ~E_6~0); 54458#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 54459#L1402-1 assume !(1 == ~E_8~0); 54155#L1407-1 assume !(1 == ~E_9~0); 54156#L1412-1 assume !(1 == ~E_10~0); 55171#L1417-1 assume !(1 == ~E_11~0); 55172#L1422-1 assume !(1 == ~E_12~0); 55390#L1427-1 assume { :end_inline_reset_delta_events } true; 53959#L1768-2 [2021-11-23 12:40:22,697 INFO L793 eck$LassoCheckResult]: Loop: 53959#L1768-2 assume !false; 53960#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54698#L1149 assume !false; 55070#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55223#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54349#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54255#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54256#L976 assume !(0 != eval_~tmp~0#1); 55389#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55399#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55190#L1174-3 assume !(0 == ~M_E~0); 55183#L1174-5 assume !(0 == ~T1_E~0); 54932#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54933#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55116#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54767#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54117#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54118#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54359#L1209-3 assume !(0 == ~T8_E~0); 53779#L1214-3 assume !(0 == ~T9_E~0); 53780#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54538#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54539#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54557#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53967#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53968#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54411#L1249-3 assume !(0 == ~E_4~0); 54870#L1254-3 assume !(0 == ~E_5~0); 55342#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54984#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53973#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53974#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55369#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54536#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54537#L1289-3 assume !(0 == ~E_12~0); 54525#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54201#L566-39 assume 1 == ~m_pc~0; 54202#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54804#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54516#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54517#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55059#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55060#L585-39 assume !(1 == ~t1_pc~0); 54209#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 54210#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54285#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54286#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55092#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54785#L604-39 assume 1 == ~t2_pc~0; 54786#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54417#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54418#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54835#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54836#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54400#L623-39 assume 1 == ~t3_pc~0; 53796#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53798#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55076#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54252#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54253#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55024#L642-39 assume 1 == ~t4_pc~0; 54595#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54596#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54124#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54125#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55222#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54173#L661-39 assume !(1 == ~t5_pc~0); 53804#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 53805#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55165#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55166#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55079#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55080#L680-39 assume 1 == ~t6_pc~0; 53866#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53867#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55009#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54332#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54333#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55347#L699-39 assume 1 == ~t7_pc~0; 54769#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54491#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54492#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55175#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 55296#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55294#L718-39 assume 1 == ~t8_pc~0; 54683#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54684#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54616#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54617#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 54919#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54888#L737-39 assume 1 == ~t9_pc~0; 54313#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54314#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54603#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55370#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55271#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55214#L756-39 assume !(1 == ~t10_pc~0); 54695#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 54696#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54440#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54441#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54573#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53913#L775-39 assume 1 == ~t11_pc~0; 53914#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54566#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54567#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55429#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54977#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54624#L794-39 assume !(1 == ~t12_pc~0); 54309#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 54310#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55130#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55031#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53855#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53856#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55323#L1307-5 assume !(1 == ~T1_E~0); 55324#L1312-3 assume !(1 == ~T2_E~0); 55435#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55049#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55050#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53994#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53965#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53966#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54712#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54837#L1352-3 assume !(1 == ~T10_E~0); 54838#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55277#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55428#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55419#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53792#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53793#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54424#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54425#L1392-3 assume !(1 == ~E_6~0); 55140#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 55386#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54803#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54079#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54080#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54728#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54729#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54089#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54090#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54956#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 54808#L1787 assume !(0 == start_simulation_~tmp~3#1); 54809#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55332#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54060#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54855#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 54856#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54407#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54408#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 54409#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 53959#L1768-2 [2021-11-23 12:40:22,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:22,698 INFO L85 PathProgramCache]: Analyzing trace with hash -101242599, now seen corresponding path program 1 times [2021-11-23 12:40:22,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:22,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722323291] [2021-11-23 12:40:22,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:22,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:22,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:22,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:22,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:22,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722323291] [2021-11-23 12:40:22,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722323291] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:22,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:22,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 12:40:22,732 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758497929] [2021-11-23 12:40:22,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:22,732 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:22,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:22,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1185649961, now seen corresponding path program 1 times [2021-11-23 12:40:22,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:22,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097834646] [2021-11-23 12:40:22,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:22,734 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:22,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:22,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:22,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:22,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097834646] [2021-11-23 12:40:22,772 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097834646] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:22,772 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:22,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:22,773 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499054567] [2021-11-23 12:40:22,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:22,773 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:22,774 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:22,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:22,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:22,774 INFO L87 Difference]: Start difference. First operand 1688 states and 2484 transitions. cyclomatic complexity: 797 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:22,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:22,934 INFO L93 Difference]: Finished difference Result 3198 states and 4671 transitions. [2021-11-23 12:40:22,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:22,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3198 states and 4671 transitions. [2021-11-23 12:40:22,951 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3037 [2021-11-23 12:40:22,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3198 states to 3198 states and 4671 transitions. [2021-11-23 12:40:22,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3198 [2021-11-23 12:40:22,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3198 [2021-11-23 12:40:22,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3198 states and 4671 transitions. [2021-11-23 12:40:22,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:22,972 INFO L681 BuchiCegarLoop]: Abstraction has 3198 states and 4671 transitions. [2021-11-23 12:40:22,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states and 4671 transitions. [2021-11-23 12:40:23,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3106. [2021-11-23 12:40:23,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3106 states, 3106 states have (on average 1.4623309723116549) internal successors, (4542), 3105 states have internal predecessors, (4542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:23,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3106 states to 3106 states and 4542 transitions. [2021-11-23 12:40:23,038 INFO L704 BuchiCegarLoop]: Abstraction has 3106 states and 4542 transitions. [2021-11-23 12:40:23,038 INFO L587 BuchiCegarLoop]: Abstraction has 3106 states and 4542 transitions. [2021-11-23 12:40:23,038 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-23 12:40:23,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3106 states and 4542 transitions. [2021-11-23 12:40:23,050 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2945 [2021-11-23 12:40:23,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:23,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:23,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:23,054 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:23,054 INFO L791 eck$LassoCheckResult]: Stem: 59448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 59449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 60324#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59798#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59601#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59602#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59687#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59998#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60122#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60123#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58896#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58897#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60058#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59493#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59494#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59400#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59401#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59793#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59138#L1174 assume !(0 == ~M_E~0); 59139#L1174-2 assume !(0 == ~T1_E~0); 58992#L1179-1 assume !(0 == ~T2_E~0); 58894#L1184-1 assume !(0 == ~T3_E~0); 58895#L1189-1 assume !(0 == ~T4_E~0); 58933#L1194-1 assume !(0 == ~T5_E~0); 59033#L1199-1 assume !(0 == ~T6_E~0); 59937#L1204-1 assume !(0 == ~T7_E~0); 59852#L1209-1 assume !(0 == ~T8_E~0); 59853#L1214-1 assume !(0 == ~T9_E~0); 60250#L1219-1 assume !(0 == ~T10_E~0); 60349#L1224-1 assume !(0 == ~T11_E~0); 59257#L1229-1 assume !(0 == ~T12_E~0); 58821#L1234-1 assume !(0 == ~E_1~0); 58822#L1239-1 assume !(0 == ~E_2~0); 58855#L1244-1 assume !(0 == ~E_3~0); 58856#L1249-1 assume !(0 == ~E_4~0); 59517#L1254-1 assume !(0 == ~E_5~0); 58749#L1259-1 assume !(0 == ~E_6~0); 58707#L1264-1 assume !(0 == ~E_7~0); 58708#L1269-1 assume !(0 == ~E_8~0); 60361#L1274-1 assume !(0 == ~E_9~0); 60277#L1279-1 assume !(0 == ~E_10~0); 58937#L1284-1 assume !(0 == ~E_11~0); 58938#L1289-1 assume !(0 == ~E_12~0); 59570#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59571#L566 assume !(1 == ~m_pc~0); 59995#L566-2 is_master_triggered_~__retres1~0#1 := 0; 59996#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59884#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59885#L1455 assume !(0 != activate_threads_~tmp~1#1); 59165#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59166#L585 assume 1 == ~t1_pc~0; 58816#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58817#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59822#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59823#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 60306#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60304#L604 assume !(1 == ~t2_pc~0); 59904#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59905#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59432#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59433#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60085#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60086#L623 assume 1 == ~t3_pc~0; 59347#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58688#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59497#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59498#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 60117#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58721#L642 assume !(1 == ~t4_pc~0); 58722#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59182#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59183#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58792#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58793#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59916#L661 assume 1 == ~t5_pc~0; 58955#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58956#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58917#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58918#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 59948#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59949#L680 assume !(1 == ~t6_pc~0); 59380#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59381#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59643#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59644#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 60184#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60302#L699 assume 1 == ~t7_pc~0; 59773#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59774#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58945#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58946#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59673#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59572#L718 assume !(1 == ~t8_pc~0); 59573#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58931#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58932#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58973#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 58974#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59105#L737 assume 1 == ~t9_pc~0; 59982#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59241#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59848#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59849#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59418#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59419#L756 assume 1 == ~t10_pc~0; 60008#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59665#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58651#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58652#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 59222#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59223#L775 assume !(1 == ~t11_pc~0); 59481#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59482#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59099#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58865#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58866#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59052#L794 assume 1 == ~t12_pc~0; 58893#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58870#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60078#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59020#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 59021#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59500#L1307 assume !(1 == ~M_E~0); 59501#L1307-2 assume !(1 == ~T1_E~0); 59613#L1312-1 assume !(1 == ~T2_E~0); 59531#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59532#L1322-1 assume !(1 == ~T4_E~0); 59232#L1327-1 assume !(1 == ~T5_E~0); 59233#L1332-1 assume !(1 == ~T6_E~0); 59777#L1337-1 assume !(1 == ~T7_E~0); 59737#L1342-1 assume !(1 == ~T8_E~0); 59738#L1347-1 assume !(1 == ~T9_E~0); 60147#L1352-1 assume !(1 == ~T10_E~0); 60016#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59398#L1362-1 assume !(1 == ~T12_E~0); 59399#L1367-1 assume !(1 == ~E_1~0); 59034#L1372-1 assume !(1 == ~E_2~0); 59035#L1377-1 assume !(1 == ~E_3~0); 59330#L1382-1 assume !(1 == ~E_4~0); 59331#L1387-1 assume !(1 == ~E_5~0); 59906#L1392-1 assume !(1 == ~E_6~0); 59352#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 59353#L1402-1 assume !(1 == ~E_8~0); 59047#L1407-1 assume !(1 == ~E_9~0); 59048#L1412-1 assume !(1 == ~E_10~0); 60076#L1417-1 assume !(1 == ~E_11~0); 60077#L1422-1 assume !(1 == ~E_12~0); 60300#L1427-1 assume { :end_inline_reset_delta_events } true; 58849#L1768-2 [2021-11-23 12:40:23,055 INFO L793 eck$LassoCheckResult]: Loop: 58849#L1768-2 assume !false; 58850#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59593#L1149 assume !false; 59970#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60128#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59238#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59149#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59150#L976 assume !(0 != eval_~tmp~0#1); 60296#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60312#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60094#L1174-3 assume !(0 == ~M_E~0); 60088#L1174-5 assume !(0 == ~T1_E~0); 59827#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59828#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60018#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59660#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59010#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59011#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59247#L1209-3 assume !(0 == ~T8_E~0); 58672#L1214-3 assume !(0 == ~T9_E~0); 58673#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59430#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59431#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59447#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58857#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58858#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59303#L1249-3 assume !(0 == ~E_4~0); 59765#L1254-3 assume !(0 == ~E_5~0); 60246#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59882#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58863#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58864#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60275#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59428#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59429#L1289-3 assume !(0 == ~E_12~0); 59417#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59087#L566-39 assume !(1 == ~m_pc~0); 59088#L566-41 is_master_triggered_~__retres1~0#1 := 0; 59697#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59408#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59409#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59958#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59959#L585-39 assume !(1 == ~t1_pc~0); 59096#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 59097#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59173#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59174#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59992#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59679#L604-39 assume 1 == ~t2_pc~0; 59680#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59309#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59310#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59730#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59731#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59289#L623-39 assume 1 == ~t3_pc~0; 58689#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58691#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59975#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59140#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59141#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59922#L642-39 assume !(1 == ~t4_pc~0); 59489#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 59488#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59014#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59015#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60127#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59061#L661-39 assume 1 == ~t5_pc~0; 59062#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58698#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60070#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60071#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59979#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59980#L680-39 assume 1 == ~t6_pc~0; 58756#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58757#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59907#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59220#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59221#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60251#L699-39 assume 1 == ~t7_pc~0; 59662#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59383#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59384#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60080#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60200#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60198#L718-39 assume 1 == ~t8_pc~0; 59576#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59577#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59508#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59509#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 59813#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59783#L737-39 assume 1 == ~t9_pc~0; 59201#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59202#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59495#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60276#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60176#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60118#L756-39 assume !(1 == ~t10_pc~0); 59588#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 59589#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59332#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59333#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59465#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58803#L775-39 assume 1 == ~t11_pc~0; 58804#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59458#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59459#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60347#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59875#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59516#L794-39 assume 1 == ~t12_pc~0; 59205#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59198#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60032#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59929#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58745#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58746#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60227#L1307-5 assume !(1 == ~T1_E~0); 60228#L1312-3 assume !(1 == ~T2_E~0); 60360#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59946#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59947#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58884#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58853#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58854#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 59605#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59728#L1352-3 assume !(1 == ~T10_E~0); 59729#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60181#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60345#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60334#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58682#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58683#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59316#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59317#L1392-3 assume !(1 == ~E_6~0); 60042#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60293#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59696#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58969#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58970#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59619#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59620#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 58977#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 58978#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59851#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 59701#L1787 assume !(0 == start_simulation_~tmp~3#1); 59702#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60236#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 58950#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59748#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 59749#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59297#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59298#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 59299#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 58849#L1768-2 [2021-11-23 12:40:23,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:23,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1338895688, now seen corresponding path program 1 times [2021-11-23 12:40:23,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:23,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947002322] [2021-11-23 12:40:23,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:23,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:23,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:23,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:23,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:23,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947002322] [2021-11-23 12:40:23,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947002322] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:23,094 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:23,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:23,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686003589] [2021-11-23 12:40:23,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:23,095 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:23,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:23,095 INFO L85 PathProgramCache]: Analyzing trace with hash -1907602711, now seen corresponding path program 1 times [2021-11-23 12:40:23,096 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:23,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090315264] [2021-11-23 12:40:23,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:23,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:23,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:23,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:23,133 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:23,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090315264] [2021-11-23 12:40:23,134 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090315264] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:23,134 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:23,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:23,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435723137] [2021-11-23 12:40:23,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:23,135 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:23,135 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:23,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:23,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:23,136 INFO L87 Difference]: Start difference. First operand 3106 states and 4542 transitions. cyclomatic complexity: 1438 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:23,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:23,415 INFO L93 Difference]: Finished difference Result 7410 states and 10750 transitions. [2021-11-23 12:40:23,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:23,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7410 states and 10750 transitions. [2021-11-23 12:40:23,448 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7150 [2021-11-23 12:40:23,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7410 states to 7410 states and 10750 transitions. [2021-11-23 12:40:23,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7410 [2021-11-23 12:40:23,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7410 [2021-11-23 12:40:23,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7410 states and 10750 transitions. [2021-11-23 12:40:23,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:23,493 INFO L681 BuchiCegarLoop]: Abstraction has 7410 states and 10750 transitions. [2021-11-23 12:40:23,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7410 states and 10750 transitions. [2021-11-23 12:40:23,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7410 to 5835. [2021-11-23 12:40:23,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5835 states, 5835 states have (on average 1.4553556126820908) internal successors, (8492), 5834 states have internal predecessors, (8492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:23,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5835 states to 5835 states and 8492 transitions. [2021-11-23 12:40:23,602 INFO L704 BuchiCegarLoop]: Abstraction has 5835 states and 8492 transitions. [2021-11-23 12:40:23,602 INFO L587 BuchiCegarLoop]: Abstraction has 5835 states and 8492 transitions. [2021-11-23 12:40:23,602 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-23 12:40:23,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5835 states and 8492 transitions. [2021-11-23 12:40:23,620 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5674 [2021-11-23 12:40:23,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:23,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:23,624 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:23,624 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:23,624 INFO L791 eck$LassoCheckResult]: Stem: 69980#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 69981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 70877#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70333#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70130#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 70131#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70219#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70539#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70663#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70664#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69417#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69418#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 70594#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70023#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70024#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69932#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69933#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70328#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69663#L1174 assume !(0 == ~M_E~0); 69664#L1174-2 assume !(0 == ~T1_E~0); 69515#L1179-1 assume !(0 == ~T2_E~0); 69415#L1184-1 assume !(0 == ~T3_E~0); 69416#L1189-1 assume !(0 == ~T4_E~0); 69455#L1194-1 assume !(0 == ~T5_E~0); 69556#L1199-1 assume !(0 == ~T6_E~0); 70473#L1204-1 assume !(0 == ~T7_E~0); 70389#L1209-1 assume !(0 == ~T8_E~0); 70390#L1214-1 assume !(0 == ~T9_E~0); 70798#L1219-1 assume !(0 == ~T10_E~0); 70899#L1224-1 assume !(0 == ~T11_E~0); 69786#L1229-1 assume !(0 == ~T12_E~0); 69343#L1234-1 assume !(0 == ~E_1~0); 69344#L1239-1 assume !(0 == ~E_2~0); 69377#L1244-1 assume !(0 == ~E_3~0); 69378#L1249-1 assume !(0 == ~E_4~0); 70046#L1254-1 assume !(0 == ~E_5~0); 69274#L1259-1 assume !(0 == ~E_6~0); 69232#L1264-1 assume !(0 == ~E_7~0); 69233#L1269-1 assume !(0 == ~E_8~0); 70912#L1274-1 assume !(0 == ~E_9~0); 70829#L1279-1 assume !(0 == ~E_10~0); 69458#L1284-1 assume !(0 == ~E_11~0); 69459#L1289-1 assume !(0 == ~E_12~0); 70099#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70100#L566 assume !(1 == ~m_pc~0); 70533#L566-2 is_master_triggered_~__retres1~0#1 := 0; 70534#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70419#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70420#L1455 assume !(0 != activate_threads_~tmp~1#1); 69690#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69691#L585 assume !(1 == ~t1_pc~0); 69876#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69877#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70359#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70360#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 70861#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70859#L604 assume !(1 == ~t2_pc~0); 70439#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 70440#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69962#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69963#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70625#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70626#L623 assume 1 == ~t3_pc~0; 69875#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69213#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70027#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70028#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 70658#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69246#L642 assume !(1 == ~t4_pc~0); 69247#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69709#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69710#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69317#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 69318#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70451#L661 assume 1 == ~t5_pc~0; 69478#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69479#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69438#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69439#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 70484#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70485#L680 assume !(1 == ~t6_pc~0); 69910#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 69911#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70174#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70175#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 70730#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70857#L699 assume 1 == ~t7_pc~0; 70308#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 70309#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69466#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69467#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 70205#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70101#L718 assume !(1 == ~t8_pc~0); 70102#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 69453#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69454#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69498#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 69499#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69630#L737 assume 1 == ~t9_pc~0; 70521#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69771#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70385#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70386#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 69948#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69949#L756 assume 1 == ~t10_pc~0; 70546#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70196#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69177#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69178#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 69751#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69752#L775 assume !(1 == ~t11_pc~0); 70011#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 70012#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69627#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69387#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69388#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69575#L794 assume 1 == ~t12_pc~0; 69414#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69392#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70618#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69543#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 69544#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70030#L1307 assume !(1 == ~M_E~0); 70031#L1307-2 assume !(1 == ~T1_E~0); 70142#L1312-1 assume !(1 == ~T2_E~0); 70060#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70061#L1322-1 assume !(1 == ~T4_E~0); 69761#L1327-1 assume !(1 == ~T5_E~0); 69762#L1332-1 assume !(1 == ~T6_E~0); 70312#L1337-1 assume !(1 == ~T7_E~0); 70269#L1342-1 assume !(1 == ~T8_E~0); 70270#L1347-1 assume !(1 == ~T9_E~0); 70689#L1352-1 assume !(1 == ~T10_E~0); 70555#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69928#L1362-1 assume !(1 == ~T12_E~0); 69929#L1367-1 assume !(1 == ~E_1~0); 69557#L1372-1 assume !(1 == ~E_2~0); 69558#L1377-1 assume !(1 == ~E_3~0); 69858#L1382-1 assume !(1 == ~E_4~0); 69859#L1387-1 assume !(1 == ~E_5~0); 70441#L1392-1 assume !(1 == ~E_6~0); 69882#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 69883#L1402-1 assume !(1 == ~E_8~0); 69573#L1407-1 assume !(1 == ~E_9~0); 69574#L1412-1 assume !(1 == ~E_10~0); 70616#L1417-1 assume !(1 == ~E_11~0); 70617#L1422-1 assume !(1 == ~E_12~0); 70855#L1427-1 assume { :end_inline_reset_delta_events } true; 69371#L1768-2 [2021-11-23 12:40:23,625 INFO L793 eck$LassoCheckResult]: Loop: 69371#L1768-2 assume !false; 69372#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70122#L1149 assume !false; 70508#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 70669#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 69767#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 69668#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69669#L976 assume !(0 != eval_~tmp~0#1); 70854#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70867#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70634#L1174-3 assume !(0 == ~M_E~0); 70628#L1174-5 assume !(0 == ~T1_E~0); 70364#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70365#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70556#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70191#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69530#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69531#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69776#L1209-3 assume !(0 == ~T8_E~0); 69198#L1214-3 assume !(0 == ~T9_E~0); 69199#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69960#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69961#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69978#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69979#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74906#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70299#L1249-3 assume !(0 == ~E_4~0); 70300#L1254-3 assume !(0 == ~E_5~0); 70794#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70417#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69385#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69386#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 70827#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69958#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69959#L1289-3 assume !(0 == ~E_12~0); 69947#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69613#L566-39 assume !(1 == ~m_pc~0); 69614#L566-41 is_master_triggered_~__retres1~0#1 := 0; 74902#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74901#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74900#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74899#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70818#L585-39 assume !(1 == ~t1_pc~0); 69622#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 69623#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69698#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69699#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70530#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70212#L604-39 assume 1 == ~t2_pc~0; 70213#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69837#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69838#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70262#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70263#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69817#L623-39 assume !(1 == ~t3_pc~0); 69215#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 69216#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70514#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69665#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69666#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70457#L642-39 assume 1 == ~t4_pc~0; 70017#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70018#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69537#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69538#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70668#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69586#L661-39 assume 1 == ~t5_pc~0; 69587#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69223#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70606#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70607#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70518#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70519#L680-39 assume 1 == ~t6_pc~0; 69281#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69282#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70442#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69749#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69750#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70799#L699-39 assume 1 == ~t7_pc~0; 70193#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69913#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69914#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70620#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70745#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70743#L718-39 assume 1 == ~t8_pc~0; 70105#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70106#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70038#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70039#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 70349#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70317#L737-39 assume 1 == ~t9_pc~0; 69729#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69730#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70025#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70828#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70722#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70659#L756-39 assume !(1 == ~t10_pc~0); 70114#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 70115#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69860#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69861#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69995#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69326#L775-39 assume !(1 == ~t11_pc~0); 69328#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 69989#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69990#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70897#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 70410#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70043#L794-39 assume 1 == ~t12_pc~0; 69728#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69721#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70569#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70464#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69270#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69271#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70775#L1307-5 assume !(1 == ~T1_E~0); 70776#L1312-3 assume !(1 == ~T2_E~0); 70911#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70482#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70483#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69403#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69375#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69376#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70134#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70260#L1352-3 assume !(1 == ~T10_E~0); 70261#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70727#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70896#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70887#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69210#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69211#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69844#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69845#L1392-3 assume !(1 == ~E_6~0); 70579#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70848#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70228#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69492#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69493#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 70150#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 70151#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 69500#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 69501#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 70388#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 70232#L1787 assume !(0 == start_simulation_~tmp~3#1); 70233#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 70784#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 69471#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 70280#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 70281#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69825#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69826#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 69827#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 69371#L1768-2 [2021-11-23 12:40:23,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:23,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1086873495, now seen corresponding path program 1 times [2021-11-23 12:40:23,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:23,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864389659] [2021-11-23 12:40:23,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:23,627 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:23,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:23,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:23,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:23,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864389659] [2021-11-23 12:40:23,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864389659] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:23,669 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:23,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 12:40:23,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490137408] [2021-11-23 12:40:23,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:23,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:23,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:23,670 INFO L85 PathProgramCache]: Analyzing trace with hash 414359176, now seen corresponding path program 1 times [2021-11-23 12:40:23,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:23,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127724068] [2021-11-23 12:40:23,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:23,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:23,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:23,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:23,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:23,709 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127724068] [2021-11-23 12:40:23,709 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127724068] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:23,709 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:23,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:23,710 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548999772] [2021-11-23 12:40:23,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:23,710 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:23,710 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:23,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 12:40:23,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-23 12:40:23,711 INFO L87 Difference]: Start difference. First operand 5835 states and 8492 transitions. cyclomatic complexity: 2659 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:24,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:24,201 INFO L93 Difference]: Finished difference Result 16236 states and 23625 transitions. [2021-11-23 12:40:24,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-23 12:40:24,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16236 states and 23625 transitions. [2021-11-23 12:40:24,279 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15874 [2021-11-23 12:40:24,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16236 states to 16236 states and 23625 transitions. [2021-11-23 12:40:24,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16236 [2021-11-23 12:40:24,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16236 [2021-11-23 12:40:24,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16236 states and 23625 transitions. [2021-11-23 12:40:24,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:24,372 INFO L681 BuchiCegarLoop]: Abstraction has 16236 states and 23625 transitions. [2021-11-23 12:40:24,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16236 states and 23625 transitions. [2021-11-23 12:40:24,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16236 to 5994. [2021-11-23 12:40:24,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5994 states, 5994 states have (on average 1.4432766099432766) internal successors, (8651), 5993 states have internal predecessors, (8651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:24,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5994 states to 5994 states and 8651 transitions. [2021-11-23 12:40:24,508 INFO L704 BuchiCegarLoop]: Abstraction has 5994 states and 8651 transitions. [2021-11-23 12:40:24,508 INFO L587 BuchiCegarLoop]: Abstraction has 5994 states and 8651 transitions. [2021-11-23 12:40:24,509 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-23 12:40:24,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5994 states and 8651 transitions. [2021-11-23 12:40:24,526 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5830 [2021-11-23 12:40:24,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:24,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:24,530 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:24,530 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:24,530 INFO L791 eck$LassoCheckResult]: Stem: 92063#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 92064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 93031#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92438#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92216#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 92217#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92314#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92649#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92785#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92786#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91503#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 91504#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 92714#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 92109#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 92110#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 92016#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 92017#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 92434#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91750#L1174 assume !(0 == ~M_E~0); 91751#L1174-2 assume !(0 == ~T1_E~0); 91601#L1179-1 assume !(0 == ~T2_E~0); 91501#L1184-1 assume !(0 == ~T3_E~0); 91502#L1189-1 assume !(0 == ~T4_E~0); 91541#L1194-1 assume !(0 == ~T5_E~0); 91643#L1199-1 assume !(0 == ~T6_E~0); 92586#L1204-1 assume !(0 == ~T7_E~0); 92501#L1209-1 assume !(0 == ~T8_E~0); 92502#L1214-1 assume !(0 == ~T9_E~0); 92932#L1219-1 assume !(0 == ~T10_E~0); 93058#L1224-1 assume !(0 == ~T11_E~0); 91871#L1229-1 assume !(0 == ~T12_E~0); 91426#L1234-1 assume !(0 == ~E_1~0); 91427#L1239-1 assume !(0 == ~E_2~0); 91460#L1244-1 assume !(0 == ~E_3~0); 91461#L1249-1 assume !(0 == ~E_4~0); 92132#L1254-1 assume !(0 == ~E_5~0); 91359#L1259-1 assume !(0 == ~E_6~0); 91317#L1264-1 assume !(0 == ~E_7~0); 91318#L1269-1 assume !(0 == ~E_8~0); 93072#L1274-1 assume !(0 == ~E_9~0); 92968#L1279-1 assume !(0 == ~E_10~0); 91544#L1284-1 assume !(0 == ~E_11~0); 91545#L1289-1 assume !(0 == ~E_12~0); 92185#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92186#L566 assume !(1 == ~m_pc~0); 92646#L566-2 is_master_triggered_~__retres1~0#1 := 0; 92647#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92531#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92532#L1455 assume !(0 != activate_threads_~tmp~1#1); 91777#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91778#L585 assume !(1 == ~t1_pc~0); 91962#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91963#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92466#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 92467#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 93005#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93001#L604 assume !(1 == ~t2_pc~0); 92552#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92553#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92981#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92907#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 92742#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92743#L623 assume 1 == ~t3_pc~0; 91961#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91297#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92113#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 92114#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 92780#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91331#L642 assume !(1 == ~t4_pc~0); 91332#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91796#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91797#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 91400#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 91401#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92564#L661 assume 1 == ~t5_pc~0; 91564#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 91565#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91524#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 91525#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 92596#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92597#L680 assume !(1 == ~t6_pc~0); 91996#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 91997#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92264#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 92265#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 92856#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 92999#L699 assume 1 == ~t7_pc~0; 92410#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 92411#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91552#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91553#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 92297#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 92187#L718 assume !(1 == ~t8_pc~0); 92188#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 91539#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91540#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91582#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 91583#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91717#L737 assume 1 == ~t9_pc~0; 92633#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 91856#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 92495#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 92496#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 92034#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 92035#L756 assume 1 == ~t10_pc~0; 92661#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 92286#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91261#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91262#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 91838#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 91839#L775 assume !(1 == ~t11_pc~0); 92097#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 92098#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91711#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 91472#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 91473#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 91662#L794 assume 1 == ~t12_pc~0; 91499#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 91477#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 92736#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 91627#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 91628#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92116#L1307 assume !(1 == ~M_E~0); 92117#L1307-2 assume !(1 == ~T1_E~0); 92228#L1312-1 assume !(1 == ~T2_E~0); 92146#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92147#L1322-1 assume !(1 == ~T4_E~0); 91847#L1327-1 assume !(1 == ~T5_E~0); 91848#L1332-1 assume !(1 == ~T6_E~0); 92415#L1337-1 assume !(1 == ~T7_E~0); 92370#L1342-1 assume !(1 == ~T8_E~0); 92371#L1347-1 assume !(1 == ~T9_E~0); 92810#L1352-1 assume !(1 == ~T10_E~0); 92670#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 92014#L1362-1 assume !(1 == ~T12_E~0); 92015#L1367-1 assume !(1 == ~E_1~0); 91644#L1372-1 assume !(1 == ~E_2~0); 91645#L1377-1 assume !(1 == ~E_3~0); 91944#L1382-1 assume !(1 == ~E_4~0); 91945#L1387-1 assume !(1 == ~E_5~0); 92554#L1392-1 assume !(1 == ~E_6~0); 91966#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 91967#L1402-1 assume !(1 == ~E_8~0); 91655#L1407-1 assume !(1 == ~E_9~0); 91656#L1412-1 assume !(1 == ~E_10~0); 92734#L1417-1 assume !(1 == ~E_11~0); 92735#L1422-1 assume !(1 == ~E_12~0); 92993#L1427-1 assume { :end_inline_reset_delta_events } true; 91456#L1768-2 [2021-11-23 12:40:24,531 INFO L793 eck$LassoCheckResult]: Loop: 91456#L1768-2 assume !false; 91457#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92206#L1149 assume !false; 92621#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 92791#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 91853#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 91755#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 91756#L976 assume !(0 != eval_~tmp~0#1); 92989#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93015#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92756#L1174-3 assume !(0 == ~M_E~0); 92747#L1174-5 assume !(0 == ~T1_E~0); 92471#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92472#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 92671#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92281#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91616#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91617#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91862#L1209-3 assume !(0 == ~T8_E~0); 91282#L1214-3 assume !(0 == ~T9_E~0); 91283#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 92358#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96783#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96782#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 91464#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91465#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91917#L1249-3 assume !(0 == ~E_4~0); 92402#L1254-3 assume !(0 == ~E_5~0); 92928#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92529#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91470#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 91471#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 92966#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 92044#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 92045#L1289-3 assume !(0 == ~E_12~0); 92033#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91697#L566-39 assume !(1 == ~m_pc~0); 91698#L566-41 is_master_triggered_~__retres1~0#1 := 0; 92325#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92326#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92934#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 92935#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92956#L585-39 assume !(1 == ~t1_pc~0); 92957#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 97248#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97247#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97246#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97245#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92304#L604-39 assume 1 == ~t2_pc~0; 92305#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 97243#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97241#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97239#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97238#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97237#L623-39 assume !(1 == ~t3_pc~0); 97235#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 97234#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97233#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97232#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97231#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97230#L642-39 assume !(1 == ~t4_pc~0); 97229#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 97227#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97225#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97223#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97222#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97221#L661-39 assume !(1 == ~t5_pc~0); 97219#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 97218#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97217#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97216#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 97215#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97214#L680-39 assume !(1 == ~t6_pc~0); 97213#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 97209#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97195#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97194#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97192#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97191#L699-39 assume !(1 == ~t7_pc~0); 97189#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 97188#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97187#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97186#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 97185#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97184#L718-39 assume !(1 == ~t8_pc~0); 97183#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 97181#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97180#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97179#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 97178#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97177#L737-39 assume 1 == ~t9_pc~0; 97175#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 97174#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97173#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93030#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 92847#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 92781#L756-39 assume !(1 == ~t10_pc~0); 92203#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 92204#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91946#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91947#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 92081#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 91413#L775-39 assume !(1 == ~t11_pc~0); 91415#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 92075#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 92076#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93053#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 92522#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 92131#L794-39 assume !(1 == ~t12_pc~0); 91811#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 91812#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96973#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96972#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 96971#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96970#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 96969#L1307-5 assume !(1 == ~T1_E~0); 96968#L1312-3 assume !(1 == ~T2_E~0); 96960#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96959#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96958#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96890#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91462#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91463#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 92220#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 92363#L1352-3 assume !(1 == ~T10_E~0); 92364#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 96836#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96829#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 96819#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96677#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96676#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96675#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96674#L1392-3 assume !(1 == ~E_6~0); 96673#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 96672#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 96671#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 96567#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 92881#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 92239#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 92240#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 91588#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 91589#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 92499#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 92330#L1787 assume !(0 == start_simulation_~tmp~3#1); 92331#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 92917#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 91557#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 92381#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 92382#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 91911#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 91912#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 91913#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 91456#L1768-2 [2021-11-23 12:40:24,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:24,532 INFO L85 PathProgramCache]: Analyzing trace with hash 92179797, now seen corresponding path program 1 times [2021-11-23 12:40:24,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:24,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712786860] [2021-11-23 12:40:24,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:24,533 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:24,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:24,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:24,569 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:24,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712786860] [2021-11-23 12:40:24,570 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1712786860] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:24,570 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:24,570 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:24,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371732857] [2021-11-23 12:40:24,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:24,571 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:24,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:24,571 INFO L85 PathProgramCache]: Analyzing trace with hash -1338459710, now seen corresponding path program 1 times [2021-11-23 12:40:24,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:24,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681863847] [2021-11-23 12:40:24,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:24,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:24,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:24,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:24,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:24,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681863847] [2021-11-23 12:40:24,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681863847] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:24,609 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:24,609 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:24,609 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821592222] [2021-11-23 12:40:24,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:24,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:24,610 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:24,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:24,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:24,611 INFO L87 Difference]: Start difference. First operand 5994 states and 8651 transitions. cyclomatic complexity: 2659 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:24,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:24,902 INFO L93 Difference]: Finished difference Result 14448 states and 20711 transitions. [2021-11-23 12:40:24,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:24,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14448 states and 20711 transitions. [2021-11-23 12:40:24,967 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14080 [2021-11-23 12:40:25,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14448 states to 14448 states and 20711 transitions. [2021-11-23 12:40:25,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14448 [2021-11-23 12:40:25,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14448 [2021-11-23 12:40:25,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14448 states and 20711 transitions. [2021-11-23 12:40:25,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:25,202 INFO L681 BuchiCegarLoop]: Abstraction has 14448 states and 20711 transitions. [2021-11-23 12:40:25,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14448 states and 20711 transitions. [2021-11-23 12:40:25,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14448 to 11385. [2021-11-23 12:40:25,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11385 states, 11385 states have (on average 1.4375054896794026) internal successors, (16366), 11384 states have internal predecessors, (16366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:25,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11385 states to 11385 states and 16366 transitions. [2021-11-23 12:40:25,379 INFO L704 BuchiCegarLoop]: Abstraction has 11385 states and 16366 transitions. [2021-11-23 12:40:25,379 INFO L587 BuchiCegarLoop]: Abstraction has 11385 states and 16366 transitions. [2021-11-23 12:40:25,379 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-23 12:40:25,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11385 states and 16366 transitions. [2021-11-23 12:40:25,415 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11220 [2021-11-23 12:40:25,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:25,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:25,419 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:25,419 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:25,420 INFO L791 eck$LassoCheckResult]: Stem: 112523#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 112524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 113469#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112887#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112673#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 112674#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112763#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113105#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113234#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113235#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111951#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111952#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 113164#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 112566#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112567#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112476#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 112477#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112882#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112197#L1174 assume !(0 == ~M_E~0); 112198#L1174-2 assume !(0 == ~T1_E~0); 112049#L1179-1 assume !(0 == ~T2_E~0); 111949#L1184-1 assume !(0 == ~T3_E~0); 111950#L1189-1 assume !(0 == ~T4_E~0); 111989#L1194-1 assume !(0 == ~T5_E~0); 112091#L1199-1 assume !(0 == ~T6_E~0); 113038#L1204-1 assume !(0 == ~T7_E~0); 112949#L1209-1 assume !(0 == ~T8_E~0); 112950#L1214-1 assume !(0 == ~T9_E~0); 113381#L1219-1 assume !(0 == ~T10_E~0); 113495#L1224-1 assume !(0 == ~T11_E~0); 112326#L1229-1 assume !(0 == ~T12_E~0); 111877#L1234-1 assume !(0 == ~E_1~0); 111878#L1239-1 assume !(0 == ~E_2~0); 111911#L1244-1 assume !(0 == ~E_3~0); 111912#L1249-1 assume !(0 == ~E_4~0); 112589#L1254-1 assume !(0 == ~E_5~0); 111808#L1259-1 assume !(0 == ~E_6~0); 111767#L1264-1 assume !(0 == ~E_7~0); 111768#L1269-1 assume !(0 == ~E_8~0); 113512#L1274-1 assume !(0 == ~E_9~0); 113416#L1279-1 assume !(0 == ~E_10~0); 111992#L1284-1 assume !(0 == ~E_11~0); 111993#L1289-1 assume !(0 == ~E_12~0); 112643#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112644#L566 assume !(1 == ~m_pc~0); 113099#L566-2 is_master_triggered_~__retres1~0#1 := 0; 113100#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112982#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112983#L1455 assume !(0 != activate_threads_~tmp~1#1); 112224#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112225#L585 assume !(1 == ~t1_pc~0); 112418#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112419#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112913#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112914#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 113445#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113443#L604 assume !(1 == ~t2_pc~0); 113004#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 113005#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112506#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112507#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 113193#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113194#L623 assume !(1 == ~t3_pc~0); 111747#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111748#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112570#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112571#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 113229#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111781#L642 assume !(1 == ~t4_pc~0); 111782#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 112245#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112246#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111851#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 111852#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113016#L661 assume 1 == ~t5_pc~0; 112012#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112013#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111972#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111973#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 113049#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113050#L680 assume !(1 == ~t6_pc~0); 112453#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 112454#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112719#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112720#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 113299#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113441#L699 assume 1 == ~t7_pc~0; 112861#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 112862#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112000#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112001#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 112749#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112645#L718 assume !(1 == ~t8_pc~0); 112646#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 111987#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111988#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112032#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 112033#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112164#L737 assume 1 == ~t9_pc~0; 113087#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112311#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112940#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 112941#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 112492#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112493#L756 assume 1 == ~t10_pc~0; 113112#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 112741#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111713#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111714#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 112289#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112290#L775 assume !(1 == ~t11_pc~0); 112554#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 112555#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112161#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111921#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 111922#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112109#L794 assume 1 == ~t12_pc~0; 111948#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111926#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 113186#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112077#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 112078#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112573#L1307 assume !(1 == ~M_E~0); 112574#L1307-2 assume !(1 == ~T1_E~0); 112688#L1312-1 assume !(1 == ~T2_E~0); 112604#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112605#L1322-1 assume !(1 == ~T4_E~0); 112300#L1327-1 assume !(1 == ~T5_E~0); 112301#L1332-1 assume !(1 == ~T6_E~0); 112865#L1337-1 assume !(1 == ~T7_E~0); 112817#L1342-1 assume !(1 == ~T8_E~0); 112818#L1347-1 assume !(1 == ~T9_E~0); 113260#L1352-1 assume !(1 == ~T10_E~0); 113121#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112472#L1362-1 assume !(1 == ~T12_E~0); 112473#L1367-1 assume !(1 == ~E_1~0); 112092#L1372-1 assume !(1 == ~E_2~0); 112093#L1377-1 assume !(1 == ~E_3~0); 112401#L1382-1 assume !(1 == ~E_4~0); 112402#L1387-1 assume !(1 == ~E_5~0); 113006#L1392-1 assume !(1 == ~E_6~0); 112424#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 112425#L1402-1 assume !(1 == ~E_8~0); 112107#L1407-1 assume !(1 == ~E_9~0); 112108#L1412-1 assume !(1 == ~E_10~0); 113184#L1417-1 assume !(1 == ~E_11~0); 113185#L1422-1 assume !(1 == ~E_12~0); 113439#L1427-1 assume { :end_inline_reset_delta_events } true; 111905#L1768-2 [2021-11-23 12:40:25,420 INFO L793 eck$LassoCheckResult]: Loop: 111905#L1768-2 assume !false; 111906#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112665#L1149 assume !false; 113074#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113241#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 112307#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 112208#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 112209#L976 assume !(0 != eval_~tmp~0#1); 113437#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113453#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113203#L1174-3 assume !(0 == ~M_E~0); 113196#L1174-5 assume !(0 == ~T1_E~0); 112919#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 112920#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 113122#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112736#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 112064#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 112065#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 112316#L1209-3 assume !(0 == ~T8_E~0); 111734#L1214-3 assume !(0 == ~T9_E~0); 111735#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 112504#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 112505#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 112522#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 111913#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 111914#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112377#L1249-3 assume !(0 == ~E_4~0); 112852#L1254-3 assume !(0 == ~E_5~0); 113375#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 112980#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 111919#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 111920#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 113411#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 112502#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 112503#L1289-3 assume !(0 == ~E_12~0); 112491#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112144#L566-39 assume !(1 == ~m_pc~0); 112145#L566-41 is_master_triggered_~__retres1~0#1 := 0; 112774#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112482#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112483#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 113059#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113060#L585-39 assume !(1 == ~t1_pc~0); 113401#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 123076#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123075#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123074#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123073#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123072#L604-39 assume 1 == ~t2_pc~0; 123071#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123069#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123067#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123064#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123063#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123062#L623-39 assume !(1 == ~t3_pc~0); 117137#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 123061#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123060#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123059#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123058#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123057#L642-39 assume !(1 == ~t4_pc~0); 123056#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 123054#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112071#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112072#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 113240#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112120#L661-39 assume 1 == ~t5_pc~0; 112121#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 111758#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113177#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113178#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113083#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113084#L680-39 assume 1 == ~t6_pc~0; 111815#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111816#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113007#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112287#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112288#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113382#L699-39 assume !(1 == ~t7_pc~0); 112739#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 112456#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112457#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113188#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 113316#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113314#L718-39 assume 1 == ~t8_pc~0; 112649#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 112650#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112581#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112582#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 112902#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112871#L737-39 assume 1 == ~t9_pc~0; 112266#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112267#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112568#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113412#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 113291#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113230#L756-39 assume !(1 == ~t10_pc~0); 112660#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 112661#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112403#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112404#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112538#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111862#L775-39 assume 1 == ~t11_pc~0; 111863#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112532#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112533#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 113493#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 112973#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112588#L794-39 assume !(1 == ~t12_pc~0); 112262#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 112263#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 122747#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122746#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 122745#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122744#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 122743#L1307-5 assume !(1 == ~T1_E~0); 122742#L1312-3 assume !(1 == ~T2_E~0); 122741#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122740#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122739#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122738#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 122737#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122736#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 122735#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122734#L1352-3 assume !(1 == ~T10_E~0); 122733#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122732#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 122731#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122230#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 122229#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122228#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122227#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122226#L1392-3 assume !(1 == ~E_6~0); 122225#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 122224#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 122223#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 122222#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 122221#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 122220#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 122219#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122217#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122205#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122204#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 112778#L1787 assume !(0 == start_simulation_~tmp~3#1); 112779#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113362#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 112005#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 112828#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 112829#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112368#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112369#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 112370#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 111905#L1768-2 [2021-11-23 12:40:25,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:25,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1014100148, now seen corresponding path program 1 times [2021-11-23 12:40:25,421 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:25,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662964889] [2021-11-23 12:40:25,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:25,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:25,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:25,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:25,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:25,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662964889] [2021-11-23 12:40:25,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [662964889] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:25,469 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:25,469 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-23 12:40:25,469 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927633891] [2021-11-23 12:40:25,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:25,472 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:25,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:25,473 INFO L85 PathProgramCache]: Analyzing trace with hash 910183366, now seen corresponding path program 1 times [2021-11-23 12:40:25,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:25,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058963039] [2021-11-23 12:40:25,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:25,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:25,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:25,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:25,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:25,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058963039] [2021-11-23 12:40:25,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058963039] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:25,513 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:25,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:25,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018165996] [2021-11-23 12:40:25,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:25,514 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:25,514 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:25,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-23 12:40:25,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-23 12:40:25,515 INFO L87 Difference]: Start difference. First operand 11385 states and 16366 transitions. cyclomatic complexity: 4983 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:25,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:25,694 INFO L93 Difference]: Finished difference Result 21752 states and 31151 transitions. [2021-11-23 12:40:25,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-23 12:40:25,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21752 states and 31151 transitions. [2021-11-23 12:40:25,789 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21568 [2021-11-23 12:40:25,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21752 states to 21752 states and 31151 transitions. [2021-11-23 12:40:25,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21752 [2021-11-23 12:40:25,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21752 [2021-11-23 12:40:25,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21752 states and 31151 transitions. [2021-11-23 12:40:25,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:25,923 INFO L681 BuchiCegarLoop]: Abstraction has 21752 states and 31151 transitions. [2021-11-23 12:40:26,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21752 states and 31151 transitions. [2021-11-23 12:40:26,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21752 to 21736. [2021-11-23 12:40:26,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21736 states, 21736 states have (on average 1.4324162679425838) internal successors, (31135), 21735 states have internal predecessors, (31135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:26,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21736 states to 21736 states and 31135 transitions. [2021-11-23 12:40:26,593 INFO L704 BuchiCegarLoop]: Abstraction has 21736 states and 31135 transitions. [2021-11-23 12:40:26,593 INFO L587 BuchiCegarLoop]: Abstraction has 21736 states and 31135 transitions. [2021-11-23 12:40:26,593 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-23 12:40:26,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21736 states and 31135 transitions. [2021-11-23 12:40:26,660 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21552 [2021-11-23 12:40:26,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:26,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:26,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:26,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:26,664 INFO L791 eck$LassoCheckResult]: Stem: 145655#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 145656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 146641#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 146022#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145811#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 145812#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145901#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 146247#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 146374#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 146375#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145095#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 145096#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 146305#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 145699#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 145700#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 145604#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 145605#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 146017#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145337#L1174 assume !(0 == ~M_E~0); 145338#L1174-2 assume !(0 == ~T1_E~0); 145189#L1179-1 assume !(0 == ~T2_E~0); 145093#L1184-1 assume !(0 == ~T3_E~0); 145094#L1189-1 assume !(0 == ~T4_E~0); 145133#L1194-1 assume !(0 == ~T5_E~0); 145231#L1199-1 assume !(0 == ~T6_E~0); 146176#L1204-1 assume !(0 == ~T7_E~0); 146088#L1209-1 assume !(0 == ~T8_E~0); 146089#L1214-1 assume !(0 == ~T9_E~0); 146543#L1219-1 assume !(0 == ~T10_E~0); 146668#L1224-1 assume !(0 == ~T11_E~0); 145461#L1229-1 assume !(0 == ~T12_E~0); 145021#L1234-1 assume !(0 == ~E_1~0); 145022#L1239-1 assume !(0 == ~E_2~0); 145055#L1244-1 assume !(0 == ~E_3~0); 145056#L1249-1 assume !(0 == ~E_4~0); 145726#L1254-1 assume !(0 == ~E_5~0); 144952#L1259-1 assume !(0 == ~E_6~0); 144911#L1264-1 assume !(0 == ~E_7~0); 144912#L1269-1 assume !(0 == ~E_8~0); 146691#L1274-1 assume !(0 == ~E_9~0); 146578#L1279-1 assume !(0 == ~E_10~0); 145136#L1284-1 assume !(0 == ~E_11~0); 145137#L1289-1 assume !(0 == ~E_12~0); 145780#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145781#L566 assume !(1 == ~m_pc~0); 146241#L566-2 is_master_triggered_~__retres1~0#1 := 0; 146242#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146121#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146122#L1455 assume !(0 != activate_threads_~tmp~1#1); 145364#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145365#L585 assume !(1 == ~t1_pc~0); 145549#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145550#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146049#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 146050#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 146616#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146614#L604 assume !(1 == ~t2_pc~0); 146141#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 146142#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146705#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146509#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 146335#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 146336#L623 assume !(1 == ~t3_pc~0); 144891#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144892#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145703#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 145704#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 146370#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144925#L642 assume !(1 == ~t4_pc~0); 144926#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 145383#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145384#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144995#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 144996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 146154#L661 assume !(1 == ~t5_pc~0); 146308#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 146039#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145116#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 145117#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 146187#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 146188#L680 assume !(1 == ~t6_pc~0); 145583#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 145584#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145856#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 145857#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 146450#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146612#L699 assume 1 == ~t7_pc~0; 145996#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 145997#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 145144#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 145145#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 145887#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 145782#L718 assume !(1 == ~t8_pc~0); 145783#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 145131#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 145132#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 145172#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 145173#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 145303#L737 assume 1 == ~t9_pc~0; 146227#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 145446#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146078#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 146079#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 145623#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 145624#L756 assume 1 == ~t10_pc~0; 146254#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 145878#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144857#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144858#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 145427#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145428#L775 assume !(1 == ~t11_pc~0); 145687#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 145688#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 145300#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 145065#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 145066#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 145249#L794 assume 1 == ~t12_pc~0; 145092#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 145070#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 146328#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 145217#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 145218#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145706#L1307 assume !(1 == ~M_E~0); 145707#L1307-2 assume !(1 == ~T1_E~0); 145826#L1312-1 assume !(1 == ~T2_E~0); 145740#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145741#L1322-1 assume !(1 == ~T4_E~0); 145436#L1327-1 assume !(1 == ~T5_E~0); 145437#L1332-1 assume !(1 == ~T6_E~0); 146000#L1337-1 assume !(1 == ~T7_E~0); 145954#L1342-1 assume !(1 == ~T8_E~0); 145955#L1347-1 assume !(1 == ~T9_E~0); 146406#L1352-1 assume !(1 == ~T10_E~0); 146264#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 145600#L1362-1 assume !(1 == ~T12_E~0); 145601#L1367-1 assume !(1 == ~E_1~0); 145232#L1372-1 assume !(1 == ~E_2~0); 145233#L1377-1 assume !(1 == ~E_3~0); 145532#L1382-1 assume !(1 == ~E_4~0); 145533#L1387-1 assume !(1 == ~E_5~0); 146143#L1392-1 assume !(1 == ~E_6~0); 145555#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 145556#L1402-1 assume !(1 == ~E_8~0); 145247#L1407-1 assume !(1 == ~E_9~0); 145248#L1412-1 assume !(1 == ~E_10~0); 146326#L1417-1 assume !(1 == ~E_11~0); 146327#L1422-1 assume !(1 == ~E_12~0); 146608#L1427-1 assume { :end_inline_reset_delta_events } true; 146609#L1768-2 [2021-11-23 12:40:26,665 INFO L793 eck$LassoCheckResult]: Loop: 146609#L1768-2 assume !false; 153370#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 153358#L1149 assume !false; 153357#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 152938#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 152925#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 152916#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 152912#L976 assume !(0 != eval_~tmp~0#1); 152913#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 165733#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 165731#L1174-3 assume !(0 == ~M_E~0); 165729#L1174-5 assume !(0 == ~T1_E~0); 165727#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 165725#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 165723#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 165721#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 165719#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 165717#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 165715#L1209-3 assume !(0 == ~T8_E~0); 165713#L1214-3 assume !(0 == ~T9_E~0); 165711#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 165709#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 165707#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 165705#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 165703#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 165701#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 165699#L1249-3 assume !(0 == ~E_4~0); 165697#L1254-3 assume !(0 == ~E_5~0); 165695#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 165693#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 165691#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 165689#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 165687#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 165685#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 165683#L1289-3 assume !(0 == ~E_12~0); 165681#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165679#L566-39 assume !(1 == ~m_pc~0); 165677#L566-41 is_master_triggered_~__retres1~0#1 := 0; 165675#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165673#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 165671#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 165669#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165667#L585-39 assume !(1 == ~t1_pc~0); 152073#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 165665#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 165663#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 165661#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 165659#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 165657#L604-39 assume !(1 == ~t2_pc~0); 146528#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 145511#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145512#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 165648#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 165644#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161813#L623-39 assume !(1 == ~t3_pc~0); 161809#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 161805#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161801#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 161796#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 161789#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161783#L642-39 assume 1 == ~t4_pc~0; 161776#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 161769#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161764#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 161760#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 161755#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161749#L661-39 assume !(1 == ~t5_pc~0); 161743#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 161736#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161730#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 161725#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 161721#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 161717#L680-39 assume 1 == ~t6_pc~0; 161710#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 161704#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161699#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 161694#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 161688#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161681#L699-39 assume !(1 == ~t7_pc~0); 161674#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 161668#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161663#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 161658#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 161652#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161646#L718-39 assume 1 == ~t8_pc~0; 161639#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 161633#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161627#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 161621#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 161615#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 161609#L737-39 assume 1 == ~t9_pc~0; 161604#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 161598#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 161594#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 161590#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 161585#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 161580#L756-39 assume 1 == ~t10_pc~0; 161574#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 161567#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 161562#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 161557#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 161551#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 161545#L775-39 assume !(1 == ~t11_pc~0); 161538#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 161531#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 161526#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 161521#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 161515#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 154285#L794-39 assume 1 == ~t12_pc~0; 154282#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 154279#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 154277#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 154275#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 154273#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154271#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 154268#L1307-5 assume !(1 == ~T1_E~0); 154266#L1312-3 assume !(1 == ~T2_E~0); 154264#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 154262#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 154260#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 154258#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 154256#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 154254#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 154252#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 154250#L1352-3 assume !(1 == ~T10_E~0); 154248#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 154246#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 154244#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 154242#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 154240#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154238#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 154236#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154234#L1392-3 assume !(1 == ~E_6~0); 154232#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 154230#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 154228#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 154226#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 154224#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 154222#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 154220#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 154215#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 154202#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 154200#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 154198#L1787 assume !(0 == start_simulation_~tmp~3#1); 154196#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 153457#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 153449#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 153445#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 153443#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 153441#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 153440#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 153392#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 146609#L1768-2 [2021-11-23 12:40:26,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:26,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1613747565, now seen corresponding path program 1 times [2021-11-23 12:40:26,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:26,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685572274] [2021-11-23 12:40:26,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:26,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:26,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:26,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:26,720 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:26,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685572274] [2021-11-23 12:40:26,720 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685572274] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:26,720 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:26,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:26,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173627337] [2021-11-23 12:40:26,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:26,721 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:26,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:26,722 INFO L85 PathProgramCache]: Analyzing trace with hash -639475068, now seen corresponding path program 1 times [2021-11-23 12:40:26,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:26,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917568319] [2021-11-23 12:40:26,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:26,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:26,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:26,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:26,768 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:26,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917568319] [2021-11-23 12:40:26,768 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917568319] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:26,768 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:26,769 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:26,769 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564371764] [2021-11-23 12:40:26,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:26,769 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:26,770 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:26,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:26,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:26,771 INFO L87 Difference]: Start difference. First operand 21736 states and 31135 transitions. cyclomatic complexity: 9403 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:27,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:27,470 INFO L93 Difference]: Finished difference Result 52527 states and 74796 transitions. [2021-11-23 12:40:27,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:27,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52527 states and 74796 transitions. [2021-11-23 12:40:27,860 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 51508 [2021-11-23 12:40:28,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52527 states to 52527 states and 74796 transitions. [2021-11-23 12:40:28,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52527 [2021-11-23 12:40:28,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52527 [2021-11-23 12:40:28,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52527 states and 74796 transitions. [2021-11-23 12:40:28,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:28,239 INFO L681 BuchiCegarLoop]: Abstraction has 52527 states and 74796 transitions. [2021-11-23 12:40:28,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52527 states and 74796 transitions. [2021-11-23 12:40:28,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52527 to 41583. [2021-11-23 12:40:28,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41583 states, 41583 states have (on average 1.4277950123848688) internal successors, (59372), 41582 states have internal predecessors, (59372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:29,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41583 states to 41583 states and 59372 transitions. [2021-11-23 12:40:29,161 INFO L704 BuchiCegarLoop]: Abstraction has 41583 states and 59372 transitions. [2021-11-23 12:40:29,161 INFO L587 BuchiCegarLoop]: Abstraction has 41583 states and 59372 transitions. [2021-11-23 12:40:29,161 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-23 12:40:29,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41583 states and 59372 transitions. [2021-11-23 12:40:29,274 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 41376 [2021-11-23 12:40:29,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:29,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:29,279 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:29,279 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:29,280 INFO L791 eck$LassoCheckResult]: Stem: 219931#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 219932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 220929#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 220301#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 220083#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 220084#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220179#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 220529#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220677#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220678#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 219369#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 219370#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220598#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 219977#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 219978#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 219882#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 219883#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 220297#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 219612#L1174 assume !(0 == ~M_E~0); 219613#L1174-2 assume !(0 == ~T1_E~0); 219464#L1179-1 assume !(0 == ~T2_E~0); 219367#L1184-1 assume !(0 == ~T3_E~0); 219368#L1189-1 assume !(0 == ~T4_E~0); 219407#L1194-1 assume !(0 == ~T5_E~0); 219505#L1199-1 assume !(0 == ~T6_E~0); 220460#L1204-1 assume !(0 == ~T7_E~0); 220366#L1209-1 assume !(0 == ~T8_E~0); 220367#L1214-1 assume !(0 == ~T9_E~0); 220833#L1219-1 assume !(0 == ~T10_E~0); 220962#L1224-1 assume !(0 == ~T11_E~0); 219734#L1229-1 assume !(0 == ~T12_E~0); 219293#L1234-1 assume !(0 == ~E_1~0); 219294#L1239-1 assume !(0 == ~E_2~0); 219327#L1244-1 assume !(0 == ~E_3~0); 219328#L1249-1 assume !(0 == ~E_4~0); 220000#L1254-1 assume !(0 == ~E_5~0); 219226#L1259-1 assume !(0 == ~E_6~0); 219185#L1264-1 assume !(0 == ~E_7~0); 219186#L1269-1 assume !(0 == ~E_8~0); 220982#L1274-1 assume !(0 == ~E_9~0); 220868#L1279-1 assume !(0 == ~E_10~0); 219410#L1284-1 assume !(0 == ~E_11~0); 219411#L1289-1 assume !(0 == ~E_12~0); 220053#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220054#L566 assume !(1 == ~m_pc~0); 220524#L566-2 is_master_triggered_~__retres1~0#1 := 0; 220525#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220398#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220399#L1455 assume !(0 != activate_threads_~tmp~1#1); 219639#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219640#L585 assume !(1 == ~t1_pc~0); 219825#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 219826#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220330#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220331#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 220902#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220900#L604 assume !(1 == ~t2_pc~0); 220421#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220422#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220882#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220802#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 220627#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220628#L623 assume !(1 == ~t3_pc~0); 219164#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 219165#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 219981#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219982#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 220671#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 219199#L642 assume !(1 == ~t4_pc~0); 219200#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 219658#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 219659#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 219267#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 219268#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220435#L661 assume !(1 == ~t5_pc~0); 220604#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 220320#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219390#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 219391#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 220470#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220471#L680 assume !(1 == ~t6_pc~0); 219862#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 219863#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220129#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220130#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 220748#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220897#L699 assume !(1 == ~t7_pc~0); 220898#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 220549#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 219418#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 219419#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 220163#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220055#L718 assume !(1 == ~t8_pc~0); 220056#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 219405#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219406#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 219445#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 219446#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 219579#L737 assume 1 == ~t9_pc~0; 220511#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 219719#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 220357#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220358#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 219902#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 219903#L756 assume 1 == ~t10_pc~0; 220540#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 220154#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219130#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 219131#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 219701#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 219702#L775 assume !(1 == ~t11_pc~0); 219965#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 219966#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 219573#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 219339#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 219340#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 219524#L794 assume 1 == ~t12_pc~0; 219365#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 219344#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 220623#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 219490#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 219491#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219984#L1307 assume !(1 == ~M_E~0); 219985#L1307-2 assume !(1 == ~T1_E~0); 220098#L1312-1 assume !(1 == ~T2_E~0); 220013#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 220014#L1322-1 assume !(1 == ~T4_E~0); 219710#L1327-1 assume !(1 == ~T5_E~0); 219711#L1332-1 assume !(1 == ~T6_E~0); 220278#L1337-1 assume !(1 == ~T7_E~0); 220231#L1342-1 assume !(1 == ~T8_E~0); 220232#L1347-1 assume !(1 == ~T9_E~0); 220707#L1352-1 assume !(1 == ~T10_E~0); 220550#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 219880#L1362-1 assume !(1 == ~T12_E~0); 219881#L1367-1 assume !(1 == ~E_1~0); 219506#L1372-1 assume !(1 == ~E_2~0); 219507#L1377-1 assume !(1 == ~E_3~0); 219808#L1382-1 assume !(1 == ~E_4~0); 219809#L1387-1 assume !(1 == ~E_5~0); 220423#L1392-1 assume !(1 == ~E_6~0); 219829#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 219830#L1402-1 assume !(1 == ~E_8~0); 219518#L1407-1 assume !(1 == ~E_9~0); 219519#L1412-1 assume !(1 == ~E_10~0); 220621#L1417-1 assume !(1 == ~E_11~0); 220622#L1422-1 assume !(1 == ~E_12~0); 220894#L1427-1 assume { :end_inline_reset_delta_events } true; 220895#L1768-2 [2021-11-23 12:40:29,280 INFO L793 eck$LassoCheckResult]: Loop: 220895#L1768-2 assume !false; 254555#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 254550#L1149 assume !false; 253988#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 253662#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 253655#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 253653#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 253652#L976 assume !(0 != eval_~tmp~0#1); 220919#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220920#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 220644#L1174-3 assume !(0 == ~M_E~0); 220645#L1174-5 assume !(0 == ~T1_E~0); 220335#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220336#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220551#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 220146#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 219479#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 219480#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 219725#L1209-3 assume !(0 == ~T8_E~0); 219151#L1214-3 assume !(0 == ~T9_E~0); 219152#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 220220#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 260679#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 260678#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 260677#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 260676#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 260675#L1249-3 assume !(0 == ~E_4~0); 260674#L1254-3 assume !(0 == ~E_5~0); 260673#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 260672#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 260671#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 260670#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 260669#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 260668#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 260667#L1289-3 assume !(0 == ~E_12~0); 260665#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260663#L566-39 assume !(1 == ~m_pc~0); 220252#L566-41 is_master_triggered_~__retres1~0#1 := 0; 220189#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220190#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 260656#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 260654#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260652#L585-39 assume !(1 == ~t1_pc~0); 260276#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 260649#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258502#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 258503#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258497#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 258495#L604-39 assume !(1 == ~t2_pc~0); 258489#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 258487#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 258485#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258483#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 258479#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258478#L623-39 assume !(1 == ~t3_pc~0); 253493#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 258475#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 258473#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 258471#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 258469#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 258465#L642-39 assume !(1 == ~t4_pc~0); 258467#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 258459#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258458#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 258457#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 258456#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 258454#L661-39 assume !(1 == ~t5_pc~0); 258452#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 258450#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258448#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 258446#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 258444#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 258442#L680-39 assume 1 == ~t6_pc~0; 258439#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 258436#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 258434#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 258432#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 258430#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254831#L699-39 assume !(1 == ~t7_pc~0); 254829#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 254819#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 254816#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 254814#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 254812#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 254810#L718-39 assume 1 == ~t8_pc~0; 254807#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 254805#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 254802#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 254800#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 254798#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 254796#L737-39 assume 1 == ~t9_pc~0; 254775#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 254773#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 254771#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 254769#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 254767#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 254764#L756-39 assume 1 == ~t10_pc~0; 254762#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 254759#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 254757#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 254755#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 254751#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 254749#L775-39 assume 1 == ~t11_pc~0; 254739#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 254737#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 254735#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 254733#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 254731#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 254729#L794-39 assume 1 == ~t12_pc~0; 254727#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 254723#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 254721#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 254719#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 254717#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 254713#L1307-5 assume !(1 == ~T1_E~0); 254712#L1312-3 assume !(1 == ~T2_E~0); 254710#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 254708#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 254706#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 254704#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 254702#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 254699#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 254697#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 254695#L1352-3 assume !(1 == ~T10_E~0); 254693#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 254691#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 254689#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 254686#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 254684#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 254682#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 254680#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 254678#L1392-3 assume !(1 == ~E_6~0); 254676#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 254673#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 254671#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 254669#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 254667#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 254666#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 254665#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 254662#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 254649#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 254646#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 254643#L1787 assume !(0 == start_simulation_~tmp~3#1); 254640#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 254620#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 254612#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 254611#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 254610#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254609#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 254608#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 254607#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 220895#L1768-2 [2021-11-23 12:40:29,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:29,281 INFO L85 PathProgramCache]: Analyzing trace with hash 205978354, now seen corresponding path program 1 times [2021-11-23 12:40:29,281 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:29,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119201942] [2021-11-23 12:40:29,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:29,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:29,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:29,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:29,325 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:29,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119201942] [2021-11-23 12:40:29,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119201942] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:29,328 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:29,328 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:29,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356661705] [2021-11-23 12:40:29,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:29,329 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:29,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:29,330 INFO L85 PathProgramCache]: Analyzing trace with hash -535667772, now seen corresponding path program 1 times [2021-11-23 12:40:29,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:29,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484482996] [2021-11-23 12:40:29,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:29,331 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:29,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:29,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:29,369 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:29,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484482996] [2021-11-23 12:40:29,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484482996] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:29,369 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:29,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:29,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542620312] [2021-11-23 12:40:29,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:29,370 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:29,370 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:29,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:29,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:29,371 INFO L87 Difference]: Start difference. First operand 41583 states and 59372 transitions. cyclomatic complexity: 17793 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:30,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:30,153 INFO L93 Difference]: Finished difference Result 100174 states and 142217 transitions. [2021-11-23 12:40:30,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:30,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100174 states and 142217 transitions. [2021-11-23 12:40:30,720 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 98304 [2021-11-23 12:40:31,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100174 states to 100174 states and 142217 transitions. [2021-11-23 12:40:31,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100174 [2021-11-23 12:40:31,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100174 [2021-11-23 12:40:31,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100174 states and 142217 transitions. [2021-11-23 12:40:31,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:31,420 INFO L681 BuchiCegarLoop]: Abstraction has 100174 states and 142217 transitions. [2021-11-23 12:40:31,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100174 states and 142217 transitions. [2021-11-23 12:40:32,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100174 to 79582. [2021-11-23 12:40:32,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79582 states, 79582 states have (on average 1.4235505516322786) internal successors, (113289), 79581 states have internal predecessors, (113289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:32,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79582 states to 79582 states and 113289 transitions. [2021-11-23 12:40:32,872 INFO L704 BuchiCegarLoop]: Abstraction has 79582 states and 113289 transitions. [2021-11-23 12:40:32,872 INFO L587 BuchiCegarLoop]: Abstraction has 79582 states and 113289 transitions. [2021-11-23 12:40:32,872 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-23 12:40:32,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79582 states and 113289 transitions. [2021-11-23 12:40:33,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 79328 [2021-11-23 12:40:33,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:33,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:33,097 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:33,098 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:33,098 INFO L791 eck$LassoCheckResult]: Stem: 361704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 361705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 362742#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 362094#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 361863#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 361864#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 361957#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 362317#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 362463#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362464#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 361135#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 361136#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 362380#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 361749#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 361750#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 361655#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 361656#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 362089#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 361379#L1174 assume !(0 == ~M_E~0); 361380#L1174-2 assume !(0 == ~T1_E~0); 361229#L1179-1 assume !(0 == ~T2_E~0); 361133#L1184-1 assume !(0 == ~T3_E~0); 361134#L1189-1 assume !(0 == ~T4_E~0); 361172#L1194-1 assume !(0 == ~T5_E~0); 361271#L1199-1 assume !(0 == ~T6_E~0); 362245#L1204-1 assume !(0 == ~T7_E~0); 362152#L1209-1 assume !(0 == ~T8_E~0); 362153#L1214-1 assume !(0 == ~T9_E~0); 362632#L1219-1 assume !(0 == ~T10_E~0); 362785#L1224-1 assume !(0 == ~T11_E~0); 361504#L1229-1 assume !(0 == ~T12_E~0); 361062#L1234-1 assume !(0 == ~E_1~0); 361063#L1239-1 assume !(0 == ~E_2~0); 361095#L1244-1 assume !(0 == ~E_3~0); 361096#L1249-1 assume !(0 == ~E_4~0); 361776#L1254-1 assume !(0 == ~E_5~0); 360992#L1259-1 assume !(0 == ~E_6~0); 360951#L1264-1 assume !(0 == ~E_7~0); 360952#L1269-1 assume !(0 == ~E_8~0); 362812#L1274-1 assume !(0 == ~E_9~0); 362679#L1279-1 assume !(0 == ~E_10~0); 361175#L1284-1 assume !(0 == ~E_11~0); 361176#L1289-1 assume !(0 == ~E_12~0); 361832#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 361833#L566 assume !(1 == ~m_pc~0); 362311#L566-2 is_master_triggered_~__retres1~0#1 := 0; 362312#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362185#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362186#L1455 assume !(0 != activate_threads_~tmp~1#1); 361406#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361407#L585 assume !(1 == ~t1_pc~0); 361596#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 361597#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362120#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 362121#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 362718#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362714#L604 assume !(1 == ~t2_pc~0); 362207#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 362208#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362845#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362597#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 362417#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 362418#L623 assume !(1 == ~t3_pc~0); 360931#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 360932#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 361754#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 361755#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 362458#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 360965#L642 assume !(1 == ~t4_pc~0); 360966#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 361425#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 361426#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 361036#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 361037#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 362221#L661 assume !(1 == ~t5_pc~0); 362387#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 362111#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 361155#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361156#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 362257#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362258#L680 assume !(1 == ~t6_pc~0); 361631#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 361632#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 361910#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 361911#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 362538#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 362711#L699 assume !(1 == ~t7_pc~0); 362712#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 362335#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 361183#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 361184#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 361943#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 361834#L718 assume !(1 == ~t8_pc~0); 361835#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 361170#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 361171#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 361212#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 361213#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 361345#L737 assume !(1 == ~t9_pc~0); 361488#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 361489#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 362146#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 362147#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 361672#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 361673#L756 assume 1 == ~t10_pc~0; 362325#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 361934#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 360897#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 360898#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 361469#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 361470#L775 assume !(1 == ~t11_pc~0); 361737#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 361738#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 361342#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 361105#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 361106#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 361290#L794 assume 1 == ~t12_pc~0; 361132#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 361110#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 362410#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 361257#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 361258#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361757#L1307 assume !(1 == ~M_E~0); 361758#L1307-2 assume !(1 == ~T1_E~0); 361878#L1312-1 assume !(1 == ~T2_E~0); 361792#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 361793#L1322-1 assume !(1 == ~T4_E~0); 361479#L1327-1 assume !(1 == ~T5_E~0); 361480#L1332-1 assume !(1 == ~T6_E~0); 362063#L1337-1 assume !(1 == ~T7_E~0); 362013#L1342-1 assume !(1 == ~T8_E~0); 362014#L1347-1 assume !(1 == ~T9_E~0); 362493#L1352-1 assume !(1 == ~T10_E~0); 362336#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 361651#L1362-1 assume !(1 == ~T12_E~0); 361652#L1367-1 assume !(1 == ~E_1~0); 361272#L1372-1 assume !(1 == ~E_2~0); 361273#L1377-1 assume !(1 == ~E_3~0); 361579#L1382-1 assume !(1 == ~E_4~0); 361580#L1387-1 assume !(1 == ~E_5~0); 362209#L1392-1 assume !(1 == ~E_6~0); 361602#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 361603#L1402-1 assume !(1 == ~E_8~0); 361288#L1407-1 assume !(1 == ~E_9~0); 361289#L1412-1 assume !(1 == ~E_10~0); 362408#L1417-1 assume !(1 == ~E_11~0); 362409#L1422-1 assume !(1 == ~E_12~0); 362708#L1427-1 assume { :end_inline_reset_delta_events } true; 362709#L1768-2 [2021-11-23 12:40:33,099 INFO L793 eck$LassoCheckResult]: Loop: 362709#L1768-2 assume !false; 433821#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 433814#L1149 assume !false; 433812#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 433797#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 433790#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 433789#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 433785#L976 assume !(0 != eval_~tmp~0#1); 433786#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 440013#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 440012#L1174-3 assume !(0 == ~M_E~0); 440010#L1174-5 assume !(0 == ~T1_E~0); 440008#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 440006#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 440004#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 440002#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 440000#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 439998#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 439996#L1209-3 assume !(0 == ~T8_E~0); 439994#L1214-3 assume !(0 == ~T9_E~0); 439992#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 439990#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 439988#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 439986#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 439984#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 439982#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 439980#L1249-3 assume !(0 == ~E_4~0); 439978#L1254-3 assume !(0 == ~E_5~0); 439976#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 439974#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 439972#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 439970#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 439968#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 439966#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 439964#L1289-3 assume !(0 == ~E_12~0); 439962#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 439960#L566-39 assume !(1 == ~m_pc~0); 439958#L566-41 is_master_triggered_~__retres1~0#1 := 0; 439956#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 439954#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 439951#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439950#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 439949#L585-39 assume !(1 == ~t1_pc~0); 435182#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 439931#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 439928#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 439926#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439924#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 439917#L604-39 assume 1 == ~t2_pc~0; 439915#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 439916#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439921#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 439906#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 439904#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 361534#L623-39 assume !(1 == ~t3_pc~0); 361535#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 362029#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362291#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 361381#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 361382#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 362227#L642-39 assume !(1 == ~t4_pc~0); 361745#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 361744#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 361251#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 361252#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 362468#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 361300#L661-39 assume !(1 == ~t5_pc~0); 360938#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 360939#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362396#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 362397#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 362294#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362295#L680-39 assume 1 == ~t6_pc~0; 360999#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 361000#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 362210#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 361467#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 361468#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 362758#L699-39 assume !(1 == ~t7_pc~0); 434264#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 434261#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 434259#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 434255#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 434252#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 434249#L718-39 assume !(1 == ~t8_pc~0); 434246#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 434242#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 434198#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 434197#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 434195#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 434192#L737-39 assume !(1 == ~t9_pc~0); 398016#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 434187#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 434184#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 434180#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 434176#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 434173#L756-39 assume 1 == ~t10_pc~0; 434170#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 434166#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 434163#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434161#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 434159#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 434156#L775-39 assume 1 == ~t11_pc~0; 434152#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 434148#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 434144#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 434140#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 434134#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 434130#L794-39 assume 1 == ~t12_pc~0; 434126#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 434121#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 434116#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 434112#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 434108#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434104#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 434100#L1307-5 assume !(1 == ~T1_E~0); 434096#L1312-3 assume !(1 == ~T2_E~0); 434093#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 434089#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 434083#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 434079#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 434075#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 434071#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 434066#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 434062#L1352-3 assume !(1 == ~T10_E~0); 434057#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 434053#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 434049#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 434044#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 434038#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 434033#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 434027#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 434022#L1392-3 assume !(1 == ~E_6~0); 434017#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 434011#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 434005#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 433998#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 433993#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 433989#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 433985#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 433949#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 433931#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 433923#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 433865#L1787 assume !(0 == start_simulation_~tmp~3#1); 433862#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 433852#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 433844#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 433842#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 433840#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 433838#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 433836#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 433833#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 362709#L1768-2 [2021-11-23 12:40:33,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:33,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1524358703, now seen corresponding path program 1 times [2021-11-23 12:40:33,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:33,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881674007] [2021-11-23 12:40:33,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:33,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:33,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:33,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:33,168 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:33,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881674007] [2021-11-23 12:40:33,169 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881674007] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:33,169 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:33,169 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:33,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605853195] [2021-11-23 12:40:33,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:33,170 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:33,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:33,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1832939803, now seen corresponding path program 1 times [2021-11-23 12:40:33,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:33,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274993321] [2021-11-23 12:40:33,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:33,171 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:33,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:33,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:33,210 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:33,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274993321] [2021-11-23 12:40:33,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274993321] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:33,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:33,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:33,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449858376] [2021-11-23 12:40:33,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:33,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:33,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:33,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:33,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:33,213 INFO L87 Difference]: Start difference. First operand 79582 states and 113289 transitions. cyclomatic complexity: 33711 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:34,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:34,458 INFO L93 Difference]: Finished difference Result 191277 states and 270806 transitions. [2021-11-23 12:40:34,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:34,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191277 states and 270806 transitions. [2021-11-23 12:40:35,695 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 187712 [2021-11-23 12:40:36,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191277 states to 191277 states and 270806 transitions. [2021-11-23 12:40:36,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191277 [2021-11-23 12:40:36,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191277 [2021-11-23 12:40:36,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191277 states and 270806 transitions. [2021-11-23 12:40:36,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:36,701 INFO L681 BuchiCegarLoop]: Abstraction has 191277 states and 270806 transitions. [2021-11-23 12:40:36,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191277 states and 270806 transitions. [2021-11-23 12:40:38,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191277 to 152221. [2021-11-23 12:40:38,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152221 states, 152221 states have (on average 1.4196595739089877) internal successors, (216102), 152220 states have internal predecessors, (216102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:38,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152221 states to 152221 states and 216102 transitions. [2021-11-23 12:40:38,773 INFO L704 BuchiCegarLoop]: Abstraction has 152221 states and 216102 transitions. [2021-11-23 12:40:38,773 INFO L587 BuchiCegarLoop]: Abstraction has 152221 states and 216102 transitions. [2021-11-23 12:40:38,773 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-23 12:40:38,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152221 states and 216102 transitions. [2021-11-23 12:40:39,873 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 151872 [2021-11-23 12:40:39,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:39,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:39,878 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:39,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:39,881 INFO L791 eck$LassoCheckResult]: Stem: 632570#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 632571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 633597#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 632963#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 632729#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 632730#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 632827#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 633190#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 633329#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 633330#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 632003#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 632004#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 633251#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 632614#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 632615#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 632523#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 632524#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 632958#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 632246#L1174 assume !(0 == ~M_E~0); 632247#L1174-2 assume !(0 == ~T1_E~0); 632096#L1179-1 assume !(0 == ~T2_E~0); 632001#L1184-1 assume !(0 == ~T3_E~0); 632002#L1189-1 assume !(0 == ~T4_E~0); 632040#L1194-1 assume !(0 == ~T5_E~0); 632137#L1199-1 assume !(0 == ~T6_E~0); 633116#L1204-1 assume !(0 == ~T7_E~0); 633027#L1209-1 assume !(0 == ~T8_E~0); 633028#L1214-1 assume !(0 == ~T9_E~0); 633484#L1219-1 assume !(0 == ~T10_E~0); 633640#L1224-1 assume !(0 == ~T11_E~0); 632370#L1229-1 assume !(0 == ~T12_E~0); 631930#L1234-1 assume !(0 == ~E_1~0); 631931#L1239-1 assume !(0 == ~E_2~0); 631963#L1244-1 assume !(0 == ~E_3~0); 631964#L1249-1 assume !(0 == ~E_4~0); 632641#L1254-1 assume !(0 == ~E_5~0); 631861#L1259-1 assume !(0 == ~E_6~0); 631820#L1264-1 assume !(0 == ~E_7~0); 631821#L1269-1 assume !(0 == ~E_8~0); 633662#L1274-1 assume !(0 == ~E_9~0); 633528#L1279-1 assume !(0 == ~E_10~0); 632043#L1284-1 assume !(0 == ~E_11~0); 632044#L1289-1 assume !(0 == ~E_12~0); 632698#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 632699#L566 assume !(1 == ~m_pc~0); 633184#L566-2 is_master_triggered_~__retres1~0#1 := 0; 633185#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633059#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 633060#L1455 assume !(0 != activate_threads_~tmp~1#1); 632272#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 632273#L585 assume !(1 == ~t1_pc~0); 632462#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 632463#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 632990#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 632991#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 633572#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 633569#L604 assume !(1 == ~t2_pc~0); 633082#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 633083#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 633683#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 633458#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 633280#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633281#L623 assume !(1 == ~t3_pc~0); 631800#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 631801#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 632619#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 632620#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 633321#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631834#L642 assume !(1 == ~t4_pc~0); 631835#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 632293#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 632294#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 631904#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 631905#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633095#L661 assume !(1 == ~t5_pc~0); 633257#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 632981#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 632023#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 632024#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 633127#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633128#L680 assume !(1 == ~t6_pc~0); 632500#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 632501#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 632775#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 632776#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 633401#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 633566#L699 assume !(1 == ~t7_pc~0); 633567#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 633205#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 632051#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 632052#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 632812#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 632700#L718 assume !(1 == ~t8_pc~0); 632701#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 632038#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 632039#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 632080#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 632081#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 632213#L737 assume !(1 == ~t9_pc~0); 632354#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 632355#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 633019#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 633020#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 632539#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 632540#L756 assume !(1 == ~t10_pc~0); 632800#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 632801#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 631766#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 631767#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 632336#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 632337#L775 assume !(1 == ~t11_pc~0); 632602#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 632603#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 632210#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 631973#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 631974#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 632156#L794 assume 1 == ~t12_pc~0; 632000#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 631978#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 633276#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 632124#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 632125#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 632622#L1307 assume !(1 == ~M_E~0); 632623#L1307-2 assume !(1 == ~T1_E~0); 632744#L1312-1 assume !(1 == ~T2_E~0); 632656#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 632657#L1322-1 assume !(1 == ~T4_E~0); 632345#L1327-1 assume !(1 == ~T5_E~0); 632346#L1332-1 assume !(1 == ~T6_E~0); 632935#L1337-1 assume !(1 == ~T7_E~0); 632884#L1342-1 assume !(1 == ~T8_E~0); 632885#L1347-1 assume !(1 == ~T9_E~0); 633356#L1352-1 assume !(1 == ~T10_E~0); 633206#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 632519#L1362-1 assume !(1 == ~T12_E~0); 632520#L1367-1 assume !(1 == ~E_1~0); 632138#L1372-1 assume !(1 == ~E_2~0); 632139#L1377-1 assume !(1 == ~E_3~0); 632445#L1382-1 assume !(1 == ~E_4~0); 632446#L1387-1 assume !(1 == ~E_5~0); 633084#L1392-1 assume !(1 == ~E_6~0); 632469#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 632470#L1402-1 assume !(1 == ~E_8~0); 632154#L1407-1 assume !(1 == ~E_9~0); 632155#L1412-1 assume !(1 == ~E_10~0); 633274#L1417-1 assume !(1 == ~E_11~0); 633275#L1422-1 assume !(1 == ~E_12~0); 633563#L1427-1 assume { :end_inline_reset_delta_events } true; 633564#L1768-2 [2021-11-23 12:40:39,882 INFO L793 eck$LassoCheckResult]: Loop: 633564#L1768-2 assume !false; 736760#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 736752#L1149 assume !false; 736750#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 736648#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 736636#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 736629#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 736619#L976 assume !(0 != eval_~tmp~0#1); 736620#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 783541#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 783540#L1174-3 assume !(0 == ~M_E~0); 783539#L1174-5 assume !(0 == ~T1_E~0); 783538#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 783537#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 783535#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 783533#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 783531#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 783529#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 783527#L1209-3 assume !(0 == ~T8_E~0); 783525#L1214-3 assume !(0 == ~T9_E~0); 783524#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 783523#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 783521#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 783519#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 783517#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 783515#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 783514#L1249-3 assume !(0 == ~E_4~0); 783513#L1254-3 assume !(0 == ~E_5~0); 783511#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 783509#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 783507#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 783505#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 783503#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 783501#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 783499#L1289-3 assume !(0 == ~E_12~0); 783497#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 783495#L566-39 assume !(1 == ~m_pc~0); 783493#L566-41 is_master_triggered_~__retres1~0#1 := 0; 783491#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 783489#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 783487#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 783485#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783483#L585-39 assume !(1 == ~t1_pc~0); 769448#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 783482#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 783481#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 783479#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 783477#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 783476#L604-39 assume 1 == ~t2_pc~0; 783475#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 783473#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783471#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 783468#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 783467#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 756938#L623-39 assume !(1 == ~t3_pc~0); 756936#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 756934#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 756932#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 756929#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 756927#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 756925#L642-39 assume !(1 == ~t4_pc~0); 756923#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 756920#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 753331#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 753330#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 753329#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 753328#L661-39 assume !(1 == ~t5_pc~0); 753327#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 753326#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 753325#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 753324#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 753323#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 752985#L680-39 assume 1 == ~t6_pc~0; 752963#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 752954#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752943#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 752933#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 752927#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 742026#L699-39 assume !(1 == ~t7_pc~0); 742023#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 742020#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 742018#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 742015#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 737045#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 737044#L718-39 assume !(1 == ~t8_pc~0); 737041#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 737037#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 737035#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 737033#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 737030#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 737028#L737-39 assume !(1 == ~t9_pc~0); 727569#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 737025#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 737023#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 737021#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 737018#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 737016#L756-39 assume !(1 == ~t10_pc~0); 675290#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 737013#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 737011#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 737009#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 737007#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 737005#L775-39 assume !(1 == ~t11_pc~0); 737003#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 737000#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 736998#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 736996#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 736993#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 736991#L794-39 assume 1 == ~t12_pc~0; 736989#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 736986#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 736984#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 736983#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 736982#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 736980#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 736978#L1307-5 assume !(1 == ~T1_E~0); 736976#L1312-3 assume !(1 == ~T2_E~0); 736974#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 736972#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 736970#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 736968#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 736965#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 736963#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 736961#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 736959#L1352-3 assume !(1 == ~T10_E~0); 736957#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 736955#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 736954#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 736952#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 736950#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 736948#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 736946#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 736944#L1392-3 assume !(1 == ~E_6~0); 736943#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 736941#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 736939#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 736937#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 736935#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 736933#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 736930#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 736868#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 736855#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 736853#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 736849#L1787 assume !(0 == start_simulation_~tmp~3#1); 736847#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 736816#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 736804#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 736799#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 736794#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 736790#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 736783#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 736777#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 633564#L1768-2 [2021-11-23 12:40:39,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:39,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1495505904, now seen corresponding path program 1 times [2021-11-23 12:40:39,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:39,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835647647] [2021-11-23 12:40:39,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:39,884 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:39,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:39,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:39,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:39,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835647647] [2021-11-23 12:40:39,943 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1835647647] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:39,944 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:39,944 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-23 12:40:39,944 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714597990] [2021-11-23 12:40:39,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:39,945 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:39,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:39,945 INFO L85 PathProgramCache]: Analyzing trace with hash 739440995, now seen corresponding path program 1 times [2021-11-23 12:40:39,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:39,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562783969] [2021-11-23 12:40:39,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:39,946 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:39,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:39,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:39,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:39,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562783969] [2021-11-23 12:40:39,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562783969] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:39,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:39,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:39,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534865989] [2021-11-23 12:40:39,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:39,982 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:39,982 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:39,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-23 12:40:39,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-23 12:40:39,983 INFO L87 Difference]: Start difference. First operand 152221 states and 216102 transitions. cyclomatic complexity: 63885 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:41,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:41,896 INFO L93 Difference]: Finished difference Result 341220 states and 489315 transitions. [2021-11-23 12:40:41,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-23 12:40:41,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 341220 states and 489315 transitions. [2021-11-23 12:40:43,691 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 340416 [2021-11-23 12:40:44,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 341220 states to 341220 states and 489315 transitions. [2021-11-23 12:40:44,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341220 [2021-11-23 12:40:44,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341220 [2021-11-23 12:40:44,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 341220 states and 489315 transitions. [2021-11-23 12:40:44,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:44,644 INFO L681 BuchiCegarLoop]: Abstraction has 341220 states and 489315 transitions. [2021-11-23 12:40:44,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341220 states and 489315 transitions. [2021-11-23 12:40:47,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341220 to 156256. [2021-11-23 12:40:47,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156256 states, 156256 states have (on average 1.4088227012082737) internal successors, (220137), 156255 states have internal predecessors, (220137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:47,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156256 states to 156256 states and 220137 transitions. [2021-11-23 12:40:47,896 INFO L704 BuchiCegarLoop]: Abstraction has 156256 states and 220137 transitions. [2021-11-23 12:40:47,896 INFO L587 BuchiCegarLoop]: Abstraction has 156256 states and 220137 transitions. [2021-11-23 12:40:47,896 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-23 12:40:47,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156256 states and 220137 transitions. [2021-11-23 12:40:48,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 155904 [2021-11-23 12:40:48,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:40:48,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:40:48,272 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:48,272 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:40:48,273 INFO L791 eck$LassoCheckResult]: Stem: 1126026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1126027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1127137#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1126420#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1126187#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1126188#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1126284#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1126654#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1126811#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1126812#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1125458#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1125459#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1126728#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1126072#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1126073#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1125975#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1125976#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1126415#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1125701#L1174 assume !(0 == ~M_E~0); 1125702#L1174-2 assume !(0 == ~T1_E~0); 1125550#L1179-1 assume !(0 == ~T2_E~0); 1125456#L1184-1 assume !(0 == ~T3_E~0); 1125457#L1189-1 assume !(0 == ~T4_E~0); 1125495#L1194-1 assume !(0 == ~T5_E~0); 1125591#L1199-1 assume !(0 == ~T6_E~0); 1126581#L1204-1 assume !(0 == ~T7_E~0); 1126485#L1209-1 assume !(0 == ~T8_E~0); 1126486#L1214-1 assume !(0 == ~T9_E~0); 1126998#L1219-1 assume !(0 == ~T10_E~0); 1127183#L1224-1 assume !(0 == ~T11_E~0); 1125824#L1229-1 assume !(0 == ~T12_E~0); 1125385#L1234-1 assume !(0 == ~E_1~0); 1125386#L1239-1 assume !(0 == ~E_2~0); 1125418#L1244-1 assume !(0 == ~E_3~0); 1125419#L1249-1 assume !(0 == ~E_4~0); 1126100#L1254-1 assume !(0 == ~E_5~0); 1125315#L1259-1 assume !(0 == ~E_6~0); 1125274#L1264-1 assume !(0 == ~E_7~0); 1125275#L1269-1 assume !(0 == ~E_8~0); 1127205#L1274-1 assume !(0 == ~E_9~0); 1127060#L1279-1 assume !(0 == ~E_10~0); 1125498#L1284-1 assume !(0 == ~E_11~0); 1125499#L1289-1 assume !(0 == ~E_12~0); 1126155#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1126156#L566 assume !(1 == ~m_pc~0); 1126650#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1126651#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1126520#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1126521#L1455 assume !(0 != activate_threads_~tmp~1#1); 1125727#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1125728#L585 assume !(1 == ~t1_pc~0); 1125918#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1125919#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1126448#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1126449#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1127114#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1127111#L604 assume !(1 == ~t2_pc~0); 1126541#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1126542#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1127082#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1126959#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1126762#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1126763#L623 assume !(1 == ~t3_pc~0); 1125254#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1125255#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126077#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1126078#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1126805#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1125288#L642 assume !(1 == ~t4_pc~0); 1125289#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1125748#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1125749#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1125356#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1125357#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126557#L661 assume !(1 == ~t5_pc~0); 1126735#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1126437#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1125478#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1125479#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1126594#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1126595#L680 assume !(1 == ~t6_pc~0); 1125956#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1125957#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1126235#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1126236#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1126894#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1127107#L699 assume !(1 == ~t7_pc~0); 1127108#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1126673#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1125506#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1125507#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1126269#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1126157#L718 assume !(1 == ~t8_pc~0); 1126158#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1125493#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1125494#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1125532#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1125533#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1125666#L737 assume !(1 == ~t9_pc~0); 1125807#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1125808#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1126477#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1126478#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1125996#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1125997#L756 assume !(1 == ~t10_pc~0); 1126258#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1126259#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1125220#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1125221#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1125790#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1125791#L775 assume !(1 == ~t11_pc~0); 1126060#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1126061#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1127007#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1125428#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 1125429#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1125610#L794 assume 1 == ~t12_pc~0; 1125455#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1125433#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1126758#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1125578#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1125579#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1126080#L1307 assume !(1 == ~M_E~0); 1126081#L1307-2 assume !(1 == ~T1_E~0); 1126203#L1312-1 assume !(1 == ~T2_E~0); 1126113#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1126114#L1322-1 assume !(1 == ~T4_E~0); 1125799#L1327-1 assume !(1 == ~T5_E~0); 1125800#L1332-1 assume !(1 == ~T6_E~0); 1126391#L1337-1 assume !(1 == ~T7_E~0); 1126337#L1342-1 assume !(1 == ~T8_E~0); 1126338#L1347-1 assume !(1 == ~T9_E~0); 1126843#L1352-1 assume !(1 == ~T10_E~0); 1126674#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1125973#L1362-1 assume !(1 == ~T12_E~0); 1125974#L1367-1 assume !(1 == ~E_1~0); 1125592#L1372-1 assume !(1 == ~E_2~0); 1125593#L1377-1 assume !(1 == ~E_3~0); 1125901#L1382-1 assume !(1 == ~E_4~0); 1125902#L1387-1 assume !(1 == ~E_5~0); 1126543#L1392-1 assume !(1 == ~E_6~0); 1125925#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1125926#L1402-1 assume !(1 == ~E_8~0); 1125606#L1407-1 assume !(1 == ~E_9~0); 1125607#L1412-1 assume !(1 == ~E_10~0); 1126756#L1417-1 assume !(1 == ~E_11~0); 1126757#L1422-1 assume !(1 == ~E_12~0); 1127103#L1427-1 assume { :end_inline_reset_delta_events } true; 1127104#L1768-2 [2021-11-23 12:40:48,273 INFO L793 eck$LassoCheckResult]: Loop: 1127104#L1768-2 assume !false; 1261813#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1261807#L1149 assume !false; 1261804#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1261771#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1261762#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1261637#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1261616#L976 assume !(0 != eval_~tmp~0#1); 1261617#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1281016#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1281014#L1174-3 assume !(0 == ~M_E~0); 1281012#L1174-5 assume !(0 == ~T1_E~0); 1281010#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1280991#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1280990#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1280989#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1280988#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1280986#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1280984#L1209-3 assume !(0 == ~T8_E~0); 1280982#L1214-3 assume !(0 == ~T9_E~0); 1280980#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1280978#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1280976#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1280974#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1280972#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1280970#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1280968#L1249-3 assume !(0 == ~E_4~0); 1280966#L1254-3 assume !(0 == ~E_5~0); 1280964#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1280962#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1280960#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1280958#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1280956#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1280954#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1280953#L1289-3 assume !(0 == ~E_12~0); 1263344#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1263284#L566-39 assume !(1 == ~m_pc~0); 1263278#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1263273#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1263268#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1263263#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1263258#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1263248#L585-39 assume !(1 == ~t1_pc~0); 1258708#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1263237#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1263230#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1263220#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1263211#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1263158#L604-39 assume !(1 == ~t2_pc~0); 1263149#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1263139#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1263130#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1263102#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1263091#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1263062#L623-39 assume !(1 == ~t3_pc~0); 1263061#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1263060#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1263059#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1263058#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1263057#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1263056#L642-39 assume !(1 == ~t4_pc~0); 1263055#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1263053#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1263052#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1263051#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1263050#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1263049#L661-39 assume !(1 == ~t5_pc~0); 1263048#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1263047#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1263046#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1263045#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1263044#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1263043#L680-39 assume !(1 == ~t6_pc~0); 1263042#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1263040#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1263039#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1263038#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1263037#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1263036#L699-39 assume !(1 == ~t7_pc~0); 1208835#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1263035#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1263034#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1263033#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1263032#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1263031#L718-39 assume !(1 == ~t8_pc~0); 1263030#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1263028#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1263027#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1263026#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1263025#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1263024#L737-39 assume !(1 == ~t9_pc~0); 1190791#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1263023#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1263022#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1263021#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1263020#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1263019#L756-39 assume !(1 == ~t10_pc~0); 1241884#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1263018#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1263017#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1263016#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1263015#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1263014#L775-39 assume !(1 == ~t11_pc~0); 1263013#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1263011#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1263009#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1263007#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 1263003#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1263000#L794-39 assume 1 == ~t12_pc~0; 1262997#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1262930#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1262542#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1262533#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1262530#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1262527#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1262524#L1307-5 assume !(1 == ~T1_E~0); 1262520#L1312-3 assume !(1 == ~T2_E~0); 1262516#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1262512#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1262508#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1262504#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1262500#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1262394#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1262392#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1262390#L1352-3 assume !(1 == ~T10_E~0); 1262388#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1262386#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1262286#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1262284#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1262282#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1262169#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1262167#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1262165#L1392-3 assume !(1 == ~E_6~0); 1262162#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1262160#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1262116#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1262115#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1262114#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1262112#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1262110#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1262065#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1262052#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1262050#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1262045#L1787 assume !(0 == start_simulation_~tmp~3#1); 1262043#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1261872#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1261861#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1261854#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1261849#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1261844#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1261834#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1261827#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1127104#L1768-2 [2021-11-23 12:40:48,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:48,274 INFO L85 PathProgramCache]: Analyzing trace with hash -748477394, now seen corresponding path program 1 times [2021-11-23 12:40:48,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:48,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834148492] [2021-11-23 12:40:48,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:48,275 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:48,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:48,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:48,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:48,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834148492] [2021-11-23 12:40:48,315 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834148492] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:48,316 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:48,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:48,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343961241] [2021-11-23 12:40:48,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:48,317 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:40:48,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:40:48,317 INFO L85 PathProgramCache]: Analyzing trace with hash 49517981, now seen corresponding path program 1 times [2021-11-23 12:40:48,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:40:48,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166632354] [2021-11-23 12:40:48,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:40:48,318 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:40:48,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:40:48,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:40:48,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:40:48,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166632354] [2021-11-23 12:40:48,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166632354] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:40:48,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:40:48,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:40:48,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505298351] [2021-11-23 12:40:48,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:40:48,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:40:48,352 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:40:48,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:40:48,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:40:48,353 INFO L87 Difference]: Start difference. First operand 156256 states and 220137 transitions. cyclomatic complexity: 63885 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:50,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-23 12:40:50,334 INFO L93 Difference]: Finished difference Result 390527 states and 546246 transitions. [2021-11-23 12:40:50,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-23 12:40:50,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390527 states and 546246 transitions. [2021-11-23 12:40:52,787 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 383392 [2021-11-23 12:40:54,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390527 states to 390527 states and 546246 transitions. [2021-11-23 12:40:54,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 390527 [2021-11-23 12:40:54,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 390527 [2021-11-23 12:40:54,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390527 states and 546246 transitions. [2021-11-23 12:40:54,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-23 12:40:54,550 INFO L681 BuchiCegarLoop]: Abstraction has 390527 states and 546246 transitions. [2021-11-23 12:40:54,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390527 states and 546246 transitions. [2021-11-23 12:40:57,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390527 to 310367. [2021-11-23 12:40:58,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 310367 states, 310367 states have (on average 1.402333366627251) internal successors, (435238), 310366 states have internal predecessors, (435238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-23 12:40:58,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310367 states to 310367 states and 435238 transitions. [2021-11-23 12:40:58,960 INFO L704 BuchiCegarLoop]: Abstraction has 310367 states and 435238 transitions. [2021-11-23 12:40:58,960 INFO L587 BuchiCegarLoop]: Abstraction has 310367 states and 435238 transitions. [2021-11-23 12:40:58,960 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-23 12:40:58,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 310367 states and 435238 transitions. [2021-11-23 12:41:00,729 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309824 [2021-11-23 12:41:00,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-23 12:41:00,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-23 12:41:00,737 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:41:00,737 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-23 12:41:00,738 INFO L791 eck$LassoCheckResult]: Stem: 1672813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1672814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1673913#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1673206#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1672975#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1672976#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1673075#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1673439#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1673597#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1673598#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1672247#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1672248#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1673511#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1672859#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1672860#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1672765#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1672766#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1673201#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1672488#L1174 assume !(0 == ~M_E~0); 1672489#L1174-2 assume !(0 == ~T1_E~0); 1672340#L1179-1 assume !(0 == ~T2_E~0); 1672245#L1184-1 assume !(0 == ~T3_E~0); 1672246#L1189-1 assume !(0 == ~T4_E~0); 1672284#L1194-1 assume !(0 == ~T5_E~0); 1672380#L1199-1 assume !(0 == ~T6_E~0); 1673366#L1204-1 assume !(0 == ~T7_E~0); 1673271#L1209-1 assume !(0 == ~T8_E~0); 1673272#L1214-1 assume !(0 == ~T9_E~0); 1673779#L1219-1 assume !(0 == ~T10_E~0); 1673965#L1224-1 assume !(0 == ~T11_E~0); 1672613#L1229-1 assume !(0 == ~T12_E~0); 1672176#L1234-1 assume !(0 == ~E_1~0); 1672177#L1239-1 assume !(0 == ~E_2~0); 1672208#L1244-1 assume !(0 == ~E_3~0); 1672209#L1249-1 assume !(0 == ~E_4~0); 1672888#L1254-1 assume !(0 == ~E_5~0); 1672107#L1259-1 assume !(0 == ~E_6~0); 1672066#L1264-1 assume !(0 == ~E_7~0); 1672067#L1269-1 assume !(0 == ~E_8~0); 1673996#L1274-1 assume !(0 == ~E_9~0); 1673835#L1279-1 assume !(0 == ~E_10~0); 1672287#L1284-1 assume !(0 == ~E_11~0); 1672288#L1289-1 assume !(0 == ~E_12~0); 1672942#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1672943#L566 assume !(1 == ~m_pc~0); 1673436#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1673437#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1673306#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1673307#L1455 assume !(0 != activate_threads_~tmp~1#1); 1672514#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1672515#L585 assume !(1 == ~t1_pc~0); 1672705#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1672706#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1673231#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1673232#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1673882#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1673878#L604 assume !(1 == ~t2_pc~0); 1673331#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1673332#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1674030#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1673744#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1673540#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1673541#L623 assume !(1 == ~t3_pc~0); 1672046#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1672047#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1672864#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1672865#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1673588#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1672080#L642 assume !(1 == ~t4_pc~0); 1672081#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1672532#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672533#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1672147#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1672148#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1673344#L661 assume !(1 == ~t5_pc~0); 1673518#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1673223#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1672267#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1672268#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1673378#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1673379#L680 assume !(1 == ~t6_pc~0); 1672742#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1672743#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1673023#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1673024#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1673675#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1673875#L699 assume !(1 == ~t7_pc~0); 1673876#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1673460#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1672295#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1672296#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1673061#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1672944#L718 assume !(1 == ~t8_pc~0); 1672945#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1672282#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1672283#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1672322#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1672323#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1672454#L737 assume !(1 == ~t9_pc~0); 1672595#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1672596#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1673261#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1673262#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1672784#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1672785#L756 assume !(1 == ~t10_pc~0); 1673051#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1673052#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1672013#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1672014#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1672578#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1672579#L775 assume !(1 == ~t11_pc~0); 1672847#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1672848#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1674029#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1672218#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 1672219#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1672397#L794 assume !(1 == ~t12_pc~0); 1672222#L794-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1672223#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1673535#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1672368#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1672369#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1672867#L1307 assume !(1 == ~M_E~0); 1672868#L1307-2 assume !(1 == ~T1_E~0); 1672993#L1312-1 assume !(1 == ~T2_E~0); 1672902#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1672903#L1322-1 assume !(1 == ~T4_E~0); 1672587#L1327-1 assume !(1 == ~T5_E~0); 1672588#L1332-1 assume !(1 == ~T6_E~0); 1673180#L1337-1 assume !(1 == ~T7_E~0); 1673128#L1342-1 assume !(1 == ~T8_E~0); 1673129#L1347-1 assume !(1 == ~T9_E~0); 1673632#L1352-1 assume !(1 == ~T10_E~0); 1673461#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1672763#L1362-1 assume !(1 == ~T12_E~0); 1672764#L1367-1 assume !(1 == ~E_1~0); 1672381#L1372-1 assume !(1 == ~E_2~0); 1672382#L1377-1 assume !(1 == ~E_3~0); 1672688#L1382-1 assume !(1 == ~E_4~0); 1672689#L1387-1 assume !(1 == ~E_5~0); 1673333#L1392-1 assume !(1 == ~E_6~0); 1672711#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1672712#L1402-1 assume !(1 == ~E_8~0); 1672393#L1407-1 assume !(1 == ~E_9~0); 1672394#L1412-1 assume !(1 == ~E_10~0); 1673533#L1417-1 assume !(1 == ~E_11~0); 1673534#L1422-1 assume !(1 == ~E_12~0); 1673872#L1427-1 assume { :end_inline_reset_delta_events } true; 1673873#L1768-2 [2021-11-23 12:41:00,739 INFO L793 eck$LassoCheckResult]: Loop: 1673873#L1768-2 assume !false; 1934981#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1923993#L1149 assume !false; 1934980#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1934497#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1934489#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1934487#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1934484#L976 assume !(0 != eval_~tmp~0#1); 1934485#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1978466#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1978465#L1174-3 assume !(0 == ~M_E~0); 1978464#L1174-5 assume !(0 == ~T1_E~0); 1978463#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1978462#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1978461#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1978460#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1978459#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1978458#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1978457#L1209-3 assume !(0 == ~T8_E~0); 1978456#L1214-3 assume !(0 == ~T9_E~0); 1978455#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1978454#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1978453#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1978452#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1978451#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1978450#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1978449#L1249-3 assume !(0 == ~E_4~0); 1978448#L1254-3 assume !(0 == ~E_5~0); 1978447#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1978446#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1978445#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1978444#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1978443#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1978442#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1978441#L1289-3 assume !(0 == ~E_12~0); 1978440#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1978439#L566-39 assume !(1 == ~m_pc~0); 1978438#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1978437#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1978436#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1978435#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1978434#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1973990#L585-39 assume !(1 == ~t1_pc~0); 1973988#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1973986#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1973984#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1973981#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1973979#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1973977#L604-39 assume 1 == ~t2_pc~0; 1973975#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1973976#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1974087#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1973965#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1973963#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1973961#L623-39 assume !(1 == ~t3_pc~0); 1951375#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1973958#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1973957#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1973956#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1973955#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1973954#L642-39 assume 1 == ~t4_pc~0; 1973952#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1973950#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1973949#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1973948#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1973947#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1973945#L661-39 assume !(1 == ~t5_pc~0); 1973943#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1973941#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1973939#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1973937#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1973935#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1973931#L680-39 assume 1 == ~t6_pc~0; 1973928#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1973926#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1973924#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1973921#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1973919#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1973917#L699-39 assume !(1 == ~t7_pc~0); 1963114#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1973915#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1973913#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1973911#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1973909#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1973907#L718-39 assume !(1 == ~t8_pc~0); 1973904#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1973901#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1973899#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1973897#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1973895#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1948587#L737-39 assume !(1 == ~t9_pc~0); 1948579#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1948571#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1948566#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1948548#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1948542#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1935113#L756-39 assume !(1 == ~t10_pc~0); 1935112#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1935111#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1935109#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1935108#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1935107#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1935105#L775-39 assume !(1 == ~t11_pc~0); 1935101#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1935099#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1935097#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1935095#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 1935092#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1935088#L794-39 assume !(1 == ~t12_pc~0); 1764227#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1935085#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1935083#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1935080#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1935078#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1935076#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1935075#L1307-5 assume !(1 == ~T1_E~0); 1935073#L1312-3 assume !(1 == ~T2_E~0); 1935071#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1935069#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1935067#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1935065#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1935063#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1935061#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1935059#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1935057#L1352-3 assume !(1 == ~T10_E~0); 1935055#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1935053#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1935051#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1935049#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1935047#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1935045#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1935043#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1935041#L1392-3 assume !(1 == ~E_6~0); 1935039#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1935037#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1935035#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1935033#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1935031#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1935029#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1935027#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1935022#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1935009#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1935007#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1935005#L1787 assume !(0 == start_simulation_~tmp~3#1); 1935003#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1934996#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1934989#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1934987#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1934985#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1934984#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1934983#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1934982#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1673873#L1768-2 [2021-11-23 12:41:00,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:41:00,740 INFO L85 PathProgramCache]: Analyzing trace with hash 170497229, now seen corresponding path program 1 times [2021-11-23 12:41:00,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:41:00,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770345247] [2021-11-23 12:41:00,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:41:00,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:41:00,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:41:00,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:41:00,783 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:41:00,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770345247] [2021-11-23 12:41:00,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770345247] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:41:00,784 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:41:00,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:41:00,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411763533] [2021-11-23 12:41:00,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:41:00,785 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-23 12:41:00,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 12:41:00,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1275826527, now seen corresponding path program 1 times [2021-11-23 12:41:00,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-23 12:41:00,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679122686] [2021-11-23 12:41:00,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-23 12:41:00,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 12:41:00,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 12:41:00,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-23 12:41:00,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-23 12:41:00,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679122686] [2021-11-23 12:41:00,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [679122686] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-23 12:41:00,823 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-23 12:41:00,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-23 12:41:00,824 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030914972] [2021-11-23 12:41:00,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-23 12:41:00,824 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-23 12:41:00,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-23 12:41:00,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-23 12:41:00,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-23 12:41:00,825 INFO L87 Difference]: Start difference. First operand 310367 states and 435238 transitions. cyclomatic complexity: 124875 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)