./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1bedc761cea545b8144ad4138a379d7139cc98703c76e9b536a2e7389d5b6a10 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 18:36:27,588 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 18:36:27,590 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 18:36:27,620 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 18:36:27,621 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 18:36:27,622 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 18:36:27,624 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 18:36:27,626 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 18:36:27,628 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 18:36:27,629 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 18:36:27,631 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 18:36:27,632 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 18:36:27,632 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 18:36:27,634 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 18:36:27,635 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 18:36:27,637 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 18:36:27,638 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 18:36:27,639 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 18:36:27,641 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 18:36:27,643 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 18:36:27,645 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 18:36:27,646 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 18:36:27,648 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 18:36:27,649 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 18:36:27,652 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 18:36:27,653 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 18:36:27,653 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 18:36:27,654 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 18:36:27,655 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 18:36:27,656 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 18:36:27,656 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 18:36:27,657 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 18:36:27,658 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 18:36:27,659 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 18:36:27,660 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 18:36:27,660 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 18:36:27,661 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 18:36:27,661 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 18:36:27,661 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 18:36:27,662 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 18:36:27,663 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 18:36:27,664 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-12-06 18:36:27,689 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 18:36:27,689 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 18:36:27,690 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 18:36:27,690 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 18:36:27,691 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 18:36:27,691 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 18:36:27,691 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 18:36:27,692 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 18:36:27,692 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 18:36:27,692 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 18:36:27,692 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 18:36:27,693 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 18:36:27,693 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 18:36:27,693 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 18:36:27,693 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 18:36:27,693 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 18:36:27,694 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 18:36:27,694 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 18:36:27,694 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 18:36:27,694 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 18:36:27,694 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 18:36:27,695 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 18:36:27,695 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 18:36:27,695 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 18:36:27,695 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 18:36:27,695 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 18:36:27,696 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 18:36:27,696 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 18:36:27,696 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 18:36:27,697 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 18:36:27,697 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1bedc761cea545b8144ad4138a379d7139cc98703c76e9b536a2e7389d5b6a10 [2021-12-06 18:36:27,895 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 18:36:27,912 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 18:36:27,914 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 18:36:27,915 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 18:36:27,915 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 18:36:27,916 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c [2021-12-06 18:36:27,965 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/data/5446a7770/bea3f0875512408b9ec42cbb7de5b73a/FLAGf649e7e9b [2021-12-06 18:36:28,328 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 18:36:28,329 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c [2021-12-06 18:36:28,334 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/data/5446a7770/bea3f0875512408b9ec42cbb7de5b73a/FLAGf649e7e9b [2021-12-06 18:36:28,345 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/data/5446a7770/bea3f0875512408b9ec42cbb7de5b73a [2021-12-06 18:36:28,347 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 18:36:28,348 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 18:36:28,350 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 18:36:28,350 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 18:36:28,352 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 18:36:28,353 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,354 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@68332511 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28, skipping insertion in model container [2021-12-06 18:36:28,354 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,359 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 18:36:28,367 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 18:36:28,477 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:36:28,483 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 18:36:28,493 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:36:28,502 INFO L208 MainTranslator]: Completed translation [2021-12-06 18:36:28,502 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28 WrapperNode [2021-12-06 18:36:28,503 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 18:36:28,503 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 18:36:28,504 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 18:36:28,504 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 18:36:28,509 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,514 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,527 INFO L137 Inliner]: procedures = 10, calls = 8, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 47 [2021-12-06 18:36:28,528 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 18:36:28,528 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 18:36:28,528 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 18:36:28,528 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 18:36:28,534 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,534 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,536 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,536 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,539 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,542 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,543 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,544 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 18:36:28,545 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 18:36:28,545 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 18:36:28,545 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 18:36:28,546 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (1/1) ... [2021-12-06 18:36:28,552 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:28,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:28,575 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:28,577 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 18:36:28,614 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 18:36:28,614 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-12-06 18:36:28,614 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 18:36:28,614 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 18:36:28,614 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-12-06 18:36:28,615 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 18:36:28,664 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 18:36:28,665 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 18:36:28,737 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 18:36:28,742 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 18:36:28,742 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 18:36:28,743 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:36:28 BoogieIcfgContainer [2021-12-06 18:36:28,743 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 18:36:28,744 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 18:36:28,744 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 18:36:28,747 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 18:36:28,747 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:36:28,747 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 06:36:28" (1/3) ... [2021-12-06 18:36:28,748 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ce7c4cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 06:36:28, skipping insertion in model container [2021-12-06 18:36:28,748 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:36:28,748 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:36:28" (2/3) ... [2021-12-06 18:36:28,749 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ce7c4cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 06:36:28, skipping insertion in model container [2021-12-06 18:36:28,749 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:36:28,749 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:36:28" (3/3) ... [2021-12-06 18:36:28,750 INFO L388 chiAutomizerObserver]: Analyzing ICFG LexIndexValue-Pointer-2.c [2021-12-06 18:36:28,781 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 18:36:28,781 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 18:36:28,782 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 18:36:28,782 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 18:36:28,782 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 18:36:28,782 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 18:36:28,782 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 18:36:28,782 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 18:36:28,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:28,805 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 18:36:28,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:28,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:28,809 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-12-06 18:36:28,809 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 18:36:28,809 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 18:36:28,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:28,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 18:36:28,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:28,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:28,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-12-06 18:36:28,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 18:36:28,816 INFO L791 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 11#L18-3true [2021-12-06 18:36:28,816 INFO L793 eck$LassoCheckResult]: Loop: 11#L18-3true assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9#L18-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11#L18-3true [2021-12-06 18:36:28,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:28,821 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-12-06 18:36:28,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:28,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313002529] [2021-12-06 18:36:28,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:28,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:28,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,893 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:28,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,913 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:28,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:28,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2021-12-06 18:36:28,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:28,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201189635] [2021-12-06 18:36:28,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:28,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:28,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,925 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:28,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:28,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:28,934 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2021-12-06 18:36:28,934 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:28,934 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353107843] [2021-12-06 18:36:28,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:28,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:28,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,950 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:28,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:28,962 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:29,160 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 18:36:29,161 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 18:36:29,161 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 18:36:29,161 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 18:36:29,161 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 18:36:29,162 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,162 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 18:36:29,162 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 18:36:29,162 INFO L133 ssoRankerPreferences]: Filename of dumped script: LexIndexValue-Pointer-2.c_Iteration1_Lasso [2021-12-06 18:36:29,162 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 18:36:29,162 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 18:36:29,182 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,187 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,189 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,191 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,268 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,270 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,274 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,278 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,280 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,282 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,283 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 18:36:29,420 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 18:36:29,423 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 18:36:29,424 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,425 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,426 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-06 18:36:29,427 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,434 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,434 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 18:36:29,435 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,435 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,435 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,436 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 18:36:29,437 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 18:36:29,438 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,458 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-06 18:36:29,458 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,458 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,459 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-06 18:36:29,460 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,467 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,468 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 18:36:29,468 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,468 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,468 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,469 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 18:36:29,469 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 18:36:29,470 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,488 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2021-12-06 18:36:29,488 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,489 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,489 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-06 18:36:29,491 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,497 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,498 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 18:36:29,498 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,498 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,498 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,499 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 18:36:29,499 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 18:36:29,500 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,518 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2021-12-06 18:36:29,519 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,520 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-06 18:36:29,521 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,528 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,528 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,528 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,528 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,533 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 18:36:29,533 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 18:36:29,539 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,565 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2021-12-06 18:36:29,565 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,566 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-06 18:36:29,567 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,574 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,574 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 18:36:29,575 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,575 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,575 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,575 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 18:36:29,575 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 18:36:29,577 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,596 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2021-12-06 18:36:29,596 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,597 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,598 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-06 18:36:29,598 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,605 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,605 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 18:36:29,605 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,605 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,605 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,606 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 18:36:29,606 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 18:36:29,607 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,626 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2021-12-06 18:36:29,626 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,626 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,627 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-06 18:36:29,630 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,637 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,637 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,637 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,637 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,640 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 18:36:29,640 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 18:36:29,643 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,661 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-12-06 18:36:29,662 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,662 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,663 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-12-06 18:36:29,664 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,671 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,671 INFO L203 nArgumentSynthesizer]: 2 stem disjuncts [2021-12-06 18:36:29,671 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,671 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,674 INFO L401 nArgumentSynthesizer]: We have 8 Motzkin's Theorem applications. [2021-12-06 18:36:29,674 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 18:36:29,680 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 18:36:29,698 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-12-06 18:36:29,698 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,699 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,700 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-12-06 18:36:29,701 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 18:36:29,708 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 18:36:29,709 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 18:36:29,709 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 18:36:29,709 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 18:36:29,714 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 18:36:29,714 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 18:36:29,725 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 18:36:29,757 INFO L443 ModelExtractionUtils]: Simplification made 11 calls to the SMT solver. [2021-12-06 18:36:29,757 INFO L444 ModelExtractionUtils]: 5 out of 19 variables were initially zero. Simplification set additionally 11 variables to zero. [2021-12-06 18:36:29,759 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:36:29,759 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:29,760 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:36:29,761 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-12-06 18:36:29,761 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 18:36:29,771 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 18:36:29,771 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 18:36:29,772 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~p~0#1.base)_1) = -8*ULTIMATE.start_main_~i~0#1 + 2095*v_rep(select #length ULTIMATE.start_main_~p~0#1.base)_1 Supporting invariants [] [2021-12-06 18:36:29,800 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-12-06 18:36:29,808 INFO L297 tatePredicateManager]: 2 out of 3 supporting invariants were superfluous and have been removed [2021-12-06 18:36:29,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:29,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:29,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 18:36:29,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:29,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:29,873 WARN L261 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 18:36:29,873 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:29,883 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-12-06 18:36:29,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:29,951 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-12-06 18:36:29,952 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,017 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 33 states and 48 transitions. Complement of second has 7 states. [2021-12-06 18:36:30,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-12-06 18:36:30,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 30 transitions. [2021-12-06 18:36:30,024 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 2 letters. [2021-12-06 18:36:30,024 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 18:36:30,024 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 4 letters. Loop has 2 letters. [2021-12-06 18:36:30,024 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 18:36:30,025 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 4 letters. [2021-12-06 18:36:30,025 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 18:36:30,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 48 transitions. [2021-12-06 18:36:30,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 10 states and 14 transitions. [2021-12-06 18:36:30,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-12-06 18:36:30,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:30,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 14 transitions. [2021-12-06 18:36:30,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:30,033 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-12-06 18:36:30,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 14 transitions. [2021-12-06 18:36:30,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-12-06 18:36:30,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.4) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 14 transitions. [2021-12-06 18:36:30,051 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-12-06 18:36:30,051 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-12-06 18:36:30,051 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 18:36:30,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 14 transitions. [2021-12-06 18:36:30,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:30,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:30,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-12-06 18:36:30,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:30,053 INFO L791 eck$LassoCheckResult]: Stem: 104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 109#L18-3 assume !(main_~i~0#1 < 1048); 110#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 108#L23-2 [2021-12-06 18:36:30,053 INFO L793 eck$LassoCheckResult]: Loop: 108#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 102#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 103#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 111#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 108#L23-2 [2021-12-06 18:36:30,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,054 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2021-12-06 18:36:30,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362065959] [2021-12-06 18:36:30,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,054 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:30,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,088 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:30,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362065959] [2021-12-06 18:36:30,088 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362065959] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:36:30,088 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:36:30,089 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:36:30,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523302294] [2021-12-06 18:36:30,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:36:30,091 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:30,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 1 times [2021-12-06 18:36:30,092 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381962585] [2021-12-06 18:36:30,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,092 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,100 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:30,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,108 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:30,180 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:30,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:36:30,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:36:30,183 INFO L87 Difference]: Start difference. First operand 10 states and 14 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:30,191 INFO L93 Difference]: Finished difference Result 11 states and 14 transitions. [2021-12-06 18:36:30,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:36:30,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 14 transitions. [2021-12-06 18:36:30,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 14 transitions. [2021-12-06 18:36:30,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:30,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:30,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 14 transitions. [2021-12-06 18:36:30,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:30,194 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 14 transitions. [2021-12-06 18:36:30,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 14 transitions. [2021-12-06 18:36:30,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2021-12-06 18:36:30,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2021-12-06 18:36:30,195 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-12-06 18:36:30,195 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-12-06 18:36:30,195 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 18:36:30,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2021-12-06 18:36:30,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:30,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:30,197 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-12-06 18:36:30,197 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:30,197 INFO L791 eck$LassoCheckResult]: Stem: 129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 130#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 136#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 133#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 134#L18-3 assume !(main_~i~0#1 < 1048); 137#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 135#L23-2 [2021-12-06 18:36:30,197 INFO L793 eck$LassoCheckResult]: Loop: 135#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 131#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 132#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 138#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 135#L23-2 [2021-12-06 18:36:30,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,197 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2021-12-06 18:36:30,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135451252] [2021-12-06 18:36:30,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:30,227 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:30,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135451252] [2021-12-06 18:36:30,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135451252] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:30,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [810804537] [2021-12-06 18:36:30,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,227 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:30,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:30,228 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:30,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-12-06 18:36:30,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:30,253 INFO L263 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 3 conjunts are in the unsatisfiable core [2021-12-06 18:36:30,254 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:30,266 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,266 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:36:30,284 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [810804537] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:36:30,285 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:36:30,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2021-12-06 18:36:30,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346019768] [2021-12-06 18:36:30,285 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:36:30,286 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:30,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 2 times [2021-12-06 18:36:30,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085002403] [2021-12-06 18:36:30,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,293 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:30,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,300 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:30,366 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:30,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-12-06 18:36:30,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:36:30,368 INFO L87 Difference]: Start difference. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:30,385 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2021-12-06 18:36:30,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 18:36:30,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 19 transitions. [2021-12-06 18:36:30,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 19 transitions. [2021-12-06 18:36:30,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:30,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:30,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 19 transitions. [2021-12-06 18:36:30,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:30,388 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-12-06 18:36:30,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 19 transitions. [2021-12-06 18:36:30,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2021-12-06 18:36:30,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.1875) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 19 transitions. [2021-12-06 18:36:30,390 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-12-06 18:36:30,390 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-12-06 18:36:30,391 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 18:36:30,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 19 transitions. [2021-12-06 18:36:30,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:30,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:30,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2021-12-06 18:36:30,392 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:30,392 INFO L791 eck$LassoCheckResult]: Stem: 197#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 202#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 203#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 204#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 199#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 200#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 210#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 209#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 208#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 207#L18-3 assume !(main_~i~0#1 < 1048); 205#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 201#L23-2 [2021-12-06 18:36:30,392 INFO L793 eck$LassoCheckResult]: Loop: 201#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 195#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 196#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 206#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 201#L23-2 [2021-12-06 18:36:30,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,393 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 2 times [2021-12-06 18:36:30,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,393 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383177609] [2021-12-06 18:36:30,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:30,446 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:30,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383177609] [2021-12-06 18:36:30,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383177609] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:30,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [319367647] [2021-12-06 18:36:30,447 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 18:36:30,447 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:30,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:30,448 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:30,449 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-12-06 18:36:30,477 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 18:36:30,477 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:36:30,477 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 18:36:30,478 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:30,501 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,501 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:36:30,545 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [319367647] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:36:30,546 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:36:30,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2021-12-06 18:36:30,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964876346] [2021-12-06 18:36:30,546 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:36:30,546 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:30,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,546 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 3 times [2021-12-06 18:36:30,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547113178] [2021-12-06 18:36:30,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,547 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,551 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:30,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:30,555 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:30,612 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:30,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-12-06 18:36:30,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-12-06 18:36:30,613 INFO L87 Difference]: Start difference. First operand 16 states and 19 transitions. cyclomatic complexity: 5 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:30,641 INFO L93 Difference]: Finished difference Result 28 states and 31 transitions. [2021-12-06 18:36:30,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-12-06 18:36:30,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 31 transitions. [2021-12-06 18:36:30,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 28 states and 31 transitions. [2021-12-06 18:36:30,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:30,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:30,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 31 transitions. [2021-12-06 18:36:30,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:30,644 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 31 transitions. [2021-12-06 18:36:30,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 31 transitions. [2021-12-06 18:36:30,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2021-12-06 18:36:30,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1071428571428572) internal successors, (31), 27 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:30,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 31 transitions. [2021-12-06 18:36:30,646 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 31 transitions. [2021-12-06 18:36:30,646 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 31 transitions. [2021-12-06 18:36:30,646 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 18:36:30,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 31 transitions. [2021-12-06 18:36:30,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:30,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:30,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:30,647 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2021-12-06 18:36:30,647 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:30,647 INFO L791 eck$LassoCheckResult]: Stem: 321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 328#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 329#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 330#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 325#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 326#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 348#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 347#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 346#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 345#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 344#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 343#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 342#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 341#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 340#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 339#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 338#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 337#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 336#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 335#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 334#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 333#L18-3 assume !(main_~i~0#1 < 1048); 331#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 327#L23-2 [2021-12-06 18:36:30,648 INFO L793 eck$LassoCheckResult]: Loop: 327#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 323#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 324#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 332#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 327#L23-2 [2021-12-06 18:36:30,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:30,648 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 3 times [2021-12-06 18:36:30,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:30,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123701314] [2021-12-06 18:36:30,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:30,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:30,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:30,753 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:30,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123701314] [2021-12-06 18:36:30,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123701314] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:30,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [949682503] [2021-12-06 18:36:30,754 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 18:36:30,754 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:30,754 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:30,788 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:30,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-12-06 18:36:30,857 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2021-12-06 18:36:30,857 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:36:30,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 12 conjunts are in the unsatisfiable core [2021-12-06 18:36:30,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:30,900 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:30,900 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:36:31,044 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:31,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [949682503] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:36:31,044 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:36:31,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2021-12-06 18:36:31,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020897870] [2021-12-06 18:36:31,045 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:36:31,045 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:31,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:31,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 4 times [2021-12-06 18:36:31,046 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:31,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26659962] [2021-12-06 18:36:31,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:31,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:31,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:31,049 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:31,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:31,053 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:31,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:31,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-12-06 18:36:31,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-12-06 18:36:31,115 INFO L87 Difference]: Start difference. First operand 28 states and 31 transitions. cyclomatic complexity: 5 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:31,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:31,170 INFO L93 Difference]: Finished difference Result 52 states and 55 transitions. [2021-12-06 18:36:31,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-12-06 18:36:31,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 55 transitions. [2021-12-06 18:36:31,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:31,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 55 transitions. [2021-12-06 18:36:31,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:31,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:31,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 55 transitions. [2021-12-06 18:36:31,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:31,174 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 55 transitions. [2021-12-06 18:36:31,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 55 transitions. [2021-12-06 18:36:31,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2021-12-06 18:36:31,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0576923076923077) internal successors, (55), 51 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:31,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 55 transitions. [2021-12-06 18:36:31,177 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 55 transitions. [2021-12-06 18:36:31,177 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 55 transitions. [2021-12-06 18:36:31,177 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 18:36:31,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 55 transitions. [2021-12-06 18:36:31,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:31,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:31,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:31,179 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2021-12-06 18:36:31,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:31,179 INFO L791 eck$LassoCheckResult]: Stem: 567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 574#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 575#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 576#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 571#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 572#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 618#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 617#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 616#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 615#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 614#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 613#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 612#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 611#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 610#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 609#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 608#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 607#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 606#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 605#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 604#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 603#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 602#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 601#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 600#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 599#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 598#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 597#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 596#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 595#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 594#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 593#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 592#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 591#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 590#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 589#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 588#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 587#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 586#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 585#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 584#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 583#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 582#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 581#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 580#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 579#L18-3 assume !(main_~i~0#1 < 1048); 577#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 573#L23-2 [2021-12-06 18:36:31,179 INFO L793 eck$LassoCheckResult]: Loop: 573#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 569#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 570#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 578#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 573#L23-2 [2021-12-06 18:36:31,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:31,180 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 4 times [2021-12-06 18:36:31,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:31,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252768496] [2021-12-06 18:36:31,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:31,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:31,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:31,382 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:31,382 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:31,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252768496] [2021-12-06 18:36:31,382 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252768496] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:31,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1175680954] [2021-12-06 18:36:31,382 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 18:36:31,383 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:31,383 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:31,383 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:31,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-12-06 18:36:31,435 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 18:36:31,435 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:36:31,437 INFO L263 TraceCheckSpWp]: Trace formula consists of 274 conjuncts, 24 conjunts are in the unsatisfiable core [2021-12-06 18:36:31,439 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:31,516 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:31,516 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:36:31,912 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:31,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1175680954] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:36:31,912 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:36:31,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2021-12-06 18:36:31,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474871275] [2021-12-06 18:36:31,912 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:36:31,913 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:31,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:31,913 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 5 times [2021-12-06 18:36:31,913 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:31,913 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196481786] [2021-12-06 18:36:31,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:31,914 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:31,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:31,918 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:31,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:31,923 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:31,969 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:31,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-12-06 18:36:31,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-12-06 18:36:31,972 INFO L87 Difference]: Start difference. First operand 52 states and 55 transitions. cyclomatic complexity: 5 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:32,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:32,064 INFO L93 Difference]: Finished difference Result 100 states and 103 transitions. [2021-12-06 18:36:32,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-12-06 18:36:32,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 103 transitions. [2021-12-06 18:36:32,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:32,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 100 states and 103 transitions. [2021-12-06 18:36:32,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:32,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:32,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 103 transitions. [2021-12-06 18:36:32,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:32,068 INFO L681 BuchiCegarLoop]: Abstraction has 100 states and 103 transitions. [2021-12-06 18:36:32,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 103 transitions. [2021-12-06 18:36:32,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2021-12-06 18:36:32,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.03) internal successors, (103), 99 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:32,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 103 transitions. [2021-12-06 18:36:32,073 INFO L704 BuchiCegarLoop]: Abstraction has 100 states and 103 transitions. [2021-12-06 18:36:32,073 INFO L587 BuchiCegarLoop]: Abstraction has 100 states and 103 transitions. [2021-12-06 18:36:32,073 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 18:36:32,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 103 transitions. [2021-12-06 18:36:32,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:32,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:32,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:32,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2021-12-06 18:36:32,077 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:32,077 INFO L791 eck$LassoCheckResult]: Stem: 1055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 1060#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1061#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1062#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1057#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1058#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1152#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1151#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1150#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1149#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1148#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1147#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1146#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1145#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1144#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1143#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1142#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1141#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1140#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1139#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1138#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1137#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1136#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1135#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1134#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1133#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1132#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1131#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1130#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1129#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1128#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1127#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1126#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1125#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1124#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1123#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1122#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1121#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1120#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1119#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1118#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1117#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1116#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1115#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1114#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1113#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1112#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1111#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1110#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1109#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1108#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1107#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1106#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1105#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1104#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1103#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1102#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1101#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1100#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1099#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1098#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1097#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1096#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1095#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1094#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1093#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1092#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1091#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1090#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1089#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1088#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1087#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1086#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1085#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1084#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1083#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1082#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1081#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1080#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1079#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1078#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1077#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1076#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1075#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1074#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1073#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1072#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1071#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1070#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1069#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1068#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1067#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1066#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1065#L18-3 assume !(main_~i~0#1 < 1048); 1063#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 1059#L23-2 [2021-12-06 18:36:32,078 INFO L793 eck$LassoCheckResult]: Loop: 1059#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 1053#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 1054#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 1064#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 1059#L23-2 [2021-12-06 18:36:32,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:32,078 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 5 times [2021-12-06 18:36:32,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:32,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163876989] [2021-12-06 18:36:32,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:32,079 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:32,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:32,761 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:32,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:32,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163876989] [2021-12-06 18:36:32,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163876989] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:32,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1437435277] [2021-12-06 18:36:32,762 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 18:36:32,762 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:32,762 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:32,763 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:32,764 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-12-06 18:36:47,664 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2021-12-06 18:36:47,665 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:36:47,691 INFO L263 TraceCheckSpWp]: Trace formula consists of 538 conjuncts, 48 conjunts are in the unsatisfiable core [2021-12-06 18:36:47,695 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:36:47,827 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:47,827 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:36:49,286 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:49,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1437435277] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:36:49,287 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:36:49,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2021-12-06 18:36:49,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359743323] [2021-12-06 18:36:49,288 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:36:49,288 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:36:49,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:49,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 6 times [2021-12-06 18:36:49,289 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:49,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753877924] [2021-12-06 18:36:49,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:49,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:49,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:49,294 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:36:49,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:36:49,298 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:36:49,345 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:36:49,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2021-12-06 18:36:49,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2021-12-06 18:36:49,350 INFO L87 Difference]: Start difference. First operand 100 states and 103 transitions. cyclomatic complexity: 5 Second operand has 97 states, 97 states have (on average 1.9896907216494846) internal successors, (193), 97 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:49,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:36:49,590 INFO L93 Difference]: Finished difference Result 196 states and 199 transitions. [2021-12-06 18:36:49,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2021-12-06 18:36:49,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196 states and 199 transitions. [2021-12-06 18:36:49,594 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:49,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196 states to 196 states and 199 transitions. [2021-12-06 18:36:49,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 18:36:49,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 18:36:49,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 199 transitions. [2021-12-06 18:36:49,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:36:49,598 INFO L681 BuchiCegarLoop]: Abstraction has 196 states and 199 transitions. [2021-12-06 18:36:49,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 199 transitions. [2021-12-06 18:36:49,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 196. [2021-12-06 18:36:49,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.0153061224489797) internal successors, (199), 195 states have internal predecessors, (199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:36:49,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 199 transitions. [2021-12-06 18:36:49,608 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 199 transitions. [2021-12-06 18:36:49,608 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 199 transitions. [2021-12-06 18:36:49,608 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 18:36:49,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 199 transitions. [2021-12-06 18:36:49,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 18:36:49,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:36:49,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:36:49,614 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1] [2021-12-06 18:36:49,614 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 18:36:49,615 INFO L791 eck$LassoCheckResult]: Stem: 2019#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset, main_#t~nondet3#1, main_#t~post2#1, main_~i~0#1, main_#t~nondet6#1, main_#t~post7#1.base, main_#t~post7#1.offset, main_#t~mem8#1, main_#t~post9#1, main_#t~mem4#1, main_#t~short5#1, main_~p~0#1.base, main_~p~0#1.offset, main_~q~0#1.base, main_~q~0#1.offset;call main_#t~malloc1#1.base, main_#t~malloc1#1.offset := #Ultimate.allocOnHeap(4192);main_~p~0#1.base, main_~p~0#1.offset := main_#t~malloc1#1.base, main_#t~malloc1#1.offset;havoc main_#t~malloc1#1.base, main_#t~malloc1#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset;main_~i~0#1 := 0; 2026#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2027#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2028#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2023#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2024#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2214#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2213#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2212#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2211#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2210#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2209#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2208#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2207#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2206#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2205#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2204#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2203#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2202#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2201#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2200#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2199#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2198#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2197#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2196#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2195#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2194#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2193#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2192#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2191#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2190#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2189#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2188#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2187#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2186#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2185#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2184#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2183#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2182#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2181#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2180#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2179#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2178#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2177#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2176#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2175#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2174#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2173#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2172#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2171#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2170#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2169#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2168#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2167#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2166#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2165#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2164#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2163#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2162#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2161#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2160#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2159#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2158#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2157#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2156#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2155#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2154#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2153#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2152#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2151#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2150#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2149#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2148#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2147#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2146#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2145#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2144#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2143#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2142#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2141#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2140#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2139#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2138#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2137#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2136#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2135#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2134#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2133#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2132#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2131#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2130#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2129#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2128#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2127#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2126#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2125#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2124#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2123#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2122#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2121#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2120#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2119#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2118#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2117#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2116#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2115#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2114#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2113#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2112#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2111#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2110#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2109#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2108#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2107#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2106#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2105#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2104#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2103#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2102#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2101#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2100#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2099#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2098#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2097#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2096#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2095#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2094#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2093#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2092#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2091#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2090#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2089#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2088#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2087#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2086#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2085#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2084#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2083#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2082#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2081#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2080#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2079#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2078#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2077#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2076#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2075#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2074#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2073#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2072#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2071#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2070#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2069#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2068#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2067#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2066#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2065#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2064#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2063#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2062#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2061#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2060#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2059#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2058#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2057#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2056#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2055#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2054#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2053#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2052#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2051#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2050#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2049#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2048#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2047#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2046#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2045#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2044#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2043#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2042#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2041#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2040#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2039#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2038#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2037#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2036#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2035#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2034#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2033#L18-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet3#1, main_~q~0#1.base, main_~q~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2032#L18-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2031#L18-3 assume !(main_~i~0#1 < 1048); 2029#L18-4 main_~q~0#1.base, main_~q~0#1.offset := main_~p~0#1.base, main_~p~0#1.offset; 2025#L23-2 [2021-12-06 18:36:49,615 INFO L793 eck$LassoCheckResult]: Loop: 2025#L23-2 assume main_~q~0#1.base == main_~p~0#1.base;main_#t~short5#1 := main_~q~0#1.offset < 4192 + main_~p~0#1.offset; 2021#L22-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~q~0#1.base, main_~q~0#1.offset, 4);main_#t~short5#1 := main_#t~mem4#1 >= 0; 2022#L22-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 2030#L23 assume 0 != main_#t~nondet6#1;havoc main_#t~nondet6#1;main_#t~post7#1.base, main_#t~post7#1.offset := main_~q~0#1.base, main_~q~0#1.offset;main_~q~0#1.base, main_~q~0#1.offset := main_#t~post7#1.base, 4 + main_#t~post7#1.offset;havoc main_#t~post7#1.base, main_#t~post7#1.offset; 2025#L23-2 [2021-12-06 18:36:49,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:36:49,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1165371207, now seen corresponding path program 6 times [2021-12-06 18:36:49,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:36:49,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666000625] [2021-12-06 18:36:49,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:36:49,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:36:49,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:36:51,763 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:36:51,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:36:51,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666000625] [2021-12-06 18:36:51,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666000625] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:36:51,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1573495332] [2021-12-06 18:36:51,763 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 18:36:51,763 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:36:51,764 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:36:51,764 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:36:51,766 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1a31846d-f8a8-4229-8d94-df6bbf2751a7/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process