./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 21:48:04,985 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 21:48:04,987 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 21:48:05,018 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 21:48:05,019 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 21:48:05,020 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 21:48:05,022 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 21:48:05,024 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 21:48:05,026 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 21:48:05,027 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 21:48:05,028 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 21:48:05,030 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 21:48:05,030 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 21:48:05,031 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 21:48:05,033 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 21:48:05,034 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 21:48:05,035 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 21:48:05,036 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 21:48:05,038 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 21:48:05,040 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 21:48:05,042 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 21:48:05,043 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 21:48:05,045 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 21:48:05,046 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 21:48:05,049 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 21:48:05,049 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 21:48:05,050 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 21:48:05,051 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 21:48:05,051 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 21:48:05,052 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 21:48:05,053 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 21:48:05,054 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 21:48:05,054 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 21:48:05,055 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 21:48:05,056 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 21:48:05,056 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 21:48:05,057 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 21:48:05,057 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 21:48:05,057 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 21:48:05,058 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 21:48:05,059 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 21:48:05,059 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-12-06 21:48:05,081 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 21:48:05,082 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 21:48:05,082 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 21:48:05,082 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 21:48:05,083 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 21:48:05,083 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 21:48:05,084 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 21:48:05,084 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 21:48:05,084 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 21:48:05,084 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 21:48:05,084 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 21:48:05,084 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 21:48:05,085 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 21:48:05,085 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 21:48:05,085 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 21:48:05,085 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 21:48:05,085 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 21:48:05,086 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 21:48:05,087 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 21:48:05,087 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 21:48:05,087 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 21:48:05,087 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 21:48:05,087 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 21:48:05,088 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 21:48:05,088 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 21:48:05,089 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2021-12-06 21:48:05,270 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 21:48:05,285 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 21:48:05,287 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 21:48:05,288 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 21:48:05,288 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 21:48:05,289 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/termination-15/array12_alloca.i [2021-12-06 21:48:05,334 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/data/f20851705/1027a5577e5e466f8885bd27c1d1b7a9/FLAG5ccbddc9c [2021-12-06 21:48:05,721 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 21:48:05,722 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/sv-benchmarks/c/termination-15/array12_alloca.i [2021-12-06 21:48:05,729 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/data/f20851705/1027a5577e5e466f8885bd27c1d1b7a9/FLAG5ccbddc9c [2021-12-06 21:48:05,739 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/data/f20851705/1027a5577e5e466f8885bd27c1d1b7a9 [2021-12-06 21:48:05,741 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 21:48:05,742 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 21:48:05,744 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 21:48:05,744 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 21:48:05,747 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 21:48:05,747 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 09:48:05" (1/1) ... [2021-12-06 21:48:05,748 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b72a201 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:05, skipping insertion in model container [2021-12-06 21:48:05,748 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 09:48:05" (1/1) ... [2021-12-06 21:48:05,753 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 21:48:05,774 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 21:48:05,969 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 21:48:05,975 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 21:48:05,999 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 21:48:06,022 INFO L208 MainTranslator]: Completed translation [2021-12-06 21:48:06,022 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06 WrapperNode [2021-12-06 21:48:06,022 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 21:48:06,023 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 21:48:06,023 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 21:48:06,023 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 21:48:06,029 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,038 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,052 INFO L137 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2021-12-06 21:48:06,052 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 21:48:06,053 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 21:48:06,053 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 21:48:06,053 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 21:48:06,059 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,059 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,060 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,061 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,064 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,067 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,067 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,069 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 21:48:06,069 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 21:48:06,069 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 21:48:06,069 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 21:48:06,070 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (1/1) ... [2021-12-06 21:48:06,076 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:06,087 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:06,098 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:06,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 21:48:06,130 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-12-06 21:48:06,130 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 21:48:06,130 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 21:48:06,130 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 21:48:06,130 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 21:48:06,131 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 21:48:06,185 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 21:48:06,186 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 21:48:06,270 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 21:48:06,276 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 21:48:06,276 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 21:48:06,278 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 09:48:06 BoogieIcfgContainer [2021-12-06 21:48:06,278 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 21:48:06,279 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 21:48:06,279 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 21:48:06,282 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 21:48:06,282 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 21:48:06,283 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 09:48:05" (1/3) ... [2021-12-06 21:48:06,283 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2d8a0dc4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 09:48:06, skipping insertion in model container [2021-12-06 21:48:06,283 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 21:48:06,284 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 09:48:06" (2/3) ... [2021-12-06 21:48:06,284 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2d8a0dc4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 09:48:06, skipping insertion in model container [2021-12-06 21:48:06,284 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 21:48:06,284 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 09:48:06" (3/3) ... [2021-12-06 21:48:06,286 INFO L388 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2021-12-06 21:48:06,326 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 21:48:06,326 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 21:48:06,326 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 21:48:06,326 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 21:48:06,327 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 21:48:06,327 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 21:48:06,327 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 21:48:06,327 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 21:48:06,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:06,351 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-12-06 21:48:06,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:06,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:06,355 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-12-06 21:48:06,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-12-06 21:48:06,356 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 21:48:06,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:06,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-12-06 21:48:06,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:06,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:06,358 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-12-06 21:48:06,358 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-12-06 21:48:06,363 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11#L367true assume !(main_~length~0#1 < 1); 8#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6#L370-3true [2021-12-06 21:48:06,364 INFO L793 eck$LassoCheckResult]: Loop: 6#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13#L372true assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6#L370-3true [2021-12-06 21:48:06,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:06,369 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2021-12-06 21:48:06,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:06,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682581011] [2021-12-06 21:48:06,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:06,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:06,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,449 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:06,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,476 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:06,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:06,480 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2021-12-06 21:48:06,480 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:06,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829807770] [2021-12-06 21:48:06,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:06,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:06,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,497 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:06,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,507 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:06,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:06,509 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2021-12-06 21:48:06,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:06,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722062428] [2021-12-06 21:48:06,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:06,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:06,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,527 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:06,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:06,543 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:06,736 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 21:48:06,736 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 21:48:06,736 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 21:48:06,736 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 21:48:06,736 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 21:48:06,736 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:06,736 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 21:48:06,737 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 21:48:06,737 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2021-12-06 21:48:06,737 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 21:48:06,737 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 21:48:06,750 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,754 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,757 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,758 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,760 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,821 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,823 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,824 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,826 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,827 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,829 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,831 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:48:06,942 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 21:48:06,946 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 21:48:06,947 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:06,947 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:06,948 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:06,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-06 21:48:06,950 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:06,957 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:06,957 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:48:06,957 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:06,958 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:06,958 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:06,959 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:48:06,959 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:48:06,960 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:06,979 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-06 21:48:06,980 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:06,980 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:06,981 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:06,981 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-06 21:48:06,982 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:06,989 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:06,989 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:06,989 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:06,989 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:06,992 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:48:06,992 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:48:06,995 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,015 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-12-06 21:48:07,016 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,016 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,017 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-06 21:48:07,018 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,026 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,026 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:48:07,026 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,026 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,026 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,027 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:48:07,027 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:48:07,029 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,049 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-12-06 21:48:07,049 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,049 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,050 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,051 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-06 21:48:07,051 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,059 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,059 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:48:07,059 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,059 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,059 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,060 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:48:07,060 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:48:07,061 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,081 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2021-12-06 21:48:07,081 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,081 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,082 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-06 21:48:07,083 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,092 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,092 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:48:07,092 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,093 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,093 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,093 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:48:07,093 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:48:07,094 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,113 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2021-12-06 21:48:07,113 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,114 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,114 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-06 21:48:07,115 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,123 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,123 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,123 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,123 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,126 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:48:07,126 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:48:07,129 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,159 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2021-12-06 21:48:07,160 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,161 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,161 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-06 21:48:07,162 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,169 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,169 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,169 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,169 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,172 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:48:07,172 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:48:07,176 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:48:07,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-12-06 21:48:07,195 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,196 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-12-06 21:48:07,197 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:48:07,204 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:48:07,204 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:48:07,204 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:48:07,204 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:48:07,210 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:48:07,210 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:48:07,225 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 21:48:07,248 INFO L443 ModelExtractionUtils]: Simplification made 13 calls to the SMT solver. [2021-12-06 21:48:07,248 INFO L444 ModelExtractionUtils]: 6 out of 22 variables were initially zero. Simplification set additionally 12 variables to zero. [2021-12-06 21:48:07,249 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:48:07,250 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,251 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-12-06 21:48:07,286 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 21:48:07,295 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 21:48:07,295 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 21:48:07,296 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~arr~0#1.offset) = -4*ULTIMATE.start_main_~i~0#1 + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2021-12-06 21:48:07,315 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-12-06 21:48:07,322 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-12-06 21:48:07,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:07,347 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-06 21:48:07,348 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:07,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:07,364 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 21:48:07,364 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:07,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:07,408 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-12-06 21:48:07,409 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:07,443 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2021-12-06 21:48:07,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-12-06 21:48:07,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:07,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2021-12-06 21:48:07,449 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2021-12-06 21:48:07,450 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:48:07,450 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2021-12-06 21:48:07,450 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:48:07,450 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2021-12-06 21:48:07,451 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:48:07,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2021-12-06 21:48:07,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:07,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2021-12-06 21:48:07,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 21:48:07,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-12-06 21:48:07,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2021-12-06 21:48:07,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:07,458 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 21:48:07,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2021-12-06 21:48:07,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-12-06 21:48:07,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:07,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2021-12-06 21:48:07,475 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 21:48:07,475 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 21:48:07,475 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 21:48:07,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2021-12-06 21:48:07,476 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:07,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:07,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:07,476 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:07,476 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:07,476 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 121#L367 assume !(main_~length~0#1 < 1); 115#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 116#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 117#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 118#L370-4 main_~j~0#1 := 0; 119#L378-2 [2021-12-06 21:48:07,477 INFO L793 eck$LassoCheckResult]: Loop: 119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 120#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 119#L378-2 [2021-12-06 21:48:07,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,477 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2021-12-06 21:48:07,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:07,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632977114] [2021-12-06 21:48:07,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:07,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:07,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:07,515 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:07,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632977114] [2021-12-06 21:48:07,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632977114] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 21:48:07,516 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 21:48:07,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 21:48:07,516 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771969676] [2021-12-06 21:48:07,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 21:48:07,518 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:48:07,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,519 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2021-12-06 21:48:07,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:07,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144175505] [2021-12-06 21:48:07,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,520 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:07,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,526 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:07,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,533 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:07,569 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:07,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 21:48:07,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-12-06 21:48:07,572 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:07,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:07,593 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2021-12-06 21:48:07,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 21:48:07,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2021-12-06 21:48:07,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:07,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2021-12-06 21:48:07,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-12-06 21:48:07,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-12-06 21:48:07,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2021-12-06 21:48:07,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:07,596 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 19 transitions. [2021-12-06 21:48:07,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2021-12-06 21:48:07,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2021-12-06 21:48:07,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:07,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2021-12-06 21:48:07,598 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-12-06 21:48:07,598 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-12-06 21:48:07,598 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 21:48:07,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2021-12-06 21:48:07,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:07,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:07,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:07,600 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:07,600 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:07,600 INFO L791 eck$LassoCheckResult]: Stem: 146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 154#L367 assume !(main_~length~0#1 < 1); 148#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 149#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 156#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 151#L370-4 main_~j~0#1 := 0; 152#L378-2 [2021-12-06 21:48:07,600 INFO L793 eck$LassoCheckResult]: Loop: 152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 153#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 152#L378-2 [2021-12-06 21:48:07,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2021-12-06 21:48:07,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:07,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999305566] [2021-12-06 21:48:07,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:07,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,614 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:07,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,628 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:07,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2021-12-06 21:48:07,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:07,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666133056] [2021-12-06 21:48:07,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,629 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:07,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,634 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:07,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:07,639 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:07,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:07,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2021-12-06 21:48:07,640 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:07,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671125950] [2021-12-06 21:48:07,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:07,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:07,759 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:07,759 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:07,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671125950] [2021-12-06 21:48:07,759 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671125950] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:07,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1683163086] [2021-12-06 21:48:07,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:07,760 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:07,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:07,760 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:07,761 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-12-06 21:48:07,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:07,794 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2021-12-06 21:48:07,795 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:07,838 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-12-06 21:48:07,891 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:48:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:07,897 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:07,900 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-12-06 21:48:07,942 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2021-12-06 21:48:07,946 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2021-12-06 21:48:07,957 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:07,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1683163086] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:07,957 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:07,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2021-12-06 21:48:07,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647223158] [2021-12-06 21:48:07,958 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:07,985 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:07,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-12-06 21:48:07,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2021-12-06 21:48:07,986 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:08,061 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2021-12-06 21:48:08,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 21:48:08,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2021-12-06 21:48:08,063 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:08,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2021-12-06 21:48:08,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-12-06 21:48:08,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-12-06 21:48:08,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2021-12-06 21:48:08,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:08,065 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 30 transitions. [2021-12-06 21:48:08,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2021-12-06 21:48:08,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2021-12-06 21:48:08,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2021-12-06 21:48:08,067 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2021-12-06 21:48:08,067 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2021-12-06 21:48:08,067 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 21:48:08,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2021-12-06 21:48:08,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:08,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:08,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:08,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:08,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:08,069 INFO L791 eck$LassoCheckResult]: Stem: 270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 278#L367 assume !(main_~length~0#1 < 1); 272#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 273#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 274#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 279#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 280#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 281#L370-4 main_~j~0#1 := 0; 287#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 275#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 276#L378-2 [2021-12-06 21:48:08,069 INFO L793 eck$LassoCheckResult]: Loop: 276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 284#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 276#L378-2 [2021-12-06 21:48:08,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2021-12-06 21:48:08,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265101834] [2021-12-06 21:48:08,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,070 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,080 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:08,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,091 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:08,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,092 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2021-12-06 21:48:08,092 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799219948] [2021-12-06 21:48:08,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,092 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,097 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:08,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:08,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,101 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2021-12-06 21:48:08,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590603592] [2021-12-06 21:48:08,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,196 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,196 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:08,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590603592] [2021-12-06 21:48:08,197 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590603592] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:08,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [113391864] [2021-12-06 21:48:08,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,197 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:08,197 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:08,198 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:08,199 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-12-06 21:48:08,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,226 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 21:48:08,227 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:08,276 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,276 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:08,308 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [113391864] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:08,308 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:08,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2021-12-06 21:48:08,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559054544] [2021-12-06 21:48:08,309 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:08,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:08,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-12-06 21:48:08,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2021-12-06 21:48:08,339 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 15 states, 15 states have (on average 1.8666666666666667) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:08,439 INFO L93 Difference]: Finished difference Result 42 states and 56 transitions. [2021-12-06 21:48:08,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 21:48:08,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 56 transitions. [2021-12-06 21:48:08,442 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:08,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 38 states and 50 transitions. [2021-12-06 21:48:08,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-12-06 21:48:08,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-12-06 21:48:08,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 50 transitions. [2021-12-06 21:48:08,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:08,444 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 50 transitions. [2021-12-06 21:48:08,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 50 transitions. [2021-12-06 21:48:08,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2021-12-06 21:48:08,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2021-12-06 21:48:08,449 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2021-12-06 21:48:08,449 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2021-12-06 21:48:08,449 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 21:48:08,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2021-12-06 21:48:08,450 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:08,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:08,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:08,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:08,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:08,451 INFO L791 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 446#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 439#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 440#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 441#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 448#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 457#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 458#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 459#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 455#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 442#L370-4 main_~j~0#1 := 0; 443#L378-2 [2021-12-06 21:48:08,451 INFO L793 eck$LassoCheckResult]: Loop: 443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 453#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 443#L378-2 [2021-12-06 21:48:08,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2021-12-06 21:48:08,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938014176] [2021-12-06 21:48:08,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,452 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,499 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:08,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938014176] [2021-12-06 21:48:08,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938014176] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:08,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [306122873] [2021-12-06 21:48:08,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,500 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:08,500 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:08,501 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:08,502 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-12-06 21:48:08,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,532 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 21:48:08,533 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:08,562 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,562 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 21:48:08,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [306122873] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 21:48:08,563 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 21:48:08,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2021-12-06 21:48:08,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039260408] [2021-12-06 21:48:08,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 21:48:08,563 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:48:08,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,563 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2021-12-06 21:48:08,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932319173] [2021-12-06 21:48:08,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,567 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:08,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,571 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:08,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:08,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 21:48:08,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2021-12-06 21:48:08,599 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:08,615 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2021-12-06 21:48:08,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 21:48:08,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2021-12-06 21:48:08,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:08,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2021-12-06 21:48:08,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-12-06 21:48:08,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-12-06 21:48:08,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2021-12-06 21:48:08,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:08,618 INFO L681 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-12-06 21:48:08,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2021-12-06 21:48:08,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2021-12-06 21:48:08,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:08,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2021-12-06 21:48:08,620 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-12-06 21:48:08,620 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2021-12-06 21:48:08,620 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 21:48:08,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2021-12-06 21:48:08,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:08,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:08,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:08,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:08,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:08,622 INFO L791 eck$LassoCheckResult]: Stem: 545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 553#L367 assume !(main_~length~0#1 < 1); 547#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 548#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 549#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 557#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 555#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 556#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 564#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 561#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 552#L370-4 main_~j~0#1 := 0; 551#L378-2 [2021-12-06 21:48:08,622 INFO L793 eck$LassoCheckResult]: Loop: 551#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 558#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 551#L378-2 [2021-12-06 21:48:08,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2021-12-06 21:48:08,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945048524] [2021-12-06 21:48:08,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,623 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,632 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:08,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,643 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:08,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,644 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2021-12-06 21:48:08,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979343119] [2021-12-06 21:48:08,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,648 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:08,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:08,651 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:08,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:08,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2021-12-06 21:48:08,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:08,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701826340] [2021-12-06 21:48:08,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:08,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,776 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,776 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:08,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701826340] [2021-12-06 21:48:08,777 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701826340] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:08,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1535692412] [2021-12-06 21:48:08,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:08,777 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:08,777 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:08,778 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:08,781 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-12-06 21:48:08,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:08,814 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2021-12-06 21:48:08,815 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:08,831 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:48:08,886 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:48:08,887 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 29 [2021-12-06 21:48:08,906 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:48:08,906 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 29 [2021-12-06 21:48:08,934 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:48:08,941 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:08,941 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:21,019 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_36| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_92 Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|))))) is different from false [2021-12-06 21:48:33,050 WARN L227 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 23 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 21:48:33,061 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2021-12-06 21:48:33,064 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 150 [2021-12-06 21:48:33,118 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2021-12-06 21:48:33,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1535692412] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:33,118 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:33,118 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2021-12-06 21:48:33,118 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272130902] [2021-12-06 21:48:33,119 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:33,142 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:33,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-12-06 21:48:33,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=239, Unknown=1, NotChecked=32, Total=342 [2021-12-06 21:48:33,143 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:45,162 WARN L838 $PredicateComparison]: unable to prove that (and (<= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (= (+ (* 4 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_36| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_92 Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|))))) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0)) is different from false [2021-12-06 21:48:57,181 WARN L838 $PredicateComparison]: unable to prove that (and (<= (+ (div (* |c_ULTIMATE.start_main_~arr~0#1.offset| (- 1)) 4) 1) |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_36| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_92 Int)) (<= 0 (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|))))) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* (div (- |c_ULTIMATE.start_main_~arr~0#1.offset|) 4) 4) |c_ULTIMATE.start_main_~arr~0#1.offset|)))) is different from false [2021-12-06 21:48:57,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:57,258 INFO L93 Difference]: Finished difference Result 31 states and 39 transitions. [2021-12-06 21:48:57,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 21:48:57,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 39 transitions. [2021-12-06 21:48:57,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:57,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 39 transitions. [2021-12-06 21:48:57,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-12-06 21:48:57,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-12-06 21:48:57,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 39 transitions. [2021-12-06 21:48:57,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:57,260 INFO L681 BuchiCegarLoop]: Abstraction has 31 states and 39 transitions. [2021-12-06 21:48:57,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 39 transitions. [2021-12-06 21:48:57,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 17. [2021-12-06 21:48:57,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:57,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2021-12-06 21:48:57,262 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2021-12-06 21:48:57,262 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2021-12-06 21:48:57,262 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 21:48:57,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2021-12-06 21:48:57,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:57,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:57,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:57,263 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:57,263 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:57,263 INFO L791 eck$LassoCheckResult]: Stem: 718#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 727#L367 assume !(main_~length~0#1 < 1); 720#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 721#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 722#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 728#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 733#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 729#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 730#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 731#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 732#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 725#L370-4 main_~j~0#1 := 0; 726#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 723#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 724#L378-2 [2021-12-06 21:48:57,263 INFO L793 eck$LassoCheckResult]: Loop: 724#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 734#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 724#L378-2 [2021-12-06 21:48:57,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2021-12-06 21:48:57,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017589142] [2021-12-06 21:48:57,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,264 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,272 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,280 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:57,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,280 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2021-12-06 21:48:57,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161529916] [2021-12-06 21:48:57,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,283 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,285 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:57,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,285 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2021-12-06 21:48:57,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579495477] [2021-12-06 21:48:57,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:57,352 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:57,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579495477] [2021-12-06 21:48:57,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579495477] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:57,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1665346074] [2021-12-06 21:48:57,353 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:48:57,353 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:57,354 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:57,354 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:57,355 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-12-06 21:48:57,386 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:48:57,386 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:48:57,387 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 14 conjunts are in the unsatisfiable core [2021-12-06 21:48:57,388 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:57,405 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:48:57,462 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:48:57,464 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,464 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:57,501 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:48:57,503 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:48:57,515 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1665346074] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:57,516 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:57,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 13 [2021-12-06 21:48:57,516 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502959313] [2021-12-06 21:48:57,516 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:57,542 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:57,542 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-12-06 21:48:57,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2021-12-06 21:48:57,542 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 6 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:57,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:57,601 INFO L93 Difference]: Finished difference Result 29 states and 37 transitions. [2021-12-06 21:48:57,601 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 21:48:57,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 37 transitions. [2021-12-06 21:48:57,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:57,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 29 states and 37 transitions. [2021-12-06 21:48:57,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 21:48:57,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 21:48:57,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2021-12-06 21:48:57,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:57,603 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-12-06 21:48:57,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2021-12-06 21:48:57,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 24. [2021-12-06 21:48:57,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:57,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2021-12-06 21:48:57,605 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2021-12-06 21:48:57,605 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2021-12-06 21:48:57,605 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 21:48:57,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2021-12-06 21:48:57,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:57,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:57,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:57,606 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:57,606 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:57,606 INFO L791 eck$LassoCheckResult]: Stem: 881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 889#L367 assume !(main_~length~0#1 < 1); 883#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 884#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 885#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 890#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 892#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 895#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 896#L370-4 main_~j~0#1 := 0; 901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 888#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 894#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 900#L378-2 [2021-12-06 21:48:57,606 INFO L793 eck$LassoCheckResult]: Loop: 900#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 899#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 900#L378-2 [2021-12-06 21:48:57,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,606 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2021-12-06 21:48:57,606 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238475454] [2021-12-06 21:48:57,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,614 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,622 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:57,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,623 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2021-12-06 21:48:57,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573112959] [2021-12-06 21:48:57,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,623 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,625 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,627 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:57,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,628 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2021-12-06 21:48:57,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677884780] [2021-12-06 21:48:57,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:57,714 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:57,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677884780] [2021-12-06 21:48:57,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677884780] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:57,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [834616793] [2021-12-06 21:48:57,715 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:48:57,715 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:57,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:57,716 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:57,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-12-06 21:48:57,746 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2021-12-06 21:48:57,747 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:48:57,747 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 21:48:57,748 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:57,807 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,808 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:57,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [834616793] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:57,840 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:57,840 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2021-12-06 21:48:57,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497471574] [2021-12-06 21:48:57,841 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:57,865 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:57,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-12-06 21:48:57,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=298, Unknown=0, NotChecked=0, Total=380 [2021-12-06 21:48:57,866 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:57,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:57,964 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2021-12-06 21:48:57,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 21:48:57,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2021-12-06 21:48:57,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:57,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2021-12-06 21:48:57,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-12-06 21:48:57,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-12-06 21:48:57,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2021-12-06 21:48:57,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:57,967 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-12-06 21:48:57,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2021-12-06 21:48:57,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2021-12-06 21:48:57,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:57,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2021-12-06 21:48:57,969 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2021-12-06 21:48:57,969 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2021-12-06 21:48:57,969 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 21:48:57,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2021-12-06 21:48:57,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:57,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:57,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:57,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:57,970 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:57,970 INFO L791 eck$LassoCheckResult]: Stem: 1081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1090#L367 assume !(main_~length~0#1 < 1); 1083#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1084#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1085#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1091#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1106#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1094#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1095#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1092#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1093#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1103#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1101#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1100#L370-4 main_~j~0#1 := 0; 1089#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1099#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1098#L378-2 [2021-12-06 21:48:57,970 INFO L793 eck$LassoCheckResult]: Loop: 1098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1097#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1098#L378-2 [2021-12-06 21:48:57,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 1 times [2021-12-06 21:48:57,970 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662169068] [2021-12-06 21:48:57,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,981 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,993 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:57,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:57,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2021-12-06 21:48:57,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:57,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902198723] [2021-12-06 21:48:57,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:57,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:57,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:57,997 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:57,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:58,000 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:58,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:58,000 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 1 times [2021-12-06 21:48:58,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:58,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192184771] [2021-12-06 21:48:58,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:58,001 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:58,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:58,079 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,079 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:58,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192184771] [2021-12-06 21:48:58,079 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192184771] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:58,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [673868521] [2021-12-06 21:48:58,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:58,080 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:58,080 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:58,080 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:58,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-12-06 21:48:58,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:58,113 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 23 conjunts are in the unsatisfiable core [2021-12-06 21:48:58,115 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:58,155 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:48:58,211 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:48:58,211 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:48:58,220 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:48:58,221 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:48:58,275 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:48:58,277 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,277 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:58,366 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:48:58,368 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:48:58,385 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,385 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [673868521] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:58,386 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:58,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2021-12-06 21:48:58,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146049243] [2021-12-06 21:48:58,386 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:58,413 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:58,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 21:48:58,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2021-12-06 21:48:58,414 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:58,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:58,512 INFO L93 Difference]: Finished difference Result 30 states and 37 transitions. [2021-12-06 21:48:58,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 21:48:58,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2021-12-06 21:48:58,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:58,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 37 transitions. [2021-12-06 21:48:58,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 21:48:58,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 21:48:58,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2021-12-06 21:48:58,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:58,514 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 37 transitions. [2021-12-06 21:48:58,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2021-12-06 21:48:58,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 22. [2021-12-06 21:48:58,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:58,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2021-12-06 21:48:58,516 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2021-12-06 21:48:58,516 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2021-12-06 21:48:58,516 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 21:48:58,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2021-12-06 21:48:58,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:58,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:58,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:58,517 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:58,517 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:58,517 INFO L791 eck$LassoCheckResult]: Stem: 1287#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1296#L367 assume !(main_~length~0#1 < 1); 1289#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1290#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1291#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1297#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1302#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1305#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1298#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1304#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1294#L370-4 main_~j~0#1 := 0; 1295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1292#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1293#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1300#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1308#L378-2 [2021-12-06 21:48:58,517 INFO L793 eck$LassoCheckResult]: Loop: 1308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1307#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1308#L378-2 [2021-12-06 21:48:58,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:58,517 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 4 times [2021-12-06 21:48:58,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:58,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279808431] [2021-12-06 21:48:58,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:58,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:58,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:58,527 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:58,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:58,536 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:58,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:58,536 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2021-12-06 21:48:58,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:58,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355354926] [2021-12-06 21:48:58,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:58,536 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:58,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:58,538 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:58,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:58,540 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:58,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:58,541 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2021-12-06 21:48:58,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:58,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927472447] [2021-12-06 21:48:58,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:58,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:58,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:58,627 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:58,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927472447] [2021-12-06 21:48:58,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927472447] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:58,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [355064251] [2021-12-06 21:48:58,628 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:48:58,628 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:58,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:58,629 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:58,630 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-12-06 21:48:58,663 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:48:58,663 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:48:58,664 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 22 conjunts are in the unsatisfiable core [2021-12-06 21:48:58,665 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:58,721 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:48:58,797 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:48:58,798 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,799 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:58,839 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:48:58,841 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:48:58,872 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:58,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [355064251] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:58,872 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:58,872 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 10] total 22 [2021-12-06 21:48:58,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945224131] [2021-12-06 21:48:58,873 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:58,902 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:58,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 21:48:58,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2021-12-06 21:48:58,903 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:59,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:59,063 INFO L93 Difference]: Finished difference Result 36 states and 45 transitions. [2021-12-06 21:48:59,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 21:48:59,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 45 transitions. [2021-12-06 21:48:59,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:48:59,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 45 transitions. [2021-12-06 21:48:59,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-12-06 21:48:59,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-12-06 21:48:59,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 45 transitions. [2021-12-06 21:48:59,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:59,065 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 45 transitions. [2021-12-06 21:48:59,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 45 transitions. [2021-12-06 21:48:59,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 29. [2021-12-06 21:48:59,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.2758620689655173) internal successors, (37), 28 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:59,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 37 transitions. [2021-12-06 21:48:59,067 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-12-06 21:48:59,067 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-12-06 21:48:59,067 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 21:48:59,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 37 transitions. [2021-12-06 21:48:59,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:59,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:59,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:59,068 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:59,068 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:59,069 INFO L791 eck$LassoCheckResult]: Stem: 1507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1515#L367 assume !(main_~length~0#1 < 1); 1509#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1510#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1511#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1516#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1524#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1526#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1527#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1517#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1518#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1521#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1522#L370-4 main_~j~0#1 := 0; 1532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1514#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1513#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1520#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1530#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1529#L378-2 [2021-12-06 21:48:59,069 INFO L793 eck$LassoCheckResult]: Loop: 1529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1528#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1529#L378-2 [2021-12-06 21:48:59,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,069 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 5 times [2021-12-06 21:48:59,069 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173609101] [2021-12-06 21:48:59,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,080 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:59,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,093 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:59,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,093 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2021-12-06 21:48:59,093 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867616748] [2021-12-06 21:48:59,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,094 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,097 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:59,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,099 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:59,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2021-12-06 21:48:59,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708186271] [2021-12-06 21:48:59,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:59,204 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,204 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:59,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708186271] [2021-12-06 21:48:59,204 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1708186271] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:59,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1948412029] [2021-12-06 21:48:59,204 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:48:59,204 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:59,205 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:59,205 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:59,206 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-12-06 21:48:59,243 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-12-06 21:48:59,243 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:48:59,243 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2021-12-06 21:48:59,245 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:59,335 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,335 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:59,387 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1948412029] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:59,388 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:59,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11] total 25 [2021-12-06 21:48:59,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777868259] [2021-12-06 21:48:59,388 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:48:59,410 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:48:59,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-12-06 21:48:59,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2021-12-06 21:48:59,411 INFO L87 Difference]: Start difference. First operand 29 states and 37 transitions. cyclomatic complexity: 11 Second operand has 25 states, 25 states have (on average 2.04) internal successors, (51), 25 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:59,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:48:59,591 INFO L93 Difference]: Finished difference Result 42 states and 51 transitions. [2021-12-06 21:48:59,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-12-06 21:48:59,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 51 transitions. [2021-12-06 21:48:59,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:59,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 34 states and 43 transitions. [2021-12-06 21:48:59,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:48:59,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:48:59,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 43 transitions. [2021-12-06 21:48:59,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:48:59,593 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2021-12-06 21:48:59,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 43 transitions. [2021-12-06 21:48:59,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 31. [2021-12-06 21:48:59,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2580645161290323) internal successors, (39), 30 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:48:59,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 39 transitions. [2021-12-06 21:48:59,595 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 39 transitions. [2021-12-06 21:48:59,595 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 39 transitions. [2021-12-06 21:48:59,595 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 21:48:59,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 39 transitions. [2021-12-06 21:48:59,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:48:59,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:48:59,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:48:59,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:48:59,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:48:59,596 INFO L791 eck$LassoCheckResult]: Stem: 1762#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1770#L367 assume !(main_~length~0#1 < 1); 1764#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1765#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1766#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1771#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1774#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1772#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1773#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1784#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1783#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1782#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1781#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1779#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1780#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1778#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1776#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1767#L370-4 main_~j~0#1 := 0; 1768#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1775#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1787#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1786#L378-2 [2021-12-06 21:48:59,596 INFO L793 eck$LassoCheckResult]: Loop: 1786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1785#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1786#L378-2 [2021-12-06 21:48:59,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1476197922, now seen corresponding path program 2 times [2021-12-06 21:48:59,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425400831] [2021-12-06 21:48:59,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,605 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:59,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,615 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:59,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,615 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2021-12-06 21:48:59,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218596560] [2021-12-06 21:48:59,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,617 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:48:59,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:48:59,619 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:48:59,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:48:59,620 INFO L85 PathProgramCache]: Analyzing trace with hash 1286996709, now seen corresponding path program 2 times [2021-12-06 21:48:59,620 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:48:59,620 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538955758] [2021-12-06 21:48:59,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:48:59,620 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:48:59,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:48:59,714 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:48:59,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538955758] [2021-12-06 21:48:59,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538955758] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:48:59,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [4370365] [2021-12-06 21:48:59,715 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:48:59,715 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:48:59,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:48:59,716 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:48:59,717 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-12-06 21:48:59,751 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:48:59,751 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:48:59,752 INFO L263 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 23 conjunts are in the unsatisfiable core [2021-12-06 21:48:59,753 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:48:59,775 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:48:59,823 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:48:59,823 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:48:59,840 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:48:59,840 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:48:59,885 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:48:59,886 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,886 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:48:59,968 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:48:59,970 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:48:59,995 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:48:59,995 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [4370365] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:48:59,995 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:48:59,995 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2021-12-06 21:48:59,996 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923654472] [2021-12-06 21:48:59,996 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:00,019 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:00,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-12-06 21:49:00,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=321, Unknown=0, NotChecked=0, Total=380 [2021-12-06 21:49:00,020 INFO L87 Difference]: Start difference. First operand 31 states and 39 transitions. cyclomatic complexity: 11 Second operand has 20 states, 19 states have (on average 2.1052631578947367) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:00,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:00,162 INFO L93 Difference]: Finished difference Result 64 states and 79 transitions. [2021-12-06 21:49:00,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 21:49:00,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 79 transitions. [2021-12-06 21:49:00,163 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:49:00,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 64 states and 79 transitions. [2021-12-06 21:49:00,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-12-06 21:49:00,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-12-06 21:49:00,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 79 transitions. [2021-12-06 21:49:00,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:49:00,165 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 79 transitions. [2021-12-06 21:49:00,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 79 transitions. [2021-12-06 21:49:00,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 37. [2021-12-06 21:49:00,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3243243243243243) internal successors, (49), 36 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:00,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 49 transitions. [2021-12-06 21:49:00,167 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 49 transitions. [2021-12-06 21:49:00,167 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 49 transitions. [2021-12-06 21:49:00,167 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 21:49:00,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 49 transitions. [2021-12-06 21:49:00,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:00,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:00,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:00,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:00,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:00,168 INFO L791 eck$LassoCheckResult]: Stem: 2036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2044#L367 assume !(main_~length~0#1 < 1); 2038#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2039#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2045#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2052#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2053#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2057#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2060#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2059#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2046#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2047#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2049#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2071#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2055#L370-4 main_~j~0#1 := 0; 2066#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2043#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2042#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2051#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2065#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2064#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2063#L378-2 [2021-12-06 21:49:00,168 INFO L793 eck$LassoCheckResult]: Loop: 2063#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2062#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2063#L378-2 [2021-12-06 21:49:00,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:00,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1286996711, now seen corresponding path program 3 times [2021-12-06 21:49:00,168 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:00,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999068447] [2021-12-06 21:49:00,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:00,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:00,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:00,178 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:00,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:00,187 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:00,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:00,187 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2021-12-06 21:49:00,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:00,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067280312] [2021-12-06 21:49:00,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:00,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:00,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:00,189 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:00,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:00,191 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:00,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:00,192 INFO L85 PathProgramCache]: Analyzing trace with hash -146740630, now seen corresponding path program 3 times [2021-12-06 21:49:00,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:00,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162212138] [2021-12-06 21:49:00,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:00,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:00,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:00,270 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:00,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:00,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162212138] [2021-12-06 21:49:00,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162212138] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:00,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [338788281] [2021-12-06 21:49:00,270 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:00,271 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:00,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:00,271 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:00,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-12-06 21:49:00,319 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-12-06 21:49:00,319 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:00,320 INFO L263 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 21:49:00,321 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:00,365 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:00,566 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:00,566 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:00,578 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:00,578 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:00,806 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:00,808 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:00,822 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 6 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:00,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [338788281] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:00,823 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:00,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 13] total 31 [2021-12-06 21:49:00,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11017162] [2021-12-06 21:49:00,823 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:00,844 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:00,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-12-06 21:49:00,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=857, Unknown=0, NotChecked=0, Total=992 [2021-12-06 21:49:00,846 INFO L87 Difference]: Start difference. First operand 37 states and 49 transitions. cyclomatic complexity: 15 Second operand has 32 states, 31 states have (on average 1.967741935483871) internal successors, (61), 32 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:01,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:01,089 INFO L93 Difference]: Finished difference Result 56 states and 69 transitions. [2021-12-06 21:49:01,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-12-06 21:49:01,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 69 transitions. [2021-12-06 21:49:01,090 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:01,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 56 states and 69 transitions. [2021-12-06 21:49:01,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2021-12-06 21:49:01,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2021-12-06 21:49:01,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 69 transitions. [2021-12-06 21:49:01,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 21:49:01,091 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 69 transitions. [2021-12-06 21:49:01,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 69 transitions. [2021-12-06 21:49:01,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 42. [2021-12-06 21:49:01,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.3095238095238095) internal successors, (55), 41 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:01,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 55 transitions. [2021-12-06 21:49:01,093 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 55 transitions. [2021-12-06 21:49:01,093 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 55 transitions. [2021-12-06 21:49:01,093 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 21:49:01,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 55 transitions. [2021-12-06 21:49:01,094 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:01,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:01,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:01,094 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:01,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:01,094 INFO L791 eck$LassoCheckResult]: Stem: 2353#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2361#L367 assume !(main_~length~0#1 < 1); 2355#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2356#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2357#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2362#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2365#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2374#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2377#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2376#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2375#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2366#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2364#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2391#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2358#L370-4 main_~j~0#1 := 0; 2359#L378-2 [2021-12-06 21:49:01,094 INFO L793 eck$LassoCheckResult]: Loop: 2359#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2359#L378-2 [2021-12-06 21:49:01,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:01,095 INFO L85 PathProgramCache]: Analyzing trace with hash -49062696, now seen corresponding path program 2 times [2021-12-06 21:49:01,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:01,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113470288] [2021-12-06 21:49:01,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:01,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:01,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,100 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:01,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,106 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:01,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:01,107 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2021-12-06 21:49:01,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:01,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449621322] [2021-12-06 21:49:01,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:01,107 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:01,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,109 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:01,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,110 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:01,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:01,111 INFO L85 PathProgramCache]: Analyzing trace with hash 95390749, now seen corresponding path program 4 times [2021-12-06 21:49:01,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:01,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623910500] [2021-12-06 21:49:01,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:01,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:01,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,117 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:01,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:01,124 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:01,767 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 21:49:01,767 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 21:49:01,767 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 21:49:01,767 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 21:49:01,767 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 21:49:01,767 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:01,767 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 21:49:01,767 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 21:49:01,767 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration14_Lasso [2021-12-06 21:49:01,767 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 21:49:01,768 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 21:49:01,769 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,770 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,771 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,772 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,773 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,775 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,776 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,777 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,778 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:01,890 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 21:49:02,019 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 21:49:02,019 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 21:49:02,019 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,019 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,020 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,021 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2021-12-06 21:49:02,021 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,028 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,028 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,028 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,028 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,028 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,029 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,029 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,030 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,048 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2021-12-06 21:49:02,048 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,049 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,049 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,050 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-12-06 21:49:02,050 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,057 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,057 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,057 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,058 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,058 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,058 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,058 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,059 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,077 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-12-06 21:49:02,077 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,077 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,078 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-12-06 21:49:02,079 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,086 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,086 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,086 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,086 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,086 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,087 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,087 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,088 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,106 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2021-12-06 21:49:02,106 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,107 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2021-12-06 21:49:02,108 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,116 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,116 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,116 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,116 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,116 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,116 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,116 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,117 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,136 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2021-12-06 21:49:02,136 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,136 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,136 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,137 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2021-12-06 21:49:02,137 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,144 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,144 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,144 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,144 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,145 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:49:02,145 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:49:02,148 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,166 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2021-12-06 21:49:02,166 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,166 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,167 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,167 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2021-12-06 21:49:02,168 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,174 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,175 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,175 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,175 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,175 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,175 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,175 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,176 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2021-12-06 21:49:02,195 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,196 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,197 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2021-12-06 21:49:02,198 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,204 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,205 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,205 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,205 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,205 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,205 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,206 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,207 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,225 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2021-12-06 21:49:02,225 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,226 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,226 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2021-12-06 21:49:02,227 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,234 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,234 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,234 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,234 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,234 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,235 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,235 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,236 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,254 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2021-12-06 21:49:02,254 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,255 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2021-12-06 21:49:02,256 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,262 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,263 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 21:49:02,263 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,263 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,263 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,263 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 21:49:02,263 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 21:49:02,264 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,282 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2021-12-06 21:49:02,282 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,283 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,283 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,284 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2021-12-06 21:49:02,285 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,291 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,291 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,291 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,291 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,293 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:49:02,293 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:49:02,297 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,315 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2021-12-06 21:49:02,315 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,316 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2021-12-06 21:49:02,317 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,323 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,324 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,324 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,324 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,325 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:49:02,325 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:49:02,329 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 21:49:02,347 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2021-12-06 21:49:02,347 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,348 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,348 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2021-12-06 21:49:02,349 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 21:49:02,356 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 21:49:02,356 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 21:49:02,356 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 21:49:02,356 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 21:49:02,359 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 21:49:02,360 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 21:49:02,368 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 21:49:02,390 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2021-12-06 21:49:02,390 INFO L444 ModelExtractionUtils]: 3 out of 25 variables were initially zero. Simplification set additionally 18 variables to zero. [2021-12-06 21:49:02,390 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 21:49:02,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,391 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2021-12-06 21:49:02,392 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 21:49:02,401 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 21:49:02,401 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 21:49:02,401 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2, ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1) = 1*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 - 1*ULTIMATE.start_main_~arr~0#1.offset - 4*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2021-12-06 21:49:02,419 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2021-12-06 21:49:02,434 INFO L297 tatePredicateManager]: 8 out of 9 supporting invariants were superfluous and have been removed [2021-12-06 21:49:02,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:02,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:02,457 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 21:49:02,457 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:02,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:02,492 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 21:49:02,492 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:02,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:02,504 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2021-12-06 21:49:02,504 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42 states and 55 transitions. cyclomatic complexity: 17 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:02,520 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42 states and 55 transitions. cyclomatic complexity: 17. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 51 states and 67 transitions. Complement of second has 6 states. [2021-12-06 21:49:02,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2021-12-06 21:49:02,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:02,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2021-12-06 21:49:02,521 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 19 letters. Loop has 2 letters. [2021-12-06 21:49:02,521 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:49:02,521 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 21 letters. Loop has 2 letters. [2021-12-06 21:49:02,522 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:49:02,522 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 19 letters. Loop has 4 letters. [2021-12-06 21:49:02,522 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 21:49:02,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 67 transitions. [2021-12-06 21:49:02,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:02,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 43 states and 56 transitions. [2021-12-06 21:49:02,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-12-06 21:49:02,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:02,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 56 transitions. [2021-12-06 21:49:02,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:02,523 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 56 transitions. [2021-12-06 21:49:02,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 56 transitions. [2021-12-06 21:49:02,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2021-12-06 21:49:02,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.3095238095238095) internal successors, (55), 41 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:02,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 55 transitions. [2021-12-06 21:49:02,525 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 55 transitions. [2021-12-06 21:49:02,525 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 55 transitions. [2021-12-06 21:49:02,525 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 21:49:02,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 55 transitions. [2021-12-06 21:49:02,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:02,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:02,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:02,526 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:02,526 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:02,526 INFO L791 eck$LassoCheckResult]: Stem: 2573#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2584#L367 assume !(main_~length~0#1 < 1); 2575#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2576#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2585#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2586#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2587#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2612#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2611#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2610#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2600#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2598#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2597#L370-4 main_~j~0#1 := 0; 2596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2595#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2580#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2591#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2578#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2579#L378-2 [2021-12-06 21:49:02,526 INFO L793 eck$LassoCheckResult]: Loop: 2579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2592#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2579#L378-2 [2021-12-06 21:49:02,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:02,527 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 6 times [2021-12-06 21:49:02,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:02,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242471842] [2021-12-06 21:49:02,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:02,527 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:02,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:02,614 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:02,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:02,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242471842] [2021-12-06 21:49:02,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242471842] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:02,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1715048052] [2021-12-06 21:49:02,615 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:02,615 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:02,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:02,615 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:02,616 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-12-06 21:49:02,655 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2021-12-06 21:49:02,656 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:02,656 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 17 conjunts are in the unsatisfiable core [2021-12-06 21:49:02,657 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:02,701 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2021-12-06 21:49:02,708 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:02,911 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:02,911 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:02,914 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:02,914 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:03,175 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:03,177 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:03,191 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 6 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:03,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1715048052] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:03,191 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:03,191 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 14] total 33 [2021-12-06 21:49:03,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950429371] [2021-12-06 21:49:03,191 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:03,191 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:03,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:03,192 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2021-12-06 21:49:03,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:03,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970334490] [2021-12-06 21:49:03,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:03,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:03,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:03,194 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:03,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:03,196 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:03,223 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:03,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-12-06 21:49:03,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=967, Unknown=0, NotChecked=0, Total=1122 [2021-12-06 21:49:03,224 INFO L87 Difference]: Start difference. First operand 42 states and 55 transitions. cyclomatic complexity: 17 Second operand has 34 states, 33 states have (on average 1.8484848484848484) internal successors, (61), 34 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:03,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:03,543 INFO L93 Difference]: Finished difference Result 59 states and 73 transitions. [2021-12-06 21:49:03,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-12-06 21:49:03,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 73 transitions. [2021-12-06 21:49:03,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:03,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 48 states and 60 transitions. [2021-12-06 21:49:03,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:03,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:03,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 60 transitions. [2021-12-06 21:49:03,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:03,544 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 60 transitions. [2021-12-06 21:49:03,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 60 transitions. [2021-12-06 21:49:03,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 42. [2021-12-06 21:49:03,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2857142857142858) internal successors, (54), 41 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:03,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 54 transitions. [2021-12-06 21:49:03,546 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 54 transitions. [2021-12-06 21:49:03,546 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 54 transitions. [2021-12-06 21:49:03,546 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 21:49:03,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 54 transitions. [2021-12-06 21:49:03,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:03,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:03,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:03,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:03,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:03,547 INFO L791 eck$LassoCheckResult]: Stem: 2903#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2914#L367 assume !(main_~length~0#1 < 1); 2905#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2906#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2915#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2918#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2916#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2917#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2937#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2932#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2926#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2930#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2925#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2912#L370-4 main_~j~0#1 := 0; 2913#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2920#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2924#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2923#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2922#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2908#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2909#L378-2 [2021-12-06 21:49:03,547 INFO L793 eck$LassoCheckResult]: Loop: 2909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2921#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2909#L378-2 [2021-12-06 21:49:03,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:03,547 INFO L85 PathProgramCache]: Analyzing trace with hash 5747943, now seen corresponding path program 4 times [2021-12-06 21:49:03,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:03,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991580393] [2021-12-06 21:49:03,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:03,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:03,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:03,661 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:03,661 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:03,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991580393] [2021-12-06 21:49:03,661 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991580393] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:03,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [655747932] [2021-12-06 21:49:03,662 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:03,662 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:03,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:03,663 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:03,663 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-12-06 21:49:03,703 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:03,704 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:03,705 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 30 conjunts are in the unsatisfiable core [2021-12-06 21:49:03,706 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:03,774 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:03,827 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:03,827 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:03,836 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:03,836 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:03,859 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:03,860 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:03,935 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:03,937 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:03,937 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:04,041 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:04,043 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:04,066 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:49:04,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [655747932] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:04,066 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:04,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13] total 28 [2021-12-06 21:49:04,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061912762] [2021-12-06 21:49:04,066 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:04,066 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:04,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:04,067 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2021-12-06 21:49:04,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:04,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112369814] [2021-12-06 21:49:04,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:04,067 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:04,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:04,069 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:04,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:04,072 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:04,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:04,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-12-06 21:49:04,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=694, Unknown=0, NotChecked=0, Total=812 [2021-12-06 21:49:04,095 INFO L87 Difference]: Start difference. First operand 42 states and 54 transitions. cyclomatic complexity: 16 Second operand has 29 states, 28 states have (on average 2.142857142857143) internal successors, (60), 29 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:04,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:04,261 INFO L93 Difference]: Finished difference Result 48 states and 60 transitions. [2021-12-06 21:49:04,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 21:49:04,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 60 transitions. [2021-12-06 21:49:04,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:04,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 47 states and 59 transitions. [2021-12-06 21:49:04,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:04,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:04,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2021-12-06 21:49:04,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:04,262 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2021-12-06 21:49:04,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2021-12-06 21:49:04,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 32. [2021-12-06 21:49:04,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.25) internal successors, (40), 31 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:04,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 40 transitions. [2021-12-06 21:49:04,264 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2021-12-06 21:49:04,264 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2021-12-06 21:49:04,264 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 21:49:04,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 40 transitions. [2021-12-06 21:49:04,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:04,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:04,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:04,265 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:04,265 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:04,265 INFO L791 eck$LassoCheckResult]: Stem: 3197#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3208#L367 assume !(main_~length~0#1 < 1); 3199#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3200#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3212#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3211#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3228#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3226#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3224#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3223#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3222#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3221#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3215#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3214#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3202#L370-4 main_~j~0#1 := 0; 3203#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3206#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3207#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3213#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3219#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3217#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3216#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3204#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3205#L378-2 [2021-12-06 21:49:04,265 INFO L793 eck$LassoCheckResult]: Loop: 3205#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3218#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3205#L378-2 [2021-12-06 21:49:04,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:04,265 INFO L85 PathProgramCache]: Analyzing trace with hash -51054482, now seen corresponding path program 7 times [2021-12-06 21:49:04,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:04,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683764366] [2021-12-06 21:49:04,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:04,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:04,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:04,363 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:04,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:04,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683764366] [2021-12-06 21:49:04,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683764366] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:04,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1258582315] [2021-12-06 21:49:04,364 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:04,364 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:04,364 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:04,365 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:04,366 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-12-06 21:49:04,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:04,403 INFO L263 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 29 conjunts are in the unsatisfiable core [2021-12-06 21:49:04,404 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:04,473 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:04,526 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:04,527 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:04,626 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:04,627 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:04,627 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:04,705 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:04,706 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:04,739 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:04,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1258582315] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:04,740 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:04,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 30 [2021-12-06 21:49:04,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378171455] [2021-12-06 21:49:04,740 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:04,740 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:04,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:04,740 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2021-12-06 21:49:04,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:04,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080756654] [2021-12-06 21:49:04,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:04,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:04,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:04,743 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:04,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:04,744 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:04,767 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:04,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-12-06 21:49:04,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=815, Unknown=0, NotChecked=0, Total=930 [2021-12-06 21:49:04,768 INFO L87 Difference]: Start difference. First operand 32 states and 40 transitions. cyclomatic complexity: 11 Second operand has 31 states, 30 states have (on average 2.066666666666667) internal successors, (62), 31 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:04,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:04,988 INFO L93 Difference]: Finished difference Result 36 states and 44 transitions. [2021-12-06 21:49:04,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 21:49:04,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 44 transitions. [2021-12-06 21:49:04,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:04,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 35 states and 43 transitions. [2021-12-06 21:49:04,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-12-06 21:49:04,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-12-06 21:49:04,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 43 transitions. [2021-12-06 21:49:04,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:04,990 INFO L681 BuchiCegarLoop]: Abstraction has 35 states and 43 transitions. [2021-12-06 21:49:04,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 43 transitions. [2021-12-06 21:49:04,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 34. [2021-12-06 21:49:04,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2352941176470589) internal successors, (42), 33 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:04,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 42 transitions. [2021-12-06 21:49:04,992 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 42 transitions. [2021-12-06 21:49:04,992 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 42 transitions. [2021-12-06 21:49:04,992 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 21:49:04,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 42 transitions. [2021-12-06 21:49:04,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:04,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:04,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:04,993 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:04,993 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:04,994 INFO L791 eck$LassoCheckResult]: Stem: 3485#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3496#L367 assume !(main_~length~0#1 < 1); 3487#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3488#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3497#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3500#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3499#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3511#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3508#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3507#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3504#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3505#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3503#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3490#L370-4 main_~j~0#1 := 0; 3491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3501#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3502#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3494#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3495#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3518#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3515#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3514#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3492#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3493#L378-2 [2021-12-06 21:49:04,994 INFO L793 eck$LassoCheckResult]: Loop: 3493#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3516#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3493#L378-2 [2021-12-06 21:49:04,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:04,994 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 8 times [2021-12-06 21:49:04,994 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:04,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243225399] [2021-12-06 21:49:04,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:04,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:05,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:05,104 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:05,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243225399] [2021-12-06 21:49:05,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243225399] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:05,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1622884386] [2021-12-06 21:49:05,105 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:05,105 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:05,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:05,106 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:05,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-12-06 21:49:05,145 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:05,146 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:05,146 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 26 conjunts are in the unsatisfiable core [2021-12-06 21:49:05,147 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:05,177 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:05,283 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:05,284 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,284 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:05,324 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:05,326 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:05,358 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,358 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1622884386] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:05,359 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:05,359 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 22 [2021-12-06 21:49:05,359 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592427169] [2021-12-06 21:49:05,359 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:05,359 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:05,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:05,359 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2021-12-06 21:49:05,359 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:05,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791164016] [2021-12-06 21:49:05,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:05,360 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:05,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:05,362 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:05,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:05,363 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:05,386 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:05,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 21:49:05,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=440, Unknown=0, NotChecked=0, Total=506 [2021-12-06 21:49:05,386 INFO L87 Difference]: Start difference. First operand 34 states and 42 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.1818181818181817) internal successors, (48), 23 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:05,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:05,549 INFO L93 Difference]: Finished difference Result 50 states and 61 transitions. [2021-12-06 21:49:05,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-12-06 21:49:05,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50 states and 61 transitions. [2021-12-06 21:49:05,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:05,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50 states to 49 states and 60 transitions. [2021-12-06 21:49:05,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:05,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:05,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 60 transitions. [2021-12-06 21:49:05,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:05,551 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 60 transitions. [2021-12-06 21:49:05,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 60 transitions. [2021-12-06 21:49:05,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2021-12-06 21:49:05,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.2439024390243902) internal successors, (51), 40 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:05,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 51 transitions. [2021-12-06 21:49:05,552 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 51 transitions. [2021-12-06 21:49:05,552 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 51 transitions. [2021-12-06 21:49:05,552 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 21:49:05,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 51 transitions. [2021-12-06 21:49:05,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:05,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:05,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:05,553 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:05,553 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:05,553 INFO L791 eck$LassoCheckResult]: Stem: 3783#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3794#L367 assume !(main_~length~0#1 < 1); 3785#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3786#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3787#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3795#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3817#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3797#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3798#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3801#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3815#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3814#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3813#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3812#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3811#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3809#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3807#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3802#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3788#L370-4 main_~j~0#1 := 0; 3789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3792#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3800#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3819#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3818#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3810#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3808#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3805#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3790#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3791#L378-2 [2021-12-06 21:49:05,553 INFO L793 eck$LassoCheckResult]: Loop: 3791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3806#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3791#L378-2 [2021-12-06 21:49:05,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:05,554 INFO L85 PathProgramCache]: Analyzing trace with hash 267849144, now seen corresponding path program 9 times [2021-12-06 21:49:05,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:05,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789661931] [2021-12-06 21:49:05,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:05,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:05,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:05,706 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,706 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:05,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789661931] [2021-12-06 21:49:05,706 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789661931] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:05,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1181696994] [2021-12-06 21:49:05,706 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:05,706 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:05,706 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:05,707 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:05,708 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-12-06 21:49:05,756 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2021-12-06 21:49:05,756 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:05,757 INFO L263 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 14 conjunts are in the unsatisfiable core [2021-12-06 21:49:05,758 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:05,886 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,886 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:05,954 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:05,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1181696994] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:05,954 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:05,954 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15] total 35 [2021-12-06 21:49:05,955 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008008670] [2021-12-06 21:49:05,955 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:05,955 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:05,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:05,955 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2021-12-06 21:49:05,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:05,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125013365] [2021-12-06 21:49:05,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:05,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:05,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:05,958 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:05,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:05,960 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:05,985 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:05,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-12-06 21:49:05,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=967, Unknown=0, NotChecked=0, Total=1190 [2021-12-06 21:49:05,986 INFO L87 Difference]: Start difference. First operand 41 states and 51 transitions. cyclomatic complexity: 13 Second operand has 35 states, 35 states have (on average 2.1714285714285713) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:06,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:06,152 INFO L93 Difference]: Finished difference Result 51 states and 61 transitions. [2021-12-06 21:49:06,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-12-06 21:49:06,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 61 transitions. [2021-12-06 21:49:06,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:06,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 39 states and 49 transitions. [2021-12-06 21:49:06,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-12-06 21:49:06,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-12-06 21:49:06,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2021-12-06 21:49:06,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:06,154 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-12-06 21:49:06,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2021-12-06 21:49:06,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 37. [2021-12-06 21:49:06,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 36 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:06,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 46 transitions. [2021-12-06 21:49:06,155 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2021-12-06 21:49:06,155 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2021-12-06 21:49:06,155 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 21:49:06,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 46 transitions. [2021-12-06 21:49:06,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:06,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:06,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:06,156 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:06,156 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:06,156 INFO L791 eck$LassoCheckResult]: Stem: 4125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4136#L367 assume !(main_~length~0#1 < 1); 4127#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4128#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4161#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4139#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4141#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4160#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4159#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4158#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4157#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4155#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4154#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4153#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4152#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4144#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4143#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4134#L370-4 main_~j~0#1 := 0; 4135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4140#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4147#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4146#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4130#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4131#L378-2 [2021-12-06 21:49:06,156 INFO L793 eck$LassoCheckResult]: Loop: 4131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4148#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4131#L378-2 [2021-12-06 21:49:06,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:06,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 10 times [2021-12-06 21:49:06,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:06,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735951378] [2021-12-06 21:49:06,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:06,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:06,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:06,274 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:06,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:06,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735951378] [2021-12-06 21:49:06,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735951378] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:06,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1946746821] [2021-12-06 21:49:06,274 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:06,274 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:06,274 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:06,275 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:06,276 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-12-06 21:49:06,323 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:06,323 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:06,325 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 33 conjunts are in the unsatisfiable core [2021-12-06 21:49:06,326 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:06,409 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:06,467 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:06,467 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:06,601 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:06,603 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:06,603 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:06,692 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:06,694 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:06,730 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:06,730 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1946746821] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:06,730 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:06,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 16] total 34 [2021-12-06 21:49:06,730 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074792740] [2021-12-06 21:49:06,730 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:06,731 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:06,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:06,731 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2021-12-06 21:49:06,731 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:06,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479381922] [2021-12-06 21:49:06,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:06,731 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:06,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:06,733 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:06,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:06,734 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:06,760 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:06,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-12-06 21:49:06,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1061, Unknown=0, NotChecked=0, Total=1190 [2021-12-06 21:49:06,761 INFO L87 Difference]: Start difference. First operand 37 states and 46 transitions. cyclomatic complexity: 12 Second operand has 35 states, 34 states have (on average 2.1176470588235294) internal successors, (72), 35 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:07,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:07,059 INFO L93 Difference]: Finished difference Result 41 states and 50 transitions. [2021-12-06 21:49:07,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-12-06 21:49:07,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 50 transitions. [2021-12-06 21:49:07,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:07,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 49 transitions. [2021-12-06 21:49:07,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-12-06 21:49:07,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-12-06 21:49:07,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 49 transitions. [2021-12-06 21:49:07,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:07,061 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 49 transitions. [2021-12-06 21:49:07,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 49 transitions. [2021-12-06 21:49:07,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2021-12-06 21:49:07,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 38 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:07,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 48 transitions. [2021-12-06 21:49:07,062 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 48 transitions. [2021-12-06 21:49:07,062 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 48 transitions. [2021-12-06 21:49:07,062 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 21:49:07,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 48 transitions. [2021-12-06 21:49:07,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:07,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:07,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:07,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:07,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:07,063 INFO L791 eck$LassoCheckResult]: Stem: 4459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4460#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4470#L367 assume !(main_~length~0#1 < 1); 4461#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4462#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4463#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4471#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4474#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4472#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4473#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4488#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4487#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4485#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4483#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4482#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4481#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4480#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4479#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4477#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4464#L370-4 main_~j~0#1 := 0; 4465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4475#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4476#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4497#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4496#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4495#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4494#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4492#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4466#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4467#L378-2 [2021-12-06 21:49:07,063 INFO L793 eck$LassoCheckResult]: Loop: 4467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4493#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4467#L378-2 [2021-12-06 21:49:07,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:07,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1281830834, now seen corresponding path program 11 times [2021-12-06 21:49:07,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:07,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65574571] [2021-12-06 21:49:07,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:07,063 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:07,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:07,199 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:07,199 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:07,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65574571] [2021-12-06 21:49:07,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65574571] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:07,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [539474510] [2021-12-06 21:49:07,199 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:07,200 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:07,200 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:07,200 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:07,201 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-12-06 21:49:07,272 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2021-12-06 21:49:07,272 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:07,274 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 30 conjunts are in the unsatisfiable core [2021-12-06 21:49:07,275 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:07,308 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:07,472 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:07,473 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:07,473 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:07,549 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:07,551 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:07,585 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:07,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [539474510] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:07,585 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:07,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2021-12-06 21:49:07,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27965721] [2021-12-06 21:49:07,585 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:07,586 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:07,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:07,586 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2021-12-06 21:49:07,586 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:07,586 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380334065] [2021-12-06 21:49:07,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:07,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:07,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:07,588 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:07,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:07,590 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:07,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:07,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-12-06 21:49:07,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2021-12-06 21:49:07,612 INFO L87 Difference]: Start difference. First operand 39 states and 48 transitions. cyclomatic complexity: 12 Second operand has 28 states, 27 states have (on average 2.111111111111111) internal successors, (57), 28 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:07,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:07,823 INFO L93 Difference]: Finished difference Result 63 states and 77 transitions. [2021-12-06 21:49:07,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-12-06 21:49:07,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 77 transitions. [2021-12-06 21:49:07,823 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:07,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 62 states and 76 transitions. [2021-12-06 21:49:07,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:49:07,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:49:07,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 76 transitions. [2021-12-06 21:49:07,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:07,824 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 76 transitions. [2021-12-06 21:49:07,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 76 transitions. [2021-12-06 21:49:07,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 47. [2021-12-06 21:49:07,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2553191489361701) internal successors, (59), 46 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:07,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 59 transitions. [2021-12-06 21:49:07,826 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2021-12-06 21:49:07,826 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2021-12-06 21:49:07,826 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 21:49:07,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 59 transitions. [2021-12-06 21:49:07,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:07,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:07,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:07,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:07,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:07,827 INFO L791 eck$LassoCheckResult]: Stem: 4810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4821#L367 assume !(main_~length~0#1 < 1); 4812#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4813#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4814#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4822#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4824#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4825#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4841#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4840#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4839#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4838#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4837#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4836#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4835#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4833#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4832#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4831#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4829#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4815#L370-4 main_~j~0#1 := 0; 4816#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4852#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4827#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4819#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4851#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4850#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4849#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4848#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4847#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4846#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4845#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4817#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4818#L378-2 [2021-12-06 21:49:07,827 INFO L793 eck$LassoCheckResult]: Loop: 4818#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4843#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4818#L378-2 [2021-12-06 21:49:07,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:07,827 INFO L85 PathProgramCache]: Analyzing trace with hash -816179209, now seen corresponding path program 12 times [2021-12-06 21:49:07,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:07,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409315424] [2021-12-06 21:49:07,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:07,827 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:07,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:08,012 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:08,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:08,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409315424] [2021-12-06 21:49:08,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409315424] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:08,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [360271570] [2021-12-06 21:49:08,013 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:08,013 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:08,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:08,014 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:08,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-12-06 21:49:08,079 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-12-06 21:49:08,079 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:08,080 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 21:49:08,081 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:08,227 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:08,227 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:08,307 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:08,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [360271570] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:08,307 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:08,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 40 [2021-12-06 21:49:08,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074545615] [2021-12-06 21:49:08,308 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:08,308 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:08,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:08,308 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2021-12-06 21:49:08,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:08,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693203045] [2021-12-06 21:49:08,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:08,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:08,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:08,311 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:08,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:08,313 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:08,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:08,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-12-06 21:49:08,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=1274, Unknown=0, NotChecked=0, Total=1560 [2021-12-06 21:49:08,336 INFO L87 Difference]: Start difference. First operand 47 states and 59 transitions. cyclomatic complexity: 16 Second operand has 40 states, 40 states have (on average 2.2) internal successors, (88), 40 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:08,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:08,541 INFO L93 Difference]: Finished difference Result 66 states and 79 transitions. [2021-12-06 21:49:08,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 21:49:08,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 79 transitions. [2021-12-06 21:49:08,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:08,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 52 states and 65 transitions. [2021-12-06 21:49:08,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:08,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:08,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 65 transitions. [2021-12-06 21:49:08,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:08,543 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 65 transitions. [2021-12-06 21:49:08,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 65 transitions. [2021-12-06 21:49:08,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 49. [2021-12-06 21:49:08,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2448979591836735) internal successors, (61), 48 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:08,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 61 transitions. [2021-12-06 21:49:08,545 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2021-12-06 21:49:08,545 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2021-12-06 21:49:08,545 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 21:49:08,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 61 transitions. [2021-12-06 21:49:08,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:08,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:08,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:08,546 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:08,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:08,547 INFO L791 eck$LassoCheckResult]: Stem: 5210#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5221#L367 assume !(main_~length~0#1 < 1); 5212#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5213#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5214#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5222#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5258#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5223#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5224#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5257#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5256#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5255#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5254#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5253#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5252#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5251#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5250#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5249#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5248#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5244#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5228#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5215#L370-4 main_~j~0#1 := 0; 5216#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5226#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5238#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5237#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5236#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5235#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5234#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5233#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5231#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5230#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5217#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5218#L378-2 [2021-12-06 21:49:08,547 INFO L793 eck$LassoCheckResult]: Loop: 5218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5232#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5218#L378-2 [2021-12-06 21:49:08,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:08,547 INFO L85 PathProgramCache]: Analyzing trace with hash -968534086, now seen corresponding path program 5 times [2021-12-06 21:49:08,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:08,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615934943] [2021-12-06 21:49:08,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:08,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:08,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:08,713 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:08,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:08,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615934943] [2021-12-06 21:49:08,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615934943] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:08,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1843028656] [2021-12-06 21:49:08,713 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:08,714 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:08,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:08,714 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:08,715 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-12-06 21:49:08,782 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-12-06 21:49:08,782 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:08,784 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 35 conjunts are in the unsatisfiable core [2021-12-06 21:49:08,785 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:08,825 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:08,882 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:08,882 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:08,901 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:08,901 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:09,027 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:09,028 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:09,028 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:09,152 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:09,154 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:09,196 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:09,196 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1843028656] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:09,196 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:09,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 30 [2021-12-06 21:49:09,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013025592] [2021-12-06 21:49:09,196 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:09,197 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:09,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:09,197 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2021-12-06 21:49:09,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:09,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219276676] [2021-12-06 21:49:09,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:09,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:09,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:09,199 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:09,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:09,201 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:09,228 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:09,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-12-06 21:49:09,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=838, Unknown=0, NotChecked=0, Total=930 [2021-12-06 21:49:09,229 INFO L87 Difference]: Start difference. First operand 49 states and 61 transitions. cyclomatic complexity: 16 Second operand has 31 states, 30 states have (on average 2.1) internal successors, (63), 31 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:09,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:09,631 INFO L93 Difference]: Finished difference Result 107 states and 128 transitions. [2021-12-06 21:49:09,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-12-06 21:49:09,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 128 transitions. [2021-12-06 21:49:09,632 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:49:09,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 106 states and 127 transitions. [2021-12-06 21:49:09,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:49:09,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:49:09,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 127 transitions. [2021-12-06 21:49:09,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:09,633 INFO L681 BuchiCegarLoop]: Abstraction has 106 states and 127 transitions. [2021-12-06 21:49:09,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 127 transitions. [2021-12-06 21:49:09,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 55. [2021-12-06 21:49:09,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.290909090909091) internal successors, (71), 54 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:09,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 71 transitions. [2021-12-06 21:49:09,634 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 71 transitions. [2021-12-06 21:49:09,634 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 71 transitions. [2021-12-06 21:49:09,634 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 21:49:09,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 71 transitions. [2021-12-06 21:49:09,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:09,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:09,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:09,635 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:09,635 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:09,635 INFO L791 eck$LassoCheckResult]: Stem: 5650#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5661#L367 assume !(main_~length~0#1 < 1); 5652#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5653#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5662#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5666#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5664#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5704#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5703#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5702#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5701#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5699#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5697#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5696#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5695#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5693#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5692#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5691#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5690#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5689#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5687#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5659#L370-4 main_~j~0#1 := 0; 5660#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5657#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5665#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5679#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5678#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5677#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5675#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5672#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5655#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5656#L378-2 [2021-12-06 21:49:09,635 INFO L793 eck$LassoCheckResult]: Loop: 5656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5673#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5656#L378-2 [2021-12-06 21:49:09,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:09,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1246649855, now seen corresponding path program 6 times [2021-12-06 21:49:09,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:09,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740161241] [2021-12-06 21:49:09,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:09,636 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:09,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:09,790 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:09,790 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:09,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740161241] [2021-12-06 21:49:09,790 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740161241] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:09,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1005228254] [2021-12-06 21:49:09,790 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:09,790 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:09,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:09,791 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:09,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-12-06 21:49:09,864 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-12-06 21:49:09,864 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:09,865 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 22 conjunts are in the unsatisfiable core [2021-12-06 21:49:09,866 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:09,961 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:10,293 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:10,294 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:10,308 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:10,308 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:10,662 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:10,664 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:10,684 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:10,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1005228254] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:10,685 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:10,685 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 46 [2021-12-06 21:49:10,685 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719279471] [2021-12-06 21:49:10,685 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:10,685 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:10,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:10,685 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2021-12-06 21:49:10,685 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:10,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230899236] [2021-12-06 21:49:10,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:10,686 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:10,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:10,688 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:10,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:10,689 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:10,713 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:10,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-12-06 21:49:10,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=1901, Unknown=0, NotChecked=0, Total=2162 [2021-12-06 21:49:10,714 INFO L87 Difference]: Start difference. First operand 55 states and 71 transitions. cyclomatic complexity: 20 Second operand has 47 states, 46 states have (on average 2.108695652173913) internal successors, (97), 47 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:11,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:11,200 INFO L93 Difference]: Finished difference Result 88 states and 105 transitions. [2021-12-06 21:49:11,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-12-06 21:49:11,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 105 transitions. [2021-12-06 21:49:11,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:11,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 69 states and 85 transitions. [2021-12-06 21:49:11,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:11,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:11,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 85 transitions. [2021-12-06 21:49:11,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:11,202 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 85 transitions. [2021-12-06 21:49:11,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 85 transitions. [2021-12-06 21:49:11,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 57. [2021-12-06 21:49:11,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.280701754385965) internal successors, (73), 56 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:11,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 73 transitions. [2021-12-06 21:49:11,203 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2021-12-06 21:49:11,203 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2021-12-06 21:49:11,203 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 21:49:11,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 73 transitions. [2021-12-06 21:49:11,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:11,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:11,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:11,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:11,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:11,204 INFO L791 eck$LassoCheckResult]: Stem: 6141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6152#L367 assume !(main_~length~0#1 < 1); 6143#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6144#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6145#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6153#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6196#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6195#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6194#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6193#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6192#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6191#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6186#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6183#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6181#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6172#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6171#L370-4 main_~j~0#1 := 0; 6157#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6158#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6170#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6169#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6168#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6167#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6165#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6164#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6162#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6161#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6148#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6149#L378-2 [2021-12-06 21:49:11,204 INFO L793 eck$LassoCheckResult]: Loop: 6149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6163#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6149#L378-2 [2021-12-06 21:49:11,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:11,204 INFO L85 PathProgramCache]: Analyzing trace with hash -747494851, now seen corresponding path program 13 times [2021-12-06 21:49:11,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:11,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615908259] [2021-12-06 21:49:11,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:11,205 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:11,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:11,354 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:11,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:11,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615908259] [2021-12-06 21:49:11,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615908259] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:11,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938423568] [2021-12-06 21:49:11,355 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:11,355 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:11,355 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:11,356 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:11,356 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-12-06 21:49:11,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:11,403 INFO L263 TraceCheckSpWp]: Trace formula consists of 208 conjuncts, 38 conjunts are in the unsatisfiable core [2021-12-06 21:49:11,405 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:11,546 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:49:11,760 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:11,761 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:11,761 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:11,814 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:11,815 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:11,859 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:11,859 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1938423568] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:11,859 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:11,859 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 18] total 38 [2021-12-06 21:49:11,859 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508547688] [2021-12-06 21:49:11,860 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:11,860 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:11,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:11,860 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2021-12-06 21:49:11,860 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:11,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79079854] [2021-12-06 21:49:11,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:11,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:11,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:11,866 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:11,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:11,867 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:11,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:11,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-12-06 21:49:11,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=1343, Unknown=0, NotChecked=0, Total=1482 [2021-12-06 21:49:11,893 INFO L87 Difference]: Start difference. First operand 57 states and 73 transitions. cyclomatic complexity: 20 Second operand has 39 states, 38 states have (on average 2.263157894736842) internal successors, (86), 39 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:12,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:12,267 INFO L93 Difference]: Finished difference Result 108 states and 135 transitions. [2021-12-06 21:49:12,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-12-06 21:49:12,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 135 transitions. [2021-12-06 21:49:12,268 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2021-12-06 21:49:12,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 107 states and 134 transitions. [2021-12-06 21:49:12,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2021-12-06 21:49:12,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2021-12-06 21:49:12,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 134 transitions. [2021-12-06 21:49:12,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:12,269 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 134 transitions. [2021-12-06 21:49:12,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 134 transitions. [2021-12-06 21:49:12,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 91. [2021-12-06 21:49:12,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.2747252747252746) internal successors, (116), 90 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:12,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 116 transitions. [2021-12-06 21:49:12,270 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 116 transitions. [2021-12-06 21:49:12,270 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 116 transitions. [2021-12-06 21:49:12,271 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 21:49:12,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 116 transitions. [2021-12-06 21:49:12,271 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2021-12-06 21:49:12,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:12,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:12,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:12,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:12,272 INFO L791 eck$LassoCheckResult]: Stem: 6602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6613#L367 assume !(main_~length~0#1 < 1); 6604#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6605#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6614#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6615#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6642#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6641#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6640#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6639#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6638#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6636#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6635#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6634#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6633#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6627#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6628#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6630#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6664#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6673#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6672#L370-4 main_~j~0#1 := 0; 6671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6668#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6666#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6645#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6647#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6649#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6610#L378-2 [2021-12-06 21:49:12,272 INFO L793 eck$LassoCheckResult]: Loop: 6610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6643#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6610#L378-2 [2021-12-06 21:49:12,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:12,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1445342542, now seen corresponding path program 7 times [2021-12-06 21:49:12,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:12,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599933843] [2021-12-06 21:49:12,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:12,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:12,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:12,448 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:12,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:12,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599933843] [2021-12-06 21:49:12,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599933843] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:12,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1796103791] [2021-12-06 21:49:12,448 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:12,448 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:12,448 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:12,449 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:12,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-12-06 21:49:12,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:12,505 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 44 conjunts are in the unsatisfiable core [2021-12-06 21:49:12,507 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:12,630 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:12,699 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:12,700 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:12,707 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:12,708 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:12,737 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:12,737 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:12,745 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:12,745 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:12,935 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:12,937 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 2 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:12,937 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:13,091 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:13,093 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:13,138 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 120 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:49:13,138 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1796103791] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:13,138 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:13,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 40 [2021-12-06 21:49:13,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621111322] [2021-12-06 21:49:13,139 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:13,139 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:13,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:13,139 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2021-12-06 21:49:13,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:13,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598610294] [2021-12-06 21:49:13,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:13,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:13,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:13,142 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:13,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:13,143 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:13,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:13,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-12-06 21:49:13,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=1480, Unknown=0, NotChecked=0, Total=1640 [2021-12-06 21:49:13,166 INFO L87 Difference]: Start difference. First operand 91 states and 116 transitions. cyclomatic complexity: 31 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:13,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:13,554 INFO L93 Difference]: Finished difference Result 99 states and 117 transitions. [2021-12-06 21:49:13,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-12-06 21:49:13,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 117 transitions. [2021-12-06 21:49:13,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:13,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 97 states and 115 transitions. [2021-12-06 21:49:13,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:49:13,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:49:13,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 115 transitions. [2021-12-06 21:49:13,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:13,556 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 115 transitions. [2021-12-06 21:49:13,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 115 transitions. [2021-12-06 21:49:13,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 54. [2021-12-06 21:49:13,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2407407407407407) internal successors, (67), 53 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:13,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 67 transitions. [2021-12-06 21:49:13,558 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-12-06 21:49:13,558 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-12-06 21:49:13,558 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 21:49:13,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 67 transitions. [2021-12-06 21:49:13,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:13,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:13,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:13,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:13,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:13,560 INFO L791 eck$LassoCheckResult]: Stem: 7104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7115#L367 assume !(main_~length~0#1 < 1); 7106#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7107#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7116#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7122#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7117#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7118#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7156#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7155#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7153#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7152#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7151#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7150#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7149#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7148#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7147#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7146#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7145#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7144#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7137#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7138#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7109#L370-4 main_~j~0#1 := 0; 7110#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7139#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7113#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7134#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7128#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7127#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7126#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7124#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7123#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7111#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7112#L378-2 [2021-12-06 21:49:13,560 INFO L793 eck$LassoCheckResult]: Loop: 7112#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7125#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7112#L378-2 [2021-12-06 21:49:13,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:13,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1083010110, now seen corresponding path program 14 times [2021-12-06 21:49:13,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:13,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385008292] [2021-12-06 21:49:13,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:13,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:13,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:13,780 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:13,780 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:13,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385008292] [2021-12-06 21:49:13,780 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385008292] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:13,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1272074] [2021-12-06 21:49:13,780 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:13,781 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:13,781 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:13,781 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:13,782 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-12-06 21:49:13,832 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:13,832 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:13,833 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 18 conjunts are in the unsatisfiable core [2021-12-06 21:49:13,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:14,048 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:14,048 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:14,149 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:14,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1272074] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:14,150 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:14,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19] total 45 [2021-12-06 21:49:14,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984317432] [2021-12-06 21:49:14,150 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:14,150 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:14,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:14,150 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2021-12-06 21:49:14,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:14,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208091523] [2021-12-06 21:49:14,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:14,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:14,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:14,153 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:14,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:14,154 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:14,177 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:14,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-12-06 21:49:14,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1623, Unknown=0, NotChecked=0, Total=1980 [2021-12-06 21:49:14,178 INFO L87 Difference]: Start difference. First operand 54 states and 67 transitions. cyclomatic complexity: 17 Second operand has 45 states, 45 states have (on average 2.2222222222222223) internal successors, (100), 45 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:14,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:14,394 INFO L93 Difference]: Finished difference Result 75 states and 89 transitions. [2021-12-06 21:49:14,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-12-06 21:49:14,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 89 transitions. [2021-12-06 21:49:14,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:14,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 59 states and 73 transitions. [2021-12-06 21:49:14,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:14,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:14,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59 states and 73 transitions. [2021-12-06 21:49:14,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:14,395 INFO L681 BuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2021-12-06 21:49:14,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states and 73 transitions. [2021-12-06 21:49:14,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 54. [2021-12-06 21:49:14,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2407407407407407) internal successors, (67), 53 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:14,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 67 transitions. [2021-12-06 21:49:14,396 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-12-06 21:49:14,396 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2021-12-06 21:49:14,396 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 21:49:14,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 67 transitions. [2021-12-06 21:49:14,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:14,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:14,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:14,397 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:14,397 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:14,397 INFO L791 eck$LassoCheckResult]: Stem: 7557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7568#L367 assume !(main_~length~0#1 < 1); 7559#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7560#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7561#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7569#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7571#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7602#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7601#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7600#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7595#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7594#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7587#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7590#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7589#L370-4 main_~j~0#1 := 0; 7572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7565#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7585#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7584#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7583#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7581#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7580#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7576#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7562#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7563#L378-2 [2021-12-06 21:49:14,397 INFO L793 eck$LassoCheckResult]: Loop: 7563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7577#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7563#L378-2 [2021-12-06 21:49:14,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:14,398 INFO L85 PathProgramCache]: Analyzing trace with hash -1277041159, now seen corresponding path program 8 times [2021-12-06 21:49:14,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:14,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457443433] [2021-12-06 21:49:14,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:14,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:14,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:14,581 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:14,581 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:14,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457443433] [2021-12-06 21:49:14,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457443433] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:14,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [430847520] [2021-12-06 21:49:14,581 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:14,581 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:14,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:14,582 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:14,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-12-06 21:49:14,636 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:14,636 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:14,637 INFO L263 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 39 conjunts are in the unsatisfiable core [2021-12-06 21:49:14,639 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:14,679 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:14,731 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:14,731 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:14,743 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:14,744 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:14,868 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:14,869 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:14,869 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:14,970 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:14,972 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:15,017 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:15,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [430847520] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:15,018 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:15,018 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2021-12-06 21:49:15,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080232723] [2021-12-06 21:49:15,018 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:15,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:15,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:15,018 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2021-12-06 21:49:15,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:15,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059539024] [2021-12-06 21:49:15,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:15,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:15,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:15,021 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:15,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:15,022 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:15,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:15,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-12-06 21:49:15,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=901, Unknown=0, NotChecked=0, Total=992 [2021-12-06 21:49:15,048 INFO L87 Difference]: Start difference. First operand 54 states and 67 transitions. cyclomatic complexity: 17 Second operand has 32 states, 31 states have (on average 2.193548387096774) internal successors, (68), 32 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:15,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:15,443 INFO L93 Difference]: Finished difference Result 117 states and 139 transitions. [2021-12-06 21:49:15,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-12-06 21:49:15,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 139 transitions. [2021-12-06 21:49:15,444 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:49:15,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 116 states and 138 transitions. [2021-12-06 21:49:15,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:49:15,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:49:15,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 138 transitions. [2021-12-06 21:49:15,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:15,445 INFO L681 BuchiCegarLoop]: Abstraction has 116 states and 138 transitions. [2021-12-06 21:49:15,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 138 transitions. [2021-12-06 21:49:15,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 60. [2021-12-06 21:49:15,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.2833333333333334) internal successors, (77), 59 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:15,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 77 transitions. [2021-12-06 21:49:15,446 INFO L704 BuchiCegarLoop]: Abstraction has 60 states and 77 transitions. [2021-12-06 21:49:15,446 INFO L587 BuchiCegarLoop]: Abstraction has 60 states and 77 transitions. [2021-12-06 21:49:15,446 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 21:49:15,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 77 transitions. [2021-12-06 21:49:15,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:15,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:15,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:15,447 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:15,447 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:15,447 INFO L791 eck$LassoCheckResult]: Stem: 8045#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8056#L367 assume !(main_~length~0#1 < 1); 8047#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8048#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8057#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8085#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8058#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8059#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8060#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8063#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8084#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8083#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8082#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8081#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8080#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8079#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8078#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8077#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8076#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8075#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8072#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8071#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8069#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8070#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8068#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8103#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8050#L370-4 main_~j~0#1 := 0; 8051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8097#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8062#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8054#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8055#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8096#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8094#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8093#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8092#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8091#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8090#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8089#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8087#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8086#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8052#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8053#L378-2 [2021-12-06 21:49:15,447 INFO L793 eck$LassoCheckResult]: Loop: 8053#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8088#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8053#L378-2 [2021-12-06 21:49:15,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:15,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1124096126, now seen corresponding path program 9 times [2021-12-06 21:49:15,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:15,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941249384] [2021-12-06 21:49:15,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:15,448 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:15,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:15,597 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:15,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:15,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941249384] [2021-12-06 21:49:15,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941249384] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:15,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [950835939] [2021-12-06 21:49:15,597 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:15,598 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:15,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:15,598 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:15,599 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-12-06 21:49:15,696 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2021-12-06 21:49:15,696 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:15,697 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 24 conjunts are in the unsatisfiable core [2021-12-06 21:49:15,698 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:15,799 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:16,181 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:16,181 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:16,197 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:16,197 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:16,640 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:16,642 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:16,669 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:16,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [950835939] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:16,670 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:16,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21, 21] total 51 [2021-12-06 21:49:16,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1886987953] [2021-12-06 21:49:16,670 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:16,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:16,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:16,670 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2021-12-06 21:49:16,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:16,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270952325] [2021-12-06 21:49:16,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:16,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:16,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:16,672 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:16,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:16,674 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:16,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:16,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-12-06 21:49:16,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=313, Invalid=2339, Unknown=0, NotChecked=0, Total=2652 [2021-12-06 21:49:16,698 INFO L87 Difference]: Start difference. First operand 60 states and 77 transitions. cyclomatic complexity: 21 Second operand has 52 states, 51 states have (on average 2.1372549019607843) internal successors, (109), 52 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:17,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:17,328 INFO L93 Difference]: Finished difference Result 97 states and 115 transitions. [2021-12-06 21:49:17,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-12-06 21:49:17,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 115 transitions. [2021-12-06 21:49:17,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:17,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 76 states and 93 transitions. [2021-12-06 21:49:17,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:17,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:17,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 93 transitions. [2021-12-06 21:49:17,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:17,330 INFO L681 BuchiCegarLoop]: Abstraction has 76 states and 93 transitions. [2021-12-06 21:49:17,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 93 transitions. [2021-12-06 21:49:17,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 62. [2021-12-06 21:49:17,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.2741935483870968) internal successors, (79), 61 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:17,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 79 transitions. [2021-12-06 21:49:17,331 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 79 transitions. [2021-12-06 21:49:17,331 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 79 transitions. [2021-12-06 21:49:17,331 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 21:49:17,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 79 transitions. [2021-12-06 21:49:17,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:17,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:17,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:17,332 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:17,332 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:17,332 INFO L791 eck$LassoCheckResult]: Stem: 8592#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8603#L367 assume !(main_~length~0#1 < 1); 8594#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8595#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8596#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8604#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8605#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8606#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8652#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8651#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8650#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8649#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8648#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8647#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8646#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8645#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8644#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8643#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8642#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8641#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8640#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8639#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8638#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8635#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8623#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8601#L370-4 main_~j~0#1 := 0; 8602#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8599#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8600#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8620#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8619#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8618#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8617#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8616#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8615#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8614#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8613#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8612#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8597#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8598#L378-2 [2021-12-06 21:49:17,332 INFO L793 eck$LassoCheckResult]: Loop: 8598#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8611#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8598#L378-2 [2021-12-06 21:49:17,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:17,332 INFO L85 PathProgramCache]: Analyzing trace with hash 306447676, now seen corresponding path program 15 times [2021-12-06 21:49:17,333 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:17,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765134532] [2021-12-06 21:49:17,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:17,333 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:17,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:17,509 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:17,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:17,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765134532] [2021-12-06 21:49:17,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765134532] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:17,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [996092026] [2021-12-06 21:49:17,509 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:17,509 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:17,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:17,510 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:17,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-12-06 21:49:17,596 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2021-12-06 21:49:17,596 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:17,597 INFO L263 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 25 conjunts are in the unsatisfiable core [2021-12-06 21:49:17,598 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:17,708 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:18,102 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:18,103 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:18,104 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:18,105 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:18,859 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:18,861 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:18,885 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:18,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [996092026] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:18,885 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:18,885 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 53 [2021-12-06 21:49:18,885 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618026604] [2021-12-06 21:49:18,885 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:18,886 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:18,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:18,886 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2021-12-06 21:49:18,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:18,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705836127] [2021-12-06 21:49:18,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:18,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:18,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:18,888 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:18,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:18,890 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:18,915 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:18,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2021-12-06 21:49:18,917 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2520, Unknown=1, NotChecked=0, Total=2862 [2021-12-06 21:49:18,917 INFO L87 Difference]: Start difference. First operand 62 states and 79 transitions. cyclomatic complexity: 21 Second operand has 54 states, 53 states have (on average 2.056603773584906) internal successors, (109), 54 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:19,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:19,708 INFO L93 Difference]: Finished difference Result 94 states and 116 transitions. [2021-12-06 21:49:19,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-12-06 21:49:19,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94 states and 116 transitions. [2021-12-06 21:49:19,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:19,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94 states to 75 states and 95 transitions. [2021-12-06 21:49:19,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:19,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:19,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 95 transitions. [2021-12-06 21:49:19,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:19,709 INFO L681 BuchiCegarLoop]: Abstraction has 75 states and 95 transitions. [2021-12-06 21:49:19,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 95 transitions. [2021-12-06 21:49:19,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 73. [2021-12-06 21:49:19,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.273972602739726) internal successors, (93), 72 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:19,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 93 transitions. [2021-12-06 21:49:19,710 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 93 transitions. [2021-12-06 21:49:19,710 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 93 transitions. [2021-12-06 21:49:19,711 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 21:49:19,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 93 transitions. [2021-12-06 21:49:19,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:19,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:19,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:19,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:19,711 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:19,711 INFO L791 eck$LassoCheckResult]: Stem: 9157#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9168#L367 assume !(main_~length~0#1 < 1); 9159#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9160#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9161#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9169#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9173#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9171#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9227#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9224#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9219#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9218#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9217#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9215#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9212#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9211#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9203#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9201#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9192#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9189#L370-4 main_~j~0#1 := 0; 9188#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9187#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9172#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9164#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9165#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9186#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9184#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9183#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9182#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9181#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9180#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9179#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9178#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9177#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9162#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9163#L378-2 [2021-12-06 21:49:19,711 INFO L793 eck$LassoCheckResult]: Loop: 9163#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9176#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9163#L378-2 [2021-12-06 21:49:19,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:19,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1079755718, now seen corresponding path program 10 times [2021-12-06 21:49:19,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:19,712 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843861676] [2021-12-06 21:49:19,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:19,712 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:19,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:19,881 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:19,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:19,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843861676] [2021-12-06 21:49:19,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1843861676] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:19,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [89845640] [2021-12-06 21:49:19,882 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:19,882 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:19,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:19,883 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:19,883 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-12-06 21:49:19,938 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:19,938 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:19,939 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 42 conjunts are in the unsatisfiable core [2021-12-06 21:49:19,940 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:20,100 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:49:20,336 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:20,337 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:20,337 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:20,395 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:20,396 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:20,438 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:20,439 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [89845640] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:20,439 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:20,439 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 20] total 42 [2021-12-06 21:49:20,439 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566997213] [2021-12-06 21:49:20,439 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:20,439 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:20,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:20,439 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2021-12-06 21:49:20,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:20,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656871005] [2021-12-06 21:49:20,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:20,440 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:20,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:20,441 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:20,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:20,443 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:20,465 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:20,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-12-06 21:49:20,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=1652, Unknown=0, NotChecked=0, Total=1806 [2021-12-06 21:49:20,466 INFO L87 Difference]: Start difference. First operand 73 states and 93 transitions. cyclomatic complexity: 24 Second operand has 43 states, 42 states have (on average 2.2857142857142856) internal successors, (96), 43 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:20,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:20,915 INFO L93 Difference]: Finished difference Result 130 states and 162 transitions. [2021-12-06 21:49:20,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-12-06 21:49:20,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 162 transitions. [2021-12-06 21:49:20,916 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18 [2021-12-06 21:49:20,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 129 states and 161 transitions. [2021-12-06 21:49:20,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-12-06 21:49:20,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-12-06 21:49:20,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129 states and 161 transitions. [2021-12-06 21:49:20,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:20,917 INFO L681 BuchiCegarLoop]: Abstraction has 129 states and 161 transitions. [2021-12-06 21:49:20,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states and 161 transitions. [2021-12-06 21:49:20,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 111. [2021-12-06 21:49:20,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 111 states have (on average 1.2702702702702702) internal successors, (141), 110 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:20,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 141 transitions. [2021-12-06 21:49:20,919 INFO L704 BuchiCegarLoop]: Abstraction has 111 states and 141 transitions. [2021-12-06 21:49:20,919 INFO L587 BuchiCegarLoop]: Abstraction has 111 states and 141 transitions. [2021-12-06 21:49:20,919 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 21:49:20,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 111 states and 141 transitions. [2021-12-06 21:49:20,919 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2021-12-06 21:49:20,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:20,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:20,920 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 7, 6, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:20,920 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:20,920 INFO L791 eck$LassoCheckResult]: Stem: 9690#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9691#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9701#L367 assume !(main_~length~0#1 < 1); 9692#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9693#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9702#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9742#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9741#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9740#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9739#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9737#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9736#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9734#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9733#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9732#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9731#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9728#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9726#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9722#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9720#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9715#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9766#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9768#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9779#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9778#L370-4 main_~j~0#1 := 0; 9777#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9776#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9775#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9774#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9772#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9770#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9745#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9751#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9748#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9750#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9698#L378-2 [2021-12-06 21:49:20,920 INFO L793 eck$LassoCheckResult]: Loop: 9698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9747#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9698#L378-2 [2021-12-06 21:49:20,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:20,920 INFO L85 PathProgramCache]: Analyzing trace with hash -1598856833, now seen corresponding path program 11 times [2021-12-06 21:49:20,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:20,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886002074] [2021-12-06 21:49:20,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:20,920 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:20,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:21,116 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:21,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:21,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886002074] [2021-12-06 21:49:21,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886002074] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:21,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1575902171] [2021-12-06 21:49:21,116 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:21,117 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:21,117 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:21,117 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:21,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-12-06 21:49:21,237 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-12-06 21:49:21,237 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:21,239 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 44 conjunts are in the unsatisfiable core [2021-12-06 21:49:21,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:21,283 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:21,325 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:49:21,325 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:21,334 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:49:21,334 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:21,356 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:49:21,357 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:21,366 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:49:21,366 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:21,500 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:21,501 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 2 proven. 157 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:21,501 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:21,699 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:21,700 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:21,742 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 1 proven. 157 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:49:21,742 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1575902171] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:21,742 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:21,742 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 34 [2021-12-06 21:49:21,742 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680180876] [2021-12-06 21:49:21,742 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:21,743 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:21,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:21,743 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2021-12-06 21:49:21,743 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:21,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935777134] [2021-12-06 21:49:21,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:21,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:21,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:21,745 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:21,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:21,747 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:21,769 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:21,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-12-06 21:49:21,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=1083, Unknown=0, NotChecked=0, Total=1190 [2021-12-06 21:49:21,770 INFO L87 Difference]: Start difference. First operand 111 states and 141 transitions. cyclomatic complexity: 36 Second operand has 35 states, 34 states have (on average 2.2058823529411766) internal successors, (75), 35 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:22,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:22,144 INFO L93 Difference]: Finished difference Result 121 states and 143 transitions. [2021-12-06 21:49:22,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-12-06 21:49:22,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 143 transitions. [2021-12-06 21:49:22,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:22,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 119 states and 141 transitions. [2021-12-06 21:49:22,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:49:22,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:49:22,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 141 transitions. [2021-12-06 21:49:22,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:22,146 INFO L681 BuchiCegarLoop]: Abstraction has 119 states and 141 transitions. [2021-12-06 21:49:22,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 141 transitions. [2021-12-06 21:49:22,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 68. [2021-12-06 21:49:22,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.25) internal successors, (85), 67 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:22,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 85 transitions. [2021-12-06 21:49:22,147 INFO L704 BuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2021-12-06 21:49:22,147 INFO L587 BuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2021-12-06 21:49:22,147 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-06 21:49:22,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 85 transitions. [2021-12-06 21:49:22,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:22,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:22,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:22,148 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:22,148 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:22,148 INFO L791 eck$LassoCheckResult]: Stem: 10258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10269#L367 assume !(main_~length~0#1 < 1); 10260#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10261#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10262#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10270#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10322#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10319#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10318#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10317#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10316#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10313#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10312#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10308#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10304#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10302#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10299#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10298#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10293#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10283#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10267#L370-4 main_~j~0#1 := 0; 10268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10265#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10266#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10291#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10289#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10287#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10286#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10285#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10282#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10281#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10280#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10279#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10278#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10263#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10264#L378-2 [2021-12-06 21:49:22,148 INFO L793 eck$LassoCheckResult]: Loop: 10264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10277#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10264#L378-2 [2021-12-06 21:49:22,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:22,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1736843903, now seen corresponding path program 12 times [2021-12-06 21:49:22,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:22,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861128028] [2021-12-06 21:49:22,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:22,149 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:22,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:22,384 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:22,384 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:22,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861128028] [2021-12-06 21:49:22,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861128028] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:22,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [868825821] [2021-12-06 21:49:22,384 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:22,384 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:22,384 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:22,385 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:22,386 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-12-06 21:49:22,496 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2021-12-06 21:49:22,496 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:22,498 INFO L263 TraceCheckSpWp]: Trace formula consists of 252 conjuncts, 20 conjunts are in the unsatisfiable core [2021-12-06 21:49:22,499 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:22,709 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:22,709 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:22,825 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:22,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [868825821] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:22,826 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:22,826 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 50 [2021-12-06 21:49:22,826 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431988453] [2021-12-06 21:49:22,826 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:22,826 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:22,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:22,826 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2021-12-06 21:49:22,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:22,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652477259] [2021-12-06 21:49:22,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:22,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:22,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:22,828 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:22,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:22,830 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:22,853 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:22,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-12-06 21:49:22,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=436, Invalid=2014, Unknown=0, NotChecked=0, Total=2450 [2021-12-06 21:49:22,854 INFO L87 Difference]: Start difference. First operand 68 states and 85 transitions. cyclomatic complexity: 21 Second operand has 50 states, 50 states have (on average 2.24) internal successors, (112), 50 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:23,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:23,132 INFO L93 Difference]: Finished difference Result 91 states and 109 transitions. [2021-12-06 21:49:23,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-12-06 21:49:23,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 109 transitions. [2021-12-06 21:49:23,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:23,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 73 states and 91 transitions. [2021-12-06 21:49:23,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:23,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:23,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 91 transitions. [2021-12-06 21:49:23,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:23,134 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 91 transitions. [2021-12-06 21:49:23,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 91 transitions. [2021-12-06 21:49:23,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 59. [2021-12-06 21:49:23,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.2372881355932204) internal successors, (73), 58 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:23,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 73 transitions. [2021-12-06 21:49:23,135 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2021-12-06 21:49:23,135 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2021-12-06 21:49:23,135 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-12-06 21:49:23,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 73 transitions. [2021-12-06 21:49:23,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:23,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:23,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:23,136 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:23,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:23,136 INFO L791 eck$LassoCheckResult]: Stem: 10778#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10789#L367 assume !(main_~length~0#1 < 1); 10780#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10781#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10790#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10795#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10792#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10834#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10831#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10828#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10827#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10825#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10822#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10819#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10810#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10816#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10813#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10812#L370-4 main_~j~0#1 := 0; 10793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10785#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10808#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10807#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10806#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10804#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10803#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10802#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10800#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10797#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10796#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10783#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10784#L378-2 [2021-12-06 21:49:23,136 INFO L793 eck$LassoCheckResult]: Loop: 10784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10798#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10784#L378-2 [2021-12-06 21:49:23,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:23,136 INFO L85 PathProgramCache]: Analyzing trace with hash -433799996, now seen corresponding path program 13 times [2021-12-06 21:49:23,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:23,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025501883] [2021-12-06 21:49:23,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:23,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:23,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:23,333 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:23,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:23,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025501883] [2021-12-06 21:49:23,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025501883] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:23,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1623026714] [2021-12-06 21:49:23,334 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:23,334 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:23,334 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:23,335 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:23,335 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-12-06 21:49:23,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:23,400 INFO L263 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 47 conjunts are in the unsatisfiable core [2021-12-06 21:49:23,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:23,558 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:23,624 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:23,625 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:23,632 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:23,632 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:23,867 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:23,868 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:23,868 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:23,980 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:23,981 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:24,027 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:24,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1623026714] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:24,027 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:24,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 46 [2021-12-06 21:49:24,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360755858] [2021-12-06 21:49:24,028 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:24,028 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:24,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:24,028 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2021-12-06 21:49:24,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:24,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473326044] [2021-12-06 21:49:24,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:24,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:24,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:24,030 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:24,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:24,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:24,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:24,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-12-06 21:49:24,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1991, Unknown=0, NotChecked=0, Total=2162 [2021-12-06 21:49:24,055 INFO L87 Difference]: Start difference. First operand 59 states and 73 transitions. cyclomatic complexity: 18 Second operand has 47 states, 46 states have (on average 2.217391304347826) internal successors, (102), 47 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:24,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:24,640 INFO L93 Difference]: Finished difference Result 75 states and 89 transitions. [2021-12-06 21:49:24,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-12-06 21:49:24,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 89 transitions. [2021-12-06 21:49:24,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:24,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 74 states and 88 transitions. [2021-12-06 21:49:24,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:24,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:24,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 88 transitions. [2021-12-06 21:49:24,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:24,642 INFO L681 BuchiCegarLoop]: Abstraction has 74 states and 88 transitions. [2021-12-06 21:49:24,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 88 transitions. [2021-12-06 21:49:24,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 54. [2021-12-06 21:49:24,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2222222222222223) internal successors, (66), 53 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:24,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 66 transitions. [2021-12-06 21:49:24,643 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 66 transitions. [2021-12-06 21:49:24,643 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 66 transitions. [2021-12-06 21:49:24,643 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-12-06 21:49:24,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 66 transitions. [2021-12-06 21:49:24,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:24,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:24,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:24,643 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:24,643 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:24,644 INFO L791 eck$LassoCheckResult]: Stem: 11276#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11287#L367 assume !(main_~length~0#1 < 1); 11278#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11279#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11280#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11288#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11322#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11289#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11290#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11293#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11294#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11321#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11319#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11318#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11317#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11316#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11315#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11314#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11313#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11312#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11309#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11307#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11306#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11305#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11304#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11298#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11285#L370-4 main_~j~0#1 := 0; 11286#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11291#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11283#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11329#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11327#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11325#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11324#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11323#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11302#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11300#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11296#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11281#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11282#L378-2 [2021-12-06 21:49:24,644 INFO L793 eck$LassoCheckResult]: Loop: 11282#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11297#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11282#L378-2 [2021-12-06 21:49:24,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:24,644 INFO L85 PathProgramCache]: Analyzing trace with hash -51110457, now seen corresponding path program 16 times [2021-12-06 21:49:24,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:24,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114506590] [2021-12-06 21:49:24,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:24,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:24,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:24,873 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:24,874 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:24,874 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114506590] [2021-12-06 21:49:24,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114506590] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:24,874 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1428873428] [2021-12-06 21:49:24,874 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:24,874 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:24,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:24,875 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:24,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-12-06 21:49:24,942 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:24,942 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:24,944 INFO L263 TraceCheckSpWp]: Trace formula consists of 258 conjuncts, 46 conjunts are in the unsatisfiable core [2021-12-06 21:49:24,945 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:25,125 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:49:25,413 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:25,415 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:25,415 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:25,482 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:25,483 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:25,540 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:25,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1428873428] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:25,540 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:25,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 22] total 46 [2021-12-06 21:49:25,540 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665231671] [2021-12-06 21:49:25,540 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:25,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:25,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:25,541 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2021-12-06 21:49:25,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:25,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668258663] [2021-12-06 21:49:25,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:25,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:25,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:25,543 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:25,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:25,545 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:25,572 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:25,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-12-06 21:49:25,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=1993, Unknown=0, NotChecked=0, Total=2162 [2021-12-06 21:49:25,573 INFO L87 Difference]: Start difference. First operand 54 states and 66 transitions. cyclomatic complexity: 15 Second operand has 47 states, 46 states have (on average 2.3043478260869565) internal successors, (106), 47 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:26,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:26,063 INFO L93 Difference]: Finished difference Result 84 states and 101 transitions. [2021-12-06 21:49:26,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-12-06 21:49:26,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 101 transitions. [2021-12-06 21:49:26,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:26,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 100 transitions. [2021-12-06 21:49:26,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:49:26,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:49:26,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 100 transitions. [2021-12-06 21:49:26,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:26,065 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 100 transitions. [2021-12-06 21:49:26,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 100 transitions. [2021-12-06 21:49:26,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 62. [2021-12-06 21:49:26,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.2419354838709677) internal successors, (77), 61 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:26,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 77 transitions. [2021-12-06 21:49:26,066 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 77 transitions. [2021-12-06 21:49:26,066 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 77 transitions. [2021-12-06 21:49:26,066 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-12-06 21:49:26,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 77 transitions. [2021-12-06 21:49:26,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:26,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:26,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:26,067 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:26,067 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:26,067 INFO L791 eck$LassoCheckResult]: Stem: 11778#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11789#L367 assume !(main_~length~0#1 < 1); 11780#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11781#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11790#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11795#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11792#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11796#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11797#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11819#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11815#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11814#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11813#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11812#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11811#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11810#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11809#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11808#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11807#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11806#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11805#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11804#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11802#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11801#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11800#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11798#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11787#L370-4 main_~j~0#1 := 0; 11788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11835#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11794#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11785#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11834#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11832#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11831#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11830#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11829#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11828#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11827#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11826#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11783#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11784#L378-2 [2021-12-06 21:49:26,067 INFO L793 eck$LassoCheckResult]: Loop: 11784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11820#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11784#L378-2 [2021-12-06 21:49:26,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:26,067 INFO L85 PathProgramCache]: Analyzing trace with hash -1872505652, now seen corresponding path program 17 times [2021-12-06 21:49:26,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:26,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116469706] [2021-12-06 21:49:26,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:26,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:26,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:26,343 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:26,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:26,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116469706] [2021-12-06 21:49:26,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116469706] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:26,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2003079407] [2021-12-06 21:49:26,343 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:26,343 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:26,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:26,344 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:26,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-12-06 21:49:26,459 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-12-06 21:49:26,459 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:26,461 INFO L263 TraceCheckSpWp]: Trace formula consists of 269 conjuncts, 22 conjunts are in the unsatisfiable core [2021-12-06 21:49:26,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:26,709 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:26,709 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:26,841 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 81 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:26,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2003079407] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:26,841 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:26,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23, 23] total 55 [2021-12-06 21:49:26,842 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528806425] [2021-12-06 21:49:26,842 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:26,842 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:26,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:26,842 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2021-12-06 21:49:26,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:26,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822208782] [2021-12-06 21:49:26,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:26,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:26,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:26,844 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:26,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:26,846 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:26,868 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:26,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2021-12-06 21:49:26,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=523, Invalid=2447, Unknown=0, NotChecked=0, Total=2970 [2021-12-06 21:49:26,869 INFO L87 Difference]: Start difference. First operand 62 states and 77 transitions. cyclomatic complexity: 19 Second operand has 55 states, 55 states have (on average 2.2363636363636363) internal successors, (123), 55 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:27,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:27,197 INFO L93 Difference]: Finished difference Result 87 states and 103 transitions. [2021-12-06 21:49:27,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-12-06 21:49:27,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 103 transitions. [2021-12-06 21:49:27,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:27,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 67 states and 83 transitions. [2021-12-06 21:49:27,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:27,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:27,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 83 transitions. [2021-12-06 21:49:27,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:27,199 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 83 transitions. [2021-12-06 21:49:27,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 83 transitions. [2021-12-06 21:49:27,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 64. [2021-12-06 21:49:27,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.234375) internal successors, (79), 63 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:27,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 79 transitions. [2021-12-06 21:49:27,200 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 79 transitions. [2021-12-06 21:49:27,200 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 79 transitions. [2021-12-06 21:49:27,200 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-12-06 21:49:27,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 79 transitions. [2021-12-06 21:49:27,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:27,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:27,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:27,200 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:27,200 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:27,201 INFO L791 eck$LassoCheckResult]: Stem: 12325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12336#L367 assume !(main_~length~0#1 < 1); 12327#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12328#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12337#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12339#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12386#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12383#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12380#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12379#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12378#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12377#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12376#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12375#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12374#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12373#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12372#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12371#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12370#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12369#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12368#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12367#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12359#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12365#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12362#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12361#L370-4 main_~j~0#1 := 0; 12340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12332#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12357#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12356#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12355#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12353#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12351#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12350#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12349#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12347#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12344#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12343#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12330#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12331#L378-2 [2021-12-06 21:49:27,201 INFO L793 eck$LassoCheckResult]: Loop: 12331#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12345#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12331#L378-2 [2021-12-06 21:49:27,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:27,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1084882941, now seen corresponding path program 14 times [2021-12-06 21:49:27,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:27,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103634044] [2021-12-06 21:49:27,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:27,201 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:27,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:27,438 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:27,438 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:27,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103634044] [2021-12-06 21:49:27,438 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103634044] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:27,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1832326833] [2021-12-06 21:49:27,438 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:27,438 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:27,438 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:27,439 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:27,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-12-06 21:49:27,501 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:27,501 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:27,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 280 conjuncts, 47 conjunts are in the unsatisfiable core [2021-12-06 21:49:27,504 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:27,561 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:27,624 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:27,625 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:27,638 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:27,639 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:27,836 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:27,837 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:27,837 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:27,960 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:27,961 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:28,015 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:28,015 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1832326833] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:28,015 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:28,015 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2021-12-06 21:49:28,015 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930931842] [2021-12-06 21:49:28,015 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:28,015 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:28,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:28,016 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2021-12-06 21:49:28,016 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:28,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730289847] [2021-12-06 21:49:28,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:28,016 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:28,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:28,018 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:28,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:28,020 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:28,042 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:28,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-12-06 21:49:28,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=1299, Unknown=0, NotChecked=0, Total=1406 [2021-12-06 21:49:28,043 INFO L87 Difference]: Start difference. First operand 64 states and 79 transitions. cyclomatic complexity: 19 Second operand has 38 states, 37 states have (on average 2.2162162162162162) internal successors, (82), 38 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:28,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:28,743 INFO L93 Difference]: Finished difference Result 139 states and 163 transitions. [2021-12-06 21:49:28,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-12-06 21:49:28,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 163 transitions. [2021-12-06 21:49:28,744 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:49:28,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 138 states and 162 transitions. [2021-12-06 21:49:28,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:49:28,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:49:28,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138 states and 162 transitions. [2021-12-06 21:49:28,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:28,745 INFO L681 BuchiCegarLoop]: Abstraction has 138 states and 162 transitions. [2021-12-06 21:49:28,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states and 162 transitions. [2021-12-06 21:49:28,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 70. [2021-12-06 21:49:28,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.2714285714285714) internal successors, (89), 69 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:28,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 89 transitions. [2021-12-06 21:49:28,747 INFO L704 BuchiCegarLoop]: Abstraction has 70 states and 89 transitions. [2021-12-06 21:49:28,747 INFO L587 BuchiCegarLoop]: Abstraction has 70 states and 89 transitions. [2021-12-06 21:49:28,747 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-12-06 21:49:28,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 89 transitions. [2021-12-06 21:49:28,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:28,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:28,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:28,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:28,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:28,747 INFO L791 eck$LassoCheckResult]: Stem: 12915#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12926#L367 assume !(main_~length~0#1 < 1); 12917#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12918#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12927#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12961#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12928#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12929#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12932#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12960#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12959#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12958#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12957#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12954#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12952#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12951#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12950#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12948#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12946#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12945#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12940#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12938#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12983#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12924#L370-4 main_~j~0#1 := 0; 12925#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12977#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12922#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12976#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12974#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12972#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12971#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12970#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12969#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12968#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12967#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12966#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12965#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12964#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12963#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12920#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12921#L378-2 [2021-12-06 21:49:28,748 INFO L793 eck$LassoCheckResult]: Loop: 12921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12962#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12921#L378-2 [2021-12-06 21:49:28,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:28,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1104549896, now seen corresponding path program 15 times [2021-12-06 21:49:28,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:28,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727249373] [2021-12-06 21:49:28,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:28,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:28,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:28,954 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:28,954 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:28,954 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727249373] [2021-12-06 21:49:28,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727249373] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:28,954 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2130491579] [2021-12-06 21:49:28,954 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:28,954 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:28,955 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:28,955 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:28,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-12-06 21:49:29,100 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2021-12-06 21:49:29,101 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:29,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 28 conjunts are in the unsatisfiable core [2021-12-06 21:49:29,104 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:29,257 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:29,798 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:29,798 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:29,818 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:29,818 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:30,404 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:30,406 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:30,437 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:30,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2130491579] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:30,438 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:30,438 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 25] total 61 [2021-12-06 21:49:30,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390830853] [2021-12-06 21:49:30,438 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:30,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:30,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:30,438 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2021-12-06 21:49:30,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:30,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747315302] [2021-12-06 21:49:30,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:30,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:30,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:30,440 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:30,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:30,442 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:30,466 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:30,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2021-12-06 21:49:30,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=432, Invalid=3350, Unknown=0, NotChecked=0, Total=3782 [2021-12-06 21:49:30,468 INFO L87 Difference]: Start difference. First operand 70 states and 89 transitions. cyclomatic complexity: 23 Second operand has 62 states, 61 states have (on average 2.180327868852459) internal successors, (133), 62 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:31,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:31,328 INFO L93 Difference]: Finished difference Result 115 states and 135 transitions. [2021-12-06 21:49:31,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-12-06 21:49:31,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 135 transitions. [2021-12-06 21:49:31,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:31,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 90 states and 109 transitions. [2021-12-06 21:49:31,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:31,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:31,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 109 transitions. [2021-12-06 21:49:31,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:31,329 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 109 transitions. [2021-12-06 21:49:31,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 109 transitions. [2021-12-06 21:49:31,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 72. [2021-12-06 21:49:31,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2638888888888888) internal successors, (91), 71 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:31,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 91 transitions. [2021-12-06 21:49:31,331 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 91 transitions. [2021-12-06 21:49:31,331 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 91 transitions. [2021-12-06 21:49:31,331 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-12-06 21:49:31,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 91 transitions. [2021-12-06 21:49:31,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:31,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:31,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:31,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:31,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:31,332 INFO L791 eck$LassoCheckResult]: Stem: 13574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13585#L367 assume !(main_~length~0#1 < 1); 13576#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13577#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13578#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13586#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13643#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13640#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13637#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13631#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13628#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13627#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13625#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13622#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13611#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13608#L370-4 main_~j~0#1 := 0; 13607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13606#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13581#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13605#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13603#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13602#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13601#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13600#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13599#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13598#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13597#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13595#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13594#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13593#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13579#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13580#L378-2 [2021-12-06 21:49:31,332 INFO L793 eck$LassoCheckResult]: Loop: 13580#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13591#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13580#L378-2 [2021-12-06 21:49:31,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:31,332 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 18 times [2021-12-06 21:49:31,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:31,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763845881] [2021-12-06 21:49:31,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:31,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:31,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:31,555 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:31,556 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:31,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763845881] [2021-12-06 21:49:31,556 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763845881] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:31,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [948627485] [2021-12-06 21:49:31,556 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:31,556 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:31,556 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:31,557 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:31,557 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-12-06 21:49:31,718 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2021-12-06 21:49:31,718 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:31,719 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 29 conjunts are in the unsatisfiable core [2021-12-06 21:49:31,721 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:31,868 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:32,396 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:32,397 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:32,399 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:32,399 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:33,580 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:33,582 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:33,610 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:33,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [948627485] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:33,611 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:33,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2021-12-06 21:49:33,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873298439] [2021-12-06 21:49:33,611 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:33,611 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:33,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:33,611 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2021-12-06 21:49:33,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:33,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899832384] [2021-12-06 21:49:33,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:33,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:33,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:33,617 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:33,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:33,618 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:33,641 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:33,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2021-12-06 21:49:33,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=3566, Unknown=2, NotChecked=0, Total=4032 [2021-12-06 21:49:33,643 INFO L87 Difference]: Start difference. First operand 72 states and 91 transitions. cyclomatic complexity: 23 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:34,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:34,853 INFO L93 Difference]: Finished difference Result 113 states and 133 transitions. [2021-12-06 21:49:34,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2021-12-06 21:49:34,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113 states and 133 transitions. [2021-12-06 21:49:34,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:34,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113 states to 90 states and 108 transitions. [2021-12-06 21:49:34,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:34,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:34,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 108 transitions. [2021-12-06 21:49:34,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:34,855 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 108 transitions. [2021-12-06 21:49:34,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 108 transitions. [2021-12-06 21:49:34,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 72. [2021-12-06 21:49:34,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.25) internal successors, (90), 71 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:34,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 90 transitions. [2021-12-06 21:49:34,856 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 90 transitions. [2021-12-06 21:49:34,856 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 90 transitions. [2021-12-06 21:49:34,856 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-12-06 21:49:34,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 90 transitions. [2021-12-06 21:49:34,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:34,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:34,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:34,857 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:34,857 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:34,857 INFO L791 eck$LassoCheckResult]: Stem: 14252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14263#L367 assume !(main_~length~0#1 < 1); 14254#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14255#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14256#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14264#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14269#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14265#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14266#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14323#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14322#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14321#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14319#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14318#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14317#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14316#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14315#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14314#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14313#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14312#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14309#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14307#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14306#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14305#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14304#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14303#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14302#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14301#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14298#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14296#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14290#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14291#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14289#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14288#L370-4 main_~j~0#1 := 0; 14267#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14284#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14282#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14280#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14278#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14277#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14276#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14273#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14271#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14270#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14257#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14258#L378-2 [2021-12-06 21:49:34,857 INFO L793 eck$LassoCheckResult]: Loop: 14258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14272#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14258#L378-2 [2021-12-06 21:49:34,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:34,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1228380549, now seen corresponding path program 16 times [2021-12-06 21:49:34,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:34,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329909340] [2021-12-06 21:49:34,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:34,858 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:34,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:35,107 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 0 proven. 248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:35,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:35,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329909340] [2021-12-06 21:49:35,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329909340] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:35,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1189466712] [2021-12-06 21:49:35,107 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:35,107 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:35,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:35,108 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:35,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-12-06 21:49:35,177 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:35,177 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:35,179 INFO L263 TraceCheckSpWp]: Trace formula consists of 294 conjuncts, 54 conjunts are in the unsatisfiable core [2021-12-06 21:49:35,181 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:35,363 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:35,434 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:35,434 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:35,439 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:35,439 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:35,472 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:35,472 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:35,743 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:35,744 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:35,745 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:35,935 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:35,937 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:35,991 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 246 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:49:35,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1189466712] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:35,991 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:35,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 25] total 52 [2021-12-06 21:49:35,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336835066] [2021-12-06 21:49:35,992 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:35,992 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:35,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:35,992 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2021-12-06 21:49:35,992 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:35,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139635353] [2021-12-06 21:49:35,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:35,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:35,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:35,994 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:35,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:35,996 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:36,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:36,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2021-12-06 21:49:36,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=2554, Unknown=0, NotChecked=0, Total=2756 [2021-12-06 21:49:36,018 INFO L87 Difference]: Start difference. First operand 72 states and 90 transitions. cyclomatic complexity: 22 Second operand has 53 states, 52 states have (on average 2.3076923076923075) internal successors, (120), 53 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:36,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:36,695 INFO L93 Difference]: Finished difference Result 90 states and 108 transitions. [2021-12-06 21:49:36,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-12-06 21:49:36,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 108 transitions. [2021-12-06 21:49:36,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:36,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 89 states and 107 transitions. [2021-12-06 21:49:36,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:36,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:36,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 107 transitions. [2021-12-06 21:49:36,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:36,697 INFO L681 BuchiCegarLoop]: Abstraction has 89 states and 107 transitions. [2021-12-06 21:49:36,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 107 transitions. [2021-12-06 21:49:36,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 62. [2021-12-06 21:49:36,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.2258064516129032) internal successors, (76), 61 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:36,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 76 transitions. [2021-12-06 21:49:36,698 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 76 transitions. [2021-12-06 21:49:36,698 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 76 transitions. [2021-12-06 21:49:36,698 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-12-06 21:49:36,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 76 transitions. [2021-12-06 21:49:36,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:36,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:36,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:36,699 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:36,699 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:36,699 INFO L791 eck$LassoCheckResult]: Stem: 14834#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14845#L367 assume !(main_~length~0#1 < 1); 14836#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14837#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14848#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14895#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14893#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14890#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14889#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14888#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14887#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14886#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14885#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14884#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14882#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14881#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14880#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14879#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14878#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14877#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14876#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14875#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14874#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14872#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14871#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14852#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14869#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14851#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14839#L370-4 main_~j~0#1 := 0; 14840#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14843#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14850#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14868#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14867#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14865#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14863#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14857#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14855#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14841#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14842#L378-2 [2021-12-06 21:49:36,699 INFO L793 eck$LassoCheckResult]: Loop: 14842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14853#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14842#L378-2 [2021-12-06 21:49:36,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:36,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1280932492, now seen corresponding path program 19 times [2021-12-06 21:49:36,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:36,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910107725] [2021-12-06 21:49:36,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:36,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:36,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:36,958 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:36,958 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:36,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910107725] [2021-12-06 21:49:36,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910107725] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:36,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [330929509] [2021-12-06 21:49:36,958 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:36,958 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:36,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:36,959 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:36,960 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-12-06 21:49:37,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:37,037 INFO L263 TraceCheckSpWp]: Trace formula consists of 297 conjuncts, 53 conjunts are in the unsatisfiable core [2021-12-06 21:49:37,039 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:37,256 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:37,330 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:37,330 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:37,653 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:37,655 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:37,655 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:37,781 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:37,783 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:37,847 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:37,848 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [330929509] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:37,848 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:37,848 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27, 26] total 54 [2021-12-06 21:49:37,848 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511362363] [2021-12-06 21:49:37,848 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:37,848 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:37,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:37,848 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2021-12-06 21:49:37,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:37,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234522260] [2021-12-06 21:49:37,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:37,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:37,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:37,851 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:37,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:37,853 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:37,875 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:37,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2021-12-06 21:49:37,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=2771, Unknown=0, NotChecked=0, Total=2970 [2021-12-06 21:49:37,877 INFO L87 Difference]: Start difference. First operand 62 states and 76 transitions. cyclomatic complexity: 17 Second operand has 55 states, 54 states have (on average 2.259259259259259) internal successors, (122), 55 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:38,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:38,510 INFO L93 Difference]: Finished difference Result 66 states and 80 transitions. [2021-12-06 21:49:38,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-12-06 21:49:38,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 80 transitions. [2021-12-06 21:49:38,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:38,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 65 states and 79 transitions. [2021-12-06 21:49:38,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-12-06 21:49:38,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-12-06 21:49:38,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 79 transitions. [2021-12-06 21:49:38,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:38,511 INFO L681 BuchiCegarLoop]: Abstraction has 65 states and 79 transitions. [2021-12-06 21:49:38,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 79 transitions. [2021-12-06 21:49:38,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 64. [2021-12-06 21:49:38,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.21875) internal successors, (78), 63 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:38,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 78 transitions. [2021-12-06 21:49:38,512 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 78 transitions. [2021-12-06 21:49:38,512 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 78 transitions. [2021-12-06 21:49:38,512 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-12-06 21:49:38,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 78 transitions. [2021-12-06 21:49:38,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:38,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:38,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:38,513 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:38,513 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:38,513 INFO L791 eck$LassoCheckResult]: Stem: 15398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15409#L367 assume !(main_~length~0#1 < 1); 15400#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15401#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15410#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15411#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15412#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15444#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15442#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15439#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15436#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15433#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15430#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15428#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15427#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15425#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15424#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15423#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15422#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15421#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15420#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15417#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15416#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15407#L370-4 main_~j~0#1 := 0; 15408#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15413#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15405#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15461#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15460#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15459#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15458#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15457#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15456#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15455#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15454#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15453#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15452#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15451#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15450#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15449#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15448#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15447#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15446#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15403#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15404#L378-2 [2021-12-06 21:49:38,513 INFO L793 eck$LassoCheckResult]: Loop: 15404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15445#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15404#L378-2 [2021-12-06 21:49:38,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:38,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485871, now seen corresponding path program 20 times [2021-12-06 21:49:38,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:38,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745421249] [2021-12-06 21:49:38,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:38,513 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:38,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:38,772 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:38,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:38,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745421249] [2021-12-06 21:49:38,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745421249] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:38,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [940824008] [2021-12-06 21:49:38,773 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:38,773 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:38,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:38,774 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:38,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-12-06 21:49:38,858 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:38,858 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:38,859 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 50 conjunts are in the unsatisfiable core [2021-12-06 21:49:38,861 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:38,936 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:39,226 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:39,227 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:39,227 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:39,317 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:39,318 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:39,386 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:39,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [940824008] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:39,386 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:39,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26] total 40 [2021-12-06 21:49:39,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18608322] [2021-12-06 21:49:39,386 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:39,387 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:39,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:39,387 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2021-12-06 21:49:39,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:39,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019369704] [2021-12-06 21:49:39,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:39,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:39,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:39,389 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:39,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:39,391 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:39,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:39,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-12-06 21:49:39,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=1520, Unknown=0, NotChecked=0, Total=1640 [2021-12-06 21:49:39,413 INFO L87 Difference]: Start difference. First operand 64 states and 78 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:39,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:39,990 INFO L93 Difference]: Finished difference Result 98 states and 117 transitions. [2021-12-06 21:49:39,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-12-06 21:49:39,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 117 transitions. [2021-12-06 21:49:39,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:39,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 97 states and 116 transitions. [2021-12-06 21:49:39,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:49:39,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:49:39,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 116 transitions. [2021-12-06 21:49:39,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:39,991 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 116 transitions. [2021-12-06 21:49:39,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 116 transitions. [2021-12-06 21:49:39,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 72. [2021-12-06 21:49:39,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 71 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:39,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 89 transitions. [2021-12-06 21:49:39,993 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 89 transitions. [2021-12-06 21:49:39,993 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 89 transitions. [2021-12-06 21:49:39,993 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-12-06 21:49:39,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 89 transitions. [2021-12-06 21:49:39,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:39,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:39,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:39,994 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:39,994 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:39,994 INFO L791 eck$LassoCheckResult]: Stem: 15972#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15973#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15983#L367 assume !(main_~length~0#1 < 1); 15974#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15975#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15984#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15985#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15986#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16018#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16016#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16015#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16013#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16012#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16010#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16009#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16008#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16007#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16006#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16004#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16003#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16002#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16000#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15999#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15998#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15997#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15996#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15995#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15994#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15993#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15991#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15977#L370-4 main_~j~0#1 := 0; 15978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16039#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15981#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16038#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16036#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16035#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16034#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16033#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16032#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16031#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16030#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16029#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16028#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16027#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16026#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16025#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16024#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16023#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16022#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15979#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15980#L378-2 [2021-12-06 21:49:39,994 INFO L793 eck$LassoCheckResult]: Loop: 15980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16020#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15980#L378-2 [2021-12-06 21:49:39,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:39,994 INFO L85 PathProgramCache]: Analyzing trace with hash 921784534, now seen corresponding path program 21 times [2021-12-06 21:49:39,994 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:39,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337840874] [2021-12-06 21:49:39,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:39,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:40,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:40,328 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:40,328 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:40,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337840874] [2021-12-06 21:49:40,328 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337840874] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:40,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [764865735] [2021-12-06 21:49:40,328 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:40,329 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:40,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:40,329 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:40,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-12-06 21:49:40,518 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2021-12-06 21:49:40,518 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:40,520 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 26 conjunts are in the unsatisfiable core [2021-12-06 21:49:40,521 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:40,851 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:40,851 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:41,026 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:41,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [764865735] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:41,027 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:41,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27, 27] total 65 [2021-12-06 21:49:41,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548198292] [2021-12-06 21:49:41,027 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:41,027 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:41,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:41,028 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2021-12-06 21:49:41,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:41,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480937484] [2021-12-06 21:49:41,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:41,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:41,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:41,030 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:41,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:41,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:41,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:41,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2021-12-06 21:49:41,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=721, Invalid=3439, Unknown=0, NotChecked=0, Total=4160 [2021-12-06 21:49:41,055 INFO L87 Difference]: Start difference. First operand 72 states and 89 transitions. cyclomatic complexity: 21 Second operand has 65 states, 65 states have (on average 2.276923076923077) internal successors, (148), 65 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:41,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:41,450 INFO L93 Difference]: Finished difference Result 101 states and 119 transitions. [2021-12-06 21:49:41,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-12-06 21:49:41,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 119 transitions. [2021-12-06 21:49:41,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:41,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 77 states and 95 transitions. [2021-12-06 21:49:41,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:41,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:41,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 95 transitions. [2021-12-06 21:49:41,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:41,452 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 95 transitions. [2021-12-06 21:49:41,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 95 transitions. [2021-12-06 21:49:41,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 74. [2021-12-06 21:49:41,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2297297297297298) internal successors, (91), 73 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:41,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 91 transitions. [2021-12-06 21:49:41,453 INFO L704 BuchiCegarLoop]: Abstraction has 74 states and 91 transitions. [2021-12-06 21:49:41,453 INFO L587 BuchiCegarLoop]: Abstraction has 74 states and 91 transitions. [2021-12-06 21:49:41,453 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-12-06 21:49:41,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 91 transitions. [2021-12-06 21:49:41,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:41,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:41,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:41,454 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:41,454 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:41,454 INFO L791 eck$LassoCheckResult]: Stem: 16617#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16628#L367 assume !(main_~length~0#1 < 1); 16619#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16620#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16621#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16629#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16690#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16630#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16631#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16634#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16689#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16687#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16686#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16685#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16683#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16682#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16681#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16680#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16679#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16677#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16676#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16675#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16674#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16671#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16670#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16669#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16668#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16667#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16666#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16665#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16664#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16661#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16657#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16635#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16622#L370-4 main_~j~0#1 := 0; 16623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16633#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16655#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16654#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16653#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16652#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16651#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16649#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16647#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16646#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16645#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16644#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16643#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16642#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16641#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16638#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16624#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16625#L378-2 [2021-12-06 21:49:41,454 INFO L793 eck$LassoCheckResult]: Loop: 16625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16639#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16625#L378-2 [2021-12-06 21:49:41,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:41,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1897673997, now seen corresponding path program 17 times [2021-12-06 21:49:41,454 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:41,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372099093] [2021-12-06 21:49:41,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:41,454 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:41,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:41,754 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:41,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:41,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372099093] [2021-12-06 21:49:41,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372099093] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:41,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [299481644] [2021-12-06 21:49:41,754 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:41,754 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:41,754 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:41,755 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:41,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-12-06 21:49:41,914 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2021-12-06 21:49:41,914 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:41,916 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 55 conjunts are in the unsatisfiable core [2021-12-06 21:49:41,918 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:41,991 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:42,069 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:42,070 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:42,083 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:42,083 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:42,391 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:42,392 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:42,392 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:42,561 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:42,562 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:42,626 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:42,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [299481644] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:42,627 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:42,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 29] total 45 [2021-12-06 21:49:42,627 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451417937] [2021-12-06 21:49:42,627 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:42,627 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:42,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:42,627 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2021-12-06 21:49:42,627 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:42,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959116649] [2021-12-06 21:49:42,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:42,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:42,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:42,629 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:42,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:42,631 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:42,653 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:42,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-12-06 21:49:42,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=1938, Unknown=0, NotChecked=0, Total=2070 [2021-12-06 21:49:42,654 INFO L87 Difference]: Start difference. First operand 74 states and 91 transitions. cyclomatic complexity: 21 Second operand has 46 states, 45 states have (on average 2.1777777777777776) internal successors, (98), 46 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:43,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:43,661 INFO L93 Difference]: Finished difference Result 161 states and 187 transitions. [2021-12-06 21:49:43,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-12-06 21:49:43,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161 states and 187 transitions. [2021-12-06 21:49:43,662 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:49:43,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161 states to 160 states and 186 transitions. [2021-12-06 21:49:43,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:49:43,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:49:43,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 160 states and 186 transitions. [2021-12-06 21:49:43,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:43,663 INFO L681 BuchiCegarLoop]: Abstraction has 160 states and 186 transitions. [2021-12-06 21:49:43,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states and 186 transitions. [2021-12-06 21:49:43,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 80. [2021-12-06 21:49:43,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2625) internal successors, (101), 79 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:43,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 101 transitions. [2021-12-06 21:49:43,664 INFO L704 BuchiCegarLoop]: Abstraction has 80 states and 101 transitions. [2021-12-06 21:49:43,664 INFO L587 BuchiCegarLoop]: Abstraction has 80 states and 101 transitions. [2021-12-06 21:49:43,664 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-12-06 21:49:43,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 101 transitions. [2021-12-06 21:49:43,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:43,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:43,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:43,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:43,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:43,665 INFO L791 eck$LassoCheckResult]: Stem: 17311#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17322#L367 assume !(main_~length~0#1 < 1); 17313#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17314#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17315#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17323#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17324#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17325#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17326#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17362#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17361#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17360#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17359#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17358#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17357#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17356#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17355#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17354#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17353#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17352#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17351#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17350#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17347#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17345#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17344#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17342#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17341#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17340#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17338#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17337#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17336#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17389#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17316#L370-4 main_~j~0#1 := 0; 17317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17383#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17320#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17321#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17382#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17380#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17378#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17375#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17374#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17371#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17370#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17369#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17368#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17367#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17365#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17364#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17318#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17319#L378-2 [2021-12-06 21:49:43,665 INFO L793 eck$LassoCheckResult]: Loop: 17319#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17366#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17319#L378-2 [2021-12-06 21:49:43,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:43,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1696386414, now seen corresponding path program 18 times [2021-12-06 21:49:43,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:43,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785923391] [2021-12-06 21:49:43,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:43,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:43,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:43,956 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:43,956 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:43,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785923391] [2021-12-06 21:49:43,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785923391] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:43,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [975053629] [2021-12-06 21:49:43,957 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:43,957 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:43,957 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:43,958 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:43,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-12-06 21:49:44,216 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2021-12-06 21:49:44,216 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:44,219 INFO L263 TraceCheckSpWp]: Trace formula consists of 341 conjuncts, 32 conjunts are in the unsatisfiable core [2021-12-06 21:49:44,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:44,425 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:45,161 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:45,162 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:45,184 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 121 proven. 221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:45,184 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:45,965 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:45,967 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:45,999 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 110 proven. 232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:45,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [975053629] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:45,999 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:45,999 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 29] total 71 [2021-12-06 21:49:45,999 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707221994] [2021-12-06 21:49:45,999 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:46,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:46,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:46,000 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2021-12-06 21:49:46,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:46,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079937220] [2021-12-06 21:49:46,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:46,000 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:46,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:46,002 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:46,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:46,007 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:46,029 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:46,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2021-12-06 21:49:46,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=571, Invalid=4541, Unknown=0, NotChecked=0, Total=5112 [2021-12-06 21:49:46,030 INFO L87 Difference]: Start difference. First operand 80 states and 101 transitions. cyclomatic complexity: 25 Second operand has 72 states, 71 states have (on average 2.211267605633803) internal successors, (157), 72 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:47,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:47,195 INFO L93 Difference]: Finished difference Result 133 states and 155 transitions. [2021-12-06 21:49:47,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2021-12-06 21:49:47,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 155 transitions. [2021-12-06 21:49:47,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:47,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 104 states and 125 transitions. [2021-12-06 21:49:47,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:47,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:47,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 125 transitions. [2021-12-06 21:49:47,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:47,197 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 125 transitions. [2021-12-06 21:49:47,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 125 transitions. [2021-12-06 21:49:47,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 82. [2021-12-06 21:49:47,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:47,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2021-12-06 21:49:47,198 INFO L704 BuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2021-12-06 21:49:47,198 INFO L587 BuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2021-12-06 21:49:47,198 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-12-06 21:49:47,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2021-12-06 21:49:47,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:47,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:47,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:47,199 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:47,199 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:47,199 INFO L791 eck$LassoCheckResult]: Stem: 18082#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18093#L367 assume !(main_~length~0#1 < 1); 18084#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18085#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18086#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18094#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18097#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18095#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18096#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18161#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18160#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18140#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18139#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18135#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18134#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18132#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18123#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18122#L370-4 main_~j~0#1 := 0; 18098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18091#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18092#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18099#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18120#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18118#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18116#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18114#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18110#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18108#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18106#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18103#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18102#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18089#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18090#L378-2 [2021-12-06 21:49:47,199 INFO L793 eck$LassoCheckResult]: Loop: 18090#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18104#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18090#L378-2 [2021-12-06 21:49:47,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:47,199 INFO L85 PathProgramCache]: Analyzing trace with hash 2089107792, now seen corresponding path program 22 times [2021-12-06 21:49:47,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:47,200 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355236011] [2021-12-06 21:49:47,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:47,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:47,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:47,523 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:47,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:47,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355236011] [2021-12-06 21:49:47,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355236011] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:47,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [64936361] [2021-12-06 21:49:47,523 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:49:47,523 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:47,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:47,524 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:47,525 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-12-06 21:49:47,608 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:49:47,608 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:47,610 INFO L263 TraceCheckSpWp]: Trace formula consists of 333 conjuncts, 58 conjunts are in the unsatisfiable core [2021-12-06 21:49:47,611 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:47,897 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:49:48,339 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:48,341 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:48,341 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:48,422 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:49:48,423 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:49:48,494 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:48,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [64936361] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:48,494 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:48,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 28] total 58 [2021-12-06 21:49:48,494 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720211172] [2021-12-06 21:49:48,494 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:48,495 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:48,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:48,495 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2021-12-06 21:49:48,495 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:48,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134470129] [2021-12-06 21:49:48,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:48,495 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:48,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:48,497 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:48,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:48,499 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:48,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:48,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2021-12-06 21:49:48,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=3208, Unknown=0, NotChecked=0, Total=3422 [2021-12-06 21:49:48,520 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 25 Second operand has 59 states, 58 states have (on average 2.3448275862068964) internal successors, (136), 59 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:49,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:49,467 INFO L93 Difference]: Finished difference Result 163 states and 200 transitions. [2021-12-06 21:49:49,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-12-06 21:49:49,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163 states and 200 transitions. [2021-12-06 21:49:49,468 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 26 [2021-12-06 21:49:49,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163 states to 162 states and 199 transitions. [2021-12-06 21:49:49,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2021-12-06 21:49:49,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2021-12-06 21:49:49,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162 states and 199 transitions. [2021-12-06 21:49:49,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:49,469 INFO L681 BuchiCegarLoop]: Abstraction has 162 states and 199 transitions. [2021-12-06 21:49:49,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states and 199 transitions. [2021-12-06 21:49:49,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 136. [2021-12-06 21:49:49,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.2573529411764706) internal successors, (171), 135 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:49,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 171 transitions. [2021-12-06 21:49:49,471 INFO L704 BuchiCegarLoop]: Abstraction has 136 states and 171 transitions. [2021-12-06 21:49:49,471 INFO L587 BuchiCegarLoop]: Abstraction has 136 states and 171 transitions. [2021-12-06 21:49:49,471 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-12-06 21:49:49,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 171 transitions. [2021-12-06 21:49:49,471 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 24 [2021-12-06 21:49:49,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:49,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:49,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 11, 11, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:49,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:49,472 INFO L791 eck$LassoCheckResult]: Stem: 18793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18804#L367 assume !(main_~length~0#1 < 1); 18795#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18796#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18797#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18805#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18809#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18810#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18849#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18848#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18840#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18837#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18834#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18831#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18828#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18827#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18825#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18822#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18817#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18806#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18807#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18901#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18900#L370-4 main_~j~0#1 := 0; 18898#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18897#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18896#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18895#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18894#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18893#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18892#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18891#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18890#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18889#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18888#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18887#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18886#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18885#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18884#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18883#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18882#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18852#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18854#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18855#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18857#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18801#L378-2 [2021-12-06 21:49:49,472 INFO L793 eck$LassoCheckResult]: Loop: 18801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18850#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18801#L378-2 [2021-12-06 21:49:49,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:49,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1956214063, now seen corresponding path program 19 times [2021-12-06 21:49:49,472 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:49,472 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108279957] [2021-12-06 21:49:49,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:49,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:49,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:49,799 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 0 proven. 357 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:49,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:49,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108279957] [2021-12-06 21:49:49,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108279957] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:49,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2127934894] [2021-12-06 21:49:49,799 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:49:49,800 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:49,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:49,800 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:49,801 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-12-06 21:49:49,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:49,889 INFO L263 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 64 conjunts are in the unsatisfiable core [2021-12-06 21:49:49,891 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:50,152 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:50,228 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:50,229 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:50,242 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:50,243 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:50,285 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:50,286 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:50,292 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:49:50,293 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:49:50,691 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:49:50,692 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 2 proven. 355 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:50,692 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:50,902 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:50,903 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:50,984 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 1 proven. 355 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:49:50,984 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2127934894] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:50,984 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:50,984 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29] total 60 [2021-12-06 21:49:50,984 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074377638] [2021-12-06 21:49:50,984 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:50,985 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:50,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:50,985 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2021-12-06 21:49:50,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:50,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175060125] [2021-12-06 21:49:50,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:50,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:50,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:50,987 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:50,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:50,989 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:51,012 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:51,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2021-12-06 21:49:51,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=230, Invalid=3430, Unknown=0, NotChecked=0, Total=3660 [2021-12-06 21:49:51,013 INFO L87 Difference]: Start difference. First operand 136 states and 171 transitions. cyclomatic complexity: 41 Second operand has 61 states, 60 states have (on average 2.3333333333333335) internal successors, (140), 61 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:52,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:52,031 INFO L93 Difference]: Finished difference Result 154 states and 177 transitions. [2021-12-06 21:49:52,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-12-06 21:49:52,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 177 transitions. [2021-12-06 21:49:52,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:52,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 152 states and 175 transitions. [2021-12-06 21:49:52,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:49:52,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:49:52,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152 states and 175 transitions. [2021-12-06 21:49:52,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:52,032 INFO L681 BuchiCegarLoop]: Abstraction has 152 states and 175 transitions. [2021-12-06 21:49:52,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states and 175 transitions. [2021-12-06 21:49:52,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 79. [2021-12-06 21:49:52,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.2278481012658229) internal successors, (97), 78 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:52,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 97 transitions. [2021-12-06 21:49:52,034 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-12-06 21:49:52,034 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-12-06 21:49:52,034 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-12-06 21:49:52,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 97 transitions. [2021-12-06 21:49:52,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:52,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:52,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:52,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:52,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:52,035 INFO L791 eck$LassoCheckResult]: Stem: 19575#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19586#L367 assume !(main_~length~0#1 < 1); 19577#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19578#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19579#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19587#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19588#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19589#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19651#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19643#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19640#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19637#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19631#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19628#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19627#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19625#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19619#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19580#L370-4 main_~j~0#1 := 0; 19581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19584#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19617#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19616#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19615#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19614#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19613#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19612#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19611#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19609#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19608#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19607#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19606#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19605#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19603#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19598#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19595#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19594#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19582#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19583#L378-2 [2021-12-06 21:49:52,035 INFO L793 eck$LassoCheckResult]: Loop: 19583#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19596#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19583#L378-2 [2021-12-06 21:49:52,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:52,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1882864149, now seen corresponding path program 23 times [2021-12-06 21:49:52,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:52,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710865354] [2021-12-06 21:49:52,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:52,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:52,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:52,398 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 133 proven. 233 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:52,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:52,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710865354] [2021-12-06 21:49:52,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710865354] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:52,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1021773995] [2021-12-06 21:49:52,398 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:49:52,398 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:52,398 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:52,414 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:52,415 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-12-06 21:49:52,582 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2021-12-06 21:49:52,582 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:52,584 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 28 conjunts are in the unsatisfiable core [2021-12-06 21:49:52,585 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:52,971 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 156 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:52,971 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:53,171 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 144 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:53,171 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1021773995] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:53,171 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:53,171 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29, 29] total 70 [2021-12-06 21:49:53,171 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483640812] [2021-12-06 21:49:53,171 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:53,172 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:53,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:53,172 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2021-12-06 21:49:53,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:53,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099929814] [2021-12-06 21:49:53,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:53,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:53,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:53,174 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:53,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:53,176 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:53,198 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:53,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2021-12-06 21:49:53,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=832, Invalid=3998, Unknown=0, NotChecked=0, Total=4830 [2021-12-06 21:49:53,199 INFO L87 Difference]: Start difference. First operand 79 states and 97 transitions. cyclomatic complexity: 22 Second operand has 70 states, 70 states have (on average 2.2714285714285714) internal successors, (159), 70 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:53,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:53,632 INFO L93 Difference]: Finished difference Result 110 states and 129 transitions. [2021-12-06 21:49:53,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-12-06 21:49:53,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 129 transitions. [2021-12-06 21:49:53,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:53,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 84 states and 103 transitions. [2021-12-06 21:49:53,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:53,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:53,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 103 transitions. [2021-12-06 21:49:53,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:53,633 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 103 transitions. [2021-12-06 21:49:53,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 103 transitions. [2021-12-06 21:49:53,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 79. [2021-12-06 21:49:53,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.2278481012658229) internal successors, (97), 78 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:53,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 97 transitions. [2021-12-06 21:49:53,635 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-12-06 21:49:53,635 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 97 transitions. [2021-12-06 21:49:53,635 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-12-06 21:49:53,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 97 transitions. [2021-12-06 21:49:53,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:53,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:53,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:53,635 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:53,635 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:53,636 INFO L791 eck$LassoCheckResult]: Stem: 20273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20284#L367 assume !(main_~length~0#1 < 1); 20275#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20276#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20285#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20287#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20351#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20350#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20349#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20348#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20347#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20346#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20343#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20337#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20334#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20331#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20325#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20322#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20313#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20319#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20316#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20315#L370-4 main_~j~0#1 := 0; 20288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20280#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20311#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20309#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20307#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20306#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20305#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20304#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20303#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20302#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20301#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20300#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20299#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20297#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20296#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20295#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20292#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20291#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20278#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20279#L378-2 [2021-12-06 21:49:53,636 INFO L793 eck$LassoCheckResult]: Loop: 20279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20293#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20279#L378-2 [2021-12-06 21:49:53,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:53,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1975564248, now seen corresponding path program 20 times [2021-12-06 21:49:53,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:53,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596476537] [2021-12-06 21:49:53,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:53,636 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:53,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:54,007 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:54,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:54,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596476537] [2021-12-06 21:49:54,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596476537] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:54,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [472327561] [2021-12-06 21:49:54,008 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:49:54,008 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:54,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:54,009 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:54,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-12-06 21:49:54,097 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:49:54,097 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:54,099 INFO L263 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 59 conjunts are in the unsatisfiable core [2021-12-06 21:49:54,100 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:54,166 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:54,238 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:54,238 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:54,251 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:49:54,252 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:49:54,534 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:49:54,536 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:54,536 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:54,683 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:49:54,684 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:49:54,755 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:54,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [472327561] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:54,755 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:54,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2021-12-06 21:49:54,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660700303] [2021-12-06 21:49:54,755 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:54,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:54,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:54,756 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2021-12-06 21:49:54,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:54,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094658177] [2021-12-06 21:49:54,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:54,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:54,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:54,758 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:54,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:54,760 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:54,781 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:54,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-12-06 21:49:54,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=2031, Unknown=0, NotChecked=0, Total=2162 [2021-12-06 21:49:54,781 INFO L87 Difference]: Start difference. First operand 79 states and 97 transitions. cyclomatic complexity: 22 Second operand has 47 states, 46 states have (on average 2.239130434782609) internal successors, (103), 47 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:55,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:55,420 INFO L93 Difference]: Finished difference Result 142 states and 167 transitions. [2021-12-06 21:49:55,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-12-06 21:49:55,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142 states and 167 transitions. [2021-12-06 21:49:55,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:49:55,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142 states to 141 states and 166 transitions. [2021-12-06 21:49:55,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-12-06 21:49:55,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-12-06 21:49:55,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141 states and 166 transitions. [2021-12-06 21:49:55,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:55,422 INFO L681 BuchiCegarLoop]: Abstraction has 141 states and 166 transitions. [2021-12-06 21:49:55,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states and 166 transitions. [2021-12-06 21:49:55,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 85. [2021-12-06 21:49:55,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.2588235294117647) internal successors, (107), 84 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:55,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 107 transitions. [2021-12-06 21:49:55,423 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 107 transitions. [2021-12-06 21:49:55,424 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 107 transitions. [2021-12-06 21:49:55,424 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-12-06 21:49:55,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 107 transitions. [2021-12-06 21:49:55,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:55,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:55,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:55,424 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:55,424 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:55,424 INFO L791 eck$LassoCheckResult]: Stem: 20960#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20971#L367 assume !(main_~length~0#1 < 1); 20962#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20963#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20964#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20972#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20975#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20973#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20974#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21042#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21039#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21036#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21035#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21033#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21032#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21031#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21030#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21028#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21027#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21026#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21025#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21024#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21021#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21020#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21019#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21018#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21016#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21015#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21012#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21013#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21010#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20965#L370-4 main_~j~0#1 := 0; 20966#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20969#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20976#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21000#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20999#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20998#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20996#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20994#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20992#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20990#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20988#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20986#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20985#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20984#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20981#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20967#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20968#L378-2 [2021-12-06 21:49:55,425 INFO L793 eck$LassoCheckResult]: Loop: 20968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20982#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20968#L378-2 [2021-12-06 21:49:55,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:55,425 INFO L85 PathProgramCache]: Analyzing trace with hash 141700765, now seen corresponding path program 21 times [2021-12-06 21:49:55,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:55,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519054562] [2021-12-06 21:49:55,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:55,425 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:55,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:55,713 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:55,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:55,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519054562] [2021-12-06 21:49:55,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519054562] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:55,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [505308461] [2021-12-06 21:49:55,713 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:49:55,713 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:55,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:55,715 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:55,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-12-06 21:49:56,093 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2021-12-06 21:49:56,093 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:49:56,097 INFO L263 TraceCheckSpWp]: Trace formula consists of 366 conjuncts, 34 conjunts are in the unsatisfiable core [2021-12-06 21:49:56,098 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:49:56,340 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:49:57,109 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:49:57,109 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:49:57,136 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 144 proven. 259 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:57,136 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:49:58,024 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:49:58,026 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:49:58,071 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 132 proven. 271 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:58,071 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [505308461] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:49:58,071 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:49:58,071 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31, 31] total 76 [2021-12-06 21:49:58,071 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955394598] [2021-12-06 21:49:58,071 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:49:58,071 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:49:58,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:58,072 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2021-12-06 21:49:58,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:58,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352625320] [2021-12-06 21:49:58,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:58,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:58,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:58,074 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:49:58,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:49:58,075 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:49:58,098 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:49:58,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2021-12-06 21:49:58,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=648, Invalid=5204, Unknown=0, NotChecked=0, Total=5852 [2021-12-06 21:49:58,099 INFO L87 Difference]: Start difference. First operand 85 states and 107 transitions. cyclomatic complexity: 26 Second operand has 77 states, 76 states have (on average 2.223684210526316) internal successors, (169), 77 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:59,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:49:59,387 INFO L93 Difference]: Finished difference Result 142 states and 165 transitions. [2021-12-06 21:49:59,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2021-12-06 21:49:59,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142 states and 165 transitions. [2021-12-06 21:49:59,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:59,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142 states to 111 states and 133 transitions. [2021-12-06 21:49:59,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:49:59,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:49:59,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 133 transitions. [2021-12-06 21:49:59,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:49:59,389 INFO L681 BuchiCegarLoop]: Abstraction has 111 states and 133 transitions. [2021-12-06 21:49:59,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 133 transitions. [2021-12-06 21:49:59,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 87. [2021-12-06 21:49:59,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.2528735632183907) internal successors, (109), 86 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:49:59,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 109 transitions. [2021-12-06 21:49:59,390 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 109 transitions. [2021-12-06 21:49:59,390 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 109 transitions. [2021-12-06 21:49:59,390 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-12-06 21:49:59,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 109 transitions. [2021-12-06 21:49:59,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:49:59,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:49:59,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:49:59,391 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 13, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:49:59,391 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:49:59,391 INFO L791 eck$LassoCheckResult]: Stem: 21787#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21798#L367 assume !(main_~length~0#1 < 1); 21789#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21790#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21799#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21800#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21801#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21871#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21868#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21866#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21865#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21864#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21862#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21860#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21856#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21855#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21853#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21852#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21851#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21850#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21848#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21847#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21846#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21845#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21844#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21843#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21842#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21841#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21830#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21827#L370-4 main_~j~0#1 := 0; 21826#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21825#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21794#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21795#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21820#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21819#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21817#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21816#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21815#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21814#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21813#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21812#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21810#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21808#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21807#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21806#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21792#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21793#L378-2 [2021-12-06 21:49:59,391 INFO L793 eck$LassoCheckResult]: Loop: 21793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21804#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21793#L378-2 [2021-12-06 21:49:59,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:49:59,391 INFO L85 PathProgramCache]: Analyzing trace with hash 164333019, now seen corresponding path program 24 times [2021-12-06 21:49:59,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:49:59,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076455001] [2021-12-06 21:49:59,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:49:59,392 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:49:59,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:49:59,740 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:49:59,741 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:49:59,741 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076455001] [2021-12-06 21:49:59,741 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076455001] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:49:59,741 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1264591976] [2021-12-06 21:49:59,741 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:49:59,741 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:49:59,741 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:49:59,742 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:49:59,743 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-12-06 21:50:00,058 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2021-12-06 21:50:00,058 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:50:00,061 INFO L263 TraceCheckSpWp]: Trace formula consists of 358 conjuncts, 35 conjunts are in the unsatisfiable core [2021-12-06 21:50:00,062 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:50:00,284 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:50:01,056 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:50:01,057 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:50:01,058 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 144 proven. 259 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:50:01,058 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:50:02,043 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:50:02,044 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:50:02,080 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 132 proven. 271 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:50:02,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1264591976] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:50:02,081 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:50:02,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 32, 32] total 78 [2021-12-06 21:50:02,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563126149] [2021-12-06 21:50:02,081 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:50:02,081 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:50:02,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:50:02,081 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 49 times [2021-12-06 21:50:02,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:50:02,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680469605] [2021-12-06 21:50:02,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:50:02,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:50:02,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:50:02,084 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:50:02,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:50:02,085 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:50:02,107 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:50:02,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2021-12-06 21:50:02,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=686, Invalid=5476, Unknown=0, NotChecked=0, Total=6162 [2021-12-06 21:50:02,108 INFO L87 Difference]: Start difference. First operand 87 states and 109 transitions. cyclomatic complexity: 26 Second operand has 79 states, 78 states have (on average 2.1666666666666665) internal successors, (169), 79 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:50:03,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:50:03,779 INFO L93 Difference]: Finished difference Result 158 states and 193 transitions. [2021-12-06 21:50:03,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2021-12-06 21:50:03,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158 states and 193 transitions. [2021-12-06 21:50:03,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:50:03,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158 states to 127 states and 161 transitions. [2021-12-06 21:50:03,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:50:03,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:50:03,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 161 transitions. [2021-12-06 21:50:03,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:50:03,781 INFO L681 BuchiCegarLoop]: Abstraction has 127 states and 161 transitions. [2021-12-06 21:50:03,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 161 transitions. [2021-12-06 21:50:03,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 125. [2021-12-06 21:50:03,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125 states, 125 states have (on average 1.272) internal successors, (159), 124 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [2021-12-06 21:55:22,059 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:55:22,060 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:55:22,197 INFO L134 CoverageAnalysis]: Checked inductivity of 1314 backedges. 0 proven. 1312 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 21:55:22,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [759549142] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:22,198 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:22,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51] total 77 [2021-12-06 21:55:22,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105602889] [2021-12-06 21:55:22,198 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:22,198 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:22,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:22,198 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 94 times [2021-12-06 21:55:22,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:22,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110659358] [2021-12-06 21:55:22,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:22,199 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:22,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:22,202 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:22,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:22,205 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:22,228 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:22,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2021-12-06 21:55:22,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=243, Invalid=5763, Unknown=0, NotChecked=0, Total=6006 [2021-12-06 21:55:22,228 INFO L87 Difference]: Start difference. First operand 248 states and 310 transitions. cyclomatic complexity: 70 Second operand has 78 states, 77 states have (on average 2.2857142857142856) internal successors, (176), 78 states have internal predecessors, (176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:24,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:24,351 INFO L93 Difference]: Finished difference Result 288 states and 327 transitions. [2021-12-06 21:55:24,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-12-06 21:55:24,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 327 transitions. [2021-12-06 21:55:24,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:24,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 286 states and 325 transitions. [2021-12-06 21:55:24,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:55:24,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:55:24,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 286 states and 325 transitions. [2021-12-06 21:55:24,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:24,354 INFO L681 BuchiCegarLoop]: Abstraction has 286 states and 325 transitions. [2021-12-06 21:55:24,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states and 325 transitions. [2021-12-06 21:55:24,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 137. [2021-12-06 21:55:24,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 137 states, 137 states have (on average 1.218978102189781) internal successors, (167), 136 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:24,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 167 transitions. [2021-12-06 21:55:24,355 INFO L704 BuchiCegarLoop]: Abstraction has 137 states and 167 transitions. [2021-12-06 21:55:24,356 INFO L587 BuchiCegarLoop]: Abstraction has 137 states and 167 transitions. [2021-12-06 21:55:24,356 INFO L425 BuchiCegarLoop]: ======== Iteration 97============ [2021-12-06 21:55:24,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 137 states and 167 transitions. [2021-12-06 21:55:24,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:24,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:24,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:24,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 23, 23, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:24,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:24,357 INFO L791 eck$LassoCheckResult]: Stem: 70317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 70318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 70328#L367 assume !(main_~length~0#1 < 1); 70319#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 70320#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 70321#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70329#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70330#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70331#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70453#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70451#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70450#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70449#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70448#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70447#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70446#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70445#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70444#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70442#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70439#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70436#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70433#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70430#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70428#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70427#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70425#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70424#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70423#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70422#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70421#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70420#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70418#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70416#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70415#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70414#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70413#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70412#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70411#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70410#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70409#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70408#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70407#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70406#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70405#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70404#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70403#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70402#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70401#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70400#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70399#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70398#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70397#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70396#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70395#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70394#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 70388#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 70335#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 70336#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 70326#L370-4 main_~j~0#1 := 0; 70327#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70324#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70333#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70380#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70378#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70375#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70374#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70371#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70370#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70369#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70368#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70367#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70366#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70365#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70364#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70363#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70362#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70361#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70359#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70358#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70356#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70355#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70354#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70353#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70352#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70351#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70350#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70348#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70346#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70344#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70341#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70338#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 70337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70322#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 70323#L378-2 [2021-12-06 21:55:24,357 INFO L793 eck$LassoCheckResult]: Loop: 70323#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 70339#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 70323#L378-2 [2021-12-06 21:55:24,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:24,357 INFO L85 PathProgramCache]: Analyzing trace with hash 508978576, now seen corresponding path program 49 times [2021-12-06 21:55:24,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:24,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695010916] [2021-12-06 21:55:24,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:24,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:24,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:25,267 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 507 proven. 827 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:25,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:55:25,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695010916] [2021-12-06 21:55:25,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695010916] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:55:25,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1796536559] [2021-12-06 21:55:25,267 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:55:25,267 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:55:25,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:55:25,269 INFO L229 MonitoredProcess]: Starting monitored process 117 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:55:25,269 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (117)] Waiting until timeout for monitored process [2021-12-06 21:55:25,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:25,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 627 conjuncts, 50 conjunts are in the unsatisfiable core [2021-12-06 21:55:25,461 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:55:26,514 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 552 proven. 782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:26,514 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:55:27,076 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 552 proven. 782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:27,076 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1796536559] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:27,076 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:27,076 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 51, 51] total 125 [2021-12-06 21:55:27,076 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359797379] [2021-12-06 21:55:27,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:27,077 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:27,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:27,077 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 95 times [2021-12-06 21:55:27,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:27,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839779893] [2021-12-06 21:55:27,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:27,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:27,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:27,081 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:27,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:27,083 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:27,106 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:27,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2021-12-06 21:55:27,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2581, Invalid=12919, Unknown=0, NotChecked=0, Total=15500 [2021-12-06 21:55:27,107 INFO L87 Difference]: Start difference. First operand 137 states and 167 transitions. cyclomatic complexity: 34 Second operand has 125 states, 125 states have (on average 2.336) internal successors, (292), 125 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:28,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:28,322 INFO L93 Difference]: Finished difference Result 190 states and 221 transitions. [2021-12-06 21:55:28,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2021-12-06 21:55:28,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190 states and 221 transitions. [2021-12-06 21:55:28,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:28,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190 states to 142 states and 173 transitions. [2021-12-06 21:55:28,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:55:28,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:55:28,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142 states and 173 transitions. [2021-12-06 21:55:28,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:28,324 INFO L681 BuchiCegarLoop]: Abstraction has 142 states and 173 transitions. [2021-12-06 21:55:28,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states and 173 transitions. [2021-12-06 21:55:28,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 134. [2021-12-06 21:55:28,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.2164179104477613) internal successors, (163), 133 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:28,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 163 transitions. [2021-12-06 21:55:28,325 INFO L704 BuchiCegarLoop]: Abstraction has 134 states and 163 transitions. [2021-12-06 21:55:28,325 INFO L587 BuchiCegarLoop]: Abstraction has 134 states and 163 transitions. [2021-12-06 21:55:28,325 INFO L425 BuchiCegarLoop]: ======== Iteration 98============ [2021-12-06 21:55:28,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 163 transitions. [2021-12-06 21:55:28,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:28,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:28,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:28,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:28,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:28,326 INFO L791 eck$LassoCheckResult]: Stem: 71560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 71561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 71571#L367 assume !(main_~length~0#1 < 1); 71562#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 71563#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 71564#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71572#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71573#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71574#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71693#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71692#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71691#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71690#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71689#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71688#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71685#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71684#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71682#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71680#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71676#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71674#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71673#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71672#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71670#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71668#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71667#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71666#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71665#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71664#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71663#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71662#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71661#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71659#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71658#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71657#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71656#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71655#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71654#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71651#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71643#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71640#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71637#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71631#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 71630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71622#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 71628#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 71625#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 71624#L370-4 main_~j~0#1 := 0; 71575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71567#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71568#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71617#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71616#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71615#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71606#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71605#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71604#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71603#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71602#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71600#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71598#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71594#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71592#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71590#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71586#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71584#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71583#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71582#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 71578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71565#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 71566#L378-2 [2021-12-06 21:55:28,326 INFO L793 eck$LassoCheckResult]: Loop: 71566#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 71580#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 71566#L378-2 [2021-12-06 21:55:28,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:28,327 INFO L85 PathProgramCache]: Analyzing trace with hash 715762249, now seen corresponding path program 50 times [2021-12-06 21:55:28,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:28,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304675084] [2021-12-06 21:55:28,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:28,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:28,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:29,176 INFO L134 CoverageAnalysis]: Checked inductivity of 1358 backedges. 0 proven. 1358 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:29,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:55:29,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304675084] [2021-12-06 21:55:29,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304675084] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:55:29,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [477046309] [2021-12-06 21:55:29,176 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:55:29,176 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:55:29,176 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:55:29,177 INFO L229 MonitoredProcess]: Starting monitored process 118 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:55:29,178 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (118)] Waiting until timeout for monitored process [2021-12-06 21:55:29,372 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:55:29,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:55:29,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 630 conjuncts, 103 conjunts are in the unsatisfiable core [2021-12-06 21:55:29,378 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:55:29,516 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:55:29,628 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:55:29,629 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:55:29,642 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:55:29,643 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:55:30,549 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:55:30,555 INFO L134 CoverageAnalysis]: Checked inductivity of 1358 backedges. 0 proven. 1358 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:30,555 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:55:30,787 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:55:30,788 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:55:30,937 INFO L134 CoverageAnalysis]: Checked inductivity of 1358 backedges. 0 proven. 1358 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:30,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [477046309] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:30,937 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:30,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 79 [2021-12-06 21:55:30,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546550606] [2021-12-06 21:55:30,937 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:30,938 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:30,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:30,938 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 96 times [2021-12-06 21:55:30,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:30,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722012776] [2021-12-06 21:55:30,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:30,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:30,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:30,942 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:30,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:30,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:30,967 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:30,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2021-12-06 21:55:30,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=6101, Unknown=0, NotChecked=0, Total=6320 [2021-12-06 21:55:30,968 INFO L87 Difference]: Start difference. First operand 134 states and 163 transitions. cyclomatic complexity: 33 Second operand has 80 states, 79 states have (on average 2.278481012658228) internal successors, (180), 80 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:34,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:34,320 INFO L93 Difference]: Finished difference Result 293 states and 331 transitions. [2021-12-06 21:55:34,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2021-12-06 21:55:34,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 293 states and 331 transitions. [2021-12-06 21:55:34,321 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:55:34,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 293 states to 292 states and 330 transitions. [2021-12-06 21:55:34,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:55:34,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:55:34,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292 states and 330 transitions. [2021-12-06 21:55:34,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:34,322 INFO L681 BuchiCegarLoop]: Abstraction has 292 states and 330 transitions. [2021-12-06 21:55:34,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states and 330 transitions. [2021-12-06 21:55:34,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 140. [2021-12-06 21:55:34,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.2357142857142858) internal successors, (173), 139 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:34,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 173 transitions. [2021-12-06 21:55:34,324 INFO L704 BuchiCegarLoop]: Abstraction has 140 states and 173 transitions. [2021-12-06 21:55:34,324 INFO L587 BuchiCegarLoop]: Abstraction has 140 states and 173 transitions. [2021-12-06 21:55:34,324 INFO L425 BuchiCegarLoop]: ======== Iteration 99============ [2021-12-06 21:55:34,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 173 transitions. [2021-12-06 21:55:34,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:34,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:34,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:34,325 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:34,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:34,325 INFO L791 eck$LassoCheckResult]: Stem: 72864#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 72865#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 72875#L367 assume !(main_~length~0#1 < 1); 72866#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 72867#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 72868#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72876#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72952#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72877#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72878#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72882#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72951#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72950#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72948#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72946#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72945#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72939#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72938#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72936#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72934#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72933#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72932#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72931#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72930#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72928#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72927#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72926#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72925#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72924#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72923#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72922#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72921#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72920#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72918#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72917#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72916#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72915#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72914#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72913#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72912#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72910#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72906#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72904#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72903#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72901#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72900#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72899#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72898#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72897#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72896#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72895#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72894#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72891#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 72890#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 72888#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72889#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 72887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 73002#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 72873#L370-4 main_~j~0#1 := 0; 72874#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72996#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72880#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72871#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72872#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72995#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72993#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72991#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72990#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72989#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72988#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72987#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72985#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72984#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72983#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72981#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72979#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72977#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72975#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72973#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72971#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72969#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72967#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72966#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72965#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72963#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72962#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72961#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72960#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72959#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72957#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72956#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72954#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 72953#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72869#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 72870#L378-2 [2021-12-06 21:55:34,325 INFO L793 eck$LassoCheckResult]: Loop: 72870#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 72955#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 72870#L378-2 [2021-12-06 21:55:34,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:34,325 INFO L85 PathProgramCache]: Analyzing trace with hash 652757198, now seen corresponding path program 51 times [2021-12-06 21:55:34,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:34,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828074203] [2021-12-06 21:55:34,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:34,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:34,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:35,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 0 proven. 1404 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:35,181 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:55:35,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828074203] [2021-12-06 21:55:35,182 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828074203] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:55:35,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1151622815] [2021-12-06 21:55:35,182 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:55:35,182 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:55:35,182 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:55:35,183 INFO L229 MonitoredProcess]: Starting monitored process 119 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:55:35,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (119)] Waiting until timeout for monitored process [2021-12-06 21:55:36,830 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2021-12-06 21:55:36,830 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:55:36,839 INFO L263 TraceCheckSpWp]: Trace formula consists of 641 conjuncts, 56 conjunts are in the unsatisfiable core [2021-12-06 21:55:36,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:55:37,558 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:55:39,613 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:55:39,613 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:55:39,658 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 529 proven. 875 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:39,658 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:55:42,163 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:55:42,165 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:55:42,232 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 506 proven. 898 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:42,232 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1151622815] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:42,232 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:42,232 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 53, 53] total 131 [2021-12-06 21:55:42,232 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835321617] [2021-12-06 21:55:42,232 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:42,233 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:42,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:42,233 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 97 times [2021-12-06 21:55:42,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:42,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596008399] [2021-12-06 21:55:42,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:42,233 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:42,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:42,237 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:42,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:42,239 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:42,261 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:42,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 132 interpolants. [2021-12-06 21:55:42,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1825, Invalid=15467, Unknown=0, NotChecked=0, Total=17292 [2021-12-06 21:55:42,263 INFO L87 Difference]: Start difference. First operand 140 states and 173 transitions. cyclomatic complexity: 37 Second operand has 132 states, 131 states have (on average 2.2977099236641223) internal successors, (301), 132 states have internal predecessors, (301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:46,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:46,169 INFO L93 Difference]: Finished difference Result 241 states and 275 transitions. [2021-12-06 21:55:46,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2021-12-06 21:55:46,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 241 states and 275 transitions. [2021-12-06 21:55:46,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:46,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 241 states to 188 states and 221 transitions. [2021-12-06 21:55:46,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:55:46,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:55:46,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 188 states and 221 transitions. [2021-12-06 21:55:46,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:46,171 INFO L681 BuchiCegarLoop]: Abstraction has 188 states and 221 transitions. [2021-12-06 21:55:46,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states and 221 transitions. [2021-12-06 21:55:46,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 142. [2021-12-06 21:55:46,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 142 states have (on average 1.232394366197183) internal successors, (175), 141 states have internal predecessors, (175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:46,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 175 transitions. [2021-12-06 21:55:46,172 INFO L704 BuchiCegarLoop]: Abstraction has 142 states and 175 transitions. [2021-12-06 21:55:46,172 INFO L587 BuchiCegarLoop]: Abstraction has 142 states and 175 transitions. [2021-12-06 21:55:46,172 INFO L425 BuchiCegarLoop]: ======== Iteration 100============ [2021-12-06 21:55:46,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142 states and 175 transitions. [2021-12-06 21:55:46,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:46,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:46,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:46,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 24, 24, 23, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:46,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:46,173 INFO L791 eck$LassoCheckResult]: Stem: 74307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 74308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 74318#L367 assume !(main_~length~0#1 < 1); 74309#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 74310#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 74311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74319#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74321#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74447#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74446#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74444#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74443#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74441#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74440#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74439#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74438#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74437#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74436#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74435#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74434#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74433#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74432#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74431#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74430#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74429#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74428#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74427#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74426#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74425#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74422#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74420#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74419#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74416#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74414#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74413#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74412#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74411#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74410#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74409#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74407#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74405#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74404#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74401#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74400#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74399#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74398#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74397#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74396#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74395#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74393#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74392#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74389#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74386#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 74383#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 74381#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 74368#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 74316#L370-4 main_~j~0#1 := 0; 74317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74370#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74323#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74314#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74315#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74367#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74365#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74364#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74363#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74361#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74360#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74359#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74357#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74356#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74355#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74353#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74351#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74350#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74349#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74347#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74345#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74343#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74341#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74339#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74338#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74337#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74336#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74335#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74334#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74333#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74332#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74331#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74330#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74329#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74326#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 74325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74312#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 74313#L378-2 [2021-12-06 21:55:46,173 INFO L793 eck$LassoCheckResult]: Loop: 74313#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 74327#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 74313#L378-2 [2021-12-06 21:55:46,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:46,173 INFO L85 PathProgramCache]: Analyzing trace with hash -2103870068, now seen corresponding path program 43 times [2021-12-06 21:55:46,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:46,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516922814] [2021-12-06 21:55:46,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:46,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:46,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:47,020 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 0 proven. 1404 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:47,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:55:47,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516922814] [2021-12-06 21:55:47,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516922814] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:55:47,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1715150476] [2021-12-06 21:55:47,021 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:55:47,021 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:55:47,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:55:47,022 INFO L229 MonitoredProcess]: Starting monitored process 120 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:55:47,023 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (120)] Waiting until timeout for monitored process [2021-12-06 21:55:47,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:47,218 INFO L263 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 106 conjunts are in the unsatisfiable core [2021-12-06 21:55:47,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:55:48,102 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:55:49,429 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:55:49,431 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 0 proven. 1404 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:49,431 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:55:49,570 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:55:49,571 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:55:49,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 0 proven. 1404 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:49,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1715150476] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:49,729 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:49,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 52] total 106 [2021-12-06 21:55:49,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1500300398] [2021-12-06 21:55:49,730 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:49,730 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:49,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:49,730 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 98 times [2021-12-06 21:55:49,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:49,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234308116] [2021-12-06 21:55:49,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:49,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:49,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:49,734 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:49,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:49,737 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:49,758 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:49,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2021-12-06 21:55:49,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=394, Invalid=10948, Unknown=0, NotChecked=0, Total=11342 [2021-12-06 21:55:49,759 INFO L87 Difference]: Start difference. First operand 142 states and 175 transitions. cyclomatic complexity: 37 Second operand has 107 states, 106 states have (on average 2.4150943396226414) internal successors, (256), 107 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:52,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:52,885 INFO L93 Difference]: Finished difference Result 295 states and 356 transitions. [2021-12-06 21:55:52,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2021-12-06 21:55:52,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 295 states and 356 transitions. [2021-12-06 21:55:52,886 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 50 [2021-12-06 21:55:52,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 295 states to 294 states and 355 transitions. [2021-12-06 21:55:52,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69 [2021-12-06 21:55:52,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69 [2021-12-06 21:55:52,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 294 states and 355 transitions. [2021-12-06 21:55:52,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:52,887 INFO L681 BuchiCegarLoop]: Abstraction has 294 states and 355 transitions. [2021-12-06 21:55:52,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states and 355 transitions. [2021-12-06 21:55:52,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 244. [2021-12-06 21:55:52,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 244 states, 244 states have (on average 1.2418032786885247) internal successors, (303), 243 states have internal predecessors, (303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:52,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 303 transitions. [2021-12-06 21:55:52,890 INFO L704 BuchiCegarLoop]: Abstraction has 244 states and 303 transitions. [2021-12-06 21:55:52,890 INFO L587 BuchiCegarLoop]: Abstraction has 244 states and 303 transitions. [2021-12-06 21:55:52,890 INFO L425 BuchiCegarLoop]: ======== Iteration 101============ [2021-12-06 21:55:52,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 244 states and 303 transitions. [2021-12-06 21:55:52,890 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 48 [2021-12-06 21:55:52,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:52,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:52,891 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 23, 23, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:52,891 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:52,891 INFO L791 eck$LassoCheckResult]: Stem: 75618#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 75619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 75629#L367 assume !(main_~length~0#1 < 1); 75620#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 75621#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 75622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75630#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75632#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75635#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75636#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75709#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75708#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75707#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75706#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75705#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75704#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75703#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75702#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75701#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75700#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75699#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75698#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75697#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75696#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75694#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75693#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75692#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75691#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75690#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75689#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75688#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75685#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75684#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75682#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75680#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75676#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75674#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75673#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75672#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75670#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75668#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75667#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75666#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75665#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75664#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75663#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75662#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75661#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75659#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75658#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75657#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75656#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75655#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75654#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75651#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 75648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75643#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75644#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75645#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75646#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 75765#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 75808#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 75807#L370-4 main_~j~0#1 := 0; 75806#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75805#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75803#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75801#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75799#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75798#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75797#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75796#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75795#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75794#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75793#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75792#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75791#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75790#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75789#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75787#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75785#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75783#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75782#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75781#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75779#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75778#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75777#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75776#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75775#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75774#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75773#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75772#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75771#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75770#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75769#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75768#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75767#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75766#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75712#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75717#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75714#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 75715#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75716#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 75626#L378-2 [2021-12-06 21:55:52,891 INFO L793 eck$LassoCheckResult]: Loop: 75626#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 75710#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 75626#L378-2 [2021-12-06 21:55:52,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:52,891 INFO L85 PathProgramCache]: Analyzing trace with hash 837257485, now seen corresponding path program 52 times [2021-12-06 21:55:52,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:52,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888140472] [2021-12-06 21:55:52,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:52,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:52,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:55:53,773 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 0 proven. 1431 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:53,773 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:55:53,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888140472] [2021-12-06 21:55:53,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888140472] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:55:53,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [758339986] [2021-12-06 21:55:53,773 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:55:53,773 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:55:53,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:55:53,774 INFO L229 MonitoredProcess]: Starting monitored process 121 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:55:53,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (121)] Waiting until timeout for monitored process [2021-12-06 21:55:53,972 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:55:53,972 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:55:53,975 INFO L263 TraceCheckSpWp]: Trace formula consists of 652 conjuncts, 112 conjunts are in the unsatisfiable core [2021-12-06 21:55:53,981 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:55:54,808 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:55:54,946 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:55:54,947 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:55:54,953 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:55:54,953 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:55:55,006 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:55:55,006 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:55:55,012 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:55:55,012 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:55:56,241 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:55:56,243 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 2 proven. 1429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:55:56,243 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:55:56,628 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:55:56,629 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:55:56,766 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 1 proven. 1429 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:55:56,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [758339986] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:55:56,766 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:55:56,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 54, 53] total 108 [2021-12-06 21:55:56,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937387135] [2021-12-06 21:55:56,766 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:55:56,766 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:55:56,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:56,767 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 99 times [2021-12-06 21:55:56,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:56,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967033371] [2021-12-06 21:55:56,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:56,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:56,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:56,771 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:55:56,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:55:56,773 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:55:56,796 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:55:56,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2021-12-06 21:55:56,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=398, Invalid=11374, Unknown=0, NotChecked=0, Total=11772 [2021-12-06 21:55:56,797 INFO L87 Difference]: Start difference. First operand 244 states and 303 transitions. cyclomatic complexity: 65 Second operand has 109 states, 108 states have (on average 2.4074074074074074) internal successors, (260), 109 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:59,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:55:59,835 INFO L93 Difference]: Finished difference Result 286 states and 321 transitions. [2021-12-06 21:55:59,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2021-12-06 21:55:59,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286 states and 321 transitions. [2021-12-06 21:55:59,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:59,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286 states to 284 states and 319 transitions. [2021-12-06 21:55:59,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:55:59,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:55:59,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 319 transitions. [2021-12-06 21:55:59,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:55:59,837 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 319 transitions. [2021-12-06 21:55:59,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 319 transitions. [2021-12-06 21:55:59,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 139. [2021-12-06 21:55:59,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 139 states have (on average 1.2158273381294964) internal successors, (169), 138 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:55:59,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 169 transitions. [2021-12-06 21:55:59,838 INFO L704 BuchiCegarLoop]: Abstraction has 139 states and 169 transitions. [2021-12-06 21:55:59,838 INFO L587 BuchiCegarLoop]: Abstraction has 139 states and 169 transitions. [2021-12-06 21:55:59,838 INFO L425 BuchiCegarLoop]: ======== Iteration 102============ [2021-12-06 21:55:59,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139 states and 169 transitions. [2021-12-06 21:55:59,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:55:59,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:55:59,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:55:59,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:55:59,839 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:55:59,839 INFO L791 eck$LassoCheckResult]: Stem: 77072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 77073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 77083#L367 assume !(main_~length~0#1 < 1); 77074#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 77075#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 77076#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77084#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77090#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77085#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77086#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77087#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77206#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77204#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77203#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77202#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77200#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77198#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77197#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77194#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77191#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77189#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77188#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77186#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77185#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77183#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77182#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77181#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77180#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77179#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77178#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77176#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77175#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77174#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77173#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77172#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77171#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77170#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77168#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77167#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77166#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77165#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77164#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77161#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77160#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 77146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 77139#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 77140#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 77077#L370-4 main_~j~0#1 := 0; 77078#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77141#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77089#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77081#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77082#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77134#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77130#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77129#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77128#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77127#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77126#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77124#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77123#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77122#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77120#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77118#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77116#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77114#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77110#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77108#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77106#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77104#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77102#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77100#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77096#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77095#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77094#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77092#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 77091#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77079#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 77080#L378-2 [2021-12-06 21:55:59,839 INFO L793 eck$LassoCheckResult]: Loop: 77080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 77093#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 77080#L378-2 [2021-12-06 21:55:59,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:55:59,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1110464337, now seen corresponding path program 44 times [2021-12-06 21:55:59,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:55:59,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057075160] [2021-12-06 21:55:59,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:55:59,840 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:55:59,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:00,697 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 553 proven. 899 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:00,698 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:00,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057075160] [2021-12-06 21:56:00,698 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057075160] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:00,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [381307267] [2021-12-06 21:56:00,698 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:56:00,698 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:00,698 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:00,699 INFO L229 MonitoredProcess]: Starting monitored process 122 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:00,699 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (122)] Waiting until timeout for monitored process [2021-12-06 21:56:00,900 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:56:00,900 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:00,903 INFO L263 TraceCheckSpWp]: Trace formula consists of 644 conjuncts, 52 conjunts are in the unsatisfiable core [2021-12-06 21:56:00,904 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:02,288 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 600 proven. 852 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:02,288 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:03,137 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 600 proven. 852 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:03,138 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [381307267] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:03,138 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:03,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53, 53] total 130 [2021-12-06 21:56:03,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767450485] [2021-12-06 21:56:03,138 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:03,138 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:03,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:03,139 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 100 times [2021-12-06 21:56:03,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:03,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671067735] [2021-12-06 21:56:03,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:03,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:03,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:03,143 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:03,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:03,146 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:03,168 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:03,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2021-12-06 21:56:03,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2110, Invalid=14660, Unknown=0, NotChecked=0, Total=16770 [2021-12-06 21:56:03,170 INFO L87 Difference]: Start difference. First operand 139 states and 169 transitions. cyclomatic complexity: 34 Second operand has 130 states, 130 states have (on average 2.3384615384615386) internal successors, (304), 130 states have internal predecessors, (304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:05,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:05,327 INFO L93 Difference]: Finished difference Result 194 states and 225 transitions. [2021-12-06 21:56:05,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2021-12-06 21:56:05,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 225 transitions. [2021-12-06 21:56:05,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:05,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 144 states and 175 transitions. [2021-12-06 21:56:05,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:56:05,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:56:05,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 175 transitions. [2021-12-06 21:56:05,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:05,329 INFO L681 BuchiCegarLoop]: Abstraction has 144 states and 175 transitions. [2021-12-06 21:56:05,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 175 transitions. [2021-12-06 21:56:05,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 139. [2021-12-06 21:56:05,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 139 states have (on average 1.2158273381294964) internal successors, (169), 138 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:05,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 169 transitions. [2021-12-06 21:56:05,330 INFO L704 BuchiCegarLoop]: Abstraction has 139 states and 169 transitions. [2021-12-06 21:56:05,330 INFO L587 BuchiCegarLoop]: Abstraction has 139 states and 169 transitions. [2021-12-06 21:56:05,330 INFO L425 BuchiCegarLoop]: ======== Iteration 103============ [2021-12-06 21:56:05,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139 states and 169 transitions. [2021-12-06 21:56:05,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:05,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:05,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:05,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:05,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:05,331 INFO L791 eck$LassoCheckResult]: Stem: 78406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 78407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 78417#L367 assume !(main_~length~0#1 < 1); 78408#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 78409#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 78410#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78418#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78423#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78420#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78544#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78543#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78542#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78539#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78536#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78532#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78530#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78529#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78528#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78527#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78524#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78522#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78521#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78520#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78518#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78517#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78516#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78515#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78514#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78513#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78512#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78511#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78510#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78509#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78508#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78507#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78506#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78505#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78503#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78502#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78501#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78500#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78499#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78497#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78496#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78495#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78494#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78493#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78492#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78491#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78488#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78487#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78485#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78483#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78482#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78481#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78480#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78479#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 78478#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78470#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 78476#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 78473#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 78472#L370-4 main_~j~0#1 := 0; 78421#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78413#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78466#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78464#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78463#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78462#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78461#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78460#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78458#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78456#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78455#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78454#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78452#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78450#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78448#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78447#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78446#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78445#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78444#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78442#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78440#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78438#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78437#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78436#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78435#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78434#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78432#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78430#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78428#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78427#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78425#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 78424#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78411#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 78412#L378-2 [2021-12-06 21:56:05,331 INFO L793 eck$LassoCheckResult]: Loop: 78412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 78426#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 78412#L378-2 [2021-12-06 21:56:05,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:05,332 INFO L85 PathProgramCache]: Analyzing trace with hash -1462619884, now seen corresponding path program 53 times [2021-12-06 21:56:05,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:05,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905848994] [2021-12-06 21:56:05,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:05,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:05,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:06,265 INFO L134 CoverageAnalysis]: Checked inductivity of 1477 backedges. 0 proven. 1477 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:06,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:06,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905848994] [2021-12-06 21:56:06,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905848994] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:06,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1426137357] [2021-12-06 21:56:06,266 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:56:06,266 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:06,266 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:06,267 INFO L229 MonitoredProcess]: Starting monitored process 123 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:06,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (123)] Waiting until timeout for monitored process [2021-12-06 21:56:07,130 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2021-12-06 21:56:07,130 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:07,137 INFO L263 TraceCheckSpWp]: Trace formula consists of 655 conjuncts, 107 conjunts are in the unsatisfiable core [2021-12-06 21:56:07,139 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:07,271 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:56:07,385 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:56:07,385 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:56:07,398 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:56:07,398 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:56:08,426 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:56:08,427 INFO L134 CoverageAnalysis]: Checked inductivity of 1477 backedges. 0 proven. 1477 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:08,427 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:08,739 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:56:08,740 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:56:08,881 INFO L134 CoverageAnalysis]: Checked inductivity of 1477 backedges. 0 proven. 1477 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:08,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1426137357] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:08,881 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:08,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 55, 55] total 84 [2021-12-06 21:56:08,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306197128] [2021-12-06 21:56:08,881 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:08,882 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:08,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:08,882 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 101 times [2021-12-06 21:56:08,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:08,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517846629] [2021-12-06 21:56:08,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:08,882 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:08,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:08,886 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:08,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:08,889 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:08,911 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:08,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2021-12-06 21:56:08,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=6904, Unknown=0, NotChecked=0, Total=7140 [2021-12-06 21:56:08,912 INFO L87 Difference]: Start difference. First operand 139 states and 169 transitions. cyclomatic complexity: 34 Second operand has 85 states, 84 states have (on average 2.25) internal successors, (189), 85 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:11,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:11,041 INFO L93 Difference]: Finished difference Result 250 states and 287 transitions. [2021-12-06 21:56:11,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2021-12-06 21:56:11,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 250 states and 287 transitions. [2021-12-06 21:56:11,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:56:11,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 250 states to 249 states and 286 transitions. [2021-12-06 21:56:11,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-12-06 21:56:11,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-12-06 21:56:11,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 286 transitions. [2021-12-06 21:56:11,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:11,043 INFO L681 BuchiCegarLoop]: Abstraction has 249 states and 286 transitions. [2021-12-06 21:56:11,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 286 transitions. [2021-12-06 21:56:11,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 145. [2021-12-06 21:56:11,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145 states, 145 states have (on average 1.2344827586206897) internal successors, (179), 144 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:11,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 179 transitions. [2021-12-06 21:56:11,044 INFO L704 BuchiCegarLoop]: Abstraction has 145 states and 179 transitions. [2021-12-06 21:56:11,044 INFO L587 BuchiCegarLoop]: Abstraction has 145 states and 179 transitions. [2021-12-06 21:56:11,044 INFO L425 BuchiCegarLoop]: ======== Iteration 104============ [2021-12-06 21:56:11,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 145 states and 179 transitions. [2021-12-06 21:56:11,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:11,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:11,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:11,045 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:11,045 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:11,045 INFO L791 eck$LassoCheckResult]: Stem: 79659#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 79660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 79670#L367 assume !(main_~length~0#1 < 1); 79661#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 79662#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 79663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79671#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79673#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79802#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79801#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79800#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79799#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79798#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79797#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79795#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79794#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79792#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79791#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79790#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79789#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79788#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79787#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79786#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79785#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79784#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79783#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79781#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79780#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79779#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79778#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79777#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79776#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79775#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79774#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79773#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79772#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79771#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79770#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79769#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79768#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79767#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79766#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79765#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79764#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79763#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79762#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79761#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79760#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79759#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79758#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79757#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79756#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79755#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79754#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79753#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79752#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79751#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79750#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79749#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79747#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79745#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79744#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79741#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79738#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 79737#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79736#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 79734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 79733#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 79664#L370-4 main_~j~0#1 := 0; 79665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79668#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79675#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79724#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79723#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79721#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79717#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79715#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79713#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79711#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79710#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79709#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79705#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79703#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79701#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79699#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79697#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79696#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79695#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79694#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79693#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79692#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79691#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79689#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79688#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79687#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79685#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79684#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79683#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79680#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 79679#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79666#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 79667#L378-2 [2021-12-06 21:56:11,046 INFO L793 eck$LassoCheckResult]: Loop: 79667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 79681#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 79667#L378-2 [2021-12-06 21:56:11,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:11,046 INFO L85 PathProgramCache]: Analyzing trace with hash -1123399463, now seen corresponding path program 54 times [2021-12-06 21:56:11,046 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:11,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286314487] [2021-12-06 21:56:11,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:11,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:11,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:11,941 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 0 proven. 1525 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:11,942 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:11,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286314487] [2021-12-06 21:56:11,942 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286314487] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:11,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1175924434] [2021-12-06 21:56:11,942 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:56:11,942 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:11,942 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:11,943 INFO L229 MonitoredProcess]: Starting monitored process 124 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:11,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (124)] Waiting until timeout for monitored process [2021-12-06 21:56:17,138 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2021-12-06 21:56:17,138 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:17,152 INFO L263 TraceCheckSpWp]: Trace formula consists of 666 conjuncts, 58 conjunts are in the unsatisfiable core [2021-12-06 21:56:17,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:17,927 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:56:20,170 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:56:20,170 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:56:20,216 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 576 proven. 949 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:20,216 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:22,899 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:56:22,901 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:56:22,977 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 552 proven. 973 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:22,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1175924434] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:22,977 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:22,978 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 55, 55] total 136 [2021-12-06 21:56:22,978 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706139860] [2021-12-06 21:56:22,978 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:22,978 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:22,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:22,979 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 102 times [2021-12-06 21:56:22,979 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:22,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520148300] [2021-12-06 21:56:22,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:22,979 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:22,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:22,985 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:22,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:22,989 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:23,013 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:23,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 137 interpolants. [2021-12-06 21:56:23,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1962, Invalid=16670, Unknown=0, NotChecked=0, Total=18632 [2021-12-06 21:56:23,014 INFO L87 Difference]: Start difference. First operand 145 states and 179 transitions. cyclomatic complexity: 38 Second operand has 137 states, 136 states have (on average 2.301470588235294) internal successors, (313), 137 states have internal predecessors, (313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:27,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:27,197 INFO L93 Difference]: Finished difference Result 250 states and 285 transitions. [2021-12-06 21:56:27,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2021-12-06 21:56:27,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 250 states and 285 transitions. [2021-12-06 21:56:27,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:27,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 250 states to 195 states and 229 transitions. [2021-12-06 21:56:27,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:56:27,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:56:27,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 229 transitions. [2021-12-06 21:56:27,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:27,199 INFO L681 BuchiCegarLoop]: Abstraction has 195 states and 229 transitions. [2021-12-06 21:56:27,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 229 transitions. [2021-12-06 21:56:27,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 147. [2021-12-06 21:56:27,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.2312925170068028) internal successors, (181), 146 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:27,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 181 transitions. [2021-12-06 21:56:27,200 INFO L704 BuchiCegarLoop]: Abstraction has 147 states and 181 transitions. [2021-12-06 21:56:27,200 INFO L587 BuchiCegarLoop]: Abstraction has 147 states and 181 transitions. [2021-12-06 21:56:27,200 INFO L425 BuchiCegarLoop]: ======== Iteration 105============ [2021-12-06 21:56:27,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 181 transitions. [2021-12-06 21:56:27,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:27,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:27,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:27,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 25, 25, 24, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:27,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:27,201 INFO L791 eck$LassoCheckResult]: Stem: 81158#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 81159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 81169#L367 assume !(main_~length~0#1 < 1); 81160#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 81161#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 81162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81170#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81173#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81171#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81172#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81302#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81300#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81298#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81297#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81296#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81294#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81293#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81292#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81291#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81290#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81288#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81287#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81286#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81285#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81284#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81282#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81281#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81279#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81278#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81276#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81275#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81274#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81272#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81270#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81269#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81267#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81266#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81265#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81264#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81263#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81262#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81261#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81260#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81259#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81258#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81257#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81256#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81255#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81254#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81253#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81252#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81251#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81250#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81249#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81248#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81245#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81244#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81243#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81242#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81241#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81240#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81239#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81238#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81237#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 81235#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 81236#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 81225#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 81224#L370-4 main_~j~0#1 := 0; 81174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81167#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81168#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81175#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81223#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81222#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81221#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81220#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81219#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81218#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81217#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81216#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81215#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81214#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81213#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81212#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81211#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81210#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81209#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81208#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81207#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81206#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81205#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81204#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81203#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81202#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81201#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81200#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81198#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81197#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81196#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81195#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81194#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81193#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81192#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81191#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81190#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81189#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81188#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81187#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81186#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81184#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81183#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81182#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81181#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81180#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 81179#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81165#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 81166#L378-2 [2021-12-06 21:56:27,201 INFO L793 eck$LassoCheckResult]: Loop: 81166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 81178#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 81166#L378-2 [2021-12-06 21:56:27,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:27,201 INFO L85 PathProgramCache]: Analyzing trace with hash -247380457, now seen corresponding path program 45 times [2021-12-06 21:56:27,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:27,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324770200] [2021-12-06 21:56:27,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:27,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:27,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:28,143 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 0 proven. 1525 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:28,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:28,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324770200] [2021-12-06 21:56:28,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324770200] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:28,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1079613396] [2021-12-06 21:56:28,144 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:56:28,144 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:28,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:28,145 INFO L229 MonitoredProcess]: Starting monitored process 125 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:28,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (125)] Waiting until timeout for monitored process [2021-12-06 21:56:31,145 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2021-12-06 21:56:31,145 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:31,156 INFO L263 TraceCheckSpWp]: Trace formula consists of 658 conjuncts, 59 conjunts are in the unsatisfiable core [2021-12-06 21:56:31,157 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:31,929 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:56:34,196 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:56:34,196 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:56:34,198 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 576 proven. 949 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:34,198 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:37,054 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:56:37,056 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:56:37,121 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 552 proven. 973 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:37,121 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1079613396] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:37,121 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:37,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 56, 56] total 138 [2021-12-06 21:56:37,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74177187] [2021-12-06 21:56:37,122 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:37,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:37,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:37,122 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 103 times [2021-12-06 21:56:37,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:37,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875162452] [2021-12-06 21:56:37,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:37,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:37,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:37,126 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:37,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:37,129 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:37,156 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:37,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 139 interpolants. [2021-12-06 21:56:37,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2024, Invalid=17158, Unknown=0, NotChecked=0, Total=19182 [2021-12-06 21:56:37,157 INFO L87 Difference]: Start difference. First operand 147 states and 181 transitions. cyclomatic complexity: 38 Second operand has 139 states, 138 states have (on average 2.2681159420289854) internal successors, (313), 139 states have internal predecessors, (313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:42,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:42,691 INFO L93 Difference]: Finished difference Result 213 states and 250 transitions. [2021-12-06 21:56:42,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2021-12-06 21:56:42,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 213 states and 250 transitions. [2021-12-06 21:56:42,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:42,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 213 states to 158 states and 194 transitions. [2021-12-06 21:56:42,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:56:42,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:56:42,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 194 transitions. [2021-12-06 21:56:42,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:42,693 INFO L681 BuchiCegarLoop]: Abstraction has 158 states and 194 transitions. [2021-12-06 21:56:42,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 194 transitions. [2021-12-06 21:56:42,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 155. [2021-12-06 21:56:42,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155 states, 155 states have (on average 1.232258064516129) internal successors, (191), 154 states have internal predecessors, (191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:42,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 191 transitions. [2021-12-06 21:56:42,694 INFO L704 BuchiCegarLoop]: Abstraction has 155 states and 191 transitions. [2021-12-06 21:56:42,694 INFO L587 BuchiCegarLoop]: Abstraction has 155 states and 191 transitions. [2021-12-06 21:56:42,694 INFO L425 BuchiCegarLoop]: ======== Iteration 106============ [2021-12-06 21:56:42,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155 states and 191 transitions. [2021-12-06 21:56:42,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:42,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:42,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:42,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:42,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:42,695 INFO L791 eck$LassoCheckResult]: Stem: 82694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 82695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 82705#L367 assume !(main_~length~0#1 < 1); 82696#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 82697#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 82698#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82706#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82848#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82840#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82837#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82834#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82831#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82828#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82827#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82825#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82822#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82819#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82815#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82814#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82813#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82812#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82811#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82810#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82809#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82808#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82807#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82806#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82805#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82804#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82802#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82801#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82800#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82799#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82798#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82797#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82795#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82794#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82792#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82791#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82790#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82789#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82788#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82787#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82786#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82785#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82784#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82782#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82783#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82707#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82708#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82774#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 82772#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 82770#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 82761#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 82703#L370-4 main_~j~0#1 := 0; 82704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82701#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82710#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82758#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82757#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82756#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82755#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82754#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82753#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82752#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82751#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82750#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82749#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82747#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82746#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82745#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82744#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82743#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82742#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82741#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82740#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82739#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82738#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82737#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82736#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82735#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82734#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82733#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82732#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82731#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82730#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82729#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82728#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82727#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82726#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82725#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82724#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82723#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82721#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82717#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82714#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 82713#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82699#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 82700#L378-2 [2021-12-06 21:56:42,695 INFO L793 eck$LassoCheckResult]: Loop: 82700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 82715#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 82700#L378-2 [2021-12-06 21:56:42,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:42,695 INFO L85 PathProgramCache]: Analyzing trace with hash -449204391, now seen corresponding path program 55 times [2021-12-06 21:56:42,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:42,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834377099] [2021-12-06 21:56:42,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:42,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:42,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:43,614 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 0 proven. 1525 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:43,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:43,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834377099] [2021-12-06 21:56:43,620 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834377099] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:43,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2127943540] [2021-12-06 21:56:43,620 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:56:43,620 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:43,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:43,621 INFO L229 MonitoredProcess]: Starting monitored process 126 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:43,622 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (126)] Waiting until timeout for monitored process [2021-12-06 21:56:43,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:43,826 INFO L263 TraceCheckSpWp]: Trace formula consists of 666 conjuncts, 110 conjunts are in the unsatisfiable core [2021-12-06 21:56:43,827 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:44,776 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:56:46,268 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:56:46,270 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 0 proven. 1525 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:46,270 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:46,425 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:56:46,426 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:56:46,574 INFO L134 CoverageAnalysis]: Checked inductivity of 1525 backedges. 0 proven. 1525 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:46,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2127943540] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:46,575 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:46,575 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 54] total 110 [2021-12-06 21:56:46,575 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215554720] [2021-12-06 21:56:46,575 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:46,575 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:46,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:46,575 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 104 times [2021-12-06 21:56:46,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:46,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220017822] [2021-12-06 21:56:46,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:46,576 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:46,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:46,581 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:46,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:46,583 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:46,604 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:46,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2021-12-06 21:56:46,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=409, Invalid=11801, Unknown=0, NotChecked=0, Total=12210 [2021-12-06 21:56:46,605 INFO L87 Difference]: Start difference. First operand 155 states and 191 transitions. cyclomatic complexity: 40 Second operand has 111 states, 110 states have (on average 2.418181818181818) internal successors, (266), 111 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:50,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:50,389 INFO L93 Difference]: Finished difference Result 314 states and 379 transitions. [2021-12-06 21:56:50,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2021-12-06 21:56:50,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 379 transitions. [2021-12-06 21:56:50,390 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 52 [2021-12-06 21:56:50,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 313 states and 378 transitions. [2021-12-06 21:56:50,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71 [2021-12-06 21:56:50,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71 [2021-12-06 21:56:50,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 313 states and 378 transitions. [2021-12-06 21:56:50,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:50,391 INFO L681 BuchiCegarLoop]: Abstraction has 313 states and 378 transitions. [2021-12-06 21:56:50,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states and 378 transitions. [2021-12-06 21:56:50,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 261. [2021-12-06 21:56:50,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 261 states, 261 states have (on average 1.2413793103448276) internal successors, (324), 260 states have internal predecessors, (324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:50,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 261 states to 261 states and 324 transitions. [2021-12-06 21:56:50,393 INFO L704 BuchiCegarLoop]: Abstraction has 261 states and 324 transitions. [2021-12-06 21:56:50,393 INFO L587 BuchiCegarLoop]: Abstraction has 261 states and 324 transitions. [2021-12-06 21:56:50,393 INFO L425 BuchiCegarLoop]: ======== Iteration 107============ [2021-12-06 21:56:50,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 261 states and 324 transitions. [2021-12-06 21:56:50,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 50 [2021-12-06 21:56:50,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:50,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:50,394 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 24, 23, 23, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:50,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:50,394 INFO L791 eck$LassoCheckResult]: Stem: 84071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 84072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 84082#L367 assume !(main_~length~0#1 < 1); 84073#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 84074#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 84075#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84083#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84172#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84171#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84170#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84168#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84167#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84166#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84165#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84164#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84161#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84160#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84140#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84139#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84135#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84134#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84133#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84132#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84131#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84130#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84128#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84127#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84125#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84123#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84122#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84121#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84119#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84118#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84117#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84116#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84115#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84114#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84113#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84112#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84111#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84110#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84109#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84107#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84106#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84104#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84102#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 84099#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84098#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84096#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84230#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 84232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 84278#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 84277#L370-4 main_~j~0#1 := 0; 84276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84273#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84272#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84271#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84270#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84268#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84267#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84266#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84264#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84262#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84260#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84258#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84257#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84256#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84255#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84254#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84253#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84252#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84250#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84248#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84247#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84246#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84245#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84244#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84242#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84240#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84238#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84237#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84236#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84235#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84234#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84233#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84177#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84180#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84178#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 84179#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84181#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 84077#L378-2 [2021-12-06 21:56:50,394 INFO L793 eck$LassoCheckResult]: Loop: 84077#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 84174#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 84077#L378-2 [2021-12-06 21:56:50,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:50,394 INFO L85 PathProgramCache]: Analyzing trace with hash 340471690, now seen corresponding path program 56 times [2021-12-06 21:56:50,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:50,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432971884] [2021-12-06 21:56:50,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:50,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:50,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:51,308 INFO L134 CoverageAnalysis]: Checked inductivity of 1553 backedges. 0 proven. 1553 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:51,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:51,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432971884] [2021-12-06 21:56:51,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432971884] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:51,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [305124480] [2021-12-06 21:56:51,309 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:56:51,309 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:51,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:51,310 INFO L229 MonitoredProcess]: Starting monitored process 127 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:51,311 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (127)] Waiting until timeout for monitored process [2021-12-06 21:56:51,528 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:56:51,528 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:51,531 INFO L263 TraceCheckSpWp]: Trace formula consists of 685 conjuncts, 112 conjunts are in the unsatisfiable core [2021-12-06 21:56:51,533 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:56:51,670 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:56:51,748 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:56:51,748 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:56:51,755 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:56:51,756 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:56:51,799 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:56:51,799 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:56:51,808 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:56:51,808 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:56:52,734 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:56:52,736 INFO L134 CoverageAnalysis]: Checked inductivity of 1553 backedges. 2 proven. 1551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:52,736 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:56:53,081 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:56:53,082 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:56:53,228 INFO L134 CoverageAnalysis]: Checked inductivity of 1553 backedges. 1 proven. 1551 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:56:53,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [305124480] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:56:53,228 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:56:53,229 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55] total 83 [2021-12-06 21:56:53,229 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524494499] [2021-12-06 21:56:53,229 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:56:53,229 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:56:53,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:53,229 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 105 times [2021-12-06 21:56:53,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:53,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856538771] [2021-12-06 21:56:53,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:53,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:53,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:53,234 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:56:53,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:56:53,236 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:56:53,259 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:56:53,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2021-12-06 21:56:53,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=234, Invalid=6738, Unknown=0, NotChecked=0, Total=6972 [2021-12-06 21:56:53,260 INFO L87 Difference]: Start difference. First operand 261 states and 324 transitions. cyclomatic complexity: 69 Second operand has 84 states, 83 states have (on average 2.3132530120481927) internal successors, (192), 84 states have internal predecessors, (192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:55,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:56:55,930 INFO L93 Difference]: Finished difference Result 305 states and 343 transitions. [2021-12-06 21:56:55,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2021-12-06 21:56:55,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 305 states and 343 transitions. [2021-12-06 21:56:55,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:55,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 305 states to 303 states and 341 transitions. [2021-12-06 21:56:55,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:56:55,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:56:55,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 341 transitions. [2021-12-06 21:56:55,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:56:55,932 INFO L681 BuchiCegarLoop]: Abstraction has 303 states and 341 transitions. [2021-12-06 21:56:55,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 341 transitions. [2021-12-06 21:56:55,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 150. [2021-12-06 21:56:55,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.22) internal successors, (183), 149 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:56:55,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 183 transitions. [2021-12-06 21:56:55,933 INFO L704 BuchiCegarLoop]: Abstraction has 150 states and 183 transitions. [2021-12-06 21:56:55,934 INFO L587 BuchiCegarLoop]: Abstraction has 150 states and 183 transitions. [2021-12-06 21:56:55,934 INFO L425 BuchiCegarLoop]: ======== Iteration 108============ [2021-12-06 21:56:55,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 183 transitions. [2021-12-06 21:56:55,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:56:55,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:56:55,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:56:55,935 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 25, 25, 25, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:56:55,935 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:56:55,935 INFO L791 eck$LassoCheckResult]: Stem: 85566#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 85567#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 85577#L367 assume !(main_~length~0#1 < 1); 85568#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 85569#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 85570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85578#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85579#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85580#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85583#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85714#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85713#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85712#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85711#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85710#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85708#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85707#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85705#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85704#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85703#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85702#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85701#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85699#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85697#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85696#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85695#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85693#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85692#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85691#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85690#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85689#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85688#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85687#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85686#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85685#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85684#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85682#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85681#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85679#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85678#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85677#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85676#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85675#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85673#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85672#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85671#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85670#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85669#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85666#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85665#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85664#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85663#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85662#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85660#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85658#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85657#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85656#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85655#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85654#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85646#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 85642#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 85635#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 85591#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 85575#L370-4 main_~j~0#1 := 0; 85576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85573#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85574#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85582#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85634#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85633#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85632#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85631#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85629#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85627#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85626#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85625#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85623#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85622#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85621#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85620#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85619#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85618#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85617#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85616#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85615#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85614#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85613#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85612#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85611#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85609#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85608#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85607#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85606#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85605#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85603#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85602#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85601#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85600#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85599#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85598#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85597#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85595#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85594#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85593#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85589#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85588#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85586#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 85585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85571#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 85572#L378-2 [2021-12-06 21:56:55,935 INFO L793 eck$LassoCheckResult]: Loop: 85572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 85587#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 85572#L378-2 [2021-12-06 21:56:55,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:56:55,935 INFO L85 PathProgramCache]: Analyzing trace with hash 2106280414, now seen corresponding path program 57 times [2021-12-06 21:56:55,935 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:56:55,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896511116] [2021-12-06 21:56:55,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:56:55,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:56:55,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:56:56,836 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 601 proven. 974 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:56:56,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:56:56,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896511116] [2021-12-06 21:56:56,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1896511116] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:56:56,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1320957565] [2021-12-06 21:56:56,836 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:56:56,836 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:56:56,837 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:56:56,838 INFO L229 MonitoredProcess]: Starting monitored process 128 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:56:56,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (128)] Waiting until timeout for monitored process [2021-12-06 21:56:58,579 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2021-12-06 21:56:58,579 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:56:58,588 INFO L263 TraceCheckSpWp]: Trace formula consists of 677 conjuncts, 54 conjunts are in the unsatisfiable core [2021-12-06 21:56:58,589 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:00,062 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 650 proven. 925 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:00,062 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:01,001 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 650 proven. 925 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:01,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1320957565] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:01,001 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:01,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 55, 55] total 135 [2021-12-06 21:57:01,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290584889] [2021-12-06 21:57:01,001 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:01,002 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:01,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:01,002 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 106 times [2021-12-06 21:57:01,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:01,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307301358] [2021-12-06 21:57:01,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:01,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:01,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:01,006 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:01,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:01,009 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:01,032 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:01,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 135 interpolants. [2021-12-06 21:57:01,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2272, Invalid=15818, Unknown=0, NotChecked=0, Total=18090 [2021-12-06 21:57:01,033 INFO L87 Difference]: Start difference. First operand 150 states and 183 transitions. cyclomatic complexity: 37 Second operand has 135 states, 135 states have (on average 2.3407407407407406) internal successors, (316), 135 states have internal predecessors, (316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:03,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:03,261 INFO L93 Difference]: Finished difference Result 207 states and 241 transitions. [2021-12-06 21:57:03,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2021-12-06 21:57:03,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 241 transitions. [2021-12-06 21:57:03,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:03,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 155 states and 189 transitions. [2021-12-06 21:57:03,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:57:03,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:57:03,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155 states and 189 transitions. [2021-12-06 21:57:03,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:03,262 INFO L681 BuchiCegarLoop]: Abstraction has 155 states and 189 transitions. [2021-12-06 21:57:03,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states and 189 transitions. [2021-12-06 21:57:03,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 144. [2021-12-06 21:57:03,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144 states, 144 states have (on average 1.2152777777777777) internal successors, (175), 143 states have internal predecessors, (175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:03,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 175 transitions. [2021-12-06 21:57:03,263 INFO L704 BuchiCegarLoop]: Abstraction has 144 states and 175 transitions. [2021-12-06 21:57:03,263 INFO L587 BuchiCegarLoop]: Abstraction has 144 states and 175 transitions. [2021-12-06 21:57:03,263 INFO L425 BuchiCegarLoop]: ======== Iteration 109============ [2021-12-06 21:57:03,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144 states and 175 transitions. [2021-12-06 21:57:03,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:03,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:03,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:03,264 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:03,264 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:03,264 INFO L791 eck$LassoCheckResult]: Stem: 86963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 86964#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 86974#L367 assume !(main_~length~0#1 < 1); 86965#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 86966#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 86967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 86975#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 86978#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 86976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 86977#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87106#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87104#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87103#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87102#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87101#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87100#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87099#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87098#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87097#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87096#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87095#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87094#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87093#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87092#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87091#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87089#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87086#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87085#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87084#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87083#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87082#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87081#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87080#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87079#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87078#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87077#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87076#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87075#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87074#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87073#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87072#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87071#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87070#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87069#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87068#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87067#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87066#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87065#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87064#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87063#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87062#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87061#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87060#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87059#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87057#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87056#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87055#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87054#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87053#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87052#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87051#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87050#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87049#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87048#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87047#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87044#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87043#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87042#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87041#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87040#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87038#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 87037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 87036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87034#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 87030#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 86980#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 86968#L370-4 main_~j~0#1 := 0; 86969#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86979#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87029#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87028#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87027#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87026#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87025#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87024#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87023#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87022#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87020#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87019#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87018#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87016#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87014#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87012#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87011#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87010#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87008#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87006#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87004#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87002#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 87001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 87000#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86999#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86998#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86996#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86994#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86992#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86990#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86988#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86986#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86985#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86984#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 86983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86970#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 86971#L378-2 [2021-12-06 21:57:03,264 INFO L793 eck$LassoCheckResult]: Loop: 86971#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 86982#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 86971#L378-2 [2021-12-06 21:57:03,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:03,265 INFO L85 PathProgramCache]: Analyzing trace with hash 1619303507, now seen corresponding path program 58 times [2021-12-06 21:57:03,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:03,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058474471] [2021-12-06 21:57:03,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:03,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:03,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:04,236 INFO L134 CoverageAnalysis]: Checked inductivity of 1601 backedges. 0 proven. 1601 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:04,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:04,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058474471] [2021-12-06 21:57:04,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058474471] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:04,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1195142572] [2021-12-06 21:57:04,237 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:57:04,237 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:04,237 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:04,238 INFO L229 MonitoredProcess]: Starting monitored process 129 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:04,238 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (129)] Waiting until timeout for monitored process [2021-12-06 21:57:04,454 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:57:04,454 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:57:04,458 INFO L263 TraceCheckSpWp]: Trace formula consists of 680 conjuncts, 115 conjunts are in the unsatisfiable core [2021-12-06 21:57:04,460 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:05,427 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:57:05,574 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:57:05,575 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:57:05,581 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:57:05,581 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:57:07,000 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:57:07,002 INFO L134 CoverageAnalysis]: Checked inductivity of 1601 backedges. 0 proven. 1601 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:07,002 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:07,286 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:57:07,287 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:57:07,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1601 backedges. 0 proven. 1601 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:07,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1195142572] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:07,446 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:07,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 57, 56] total 114 [2021-12-06 21:57:07,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611122522] [2021-12-06 21:57:07,446 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:07,446 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:07,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:07,447 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 107 times [2021-12-06 21:57:07,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:07,447 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427291002] [2021-12-06 21:57:07,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:07,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:07,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:07,451 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:07,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:07,454 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:07,476 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:07,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 115 interpolants. [2021-12-06 21:57:07,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=409, Invalid=12701, Unknown=0, NotChecked=0, Total=13110 [2021-12-06 21:57:07,477 INFO L87 Difference]: Start difference. First operand 144 states and 175 transitions. cyclomatic complexity: 35 Second operand has 115 states, 114 states have (on average 2.3859649122807016) internal successors, (272), 115 states have internal predecessors, (272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:11,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:11,177 INFO L93 Difference]: Finished difference Result 194 states and 225 transitions. [2021-12-06 21:57:11,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2021-12-06 21:57:11,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 225 transitions. [2021-12-06 21:57:11,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:11,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 193 states and 224 transitions. [2021-12-06 21:57:11,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:57:11,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:57:11,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 224 transitions. [2021-12-06 21:57:11,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:11,178 INFO L681 BuchiCegarLoop]: Abstraction has 193 states and 224 transitions. [2021-12-06 21:57:11,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 224 transitions. [2021-12-06 21:57:11,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 139. [2021-12-06 21:57:11,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 139 states have (on average 1.20863309352518) internal successors, (168), 138 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:11,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 168 transitions. [2021-12-06 21:57:11,179 INFO L704 BuchiCegarLoop]: Abstraction has 139 states and 168 transitions. [2021-12-06 21:57:11,179 INFO L587 BuchiCegarLoop]: Abstraction has 139 states and 168 transitions. [2021-12-06 21:57:11,179 INFO L425 BuchiCegarLoop]: ======== Iteration 110============ [2021-12-06 21:57:11,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139 states and 168 transitions. [2021-12-06 21:57:11,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:11,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:11,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:11,180 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 26, 26, 25, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:11,180 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:11,180 INFO L791 eck$LassoCheckResult]: Stem: 88277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 88278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 88288#L367 assume !(main_~length~0#1 < 1); 88279#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 88280#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 88281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88289#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88374#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88290#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88291#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88292#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88295#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88373#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88372#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88371#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88370#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88369#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88368#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88367#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88366#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88365#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88364#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88361#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88360#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88359#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88358#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88357#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88356#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88355#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88354#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88352#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88351#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88350#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88349#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88348#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88347#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88346#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88343#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88337#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88334#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88331#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88325#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88322#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88319#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88318#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88317#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88316#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88313#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88312#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88310#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88309#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88308#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88307#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 88297#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 88302#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 88296#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 88282#L370-4 main_~j~0#1 := 0; 88283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88293#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88286#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88287#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88415#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88413#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88411#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88409#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88408#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88407#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88405#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88403#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88402#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88401#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88400#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88399#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88398#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88397#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88396#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88395#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88394#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88393#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88392#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88391#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88390#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88389#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88388#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88387#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88386#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88385#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88384#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88383#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88382#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88381#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88380#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88379#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88378#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88377#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88376#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88375#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88304#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88303#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88301#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88299#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 88298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88284#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 88285#L378-2 [2021-12-06 21:57:11,180 INFO L793 eck$LassoCheckResult]: Loop: 88285#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 88300#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 88285#L378-2 [2021-12-06 21:57:11,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:11,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1413187094, now seen corresponding path program 46 times [2021-12-06 21:57:11,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:11,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60144082] [2021-12-06 21:57:11,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:11,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:11,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:12,176 INFO L134 CoverageAnalysis]: Checked inductivity of 1651 backedges. 0 proven. 1651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:12,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:12,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60144082] [2021-12-06 21:57:12,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60144082] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:12,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [451032387] [2021-12-06 21:57:12,176 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:57:12,176 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:12,176 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:12,177 INFO L229 MonitoredProcess]: Starting monitored process 130 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:12,178 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (130)] Waiting until timeout for monitored process [2021-12-06 21:57:12,403 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:57:12,403 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:57:12,406 INFO L263 TraceCheckSpWp]: Trace formula consists of 683 conjuncts, 114 conjunts are in the unsatisfiable core [2021-12-06 21:57:12,408 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:13,459 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:57:15,021 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:57:15,022 INFO L134 CoverageAnalysis]: Checked inductivity of 1651 backedges. 0 proven. 1651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:15,023 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:15,185 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:57:15,186 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:57:15,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1651 backedges. 0 proven. 1651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:15,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [451032387] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:15,338 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:15,338 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 56] total 114 [2021-12-06 21:57:15,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762266232] [2021-12-06 21:57:15,338 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:15,338 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:15,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:15,339 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 108 times [2021-12-06 21:57:15,339 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:15,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588438222] [2021-12-06 21:57:15,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:15,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:15,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:15,343 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:15,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:15,346 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:15,368 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:15,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 115 interpolants. [2021-12-06 21:57:15,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=424, Invalid=12686, Unknown=0, NotChecked=0, Total=13110 [2021-12-06 21:57:15,369 INFO L87 Difference]: Start difference. First operand 139 states and 168 transitions. cyclomatic complexity: 32 Second operand has 115 states, 114 states have (on average 2.4210526315789473) internal successors, (276), 115 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:18,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:18,543 INFO L93 Difference]: Finished difference Result 203 states and 237 transitions. [2021-12-06 21:57:18,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2021-12-06 21:57:18,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203 states and 237 transitions. [2021-12-06 21:57:18,544 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:57:18,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203 states to 202 states and 236 transitions. [2021-12-06 21:57:18,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:57:18,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:57:18,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202 states and 236 transitions. [2021-12-06 21:57:18,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:18,545 INFO L681 BuchiCegarLoop]: Abstraction has 202 states and 236 transitions. [2021-12-06 21:57:18,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states and 236 transitions. [2021-12-06 21:57:18,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 147. [2021-12-06 21:57:18,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.217687074829932) internal successors, (179), 146 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:18,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 179 transitions. [2021-12-06 21:57:18,546 INFO L704 BuchiCegarLoop]: Abstraction has 147 states and 179 transitions. [2021-12-06 21:57:18,546 INFO L587 BuchiCegarLoop]: Abstraction has 147 states and 179 transitions. [2021-12-06 21:57:18,546 INFO L425 BuchiCegarLoop]: ======== Iteration 111============ [2021-12-06 21:57:18,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 179 transitions. [2021-12-06 21:57:18,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:18,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:18,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:18,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:18,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:18,547 INFO L791 eck$LassoCheckResult]: Stem: 89561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 89562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 89572#L367 assume !(main_~length~0#1 < 1); 89563#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 89564#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 89565#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89573#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89574#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89575#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89579#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89651#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89643#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89640#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89637#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89631#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89628#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89627#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89625#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89622#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89619#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89614#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89613#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89612#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89611#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89610#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89609#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89607#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89606#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89605#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89604#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89603#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89601#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89600#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89599#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89598#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89596#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89595#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89594#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89593#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89592#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89590#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89589#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89586#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 89583#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 89582#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 89580#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 89566#L370-4 main_~j~0#1 := 0; 89567#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89703#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89570#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89702#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89700#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89699#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89698#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89697#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89696#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89695#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89694#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89692#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89691#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89690#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89688#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89686#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89684#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89683#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89682#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89680#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89679#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89678#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89677#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89676#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89675#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89674#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89672#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89668#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89666#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89660#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89659#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89658#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89657#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89656#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 89655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89568#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 89569#L378-2 [2021-12-06 21:57:18,547 INFO L793 eck$LassoCheckResult]: Loop: 89569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 89654#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 89569#L378-2 [2021-12-06 21:57:18,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:18,547 INFO L85 PathProgramCache]: Analyzing trace with hash 863135067, now seen corresponding path program 47 times [2021-12-06 21:57:18,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:18,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295940379] [2021-12-06 21:57:18,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:18,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:18,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:19,647 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 651 proven. 1052 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:19,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:19,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295940379] [2021-12-06 21:57:19,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295940379] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:19,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [62561222] [2021-12-06 21:57:19,648 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:57:19,648 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:19,648 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:19,649 INFO L229 MonitoredProcess]: Starting monitored process 131 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:19,650 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (131)] Waiting until timeout for monitored process [2021-12-06 21:57:22,058 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2021-12-06 21:57:22,058 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:57:22,067 INFO L263 TraceCheckSpWp]: Trace formula consists of 694 conjuncts, 56 conjunts are in the unsatisfiable core [2021-12-06 21:57:22,068 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:23,378 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 702 proven. 1001 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:23,378 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:24,071 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 676 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:24,071 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [62561222] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:24,071 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:24,071 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57, 57] total 140 [2021-12-06 21:57:24,071 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715807949] [2021-12-06 21:57:24,071 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:24,071 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:24,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:24,072 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 109 times [2021-12-06 21:57:24,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:24,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126426883] [2021-12-06 21:57:24,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:24,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:24,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:24,076 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:24,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:24,079 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:24,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:24,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 140 interpolants. [2021-12-06 21:57:24,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3226, Invalid=16234, Unknown=0, NotChecked=0, Total=19460 [2021-12-06 21:57:24,102 INFO L87 Difference]: Start difference. First operand 147 states and 179 transitions. cyclomatic complexity: 36 Second operand has 140 states, 140 states have (on average 2.335714285714286) internal successors, (327), 140 states have internal predecessors, (327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:25,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:25,508 INFO L93 Difference]: Finished difference Result 206 states and 239 transitions. [2021-12-06 21:57:25,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2021-12-06 21:57:25,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 206 states and 239 transitions. [2021-12-06 21:57:25,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:25,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 206 states to 152 states and 185 transitions. [2021-12-06 21:57:25,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:57:25,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:57:25,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152 states and 185 transitions. [2021-12-06 21:57:25,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:25,510 INFO L681 BuchiCegarLoop]: Abstraction has 152 states and 185 transitions. [2021-12-06 21:57:25,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states and 185 transitions. [2021-12-06 21:57:25,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 149. [2021-12-06 21:57:25,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.2147651006711409) internal successors, (181), 148 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:25,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 181 transitions. [2021-12-06 21:57:25,511 INFO L704 BuchiCegarLoop]: Abstraction has 149 states and 181 transitions. [2021-12-06 21:57:25,511 INFO L587 BuchiCegarLoop]: Abstraction has 149 states and 181 transitions. [2021-12-06 21:57:25,511 INFO L425 BuchiCegarLoop]: ======== Iteration 112============ [2021-12-06 21:57:25,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 181 transitions. [2021-12-06 21:57:25,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:25,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:25,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:25,511 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:25,511 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:25,512 INFO L791 eck$LassoCheckResult]: Stem: 90941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 90942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 90952#L367 assume !(main_~length~0#1 < 1); 90943#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 90944#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 90945#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 90953#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 90958#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 90954#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 90955#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91089#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91088#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91087#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91086#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91085#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91084#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91083#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91082#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91081#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91080#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91079#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91078#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91077#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91076#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91075#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91072#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91071#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91070#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91069#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91068#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91067#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91066#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91065#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91064#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91063#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91062#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91060#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91059#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91058#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91057#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91056#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91055#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91054#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91053#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91052#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91051#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91050#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91048#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91046#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91045#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91042#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91039#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91036#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91035#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91033#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91032#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91031#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91030#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91028#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91027#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91026#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91025#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91024#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91021#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91020#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91019#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91018#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 91017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91016#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91009#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 91015#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 91012#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 91011#L370-4 main_~j~0#1 := 0; 90956#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90948#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90949#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 91007#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 91006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 91005#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 91004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 91003#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 91002#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 91001#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 91000#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90999#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90998#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90997#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90995#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90993#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90991#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90990#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90989#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90988#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90987#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90985#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90984#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90983#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90981#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90979#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90977#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90975#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90973#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90971#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90969#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90967#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90966#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90965#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90963#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90962#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90960#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 90959#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90946#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 90947#L378-2 [2021-12-06 21:57:25,512 INFO L793 eck$LassoCheckResult]: Loop: 90947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 90961#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 90947#L378-2 [2021-12-06 21:57:25,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:25,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1023387934, now seen corresponding path program 59 times [2021-12-06 21:57:25,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:25,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878549508] [2021-12-06 21:57:25,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:25,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:25,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:26,565 INFO L134 CoverageAnalysis]: Checked inductivity of 1730 backedges. 0 proven. 1730 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:26,565 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:26,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878549508] [2021-12-06 21:57:26,565 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878549508] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:26,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [845420332] [2021-12-06 21:57:26,565 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:57:26,565 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:26,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:26,566 INFO L229 MonitoredProcess]: Starting monitored process 132 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:26,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (132)] Waiting until timeout for monitored process [2021-12-06 21:57:27,622 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2021-12-06 21:57:27,622 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:57:27,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 705 conjuncts, 115 conjunts are in the unsatisfiable core [2021-12-06 21:57:27,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:27,788 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:57:27,903 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:57:27,903 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:57:27,917 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:57:27,917 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:57:29,104 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:57:29,106 INFO L134 CoverageAnalysis]: Checked inductivity of 1730 backedges. 0 proven. 1730 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:29,106 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:29,473 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:57:29,474 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:57:29,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1730 backedges. 0 proven. 1730 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:29,626 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [845420332] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:29,626 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:29,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59, 59] total 90 [2021-12-06 21:57:29,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838798316] [2021-12-06 21:57:29,626 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:29,626 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:29,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:29,627 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 110 times [2021-12-06 21:57:29,627 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:29,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092688333] [2021-12-06 21:57:29,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:29,627 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:29,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:29,631 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:29,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:29,634 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:29,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:29,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2021-12-06 21:57:29,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=252, Invalid=7938, Unknown=0, NotChecked=0, Total=8190 [2021-12-06 21:57:29,658 INFO L87 Difference]: Start difference. First operand 149 states and 181 transitions. cyclomatic complexity: 36 Second operand has 91 states, 90 states have (on average 2.2555555555555555) internal successors, (203), 91 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:33,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:33,945 INFO L93 Difference]: Finished difference Result 326 states and 367 transitions. [2021-12-06 21:57:33,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2021-12-06 21:57:33,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 326 states and 367 transitions. [2021-12-06 21:57:33,946 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:57:33,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 326 states to 325 states and 366 transitions. [2021-12-06 21:57:33,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:57:33,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:57:33,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 325 states and 366 transitions. [2021-12-06 21:57:33,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:33,947 INFO L681 BuchiCegarLoop]: Abstraction has 325 states and 366 transitions. [2021-12-06 21:57:33,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states and 366 transitions. [2021-12-06 21:57:33,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 155. [2021-12-06 21:57:33,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155 states, 155 states have (on average 1.232258064516129) internal successors, (191), 154 states have internal predecessors, (191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:33,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 191 transitions. [2021-12-06 21:57:33,948 INFO L704 BuchiCegarLoop]: Abstraction has 155 states and 191 transitions. [2021-12-06 21:57:33,948 INFO L587 BuchiCegarLoop]: Abstraction has 155 states and 191 transitions. [2021-12-06 21:57:33,948 INFO L425 BuchiCegarLoop]: ======== Iteration 113============ [2021-12-06 21:57:33,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155 states and 191 transitions. [2021-12-06 21:57:33,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:33,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:33,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:33,949 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:33,949 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:33,949 INFO L791 eck$LassoCheckResult]: Stem: 92400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 92401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 92411#L367 assume !(main_~length~0#1 < 1); 92402#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 92403#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 92404#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92412#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92497#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92413#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92414#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92418#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92496#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92495#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92494#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92493#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92492#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92491#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92490#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92488#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92487#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92486#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92485#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92484#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92483#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92482#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92481#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92480#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92477#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92476#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92475#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92474#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92472#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92471#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92470#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92469#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92468#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92466#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92465#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92464#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92463#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92461#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92460#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92459#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92458#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92457#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92456#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92455#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92454#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92453#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92451#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92450#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92449#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92448#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92447#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92446#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92445#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92444#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92442#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92439#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92436#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92433#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92430#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92428#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92427#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 92426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92424#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92425#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 92423#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 92553#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 92409#L370-4 main_~j~0#1 := 0; 92410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92547#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92416#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92407#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92408#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92546#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92543#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92542#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92536#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92534#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92532#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92530#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92528#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92527#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92526#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92525#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92524#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92523#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92522#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92520#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92519#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92518#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92516#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92515#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92514#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92513#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92512#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92511#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92510#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92509#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92508#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92506#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92504#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92502#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92499#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 92498#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92405#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 92406#L378-2 [2021-12-06 21:57:33,949 INFO L793 eck$LassoCheckResult]: Loop: 92406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 92500#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 92406#L378-2 [2021-12-06 21:57:33,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:33,949 INFO L85 PathProgramCache]: Analyzing trace with hash -71702941, now seen corresponding path program 60 times [2021-12-06 21:57:33,949 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:33,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475057170] [2021-12-06 21:57:33,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:33,949 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:33,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:34,978 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 0 proven. 1782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:34,978 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:34,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475057170] [2021-12-06 21:57:34,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1475057170] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:34,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1463083595] [2021-12-06 21:57:34,979 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:57:34,979 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:34,979 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:34,980 INFO L229 MonitoredProcess]: Starting monitored process 133 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:34,981 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (133)] Waiting until timeout for monitored process [2021-12-06 21:57:40,764 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2021-12-06 21:57:40,764 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:57:40,783 INFO L263 TraceCheckSpWp]: Trace formula consists of 716 conjuncts, 62 conjunts are in the unsatisfiable core [2021-12-06 21:57:40,785 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:57:41,685 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:57:44,172 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:57:44,172 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:57:44,223 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 676 proven. 1106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:44,223 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:57:47,286 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:57:47,288 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:57:47,357 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 650 proven. 1132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:47,357 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1463083595] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:57:47,357 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:57:47,357 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59, 59] total 146 [2021-12-06 21:57:47,357 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835145667] [2021-12-06 21:57:47,357 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:57:47,357 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:57:47,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:47,358 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 111 times [2021-12-06 21:57:47,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:47,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800179572] [2021-12-06 21:57:47,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:47,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:47,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:47,362 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:57:47,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:57:47,365 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:57:47,387 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:57:47,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 147 interpolants. [2021-12-06 21:57:47,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2251, Invalid=19211, Unknown=0, NotChecked=0, Total=21462 [2021-12-06 21:57:47,388 INFO L87 Difference]: Start difference. First operand 155 states and 191 transitions. cyclomatic complexity: 40 Second operand has 147 states, 146 states have (on average 2.308219178082192) internal successors, (337), 147 states have internal predecessors, (337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:52,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:57:52,114 INFO L93 Difference]: Finished difference Result 268 states and 305 transitions. [2021-12-06 21:57:52,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 114 states. [2021-12-06 21:57:52,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 268 states and 305 transitions. [2021-12-06 21:57:52,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:52,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 268 states to 209 states and 245 transitions. [2021-12-06 21:57:52,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:57:52,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:57:52,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209 states and 245 transitions. [2021-12-06 21:57:52,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:57:52,116 INFO L681 BuchiCegarLoop]: Abstraction has 209 states and 245 transitions. [2021-12-06 21:57:52,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states and 245 transitions. [2021-12-06 21:57:52,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 157. [2021-12-06 21:57:52,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.2292993630573248) internal successors, (193), 156 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:57:52,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 193 transitions. [2021-12-06 21:57:52,117 INFO L704 BuchiCegarLoop]: Abstraction has 157 states and 193 transitions. [2021-12-06 21:57:52,117 INFO L587 BuchiCegarLoop]: Abstraction has 157 states and 193 transitions. [2021-12-06 21:57:52,117 INFO L425 BuchiCegarLoop]: ======== Iteration 114============ [2021-12-06 21:57:52,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 193 transitions. [2021-12-06 21:57:52,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:57:52,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:57:52,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:57:52,118 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 27, 27, 26, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:57:52,118 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:57:52,118 INFO L791 eck$LassoCheckResult]: Stem: 94011#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 94012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 94022#L367 assume !(main_~length~0#1 < 1); 94013#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 94014#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 94015#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94023#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94026#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94024#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94025#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94167#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94166#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94165#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94164#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94163#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94162#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94161#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94160#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94159#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94156#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94155#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94153#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94152#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94151#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94150#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94149#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94148#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94147#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94146#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94145#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94144#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94143#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94141#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94140#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94138#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94137#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94136#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94135#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94134#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94133#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94132#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94131#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94130#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94129#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94127#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94126#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94125#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94124#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94123#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94122#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94121#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94120#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94118#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94117#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94116#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94114#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94113#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94112#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94111#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94110#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94108#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94107#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94106#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94105#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94104#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94103#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94102#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94100#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94099#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94098#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94097#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94096#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94095#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94094#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 94093#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 94091#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 94082#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 94081#L370-4 main_~j~0#1 := 0; 94027#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94020#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94028#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94079#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94078#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94077#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94076#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94075#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94074#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94073#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94072#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94071#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94070#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94069#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94068#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94067#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94066#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94065#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94064#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94063#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94062#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94061#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94060#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94059#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94058#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94057#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94055#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94054#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94053#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94052#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94051#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94050#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94049#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94048#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94047#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94046#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94045#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94043#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94042#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94041#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94040#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94039#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94038#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94037#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94036#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94035#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94034#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94033#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 94032#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94018#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 94019#L378-2 [2021-12-06 21:57:52,118 INFO L793 eck$LassoCheckResult]: Loop: 94019#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 94031#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 94019#L378-2 [2021-12-06 21:57:52,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:57:52,118 INFO L85 PathProgramCache]: Analyzing trace with hash 362026145, now seen corresponding path program 48 times [2021-12-06 21:57:52,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:57:52,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548914635] [2021-12-06 21:57:52,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:57:52,118 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:57:52,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:57:53,193 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 0 proven. 1782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:57:53,193 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:57:53,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548914635] [2021-12-06 21:57:53,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1548914635] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:57:53,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [861288811] [2021-12-06 21:57:53,194 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:57:53,194 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:57:53,194 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:57:53,195 INFO L229 MonitoredProcess]: Starting monitored process 134 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:57:53,195 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (134)] Waiting until timeout for monitored process [2021-12-06 21:58:03,002 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2021-12-06 21:58:03,003 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:58:03,024 INFO L263 TraceCheckSpWp]: Trace formula consists of 708 conjuncts, 63 conjunts are in the unsatisfiable core [2021-12-06 21:58:03,026 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:03,950 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:58:06,490 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:58:06,490 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:58:06,492 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 676 proven. 1106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:06,492 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:09,716 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:58:09,718 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:58:09,787 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 650 proven. 1132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:09,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [861288811] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:09,788 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:09,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 60, 60] total 148 [2021-12-06 21:58:09,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703484476] [2021-12-06 21:58:09,788 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:09,788 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:09,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:09,788 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 112 times [2021-12-06 21:58:09,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:09,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286622804] [2021-12-06 21:58:09,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:09,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:09,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:09,793 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:09,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:09,796 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:09,818 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:09,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 149 interpolants. [2021-12-06 21:58:09,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2317, Invalid=19735, Unknown=0, NotChecked=0, Total=22052 [2021-12-06 21:58:09,819 INFO L87 Difference]: Start difference. First operand 157 states and 193 transitions. cyclomatic complexity: 40 Second operand has 149 states, 148 states have (on average 2.277027027027027) internal successors, (337), 149 states have internal predecessors, (337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:15,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:58:15,794 INFO L93 Difference]: Finished difference Result 298 states and 361 transitions. [2021-12-06 21:58:15,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 115 states. [2021-12-06 21:58:15,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 298 states and 361 transitions. [2021-12-06 21:58:15,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:15,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 298 states to 239 states and 301 transitions. [2021-12-06 21:58:15,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:58:15,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:58:15,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 239 states and 301 transitions. [2021-12-06 21:58:15,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:58:15,795 INFO L681 BuchiCegarLoop]: Abstraction has 239 states and 301 transitions. [2021-12-06 21:58:15,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states and 301 transitions. [2021-12-06 21:58:15,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 237. [2021-12-06 21:58:15,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 237 states, 237 states have (on average 1.261603375527426) internal successors, (299), 236 states have internal predecessors, (299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:15,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 299 transitions. [2021-12-06 21:58:15,797 INFO L704 BuchiCegarLoop]: Abstraction has 237 states and 299 transitions. [2021-12-06 21:58:15,797 INFO L587 BuchiCegarLoop]: Abstraction has 237 states and 299 transitions. [2021-12-06 21:58:15,797 INFO L425 BuchiCegarLoop]: ======== Iteration 115============ [2021-12-06 21:58:15,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 237 states and 299 transitions. [2021-12-06 21:58:15,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:15,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:58:15,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:58:15,798 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:58:15,798 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:58:15,798 INFO L791 eck$LassoCheckResult]: Stem: 95708#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 95709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 95719#L367 assume !(main_~length~0#1 < 1); 95710#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 95711#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 95712#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95720#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95723#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95944#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95940#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95937#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95934#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95931#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95928#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95927#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95925#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95922#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95921#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95919#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95915#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95913#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95910#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95909#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95901#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95895#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95889#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95886#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95885#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95883#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95880#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95879#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95877#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95874#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95871#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95865#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95853#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95850#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95849#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95847#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95841#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95837#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95835#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95832#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95829#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95825#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95823#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95820#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95819#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95817#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95813#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95811#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95808#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95807#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95805#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95802#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95801#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95799#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95795#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 95791#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 95789#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 95782#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 95781#L370-4 main_~j~0#1 := 0; 95725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95717#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95726#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95779#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95778#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95777#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95776#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95775#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95774#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95773#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95772#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95771#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95770#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95769#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95768#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95767#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95766#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95765#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95764#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95763#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95762#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95761#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95760#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95759#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95758#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95757#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95756#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95755#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95754#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95753#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95752#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95751#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95750#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95749#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95747#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95746#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95745#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95744#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95743#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95742#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95741#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95740#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95739#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95738#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95737#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95736#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95735#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95734#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95733#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 95732#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95715#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 95716#L378-2 [2021-12-06 21:58:15,798 INFO L793 eck$LassoCheckResult]: Loop: 95716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 95731#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 95716#L378-2 [2021-12-06 21:58:15,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:15,798 INFO L85 PathProgramCache]: Analyzing trace with hash -55862557, now seen corresponding path program 61 times [2021-12-06 21:58:15,798 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:15,798 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837064358] [2021-12-06 21:58:15,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:15,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:15,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:16,881 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 0 proven. 1782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:16,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:58:16,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837064358] [2021-12-06 21:58:16,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837064358] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:58:16,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1759081087] [2021-12-06 21:58:16,881 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:58:16,881 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:58:16,881 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:58:16,883 INFO L229 MonitoredProcess]: Starting monitored process 135 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:58:16,883 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (135)] Waiting until timeout for monitored process [2021-12-06 21:58:17,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:17,126 INFO L263 TraceCheckSpWp]: Trace formula consists of 716 conjuncts, 118 conjunts are in the unsatisfiable core [2021-12-06 21:58:17,127 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:18,214 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:58:19,852 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:58:19,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 0 proven. 1782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:19,853 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:20,012 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:58:20,013 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:58:20,183 INFO L134 CoverageAnalysis]: Checked inductivity of 1782 backedges. 0 proven. 1782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:20,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1759081087] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:20,184 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:20,184 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 58] total 118 [2021-12-06 21:58:20,184 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933361296] [2021-12-06 21:58:20,184 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:20,184 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:20,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:20,185 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 113 times [2021-12-06 21:58:20,185 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:20,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65938822] [2021-12-06 21:58:20,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:20,185 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:20,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:20,190 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:20,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:20,193 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:20,217 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:20,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2021-12-06 21:58:20,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=439, Invalid=13603, Unknown=0, NotChecked=0, Total=14042 [2021-12-06 21:58:20,218 INFO L87 Difference]: Start difference. First operand 237 states and 299 transitions. cyclomatic complexity: 66 Second operand has 119 states, 118 states have (on average 2.4237288135593222) internal successors, (286), 119 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:24,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:58:24,192 INFO L93 Difference]: Finished difference Result 408 states and 501 transitions. [2021-12-06 21:58:24,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2021-12-06 21:58:24,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 501 transitions. [2021-12-06 21:58:24,193 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56 [2021-12-06 21:58:24,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 407 states and 500 transitions. [2021-12-06 21:58:24,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2021-12-06 21:58:24,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2021-12-06 21:58:24,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 500 transitions. [2021-12-06 21:58:24,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:58:24,194 INFO L681 BuchiCegarLoop]: Abstraction has 407 states and 500 transitions. [2021-12-06 21:58:24,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 500 transitions. [2021-12-06 21:58:24,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 351. [2021-12-06 21:58:24,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 351 states, 351 states have (on average 1.2592592592592593) internal successors, (442), 350 states have internal predecessors, (442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:24,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351 states to 351 states and 442 transitions. [2021-12-06 21:58:24,196 INFO L704 BuchiCegarLoop]: Abstraction has 351 states and 442 transitions. [2021-12-06 21:58:24,196 INFO L587 BuchiCegarLoop]: Abstraction has 351 states and 442 transitions. [2021-12-06 21:58:24,197 INFO L425 BuchiCegarLoop]: ======== Iteration 116============ [2021-12-06 21:58:24,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 351 states and 442 transitions. [2021-12-06 21:58:24,197 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 54 [2021-12-06 21:58:24,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:58:24,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:58:24,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 26, 25, 25, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:58:24,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:58:24,201 INFO L791 eck$LassoCheckResult]: Stem: 97329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 97330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 97340#L367 assume !(main_~length~0#1 < 1); 97331#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 97332#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 97333#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97341#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97508#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97504#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97502#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97498#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97496#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97494#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97492#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97488#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97486#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97482#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97480#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97478#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97476#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97474#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97472#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97470#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97468#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97466#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97464#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97462#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97458#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97456#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97450#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97446#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97444#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97438#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97436#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97432#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97430#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97428#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97426#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97422#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97420#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97416#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97414#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97412#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97410#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97408#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97404#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97402#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97400#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97398#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97396#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97392#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97390#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97386#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97384#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97380#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97378#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97376#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97374#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97372#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97370#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97368#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97366#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97360#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 97357#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97356#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97354#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97570#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 97572#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 97623#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 97621#L370-4 main_~j~0#1 := 0; 97619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97617#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97616#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97615#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97606#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97605#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97604#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97603#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97602#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97600#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97598#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97594#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97592#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97590#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97586#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97584#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97583#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97582#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97580#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97578#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97577#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97576#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97574#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97513#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97514#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 97515#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97516#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 97335#L378-2 [2021-12-06 21:58:24,201 INFO L793 eck$LassoCheckResult]: Loop: 97335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 97510#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 97335#L378-2 [2021-12-06 21:58:24,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:24,201 INFO L85 PathProgramCache]: Analyzing trace with hash 2038532884, now seen corresponding path program 62 times [2021-12-06 21:58:24,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:24,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397204474] [2021-12-06 21:58:24,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:24,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:24,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:25,332 INFO L134 CoverageAnalysis]: Checked inductivity of 1812 backedges. 0 proven. 1812 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:25,332 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:58:25,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397204474] [2021-12-06 21:58:25,332 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [397204474] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:58:25,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [607054068] [2021-12-06 21:58:25,332 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:58:25,333 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:58:25,333 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:58:25,334 INFO L229 MonitoredProcess]: Starting monitored process 136 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:58:25,334 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (136)] Waiting until timeout for monitored process [2021-12-06 21:58:25,578 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:58:25,578 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:58:25,582 INFO L263 TraceCheckSpWp]: Trace formula consists of 735 conjuncts, 120 conjunts are in the unsatisfiable core [2021-12-06 21:58:25,584 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:25,723 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:58:25,811 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:58:25,812 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:25,820 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:58:25,820 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:25,864 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:58:25,864 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:25,873 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 21:58:25,873 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:26,995 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:58:26,996 INFO L134 CoverageAnalysis]: Checked inductivity of 1812 backedges. 2 proven. 1810 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:26,996 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:27,375 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:58:27,376 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:58:27,533 INFO L134 CoverageAnalysis]: Checked inductivity of 1812 backedges. 1 proven. 1810 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 21:58:27,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [607054068] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:27,533 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:27,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59] total 89 [2021-12-06 21:58:27,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231487332] [2021-12-06 21:58:27,534 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:27,534 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:27,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:27,534 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 114 times [2021-12-06 21:58:27,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:27,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978178384] [2021-12-06 21:58:27,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:27,534 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:27,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:27,539 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:27,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:27,542 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:27,564 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:27,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2021-12-06 21:58:27,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=250, Invalid=7760, Unknown=0, NotChecked=0, Total=8010 [2021-12-06 21:58:27,564 INFO L87 Difference]: Start difference. First operand 351 states and 442 transitions. cyclomatic complexity: 97 Second operand has 90 states, 89 states have (on average 2.3146067415730336) internal successors, (206), 90 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:30,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:58:30,956 INFO L93 Difference]: Finished difference Result 399 states and 463 transitions. [2021-12-06 21:58:30,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2021-12-06 21:58:30,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399 states and 463 transitions. [2021-12-06 21:58:30,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:30,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399 states to 397 states and 461 transitions. [2021-12-06 21:58:30,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 21:58:30,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 21:58:30,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 397 states and 461 transitions. [2021-12-06 21:58:30,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:58:30,958 INFO L681 BuchiCegarLoop]: Abstraction has 397 states and 461 transitions. [2021-12-06 21:58:30,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states and 461 transitions. [2021-12-06 21:58:30,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 232. [2021-12-06 21:58:30,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 232 states, 232 states have (on average 1.2543103448275863) internal successors, (291), 231 states have internal predecessors, (291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:30,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 291 transitions. [2021-12-06 21:58:30,959 INFO L704 BuchiCegarLoop]: Abstraction has 232 states and 291 transitions. [2021-12-06 21:58:30,959 INFO L587 BuchiCegarLoop]: Abstraction has 232 states and 291 transitions. [2021-12-06 21:58:30,959 INFO L425 BuchiCegarLoop]: ======== Iteration 117============ [2021-12-06 21:58:30,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 232 states and 291 transitions. [2021-12-06 21:58:30,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:30,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:58:30,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:58:30,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 27, 27, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:58:30,960 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:58:30,960 INFO L791 eck$LassoCheckResult]: Stem: 99078#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 99079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 99089#L367 assume !(main_~length~0#1 < 1); 99080#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 99081#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 99082#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99090#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99093#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99091#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99092#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99303#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99299#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99297#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99291#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99287#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99285#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99279#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99275#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99273#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99269#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99267#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99265#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99263#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99261#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99259#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99255#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99253#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99251#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99249#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99245#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99243#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99241#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99237#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99233#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99231#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99225#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99221#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99219#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99215#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99213#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99209#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99207#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99203#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99201#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99197#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99195#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99191#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99183#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99181#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99179#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99177#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99175#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99173#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99171#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99167#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99165#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99160#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 99158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 99151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 99152#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 99083#L370-4 main_~j~0#1 := 0; 99084#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99153#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99096#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99087#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99088#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99148#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99147#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99146#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99144#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99143#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99142#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99140#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99139#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99134#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99130#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99129#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99128#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99127#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99126#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99124#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99123#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99122#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99120#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99118#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99116#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99114#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99110#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99108#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99106#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99102#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99101#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99100#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99098#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 99097#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99085#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 99086#L378-2 [2021-12-06 21:58:30,960 INFO L793 eck$LassoCheckResult]: Loop: 99086#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 99099#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 99086#L378-2 [2021-12-06 21:58:30,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:30,960 INFO L85 PathProgramCache]: Analyzing trace with hash -2144306456, now seen corresponding path program 63 times [2021-12-06 21:58:30,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:30,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788371446] [2021-12-06 21:58:30,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:30,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:30,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:31,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1836 backedges. 703 proven. 1133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:31,992 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:58:31,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788371446] [2021-12-06 21:58:31,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788371446] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:58:31,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [966706489] [2021-12-06 21:58:31,992 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:58:31,992 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:58:31,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:58:31,993 INFO L229 MonitoredProcess]: Starting monitored process 137 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:58:31,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (137)] Waiting until timeout for monitored process [2021-12-06 21:58:39,904 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2021-12-06 21:58:39,905 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:58:39,923 INFO L263 TraceCheckSpWp]: Trace formula consists of 727 conjuncts, 58 conjunts are in the unsatisfiable core [2021-12-06 21:58:39,924 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:41,620 INFO L134 CoverageAnalysis]: Checked inductivity of 1836 backedges. 756 proven. 1080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:41,620 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:42,696 INFO L134 CoverageAnalysis]: Checked inductivity of 1836 backedges. 756 proven. 1080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:42,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [966706489] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:42,696 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:42,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 59, 59] total 145 [2021-12-06 21:58:42,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92368478] [2021-12-06 21:58:42,696 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:42,696 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:42,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:42,697 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 115 times [2021-12-06 21:58:42,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:42,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144960826] [2021-12-06 21:58:42,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:42,697 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:42,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:42,702 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:42,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:42,705 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:42,727 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:42,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 145 interpolants. [2021-12-06 21:58:42,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2614, Invalid=18266, Unknown=0, NotChecked=0, Total=20880 [2021-12-06 21:58:42,728 INFO L87 Difference]: Start difference. First operand 232 states and 291 transitions. cyclomatic complexity: 63 Second operand has 145 states, 145 states have (on average 2.3448275862068964) internal successors, (340), 145 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:45,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:58:45,408 INFO L93 Difference]: Finished difference Result 293 states and 353 transitions. [2021-12-06 21:58:45,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2021-12-06 21:58:45,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 293 states and 353 transitions. [2021-12-06 21:58:45,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:45,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 293 states to 237 states and 297 transitions. [2021-12-06 21:58:45,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:58:45,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:58:45,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 237 states and 297 transitions. [2021-12-06 21:58:45,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:58:45,410 INFO L681 BuchiCegarLoop]: Abstraction has 237 states and 297 transitions. [2021-12-06 21:58:45,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states and 297 transitions. [2021-12-06 21:58:45,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 154. [2021-12-06 21:58:45,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 154 states, 154 states have (on average 1.2142857142857142) internal successors, (187), 153 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:45,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 187 transitions. [2021-12-06 21:58:45,411 INFO L704 BuchiCegarLoop]: Abstraction has 154 states and 187 transitions. [2021-12-06 21:58:45,411 INFO L587 BuchiCegarLoop]: Abstraction has 154 states and 187 transitions. [2021-12-06 21:58:45,411 INFO L425 BuchiCegarLoop]: ======== Iteration 118============ [2021-12-06 21:58:45,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 154 states and 187 transitions. [2021-12-06 21:58:45,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:45,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:58:45,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:58:45,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:58:45,412 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:58:45,412 INFO L791 eck$LassoCheckResult]: Stem: 100721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 100722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 100732#L367 assume !(main_~length~0#1 < 1); 100723#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 100724#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 100725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100733#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100736#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100735#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100874#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100872#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100871#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100869#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100866#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100865#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100864#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100863#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100860#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100859#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100854#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100853#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100852#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100851#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100850#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100849#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100848#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100847#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100845#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100842#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100841#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100839#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100837#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100836#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100835#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100834#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100833#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100832#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100830#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100827#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100825#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100824#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100823#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100822#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100821#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100820#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100819#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100818#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100817#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100816#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100815#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100813#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100812#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100811#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100810#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100809#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100808#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100807#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100806#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100805#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100804#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100803#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100802#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100801#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100800#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 100799#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100798#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100796#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 100792#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 100738#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 100726#L370-4 main_~j~0#1 := 0; 100727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100737#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100790#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100788#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100787#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100786#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100785#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100784#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100783#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100782#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100781#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100780#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100778#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100777#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100776#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100775#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100774#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100772#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100770#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100768#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100766#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100764#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100762#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100761#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100760#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100759#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100758#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100757#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100756#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100755#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100754#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100753#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100752#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100751#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100750#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100748#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100747#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100746#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100745#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100744#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100743#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100741#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 100740#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100728#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 100729#L378-2 [2021-12-06 21:58:45,412 INFO L793 eck$LassoCheckResult]: Loop: 100729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 100742#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 100729#L378-2 [2021-12-06 21:58:45,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:45,412 INFO L85 PathProgramCache]: Analyzing trace with hash 698722653, now seen corresponding path program 64 times [2021-12-06 21:58:45,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:45,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10031045] [2021-12-06 21:58:45,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:45,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:45,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:46,527 INFO L134 CoverageAnalysis]: Checked inductivity of 1864 backedges. 0 proven. 1864 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:46,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:58:46,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10031045] [2021-12-06 21:58:46,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10031045] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:58:46,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1704678455] [2021-12-06 21:58:46,527 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 21:58:46,527 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:58:46,527 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:58:46,528 INFO L229 MonitoredProcess]: Starting monitored process 138 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:58:46,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (138)] Waiting until timeout for monitored process [2021-12-06 21:58:46,773 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 21:58:46,773 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:58:46,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 730 conjuncts, 123 conjunts are in the unsatisfiable core [2021-12-06 21:58:46,778 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:47,880 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:58:48,035 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:58:48,036 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:48,042 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 21:58:48,043 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 21:58:49,677 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:58:49,679 INFO L134 CoverageAnalysis]: Checked inductivity of 1864 backedges. 0 proven. 1864 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:49,679 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:49,968 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:58:49,970 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:58:50,129 INFO L134 CoverageAnalysis]: Checked inductivity of 1864 backedges. 0 proven. 1864 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:50,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1704678455] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:50,130 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:50,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61, 60] total 122 [2021-12-06 21:58:50,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136013253] [2021-12-06 21:58:50,130 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:50,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:50,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:50,131 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 116 times [2021-12-06 21:58:50,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:50,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335144510] [2021-12-06 21:58:50,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:50,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:50,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:50,136 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:50,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:50,139 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:50,161 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:50,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 123 interpolants. [2021-12-06 21:58:50,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=437, Invalid=14569, Unknown=0, NotChecked=0, Total=15006 [2021-12-06 21:58:50,162 INFO L87 Difference]: Start difference. First operand 154 states and 187 transitions. cyclomatic complexity: 37 Second operand has 123 states, 122 states have (on average 2.3934426229508197) internal successors, (292), 123 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:54,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:58:54,150 INFO L93 Difference]: Finished difference Result 208 states and 241 transitions. [2021-12-06 21:58:54,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2021-12-06 21:58:54,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 241 transitions. [2021-12-06 21:58:54,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:54,151 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 207 states and 240 transitions. [2021-12-06 21:58:54,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:58:54,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:58:54,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 207 states and 240 transitions. [2021-12-06 21:58:54,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:58:54,151 INFO L681 BuchiCegarLoop]: Abstraction has 207 states and 240 transitions. [2021-12-06 21:58:54,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states and 240 transitions. [2021-12-06 21:58:54,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 149. [2021-12-06 21:58:54,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.2080536912751678) internal successors, (180), 148 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:58:54,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 180 transitions. [2021-12-06 21:58:54,152 INFO L704 BuchiCegarLoop]: Abstraction has 149 states and 180 transitions. [2021-12-06 21:58:54,152 INFO L587 BuchiCegarLoop]: Abstraction has 149 states and 180 transitions. [2021-12-06 21:58:54,152 INFO L425 BuchiCegarLoop]: ======== Iteration 119============ [2021-12-06 21:58:54,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 180 transitions. [2021-12-06 21:58:54,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:58:54,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:58:54,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:58:54,153 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 28, 28, 27, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:58:54,153 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:58:54,153 INFO L791 eck$LassoCheckResult]: Stem: 102131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 102132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 102142#L367 assume !(main_~length~0#1 < 1); 102133#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 102134#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 102135#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102233#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102145#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102146#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102232#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102231#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102230#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102229#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102228#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102226#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102224#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102223#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102222#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102221#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102220#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102219#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102218#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102217#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102216#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102215#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102214#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102213#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102212#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102211#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102210#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102209#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102208#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102207#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102206#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102205#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102204#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102203#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102202#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102201#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102200#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102199#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102198#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102197#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102196#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102195#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102194#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102193#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102192#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102191#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102190#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102189#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102188#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102187#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102184#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102183#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102182#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102181#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102180#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102179#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102178#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102177#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102176#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102175#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102174#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102173#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102172#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102171#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102169#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102168#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102167#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102166#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102165#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102164#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102163#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102161#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102160#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102159#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102158#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 102151#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 102155#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 102150#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 102136#L370-4 main_~j~0#1 := 0; 102137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102147#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102140#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102279#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102278#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102277#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102275#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102274#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102273#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102271#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102270#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102269#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102267#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102266#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102265#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102263#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102262#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102261#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102257#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102255#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102253#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102252#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102251#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102250#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102249#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102248#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102247#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102245#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102243#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102242#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102241#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102239#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102237#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102235#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102234#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102157#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102156#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102154#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 102153#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102138#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 102139#L378-2 [2021-12-06 21:58:54,153 INFO L793 eck$LassoCheckResult]: Loop: 102139#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 102152#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 102139#L378-2 [2021-12-06 21:58:54,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:54,154 INFO L85 PathProgramCache]: Analyzing trace with hash 1659398560, now seen corresponding path program 49 times [2021-12-06 21:58:54,154 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:54,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039850743] [2021-12-06 21:58:54,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:54,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:54,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:55,306 INFO L134 CoverageAnalysis]: Checked inductivity of 1918 backedges. 0 proven. 1918 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:55,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:58:55,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039850743] [2021-12-06 21:58:55,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039850743] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:58:55,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [155620476] [2021-12-06 21:58:55,307 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 21:58:55,307 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:58:55,307 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:58:55,308 INFO L229 MonitoredProcess]: Starting monitored process 139 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:58:55,309 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (139)] Waiting until timeout for monitored process [2021-12-06 21:58:55,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:58:55,552 INFO L263 TraceCheckSpWp]: Trace formula consists of 733 conjuncts, 122 conjunts are in the unsatisfiable core [2021-12-06 21:58:55,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:58:56,732 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 21:58:58,437 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 21:58:58,439 INFO L134 CoverageAnalysis]: Checked inductivity of 1918 backedges. 0 proven. 1918 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:58,439 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:58:58,608 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 21:58:58,610 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 21:58:58,777 INFO L134 CoverageAnalysis]: Checked inductivity of 1918 backedges. 0 proven. 1918 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:58:58,777 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [155620476] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:58:58,777 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:58:58,777 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 60] total 122 [2021-12-06 21:58:58,777 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857069195] [2021-12-06 21:58:58,777 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:58:58,778 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:58:58,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:58:58,778 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 117 times [2021-12-06 21:58:58,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:58:58,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689029609] [2021-12-06 21:58:58,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:58:58,778 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:58:58,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:58,783 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:58:58,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:58:58,786 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:58:58,809 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:58:58,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 123 interpolants. [2021-12-06 21:58:58,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=454, Invalid=14552, Unknown=0, NotChecked=0, Total=15006 [2021-12-06 21:58:58,810 INFO L87 Difference]: Start difference. First operand 149 states and 180 transitions. cyclomatic complexity: 34 Second operand has 123 states, 122 states have (on average 2.4262295081967213) internal successors, (296), 123 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:02,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:59:02,851 INFO L93 Difference]: Finished difference Result 217 states and 253 transitions. [2021-12-06 21:59:02,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2021-12-06 21:59:02,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 253 transitions. [2021-12-06 21:59:02,851 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 21:59:02,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 216 states and 252 transitions. [2021-12-06 21:59:02,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 21:59:02,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 21:59:02,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216 states and 252 transitions. [2021-12-06 21:59:02,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:59:02,852 INFO L681 BuchiCegarLoop]: Abstraction has 216 states and 252 transitions. [2021-12-06 21:59:02,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states and 252 transitions. [2021-12-06 21:59:02,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 157. [2021-12-06 21:59:02,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.21656050955414) internal successors, (191), 156 states have internal predecessors, (191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:02,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 191 transitions. [2021-12-06 21:59:02,853 INFO L704 BuchiCegarLoop]: Abstraction has 157 states and 191 transitions. [2021-12-06 21:59:02,853 INFO L587 BuchiCegarLoop]: Abstraction has 157 states and 191 transitions. [2021-12-06 21:59:02,853 INFO L425 BuchiCegarLoop]: ======== Iteration 120============ [2021-12-06 21:59:02,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 191 transitions. [2021-12-06 21:59:02,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:02,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:59:02,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:59:02,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:59:02,854 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:59:02,854 INFO L791 eck$LassoCheckResult]: Stem: 103507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 103508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 103518#L367 assume !(main_~length~0#1 < 1); 103509#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 103510#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 103511#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103519#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103524#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103520#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103521#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103526#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103602#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103601#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103600#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103595#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103594#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103593#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103592#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103591#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103590#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103589#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103588#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103587#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103586#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103585#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103584#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103583#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103582#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103581#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103580#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103579#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103578#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103576#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103575#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103573#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103572#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103571#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103569#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103568#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103566#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103564#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103563#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103562#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103561#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103560#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103559#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103558#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103557#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103556#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103555#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103554#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103553#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103552#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103551#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103550#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103549#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103548#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103547#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103545#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103544#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103543#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103542#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103539#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103536#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103532#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 103530#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 103529#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 103527#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 103516#L370-4 main_~j~0#1 := 0; 103517#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103659#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103523#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103514#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103515#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103658#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103657#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103656#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103654#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103653#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103652#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103651#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103650#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103649#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103648#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103647#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103646#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103645#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103644#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103643#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103642#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103641#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103640#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103639#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103638#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103636#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103635#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103634#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103633#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103632#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103631#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103630#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103629#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103628#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103627#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103626#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103624#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103621#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103617#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103616#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103615#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103608#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 103607#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103512#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 103513#L378-2 [2021-12-06 21:59:02,854 INFO L793 eck$LassoCheckResult]: Loop: 103513#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 103606#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 103513#L378-2 [2021-12-06 21:59:02,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:02,854 INFO L85 PathProgramCache]: Analyzing trace with hash 1249152613, now seen corresponding path program 50 times [2021-12-06 21:59:02,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:02,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490235959] [2021-12-06 21:59:02,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:02,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:02,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:59:03,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1974 backedges. 757 proven. 1217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:03,904 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:59:03,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490235959] [2021-12-06 21:59:03,904 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [490235959] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:59:03,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1211782371] [2021-12-06 21:59:03,904 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 21:59:03,904 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:59:03,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:59:03,905 INFO L229 MonitoredProcess]: Starting monitored process 140 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:59:03,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (140)] Waiting until timeout for monitored process [2021-12-06 21:59:04,156 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 21:59:04,157 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:59:04,160 INFO L263 TraceCheckSpWp]: Trace formula consists of 744 conjuncts, 60 conjunts are in the unsatisfiable core [2021-12-06 21:59:04,161 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:59:05,965 INFO L134 CoverageAnalysis]: Checked inductivity of 1974 backedges. 812 proven. 1162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:05,965 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:59:07,090 INFO L134 CoverageAnalysis]: Checked inductivity of 1974 backedges. 812 proven. 1162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:07,090 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1211782371] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:59:07,090 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:59:07,090 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61, 61] total 150 [2021-12-06 21:59:07,090 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432169857] [2021-12-06 21:59:07,090 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:59:07,091 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:59:07,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:07,091 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 118 times [2021-12-06 21:59:07,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:07,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656748730] [2021-12-06 21:59:07,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:07,091 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:07,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:07,099 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:59:07,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:07,102 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:59:07,125 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:59:07,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 150 interpolants. [2021-12-06 21:59:07,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2794, Invalid=19556, Unknown=0, NotChecked=0, Total=22350 [2021-12-06 21:59:07,126 INFO L87 Difference]: Start difference. First operand 157 states and 191 transitions. cyclomatic complexity: 38 Second operand has 150 states, 150 states have (on average 2.3466666666666667) internal successors, (352), 150 states have internal predecessors, (352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:10,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:59:10,008 INFO L93 Difference]: Finished difference Result 220 states and 255 transitions. [2021-12-06 21:59:10,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2021-12-06 21:59:10,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220 states and 255 transitions. [2021-12-06 21:59:10,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:10,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220 states to 162 states and 197 transitions. [2021-12-06 21:59:10,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:59:10,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:59:10,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162 states and 197 transitions. [2021-12-06 21:59:10,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:59:10,010 INFO L681 BuchiCegarLoop]: Abstraction has 162 states and 197 transitions. [2021-12-06 21:59:10,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states and 197 transitions. [2021-12-06 21:59:10,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 159. [2021-12-06 21:59:10,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159 states, 159 states have (on average 1.2138364779874213) internal successors, (193), 158 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:10,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 193 transitions. [2021-12-06 21:59:10,011 INFO L704 BuchiCegarLoop]: Abstraction has 159 states and 193 transitions. [2021-12-06 21:59:10,011 INFO L587 BuchiCegarLoop]: Abstraction has 159 states and 193 transitions. [2021-12-06 21:59:10,011 INFO L425 BuchiCegarLoop]: ======== Iteration 121============ [2021-12-06 21:59:10,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 159 states and 193 transitions. [2021-12-06 21:59:10,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:10,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:59:10,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:59:10,012 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:59:10,012 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:59:10,012 INFO L791 eck$LassoCheckResult]: Stem: 105041#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 105042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 105052#L367 assume !(main_~length~0#1 < 1); 105043#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 105044#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 105045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105053#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105054#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105055#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105198#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105197#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105194#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105191#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105189#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105188#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105186#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105185#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105183#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105182#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105181#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105180#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105179#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105178#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105176#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105175#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105174#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105173#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105172#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105171#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105170#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105168#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105167#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105166#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105165#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105164#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105161#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105160#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105140#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105139#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105135#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105134#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105133#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105132#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105131#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105130#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105128#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105127#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105125#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105123#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105122#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 105121#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105113#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 105119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 105116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 105115#L370-4 main_~j~0#1 := 0; 105056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105048#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105111#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105110#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105109#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105108#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105107#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105106#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105105#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105104#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105103#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105102#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105101#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105100#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105099#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105097#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105096#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105095#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105094#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105093#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105092#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105091#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105090#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105089#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105088#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105087#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105086#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105085#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105084#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105083#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105082#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105081#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105079#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105078#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105077#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105076#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105075#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105074#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105073#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105072#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105071#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105070#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105069#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105068#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105067#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105066#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105065#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105064#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105063#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105062#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105060#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 105059#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105046#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 105047#L378-2 [2021-12-06 21:59:10,012 INFO L793 eck$LassoCheckResult]: Loop: 105047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 105061#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 105047#L378-2 [2021-12-06 21:59:10,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:10,012 INFO L85 PathProgramCache]: Analyzing trace with hash -627450840, now seen corresponding path program 65 times [2021-12-06 21:59:10,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:10,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048130433] [2021-12-06 21:59:10,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:10,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:10,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:59:11,201 INFO L134 CoverageAnalysis]: Checked inductivity of 2003 backedges. 0 proven. 2003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:11,201 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:59:11,201 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2048130433] [2021-12-06 21:59:11,201 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2048130433] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:59:11,201 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1350301343] [2021-12-06 21:59:11,201 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 21:59:11,201 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:59:11,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:59:11,203 INFO L229 MonitoredProcess]: Starting monitored process 141 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:59:11,203 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (141)] Waiting until timeout for monitored process [2021-12-06 21:59:12,671 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2021-12-06 21:59:12,671 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:59:12,679 INFO L263 TraceCheckSpWp]: Trace formula consists of 755 conjuncts, 123 conjunts are in the unsatisfiable core [2021-12-06 21:59:12,681 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:59:12,833 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:59:12,957 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:59:12,957 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:59:12,970 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 21:59:12,970 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 21:59:14,313 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 21:59:14,315 INFO L134 CoverageAnalysis]: Checked inductivity of 2003 backedges. 0 proven. 2003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:14,315 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:59:14,669 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 21:59:14,670 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 21:59:14,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2003 backedges. 0 proven. 2003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:14,845 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1350301343] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:59:14,845 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:59:14,845 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 63, 63] total 96 [2021-12-06 21:59:14,845 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746251673] [2021-12-06 21:59:14,845 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:59:14,846 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:59:14,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:14,846 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 119 times [2021-12-06 21:59:14,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:14,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082383853] [2021-12-06 21:59:14,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:14,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:14,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:14,851 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:59:14,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:14,854 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:59:14,876 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:59:14,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2021-12-06 21:59:14,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=268, Invalid=9044, Unknown=0, NotChecked=0, Total=9312 [2021-12-06 21:59:14,877 INFO L87 Difference]: Start difference. First operand 159 states and 193 transitions. cyclomatic complexity: 38 Second operand has 97 states, 96 states have (on average 2.2604166666666665) internal successors, (217), 97 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:19,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:59:19,999 INFO L93 Difference]: Finished difference Result 349 states and 392 transitions. [2021-12-06 21:59:19,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2021-12-06 21:59:19,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 392 transitions. [2021-12-06 21:59:20,000 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 21:59:20,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 348 states and 391 transitions. [2021-12-06 21:59:20,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 21:59:20,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 21:59:20,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 348 states and 391 transitions. [2021-12-06 21:59:20,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:59:20,000 INFO L681 BuchiCegarLoop]: Abstraction has 348 states and 391 transitions. [2021-12-06 21:59:20,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 348 states and 391 transitions. [2021-12-06 21:59:20,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 348 to 165. [2021-12-06 21:59:20,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 165 states, 165 states have (on average 1.2303030303030302) internal successors, (203), 164 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:20,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 203 transitions. [2021-12-06 21:59:20,002 INFO L704 BuchiCegarLoop]: Abstraction has 165 states and 203 transitions. [2021-12-06 21:59:20,002 INFO L587 BuchiCegarLoop]: Abstraction has 165 states and 203 transitions. [2021-12-06 21:59:20,002 INFO L425 BuchiCegarLoop]: ======== Iteration 122============ [2021-12-06 21:59:20,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 165 states and 203 transitions. [2021-12-06 21:59:20,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:20,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:59:20,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:59:20,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:59:20,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:59:20,003 INFO L791 eck$LassoCheckResult]: Stem: 106603#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 106604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 106614#L367 assume !(main_~length~0#1 < 1); 106605#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 106606#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 106607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106615#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106616#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106621#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106767#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106766#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106765#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106764#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106763#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106762#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106761#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106760#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106759#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106758#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106756#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106755#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106754#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106753#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106752#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106751#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106750#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106749#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106748#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106747#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106746#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106745#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106744#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106743#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106742#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106741#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106740#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106739#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106737#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106736#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106734#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106733#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106732#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106731#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106729#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106728#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106727#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106726#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106725#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106723#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106722#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106720#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106719#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106718#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106717#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106716#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106714#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106713#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106712#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106711#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106710#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106707#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106705#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106704#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106701#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106698#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106696#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106695#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106694#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106693#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106692#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 106691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106690#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106689#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 106688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 106687#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 106612#L370-4 main_~j~0#1 := 0; 106613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106678#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106677#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106675#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106673#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106671#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106669#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106668#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106667#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106666#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106665#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106663#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106662#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106661#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106660#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106659#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106657#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106655#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106654#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106653#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106652#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106651#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106649#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106647#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106646#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106645#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106644#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106643#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106642#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106641#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106639#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106638#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106637#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106636#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106635#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106634#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106633#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106632#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106631#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106629#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106626#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 106625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106608#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 106609#L378-2 [2021-12-06 21:59:20,003 INFO L793 eck$LassoCheckResult]: Loop: 106609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 106627#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 106609#L378-2 [2021-12-06 21:59:20,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:20,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1684832531, now seen corresponding path program 66 times [2021-12-06 21:59:20,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:20,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123863593] [2021-12-06 21:59:20,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:20,003 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:20,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:59:21,136 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 0 proven. 2059 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:21,136 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:59:21,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123863593] [2021-12-06 21:59:21,136 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123863593] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:59:21,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1861476066] [2021-12-06 21:59:21,136 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 21:59:21,136 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:59:21,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:59:21,138 INFO L229 MonitoredProcess]: Starting monitored process 142 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:59:21,138 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (142)] Waiting until timeout for monitored process [2021-12-06 21:59:29,158 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 30 check-sat command(s) [2021-12-06 21:59:29,158 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:59:29,179 INFO L263 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 66 conjunts are in the unsatisfiable core [2021-12-06 21:59:29,180 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:59:30,202 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:59:32,993 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:59:32,993 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:59:33,039 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 784 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:33,039 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:59:36,464 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:59:36,466 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:59:36,558 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 756 proven. 1303 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:36,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1861476066] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:59:36,558 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:59:36,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 63, 63] total 156 [2021-12-06 21:59:36,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758179310] [2021-12-06 21:59:36,558 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:59:36,558 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:59:36,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:36,559 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 120 times [2021-12-06 21:59:36,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:36,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810964011] [2021-12-06 21:59:36,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:36,559 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:36,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:36,564 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:59:36,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:36,567 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:59:36,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:59:36,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 157 interpolants. [2021-12-06 21:59:36,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2560, Invalid=21932, Unknown=0, NotChecked=0, Total=24492 [2021-12-06 21:59:36,591 INFO L87 Difference]: Start difference. First operand 165 states and 203 transitions. cyclomatic complexity: 42 Second operand has 157 states, 156 states have (on average 2.3141025641025643) internal successors, (361), 157 states have internal predecessors, (361), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:41,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 21:59:41,991 INFO L93 Difference]: Finished difference Result 286 states and 325 transitions. [2021-12-06 21:59:41,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 122 states. [2021-12-06 21:59:41,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286 states and 325 transitions. [2021-12-06 21:59:41,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:41,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286 states to 223 states and 261 transitions. [2021-12-06 21:59:41,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 21:59:41,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 21:59:41,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 261 transitions. [2021-12-06 21:59:41,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 21:59:41,993 INFO L681 BuchiCegarLoop]: Abstraction has 223 states and 261 transitions. [2021-12-06 21:59:41,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 261 transitions. [2021-12-06 21:59:41,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 167. [2021-12-06 21:59:41,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 167 states, 167 states have (on average 1.2275449101796407) internal successors, (205), 166 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 21:59:41,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 205 transitions. [2021-12-06 21:59:41,994 INFO L704 BuchiCegarLoop]: Abstraction has 167 states and 205 transitions. [2021-12-06 21:59:41,994 INFO L587 BuchiCegarLoop]: Abstraction has 167 states and 205 transitions. [2021-12-06 21:59:41,994 INFO L425 BuchiCegarLoop]: ======== Iteration 123============ [2021-12-06 21:59:41,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 167 states and 205 transitions. [2021-12-06 21:59:41,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 21:59:41,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 21:59:41,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 21:59:41,995 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 29, 29, 28, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 21:59:41,995 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 21:59:41,995 INFO L791 eck$LassoCheckResult]: Stem: 108326#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 108327#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 108337#L367 assume !(main_~length~0#1 < 1); 108328#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 108329#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 108330#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108338#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108341#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108492#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108491#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108490#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108488#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108487#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108486#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108485#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108484#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108483#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108482#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108481#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108480#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108477#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108476#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108475#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108474#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108472#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108471#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108470#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108469#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108468#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108466#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108465#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108464#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108463#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108461#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108460#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108459#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108458#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108457#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108456#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108455#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108454#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108453#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108451#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108450#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108449#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108448#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108447#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108446#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108445#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108444#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108442#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108439#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108436#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108433#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108430#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108428#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108427#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108425#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108424#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108423#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108422#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108421#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108420#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108418#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108416#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108415#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108414#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108413#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 108412#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 108410#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 108401#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 108400#L370-4 main_~j~0#1 := 0; 108342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108335#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108336#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108343#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108399#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108398#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108396#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108394#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108393#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108392#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108391#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108390#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108389#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108388#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108386#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108385#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108384#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108383#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108382#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108380#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108378#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108375#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108374#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108371#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108370#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108369#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108368#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108367#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108366#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108365#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108364#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108363#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108362#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108361#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108359#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108358#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108356#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108355#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108354#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108353#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108352#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108351#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108350#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108348#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 108347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108333#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 108334#L378-2 [2021-12-06 21:59:41,995 INFO L793 eck$LassoCheckResult]: Loop: 108334#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 108346#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 108334#L378-2 [2021-12-06 21:59:41,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:41,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1005560277, now seen corresponding path program 51 times [2021-12-06 21:59:41,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:41,995 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858998999] [2021-12-06 21:59:41,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:41,995 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:42,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 21:59:43,222 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 0 proven. 2059 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:43,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 21:59:43,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858998999] [2021-12-06 21:59:43,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858998999] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 21:59:43,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [996147809] [2021-12-06 21:59:43,223 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 21:59:43,223 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 21:59:43,223 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 21:59:43,224 INFO L229 MonitoredProcess]: Starting monitored process 143 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 21:59:43,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (143)] Waiting until timeout for monitored process [2021-12-06 21:59:45,640 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2021-12-06 21:59:45,640 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 21:59:45,651 INFO L263 TraceCheckSpWp]: Trace formula consists of 758 conjuncts, 67 conjunts are in the unsatisfiable core [2021-12-06 21:59:45,653 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 21:59:46,668 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 21:59:49,618 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 21:59:49,619 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2021-12-06 21:59:49,621 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 784 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:49,621 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 21:59:53,458 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 21:59:53,459 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 32 [2021-12-06 21:59:53,539 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 756 proven. 1303 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 21:59:53,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [996147809] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 21:59:53,539 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 21:59:53,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 64, 64] total 158 [2021-12-06 21:59:53,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027376594] [2021-12-06 21:59:53,539 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 21:59:53,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 21:59:53,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 21:59:53,540 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 121 times [2021-12-06 21:59:53,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 21:59:53,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811230903] [2021-12-06 21:59:53,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 21:59:53,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 21:59:53,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:53,545 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 21:59:53,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 21:59:53,548 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 21:59:53,572 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 21:59:53,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 159 interpolants. [2021-12-06 21:59:53,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2630, Invalid=22492, Unknown=0, NotChecked=0, Total=25122 [2021-12-06 21:59:53,574 INFO L87 Difference]: Start difference. First operand 167 states and 205 transitions. cyclomatic complexity: 42 Second operand has 159 states, 158 states have (on average 2.2848101265822787) internal successors, (361), 159 states have internal predecessors, (361), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:04,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:00:04,573 INFO L93 Difference]: Finished difference Result 472 states and 563 transitions. [2021-12-06 22:00:04,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 217 states. [2021-12-06 22:00:04,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 472 states and 563 transitions. [2021-12-06 22:00:04,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 22:00:04,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 472 states to 354 states and 442 transitions. [2021-12-06 22:00:04,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 22:00:04,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 22:00:04,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 442 transitions. [2021-12-06 22:00:04,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 22:00:04,575 INFO L681 BuchiCegarLoop]: Abstraction has 354 states and 442 transitions. [2021-12-06 22:00:04,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 442 transitions. [2021-12-06 22:00:04,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 262. [2021-12-06 22:00:04,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 262 states, 262 states have (on average 1.2633587786259541) internal successors, (331), 261 states have internal predecessors, (331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:04,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 331 transitions. [2021-12-06 22:00:04,576 INFO L704 BuchiCegarLoop]: Abstraction has 262 states and 331 transitions. [2021-12-06 22:00:04,576 INFO L587 BuchiCegarLoop]: Abstraction has 262 states and 331 transitions. [2021-12-06 22:00:04,576 INFO L425 BuchiCegarLoop]: ======== Iteration 124============ [2021-12-06 22:00:04,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 262 states and 331 transitions. [2021-12-06 22:00:04,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 22:00:04,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:00:04,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:00:04,577 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:00:04,577 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 22:00:04,577 INFO L791 eck$LassoCheckResult]: Stem: 110417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 110418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 110428#L367 assume !(main_~length~0#1 < 1); 110419#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 110420#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 110421#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110429#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110608#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110606#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110605#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110604#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110600#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110597#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110594#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110592#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110591#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110587#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110586#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110584#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110430#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110431#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110435#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110678#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110578#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110676#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110675#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110674#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110671#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110670#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110669#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110668#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110667#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110666#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110665#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110664#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110663#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110662#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110660#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110644#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110659#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110658#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110640#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110656#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110655#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110654#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110629#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110650#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110649#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110648#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110622#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110520#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110518#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110515#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110514#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110513#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110509#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 110503#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 110501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 110493#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 110492#L370-4 main_~j~0#1 := 0; 110433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110426#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110427#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110434#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110490#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110489#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110488#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110486#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110485#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110484#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110483#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110482#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110481#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110480#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110479#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110478#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110477#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110476#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110474#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110473#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110470#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110466#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110464#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110463#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110462#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110461#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110460#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110458#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110456#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110455#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110454#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110452#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110450#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110448#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110447#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110446#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110445#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110444#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110442#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110439#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 110438#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110424#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 110425#L378-2 [2021-12-06 22:00:04,578 INFO L793 eck$LassoCheckResult]: Loop: 110425#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 110440#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 110425#L378-2 [2021-12-06 22:00:04,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:00:04,578 INFO L85 PathProgramCache]: Analyzing trace with hash 1044848621, now seen corresponding path program 67 times [2021-12-06 22:00:04,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:00:04,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195938739] [2021-12-06 22:00:04,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:00:04,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:00:04,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:00:05,779 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 0 proven. 2059 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:05,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:00:05,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195938739] [2021-12-06 22:00:05,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195938739] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 22:00:05,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [662766144] [2021-12-06 22:00:05,779 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 22:00:05,779 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 22:00:05,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 22:00:05,780 INFO L229 MonitoredProcess]: Starting monitored process 144 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 22:00:05,781 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (144)] Waiting until timeout for monitored process [2021-12-06 22:00:06,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:00:06,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 126 conjunts are in the unsatisfiable core [2021-12-06 22:00:06,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 22:00:07,257 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 22:00:09,120 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 22:00:09,122 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 0 proven. 2059 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:09,122 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 22:00:09,293 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2021-12-06 22:00:09,294 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2021-12-06 22:00:09,465 INFO L134 CoverageAnalysis]: Checked inductivity of 2059 backedges. 0 proven. 2059 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:09,465 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [662766144] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 22:00:09,465 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 22:00:09,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 62] total 126 [2021-12-06 22:00:09,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065018774] [2021-12-06 22:00:09,466 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 22:00:09,466 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:00:09,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:00:09,466 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 122 times [2021-12-06 22:00:09,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:00:09,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081939953] [2021-12-06 22:00:09,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:00:09,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:00:09,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:00:09,476 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:00:09,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:00:09,479 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:00:09,502 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:00:09,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2021-12-06 22:00:09,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=469, Invalid=15533, Unknown=0, NotChecked=0, Total=16002 [2021-12-06 22:00:09,503 INFO L87 Difference]: Start difference. First operand 262 states and 331 transitions. cyclomatic complexity: 73 Second operand has 127 states, 126 states have (on average 2.4285714285714284) internal successors, (306), 127 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:14,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:00:14,306 INFO L93 Difference]: Finished difference Result 445 states and 547 transitions. [2021-12-06 22:00:14,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2021-12-06 22:00:14,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 445 states and 547 transitions. [2021-12-06 22:00:14,307 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 60 [2021-12-06 22:00:14,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 445 states to 444 states and 546 transitions. [2021-12-06 22:00:14,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79 [2021-12-06 22:00:14,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79 [2021-12-06 22:00:14,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 444 states and 546 transitions. [2021-12-06 22:00:14,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 22:00:14,308 INFO L681 BuchiCegarLoop]: Abstraction has 444 states and 546 transitions. [2021-12-06 22:00:14,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 444 states and 546 transitions. [2021-12-06 22:00:14,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 444 to 384. [2021-12-06 22:00:14,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.2604166666666667) internal successors, (484), 383 states have internal predecessors, (484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:14,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 484 transitions. [2021-12-06 22:00:14,312 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 484 transitions. [2021-12-06 22:00:14,312 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 484 transitions. [2021-12-06 22:00:14,312 INFO L425 BuchiCegarLoop]: ======== Iteration 125============ [2021-12-06 22:00:14,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 484 transitions. [2021-12-06 22:00:14,313 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 58 [2021-12-06 22:00:14,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:00:14,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:00:14,313 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 30, 28, 27, 27, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:00:14,313 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 22:00:14,314 INFO L791 eck$LassoCheckResult]: Stem: 112168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 112169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 112179#L367 assume !(main_~length~0#1 < 1); 112170#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 112171#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 112172#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112180#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112361#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112360#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112359#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112358#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112357#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112356#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112355#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112354#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112352#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112350#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112347#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112345#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112342#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112335#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112328#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112329#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112351#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112322#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112346#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112343#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112341#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112309#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112336#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112330#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112325#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112323#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112318#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112316#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112312#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112310#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112303#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112278#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112300#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112298#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112295#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112293#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112264#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112290#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112257#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112253#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112251#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112249#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112246#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112243#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112240#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112237#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112234#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112231#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112228#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112222#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112219#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112216#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112213#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112209#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112205#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112203#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112199#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 112196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112193#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112434#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 112436#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 112491#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 112489#L370-4 main_~j~0#1 := 0; 112487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112486#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112485#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112484#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112483#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112482#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112481#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112480#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112479#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112478#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112477#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112476#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112474#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112473#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112470#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112466#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112464#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112463#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112462#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112461#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112460#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112458#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112456#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112455#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112454#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112452#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112450#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112448#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112447#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112446#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112445#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112444#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112442#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112440#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112438#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112437#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112374#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 112375#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112376#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 112176#L378-2 [2021-12-06 22:00:14,314 INFO L793 eck$LassoCheckResult]: Loop: 112176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 112370#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 112176#L378-2 [2021-12-06 22:00:14,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:00:14,314 INFO L85 PathProgramCache]: Analyzing trace with hash 2046456606, now seen corresponding path program 68 times [2021-12-06 22:00:14,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:00:14,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524683250] [2021-12-06 22:00:14,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:00:14,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:00:14,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:00:15,577 INFO L134 CoverageAnalysis]: Checked inductivity of 2091 backedges. 0 proven. 2091 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:15,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:00:15,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524683250] [2021-12-06 22:00:15,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524683250] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 22:00:15,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [482863644] [2021-12-06 22:00:15,577 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 22:00:15,577 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 22:00:15,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 22:00:15,582 INFO L229 MonitoredProcess]: Starting monitored process 145 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 22:00:15,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (145)] Waiting until timeout for monitored process [2021-12-06 22:00:15,849 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 22:00:15,849 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 22:00:15,854 INFO L263 TraceCheckSpWp]: Trace formula consists of 785 conjuncts, 128 conjunts are in the unsatisfiable core [2021-12-06 22:00:15,857 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 22:00:16,019 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 22:00:16,110 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 22:00:16,110 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 22:00:16,118 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 22:00:16,118 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 22:00:16,164 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 22:00:16,164 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 22:00:16,172 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 22:00:16,172 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 22:00:17,423 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 22:00:17,424 INFO L134 CoverageAnalysis]: Checked inductivity of 2091 backedges. 2 proven. 2089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:17,425 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 22:00:17,818 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2021-12-06 22:00:17,819 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2021-12-06 22:00:17,992 INFO L134 CoverageAnalysis]: Checked inductivity of 2091 backedges. 1 proven. 2089 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 22:00:17,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [482863644] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 22:00:17,992 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 22:00:17,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 63] total 95 [2021-12-06 22:00:17,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072692990] [2021-12-06 22:00:17,992 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 22:00:17,993 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:00:17,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:00:17,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 123 times [2021-12-06 22:00:17,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:00:17,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598140757] [2021-12-06 22:00:17,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:00:17,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:00:17,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:00:17,999 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:00:17,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:00:18,002 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:00:18,025 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:00:18,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2021-12-06 22:00:18,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=266, Invalid=8854, Unknown=0, NotChecked=0, Total=9120 [2021-12-06 22:00:18,026 INFO L87 Difference]: Start difference. First operand 384 states and 484 transitions. cyclomatic complexity: 106 Second operand has 96 states, 95 states have (on average 2.3157894736842106) internal successors, (220), 96 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:21,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:00:21,932 INFO L93 Difference]: Finished difference Result 436 states and 507 transitions. [2021-12-06 22:00:21,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2021-12-06 22:00:21,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 507 transitions. [2021-12-06 22:00:21,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 22:00:21,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 434 states and 505 transitions. [2021-12-06 22:00:21,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 22:00:21,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 22:00:21,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 434 states and 505 transitions. [2021-12-06 22:00:21,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 22:00:21,934 INFO L681 BuchiCegarLoop]: Abstraction has 434 states and 505 transitions. [2021-12-06 22:00:21,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states and 505 transitions. [2021-12-06 22:00:21,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 257. [2021-12-06 22:00:21,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 257 states, 257 states have (on average 1.2568093385214008) internal successors, (323), 256 states have internal predecessors, (323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:00:21,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 323 transitions. [2021-12-06 22:00:21,936 INFO L704 BuchiCegarLoop]: Abstraction has 257 states and 323 transitions. [2021-12-06 22:00:21,936 INFO L587 BuchiCegarLoop]: Abstraction has 257 states and 323 transitions. [2021-12-06 22:00:21,936 INFO L425 BuchiCegarLoop]: ======== Iteration 126============ [2021-12-06 22:00:21,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 257 states and 323 transitions. [2021-12-06 22:00:21,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 22:00:21,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:00:21,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:00:21,937 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 29, 29, 29, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:00:21,937 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 22:00:21,937 INFO L791 eck$LassoCheckResult]: Stem: 114057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 114058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 114068#L367 assume !(main_~length~0#1 < 1); 114059#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 114060#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 114061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114069#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114072#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114070#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114071#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114313#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114312#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114311#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114310#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114309#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114308#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114305#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114302#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114300#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114298#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114294#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114293#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114289#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114291#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114288#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114285#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114282#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114278#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114279#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114276#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114272#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114270#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114264#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114262#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114260#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114258#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114256#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114254#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114252#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114248#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114249#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114246#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114244#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114242#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114240#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114234#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114235#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114231#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114226#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114222#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114216#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114217#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114213#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114207#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114204#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114198#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114190#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114182#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114178#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114175#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114174#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114170#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114167#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114166#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114156#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114153#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114147#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 114140#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 114133#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 114134#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 114062#L370-4 main_~j~0#1 := 0; 114063#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114135#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114074#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114066#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114067#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114130#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114129#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114128#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114127#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114126#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114124#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114123#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114122#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114121#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114120#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114118#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114116#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114114#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114110#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114108#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114106#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114104#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114102#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114100#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114099#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114098#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114097#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114096#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114094#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114093#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114092#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114091#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114090#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114089#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114088#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114087#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114086#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114085#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114084#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114079#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114078#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114076#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 114075#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114064#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 114065#L378-2 [2021-12-06 22:00:21,937 INFO L793 eck$LassoCheckResult]: Loop: 114065#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 114077#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 114065#L378-2 [2021-12-06 22:00:21,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:00:21,937 INFO L85 PathProgramCache]: Analyzing trace with hash -922819214, now seen corresponding path program 69 times [2021-12-06 22:00:21,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:00:21,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128619162] [2021-12-06 22:00:21,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:00:21,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:00:21,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:00:23,217 INFO L134 CoverageAnalysis]: Checked inductivity of 2117 backedges. 813 proven. 1304 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:00:23,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:00:23,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128619162] [2021-12-06 22:00:23,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128619162] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 22:00:23,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [648300921] [2021-12-06 22:00:23,217 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 22:00:23,217 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 22:00:23,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 22:00:23,218 INFO L229 MonitoredProcess]: Starting monitored process 146 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 22:00:23,219 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a095e5fe-5988-4840-b073-a234c60c433f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (146)] Waiting until timeout for monitored process