./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 23:38:54,691 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 23:38:54,693 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 23:38:54,724 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 23:38:54,724 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 23:38:54,726 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 23:38:54,727 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 23:38:54,730 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 23:38:54,732 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 23:38:54,733 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 23:38:54,734 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 23:38:54,735 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 23:38:54,735 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 23:38:54,736 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 23:38:54,738 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 23:38:54,740 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 23:38:54,741 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 23:38:54,742 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 23:38:54,744 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 23:38:54,746 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 23:38:54,748 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 23:38:54,750 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 23:38:54,751 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 23:38:54,752 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 23:38:54,756 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 23:38:54,757 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 23:38:54,757 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 23:38:54,758 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 23:38:54,759 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 23:38:54,760 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 23:38:54,760 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 23:38:54,761 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 23:38:54,762 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 23:38:54,763 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 23:38:54,764 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 23:38:54,764 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 23:38:54,764 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 23:38:54,764 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 23:38:54,765 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 23:38:54,765 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 23:38:54,766 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 23:38:54,766 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-12-06 23:38:54,796 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 23:38:54,796 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 23:38:54,796 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 23:38:54,797 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 23:38:54,797 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 23:38:54,798 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 23:38:54,798 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 23:38:54,799 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 23:38:54,799 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 23:38:54,799 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 23:38:54,799 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 23:38:54,799 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 23:38:54,799 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 23:38:54,805 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 23:38:54,805 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 23:38:54,806 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 23:38:54,806 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 23:38:54,806 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 23:38:54,807 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 23:38:54,807 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2021-12-06 23:38:54,969 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 23:38:54,983 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 23:38:54,985 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 23:38:54,986 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 23:38:54,986 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 23:38:54,987 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2021-12-06 23:38:55,034 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/data/524b9ed6a/3d1c4c85fa8d4c79bfe030f563f8186a/FLAG9bd2292e5 [2021-12-06 23:38:55,439 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 23:38:55,440 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2021-12-06 23:38:55,449 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/data/524b9ed6a/3d1c4c85fa8d4c79bfe030f563f8186a/FLAG9bd2292e5 [2021-12-06 23:38:55,458 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/data/524b9ed6a/3d1c4c85fa8d4c79bfe030f563f8186a [2021-12-06 23:38:55,460 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 23:38:55,461 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 23:38:55,462 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 23:38:55,462 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 23:38:55,464 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 23:38:55,465 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,466 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c79194c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55, skipping insertion in model container [2021-12-06 23:38:55,466 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,476 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 23:38:55,509 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 23:38:55,727 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 23:38:55,733 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 23:38:55,769 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 23:38:55,796 INFO L208 MainTranslator]: Completed translation [2021-12-06 23:38:55,797 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55 WrapperNode [2021-12-06 23:38:55,797 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 23:38:55,797 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 23:38:55,798 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 23:38:55,798 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 23:38:55,803 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,815 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,832 INFO L137 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2021-12-06 23:38:55,832 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 23:38:55,833 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 23:38:55,833 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 23:38:55,833 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 23:38:55,838 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,839 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,841 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,841 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,846 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,850 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,851 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,853 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 23:38:55,854 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 23:38:55,854 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 23:38:55,855 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 23:38:55,855 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (1/1) ... [2021-12-06 23:38:55,863 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:55,872 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:55,882 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:55,884 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 23:38:55,912 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-12-06 23:38:55,912 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 23:38:55,912 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 23:38:55,912 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 23:38:55,912 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 23:38:55,912 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 23:38:55,965 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 23:38:55,966 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 23:38:56,048 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 23:38:56,052 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 23:38:56,053 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 23:38:56,054 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 11:38:56 BoogieIcfgContainer [2021-12-06 23:38:56,054 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 23:38:56,055 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 23:38:56,055 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 23:38:56,057 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 23:38:56,058 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 23:38:56,058 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 11:38:55" (1/3) ... [2021-12-06 23:38:56,059 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c8c0faa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 11:38:56, skipping insertion in model container [2021-12-06 23:38:56,059 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 23:38:56,059 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 11:38:55" (2/3) ... [2021-12-06 23:38:56,059 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c8c0faa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 11:38:56, skipping insertion in model container [2021-12-06 23:38:56,060 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 23:38:56,060 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 11:38:56" (3/3) ... [2021-12-06 23:38:56,061 INFO L388 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2021-12-06 23:38:56,093 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 23:38:56,093 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 23:38:56,093 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 23:38:56,093 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 23:38:56,093 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 23:38:56,093 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 23:38:56,093 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 23:38:56,094 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 23:38:56,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:56,117 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-12-06 23:38:56,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:56,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:56,122 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-12-06 23:38:56,122 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-12-06 23:38:56,122 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 23:38:56,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:56,124 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-12-06 23:38:56,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:56,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:56,125 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-12-06 23:38:56,125 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-12-06 23:38:56,129 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11#L367true assume !(main_~length~0#1 < 1); 8#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6#L370-3true [2021-12-06 23:38:56,130 INFO L793 eck$LassoCheckResult]: Loop: 6#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13#L372true assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6#L370-3true [2021-12-06 23:38:56,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:56,134 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2021-12-06 23:38:56,140 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:56,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946243650] [2021-12-06 23:38:56,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:56,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:56,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,216 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:56,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,236 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:56,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:56,238 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2021-12-06 23:38:56,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:56,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690996988] [2021-12-06 23:38:56,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:56,239 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:56,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,254 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:56,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,265 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:56,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:56,267 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2021-12-06 23:38:56,267 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:56,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320722983] [2021-12-06 23:38:56,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:56,267 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:56,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,285 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:56,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:56,308 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:56,499 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 23:38:56,500 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 23:38:56,500 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 23:38:56,500 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 23:38:56,500 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 23:38:56,500 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,500 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 23:38:56,500 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 23:38:56,500 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2021-12-06 23:38:56,500 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 23:38:56,500 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 23:38:56,516 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,523 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,525 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,526 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,592 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,593 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,595 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,596 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,598 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,600 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,602 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:56,723 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 23:38:56,726 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 23:38:56,728 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,729 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,730 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-06 23:38:56,730 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,738 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,738 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:56,738 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,738 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,739 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,740 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:56,740 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:56,742 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,761 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-06 23:38:56,761 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,762 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-06 23:38:56,764 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,771 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,771 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,771 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,771 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,774 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:56,774 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:56,776 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,795 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2021-12-06 23:38:56,795 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,796 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-06 23:38:56,797 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,804 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,804 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:56,804 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,804 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,804 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,805 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:56,805 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:56,806 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-12-06 23:38:56,826 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,827 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,828 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-06 23:38:56,828 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,836 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,836 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:56,836 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,836 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,836 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,837 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:56,837 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:56,838 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,857 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-12-06 23:38:56,857 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,857 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,858 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,858 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-06 23:38:56,859 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,866 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,866 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:56,866 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,866 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,866 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,867 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:56,867 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:56,868 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,886 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2021-12-06 23:38:56,886 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,887 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,888 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-06 23:38:56,888 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,895 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,895 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,895 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,895 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,897 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:56,897 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:56,900 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,918 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2021-12-06 23:38:56,918 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,919 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,920 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-06 23:38:56,921 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,929 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,933 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:56,933 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:56,937 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:56,956 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-12-06 23:38:56,956 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:56,956 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:56,957 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:56,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-12-06 23:38:56,958 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:56,965 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:56,965 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:56,965 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:56,965 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:56,970 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:56,970 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:56,979 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 23:38:57,003 INFO L443 ModelExtractionUtils]: Simplification made 13 calls to the SMT solver. [2021-12-06 23:38:57,003 INFO L444 ModelExtractionUtils]: 6 out of 22 variables were initially zero. Simplification set additionally 12 variables to zero. [2021-12-06 23:38:57,004 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,005 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,005 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,006 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-12-06 23:38:57,006 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 23:38:57,016 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 23:38:57,016 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 23:38:57,017 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2021-12-06 23:38:57,048 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-12-06 23:38:57,055 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-12-06 23:38:57,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:57,102 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-06 23:38:57,103 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:57,104 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-12-06 23:38:57,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:57,120 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 23:38:57,120 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:57,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:57,163 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-12-06 23:38:57,164 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:57,198 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2021-12-06 23:38:57,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-12-06 23:38:57,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:57,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2021-12-06 23:38:57,204 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2021-12-06 23:38:57,205 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:57,205 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2021-12-06 23:38:57,205 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:57,205 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2021-12-06 23:38:57,205 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:57,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2021-12-06 23:38:57,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:57,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2021-12-06 23:38:57,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-12-06 23:38:57,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-12-06 23:38:57,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2021-12-06 23:38:57,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 23:38:57,212 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 23:38:57,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2021-12-06 23:38:57,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-12-06 23:38:57,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:57,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2021-12-06 23:38:57,230 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 23:38:57,230 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-12-06 23:38:57,230 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 23:38:57,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2021-12-06 23:38:57,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:57,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:57,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:57,231 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:57,231 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:57,231 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 121#L367 assume !(main_~length~0#1 < 1); 115#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 116#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 117#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 118#L370-4 main_~j~0#1 := 0; 119#L378-2 [2021-12-06 23:38:57,231 INFO L793 eck$LassoCheckResult]: Loop: 119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 120#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 119#L378-2 [2021-12-06 23:38:57,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2021-12-06 23:38:57,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:57,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711837814] [2021-12-06 23:38:57,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:57,232 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:57,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:57,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:57,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:38:57,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711837814] [2021-12-06 23:38:57,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711837814] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 23:38:57,267 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 23:38:57,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 23:38:57,268 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813019658] [2021-12-06 23:38:57,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 23:38:57,269 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:38:57,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,270 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2021-12-06 23:38:57,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:57,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346585394] [2021-12-06 23:38:57,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:57,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:57,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,276 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:57,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,282 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:57,320 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:38:57,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 23:38:57,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-12-06 23:38:57,323 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:57,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:38:57,341 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2021-12-06 23:38:57,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 23:38:57,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2021-12-06 23:38:57,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:57,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2021-12-06 23:38:57,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-12-06 23:38:57,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-12-06 23:38:57,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2021-12-06 23:38:57,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 23:38:57,344 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 19 transitions. [2021-12-06 23:38:57,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2021-12-06 23:38:57,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2021-12-06 23:38:57,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:57,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2021-12-06 23:38:57,345 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-12-06 23:38:57,345 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-12-06 23:38:57,345 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 23:38:57,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2021-12-06 23:38:57,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:57,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:57,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:57,346 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:57,346 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:57,346 INFO L791 eck$LassoCheckResult]: Stem: 146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 154#L367 assume !(main_~length~0#1 < 1); 148#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 149#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 155#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 156#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 151#L370-4 main_~j~0#1 := 0; 152#L378-2 [2021-12-06 23:38:57,346 INFO L793 eck$LassoCheckResult]: Loop: 152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 153#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 152#L378-2 [2021-12-06 23:38:57,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2021-12-06 23:38:57,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:57,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450565234] [2021-12-06 23:38:57,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:57,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:57,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,358 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:57,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,369 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:57,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,370 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2021-12-06 23:38:57,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:57,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024128252] [2021-12-06 23:38:57,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:57,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:57,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,375 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:57,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,380 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:57,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:57,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2021-12-06 23:38:57,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:57,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404549173] [2021-12-06 23:38:57,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:57,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:57,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,397 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:57,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:57,412 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:57,586 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 23:38:57,586 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 23:38:57,586 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 23:38:57,586 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 23:38:57,586 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 23:38:57,586 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,587 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 23:38:57,587 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 23:38:57,587 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2021-12-06 23:38:57,587 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 23:38:57,587 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 23:38:57,589 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,592 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,593 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,673 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,676 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,677 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,680 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,682 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 23:38:57,850 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 23:38:57,850 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 23:38:57,851 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,851 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,852 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,852 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-12-06 23:38:57,854 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:57,862 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:57,863 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:57,863 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:57,863 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:57,863 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:57,863 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:57,864 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:57,865 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:57,884 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2021-12-06 23:38:57,885 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,886 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,887 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-12-06 23:38:57,888 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:57,894 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:57,895 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 23:38:57,895 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:57,895 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:57,895 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:57,895 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 23:38:57,895 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 23:38:57,896 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:57,915 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2021-12-06 23:38:57,916 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,917 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,917 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-12-06 23:38:57,918 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:57,924 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:57,925 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:57,925 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:57,925 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:57,926 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:57,926 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:57,929 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 23:38:57,947 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2021-12-06 23:38:57,947 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,947 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,948 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-12-06 23:38:57,949 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 23:38:57,957 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 23:38:57,957 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 23:38:57,957 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 23:38:57,957 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 23:38:57,962 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 23:38:57,962 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 23:38:57,971 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 23:38:57,986 INFO L443 ModelExtractionUtils]: Simplification made 9 calls to the SMT solver. [2021-12-06 23:38:57,987 INFO L444 ModelExtractionUtils]: 5 out of 25 variables were initially zero. Simplification set additionally 16 variables to zero. [2021-12-06 23:38:57,987 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 23:38:57,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:57,988 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 23:38:57,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-12-06 23:38:57,989 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 23:38:57,997 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 23:38:57,997 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 23:38:57,998 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2, ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1) = 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2 - 1*ULTIMATE.start_main_~arr~0#1.offset - 4*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2021-12-06 23:38:58,018 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2021-12-06 23:38:58,023 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-12-06 23:38:58,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-06 23:38:58,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:58,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,059 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 23:38:58,059 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:58,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,071 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-12-06 23:38:58,072 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,082 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 16 states and 22 transitions. Complement of second has 5 states. [2021-12-06 23:38:58,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-12-06 23:38:58,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 14 transitions. [2021-12-06 23:38:58,084 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 2 letters. [2021-12-06 23:38:58,084 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:58,084 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 12 letters. Loop has 2 letters. [2021-12-06 23:38:58,084 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:58,085 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 4 letters. [2021-12-06 23:38:58,085 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 23:38:58,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 22 transitions. [2021-12-06 23:38:58,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:58,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 22 transitions. [2021-12-06 23:38:58,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-12-06 23:38:58,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-12-06 23:38:58,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 22 transitions. [2021-12-06 23:38:58,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:38:58,087 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-12-06 23:38:58,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 22 transitions. [2021-12-06 23:38:58,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2021-12-06 23:38:58,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.375) internal successors, (22), 15 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 22 transitions. [2021-12-06 23:38:58,090 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-12-06 23:38:58,090 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-12-06 23:38:58,090 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 23:38:58,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 22 transitions. [2021-12-06 23:38:58,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:58,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:58,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:58,091 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:58,091 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:58,092 INFO L791 eck$LassoCheckResult]: Stem: 243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 254#L367 assume !(main_~length~0#1 < 1); 245#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 246#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 247#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 255#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 257#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 256#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 248#L370-4 main_~j~0#1 := 0; 249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 250#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 251#L378-2 [2021-12-06 23:38:58,092 INFO L793 eck$LassoCheckResult]: Loop: 251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 258#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 251#L378-2 [2021-12-06 23:38:58,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2021-12-06 23:38:58,092 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:58,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409679149] [2021-12-06 23:38:58,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,093 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:58,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:38:58,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409679149] [2021-12-06 23:38:58,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409679149] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:38:58,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [629715077] [2021-12-06 23:38:58,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,236 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:38:58,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:58,236 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:38:58,237 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-12-06 23:38:58,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,261 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 17 conjunts are in the unsatisfiable core [2021-12-06 23:38:58,262 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:58,299 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-12-06 23:38:58,346 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2021-12-06 23:38:58,354 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,354 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:38:58,418 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-12-06 23:38:58,421 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-12-06 23:38:58,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [629715077] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:38:58,433 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:38:58,433 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2021-12-06 23:38:58,433 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007996575] [2021-12-06 23:38:58,433 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:38:58,434 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:38:58,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,434 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2021-12-06 23:38:58,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:58,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87096113] [2021-12-06 23:38:58,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:58,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:58,438 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:58,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:58,442 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:58,482 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:38:58,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-12-06 23:38:58,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2021-12-06 23:38:58,483 INFO L87 Difference]: Start difference. First operand 16 states and 22 transitions. cyclomatic complexity: 9 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,500 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2021-12-06 23:38:58,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:38:58,572 INFO L93 Difference]: Finished difference Result 30 states and 41 transitions. [2021-12-06 23:38:58,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 23:38:58,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 41 transitions. [2021-12-06 23:38:58,574 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:38:58,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 40 transitions. [2021-12-06 23:38:58,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 23:38:58,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 23:38:58,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 40 transitions. [2021-12-06 23:38:58,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:38:58,576 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 40 transitions. [2021-12-06 23:38:58,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 40 transitions. [2021-12-06 23:38:58,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2021-12-06 23:38:58,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2021-12-06 23:38:58,578 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2021-12-06 23:38:58,578 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2021-12-06 23:38:58,578 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 23:38:58,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2021-12-06 23:38:58,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:58,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:58,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:58,579 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:58,579 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:58,579 INFO L791 eck$LassoCheckResult]: Stem: 379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 390#L367 assume !(main_~length~0#1 < 1); 381#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 382#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 383#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 391#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 399#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 398#L370-4 main_~j~0#1 := 0; 397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 388#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 389#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 386#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 387#L378-2 [2021-12-06 23:38:58,579 INFO L793 eck$LassoCheckResult]: Loop: 387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 395#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 387#L378-2 [2021-12-06 23:38:58,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,579 INFO L85 PathProgramCache]: Analyzing trace with hash -645453020, now seen corresponding path program 1 times [2021-12-06 23:38:58,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:58,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617549553] [2021-12-06 23:38:58,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:58,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,657 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:38:58,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617549553] [2021-12-06 23:38:58,658 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617549553] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:38:58,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1960109281] [2021-12-06 23:38:58,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,659 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:38:58,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:58,660 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:38:58,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-12-06 23:38:58,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,689 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 23:38:58,690 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:58,736 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,736 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:38:58,761 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,761 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1960109281] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:38:58,761 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:38:58,761 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2021-12-06 23:38:58,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129579164] [2021-12-06 23:38:58,762 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:38:58,762 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:38:58,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,762 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2021-12-06 23:38:58,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:58,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318711280] [2021-12-06 23:38:58,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,763 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:58,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:58,767 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:58,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:58,772 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:58,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:38:58,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-12-06 23:38:58,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2021-12-06 23:38:58,803 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 13 Second operand has 15 states, 15 states have (on average 1.8666666666666667) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:38:58,887 INFO L93 Difference]: Finished difference Result 47 states and 63 transitions. [2021-12-06 23:38:58,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 23:38:58,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 63 transitions. [2021-12-06 23:38:58,889 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:38:58,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 42 states and 56 transitions. [2021-12-06 23:38:58,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-12-06 23:38:58,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-12-06 23:38:58,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 56 transitions. [2021-12-06 23:38:58,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:38:58,890 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 56 transitions. [2021-12-06 23:38:58,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 56 transitions. [2021-12-06 23:38:58,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 37. [2021-12-06 23:38:58,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3513513513513513) internal successors, (50), 36 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:58,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 50 transitions. [2021-12-06 23:38:58,892 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2021-12-06 23:38:58,892 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2021-12-06 23:38:58,892 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 23:38:58,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 50 transitions. [2021-12-06 23:38:58,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:38:58,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:58,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:58,894 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:58,894 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:58,894 INFO L791 eck$LassoCheckResult]: Stem: 552#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 553#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 563#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 564#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 556#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 557#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 582#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 580#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 581#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 579#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 578#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 576#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 558#L370-4 main_~j~0#1 := 0; 559#L378-2 [2021-12-06 23:38:58,894 INFO L793 eck$LassoCheckResult]: Loop: 559#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 560#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 559#L378-2 [2021-12-06 23:38:58,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:58,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2021-12-06 23:38:58,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:58,894 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857848770] [2021-12-06 23:38:58,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:58,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:58,948 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:58,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:38:58,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857848770] [2021-12-06 23:38:58,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857848770] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:38:58,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [566902739] [2021-12-06 23:38:58,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:58,949 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:38:58,949 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:58,972 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:38:58,973 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-12-06 23:38:59,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:59,001 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 23:38:59,002 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:59,033 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:59,033 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 23:38:59,034 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [566902739] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 23:38:59,034 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 23:38:59,034 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2021-12-06 23:38:59,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780528957] [2021-12-06 23:38:59,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 23:38:59,035 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:38:59,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:59,035 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2021-12-06 23:38:59,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:59,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401740356] [2021-12-06 23:38:59,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:59,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:59,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:59,039 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:38:59,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:38:59,044 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:38:59,074 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:38:59,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 23:38:59,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2021-12-06 23:38:59,075 INFO L87 Difference]: Start difference. First operand 37 states and 50 transitions. cyclomatic complexity: 20 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:59,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:38:59,090 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2021-12-06 23:38:59,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 23:38:59,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 39 transitions. [2021-12-06 23:38:59,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:59,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 24 states and 32 transitions. [2021-12-06 23:38:59,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:38:59,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:38:59,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 32 transitions. [2021-12-06 23:38:59,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:38:59,092 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-12-06 23:38:59,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 32 transitions. [2021-12-06 23:38:59,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2021-12-06 23:38:59,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:38:59,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2021-12-06 23:38:59,093 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-12-06 23:38:59,093 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-12-06 23:38:59,094 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 23:38:59,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 32 transitions. [2021-12-06 23:38:59,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:38:59,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:38:59,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:38:59,094 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:38:59,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:38:59,095 INFO L791 eck$LassoCheckResult]: Stem: 668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 677#L367 assume !(main_~length~0#1 < 1); 666#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 667#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 670#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 678#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 679#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 680#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 688#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 686#L370-4 main_~j~0#1 := 0; 685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 673#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 674#L378-2 [2021-12-06 23:38:59,095 INFO L793 eck$LassoCheckResult]: Loop: 674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 683#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 674#L378-2 [2021-12-06 23:38:59,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:38:59,095 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2021-12-06 23:38:59,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:38:59,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960017807] [2021-12-06 23:38:59,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:59,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:38:59,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:59,228 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:59,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:38:59,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960017807] [2021-12-06 23:38:59,229 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960017807] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:38:59,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1588983872] [2021-12-06 23:38:59,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:38:59,229 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:38:59,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:38:59,230 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:38:59,230 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-12-06 23:38:59,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:38:59,261 INFO L263 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 22 conjunts are in the unsatisfiable core [2021-12-06 23:38:59,262 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:38:59,278 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:38:59,322 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:38:59,323 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2021-12-06 23:38:59,336 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:38:59,336 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2021-12-06 23:38:59,365 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2021-12-06 23:38:59,374 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:38:59,374 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:39:35,486 WARN L227 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 22 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 23:39:35,544 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 43 [2021-12-06 23:39:35,547 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 74 [2021-12-06 23:39:35,582 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:35,582 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1588983872] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:39:35,582 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:39:35,582 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2021-12-06 23:39:35,582 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776383475] [2021-12-06 23:39:35,582 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:39:35,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:39:35,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:35,583 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2021-12-06 23:39:35,583 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:35,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210038431] [2021-12-06 23:39:35,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:35,583 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:35,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:35,586 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:39:35,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:35,589 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:39:35,624 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:39:35,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-12-06 23:39:35,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=266, Unknown=2, NotChecked=0, Total=342 [2021-12-06 23:39:35,625 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. cyclomatic complexity: 12 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:35,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:39:35,765 INFO L93 Difference]: Finished difference Result 51 states and 69 transitions. [2021-12-06 23:39:35,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-12-06 23:39:35,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 69 transitions. [2021-12-06 23:39:35,767 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8 [2021-12-06 23:39:35,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 68 transitions. [2021-12-06 23:39:35,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2021-12-06 23:39:35,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2021-12-06 23:39:35,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 68 transitions. [2021-12-06 23:39:35,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:39:35,768 INFO L681 BuchiCegarLoop]: Abstraction has 50 states and 68 transitions. [2021-12-06 23:39:35,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 68 transitions. [2021-12-06 23:39:35,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 26. [2021-12-06 23:39:35,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3461538461538463) internal successors, (35), 25 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:35,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 35 transitions. [2021-12-06 23:39:35,770 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 35 transitions. [2021-12-06 23:39:35,770 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 35 transitions. [2021-12-06 23:39:35,770 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 23:39:35,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 35 transitions. [2021-12-06 23:39:35,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:39:35,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:39:35,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:39:35,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:39:35,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:39:35,771 INFO L791 eck$LassoCheckResult]: Stem: 854#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 855#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 865#L367 assume !(main_~length~0#1 < 1); 856#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 857#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 866#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 872#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 868#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 876#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 875#L370-4 main_~j~0#1 := 0; 874#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 863#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 861#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 862#L378-2 [2021-12-06 23:39:35,771 INFO L793 eck$LassoCheckResult]: Loop: 862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 871#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 862#L378-2 [2021-12-06 23:39:35,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:35,771 INFO L85 PathProgramCache]: Analyzing trace with hash 123352160, now seen corresponding path program 1 times [2021-12-06 23:39:35,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:35,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529773059] [2021-12-06 23:39:35,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:35,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:35,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:39:35,832 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:35,833 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:39:35,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529773059] [2021-12-06 23:39:35,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529773059] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:39:35,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [550339602] [2021-12-06 23:39:35,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:35,833 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:39:35,833 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:39:35,834 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:39:35,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-12-06 23:39:35,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:39:35,866 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 15 conjunts are in the unsatisfiable core [2021-12-06 23:39:35,867 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:39:35,884 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:39:35,916 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:39:35,918 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:35,918 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:39:35,960 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 23:39:35,967 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 26 [2021-12-06 23:39:35,981 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:35,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [550339602] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:39:35,981 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:39:35,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 13 [2021-12-06 23:39:35,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117905982] [2021-12-06 23:39:35,981 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:39:35,981 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:39:35,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:35,982 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2021-12-06 23:39:35,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:35,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746959996] [2021-12-06 23:39:35,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:35,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:35,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:35,985 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:39:35,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:35,988 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:39:36,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:39:36,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-12-06 23:39:36,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2021-12-06 23:39:36,017 INFO L87 Difference]: Start difference. First operand 26 states and 35 transitions. cyclomatic complexity: 13 Second operand has 14 states, 13 states have (on average 2.230769230769231) internal successors, (29), 14 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:36,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:39:36,092 INFO L93 Difference]: Finished difference Result 41 states and 54 transitions. [2021-12-06 23:39:36,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-06 23:39:36,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 54 transitions. [2021-12-06 23:39:36,093 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:39:36,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 53 transitions. [2021-12-06 23:39:36,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 23:39:36,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 23:39:36,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 53 transitions. [2021-12-06 23:39:36,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:39:36,094 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 53 transitions. [2021-12-06 23:39:36,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 53 transitions. [2021-12-06 23:39:36,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 33. [2021-12-06 23:39:36,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.3333333333333333) internal successors, (44), 32 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:36,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 44 transitions. [2021-12-06 23:39:36,097 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 44 transitions. [2021-12-06 23:39:36,097 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 44 transitions. [2021-12-06 23:39:36,097 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 23:39:36,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 44 transitions. [2021-12-06 23:39:36,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:39:36,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:39:36,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:39:36,099 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:39:36,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:39:36,100 INFO L791 eck$LassoCheckResult]: Stem: 1036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1047#L367 assume !(main_~length~0#1 < 1); 1038#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1039#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1048#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1062#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1050#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1054#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1055#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1045#L370-4 main_~j~0#1 := 0; 1046#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1043#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1041#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1042#L378-2 [2021-12-06 23:39:36,100 INFO L793 eck$LassoCheckResult]: Loop: 1042#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1056#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1042#L378-2 [2021-12-06 23:39:36,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:36,100 INFO L85 PathProgramCache]: Analyzing trace with hash -685994466, now seen corresponding path program 2 times [2021-12-06 23:39:36,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:36,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54528917] [2021-12-06 23:39:36,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:36,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:36,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:39:36,209 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:36,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:39:36,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54528917] [2021-12-06 23:39:36,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54528917] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:39:36,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [92678973] [2021-12-06 23:39:36,210 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:39:36,210 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:39:36,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:39:36,211 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:39:36,212 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-12-06 23:39:36,241 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:39:36,242 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:39:36,242 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 17 conjunts are in the unsatisfiable core [2021-12-06 23:39:36,243 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:39:36,261 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:39:36,322 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:39:36,324 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:36,324 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:39:36,375 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:39:36,378 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:39:36,391 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:36,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [92678973] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:39:36,391 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:39:36,391 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 13 [2021-12-06 23:39:36,391 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489389806] [2021-12-06 23:39:36,391 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:39:36,391 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:39:36,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:36,392 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2021-12-06 23:39:36,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:36,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791290568] [2021-12-06 23:39:36,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:36,392 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:36,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:36,395 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:39:36,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:39:36,397 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:39:36,428 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:39:36,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-12-06 23:39:36,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2021-12-06 23:39:36,429 INFO L87 Difference]: Start difference. First operand 33 states and 44 transitions. cyclomatic complexity: 15 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:36,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:39:36,542 INFO L93 Difference]: Finished difference Result 45 states and 58 transitions. [2021-12-06 23:39:36,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 23:39:36,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 58 transitions. [2021-12-06 23:39:36,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:39:36,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 57 transitions. [2021-12-06 23:39:36,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-12-06 23:39:36,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-12-06 23:39:36,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 57 transitions. [2021-12-06 23:39:36,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:39:36,544 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 57 transitions. [2021-12-06 23:39:36,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 57 transitions. [2021-12-06 23:39:36,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2021-12-06 23:39:36,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.3333333333333333) internal successors, (44), 32 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:39:36,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 44 transitions. [2021-12-06 23:39:36,546 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 44 transitions. [2021-12-06 23:39:36,546 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 44 transitions. [2021-12-06 23:39:36,546 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 23:39:36,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 44 transitions. [2021-12-06 23:39:36,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:39:36,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:39:36,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:39:36,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:39:36,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:39:36,547 INFO L791 eck$LassoCheckResult]: Stem: 1231#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1242#L367 assume !(main_~length~0#1 < 1); 1233#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1234#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1235#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1243#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1263#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1262#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1260#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1261#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1246#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1249#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1250#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1240#L370-4 main_~j~0#1 := 0; 1241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1236#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1237#L378-2 [2021-12-06 23:39:36,547 INFO L793 eck$LassoCheckResult]: Loop: 1237#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1251#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1237#L378-2 [2021-12-06 23:39:36,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:39:36,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1119422815, now seen corresponding path program 2 times [2021-12-06 23:39:36,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:39:36,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144391403] [2021-12-06 23:39:36,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:39:36,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:39:36,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:39:36,730 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:36,730 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:39:36,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144391403] [2021-12-06 23:39:36,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144391403] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:39:36,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1921655802] [2021-12-06 23:39:36,731 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:39:36,731 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:39:36,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:39:36,733 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:39:36,733 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-12-06 23:39:36,766 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:39:36,766 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:39:36,767 INFO L263 TraceCheckSpWp]: Trace formula consists of 96 conjuncts, 24 conjunts are in the unsatisfiable core [2021-12-06 23:39:36,768 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:39:36,793 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:39:36,846 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:39:36,846 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:39:36,855 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:39:36,855 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:39:36,875 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:39:36,875 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:39:36,917 INFO L173 IndexEqualityManager]: detected equality via solver [2021-12-06 23:39:36,918 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:39:36,918 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 12 [2021-12-06 23:39:36,927 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:39:36,927 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:40:49,505 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 27 [2021-12-06 23:40:49,510 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 98 [2021-12-06 23:40:49,563 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 23:40:49,563 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1921655802] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:40:49,563 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:40:49,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2021-12-06 23:40:49,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717921234] [2021-12-06 23:40:49,563 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:40:49,564 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:40:49,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:40:49,564 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2021-12-06 23:40:49,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:40:49,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130276797] [2021-12-06 23:40:49,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:40:49,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:40:49,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:40:49,567 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:40:49,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:40:49,569 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:40:49,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:40:49,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-12-06 23:40:49,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=560, Unknown=4, NotChecked=0, Total=702 [2021-12-06 23:40:49,597 INFO L87 Difference]: Start difference. First operand 33 states and 44 transitions. cyclomatic complexity: 15 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:40:49,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:40:49,757 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2021-12-06 23:40:49,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 23:40:49,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 45 transitions. [2021-12-06 23:40:49,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:40:49,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 34 states and 44 transitions. [2021-12-06 23:40:49,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-12-06 23:40:49,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-12-06 23:40:49,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 44 transitions. [2021-12-06 23:40:49,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:40:49,759 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 44 transitions. [2021-12-06 23:40:49,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 44 transitions. [2021-12-06 23:40:49,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2021-12-06 23:40:49,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.3103448275862069) internal successors, (38), 28 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:40:49,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 38 transitions. [2021-12-06 23:40:49,760 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 38 transitions. [2021-12-06 23:40:49,760 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 38 transitions. [2021-12-06 23:40:49,760 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 23:40:49,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 38 transitions. [2021-12-06 23:40:49,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:40:49,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:40:49,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:40:49,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:40:49,761 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:40:49,761 INFO L791 eck$LassoCheckResult]: Stem: 1441#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1452#L367 assume !(main_~length~0#1 < 1); 1443#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1444#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1445#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1453#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1468#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1454#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1455#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1465#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1464#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1463#L370-4 main_~j~0#1 := 0; 1462#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1461#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1458#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1450#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1448#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1449#L378-2 [2021-12-06 23:40:49,761 INFO L793 eck$LassoCheckResult]: Loop: 1449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1460#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1449#L378-2 [2021-12-06 23:40:49,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:40:49,762 INFO L85 PathProgramCache]: Analyzing trace with hash -1717659101, now seen corresponding path program 2 times [2021-12-06 23:40:49,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:40:49,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634512703] [2021-12-06 23:40:49,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:40:49,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:40:49,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:40:49,836 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:40:49,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:40:49,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634512703] [2021-12-06 23:40:49,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634512703] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:40:49,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [340914713] [2021-12-06 23:40:49,836 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:40:49,836 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:40:49,836 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:40:49,837 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:40:49,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-12-06 23:40:49,868 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:40:49,868 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:40:49,869 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 23:40:49,870 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:40:49,941 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:40:49,942 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:40:49,981 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:40:49,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [340914713] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:40:49,981 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:40:49,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2021-12-06 23:40:49,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376187365] [2021-12-06 23:40:49,981 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:40:49,982 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:40:49,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:40:49,982 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2021-12-06 23:40:49,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:40:49,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225556479] [2021-12-06 23:40:49,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:40:49,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:40:49,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:40:49,985 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:40:49,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:40:49,987 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:40:50,022 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:40:50,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-12-06 23:40:50,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=316, Unknown=0, NotChecked=0, Total=380 [2021-12-06 23:40:50,023 INFO L87 Difference]: Start difference. First operand 29 states and 38 transitions. cyclomatic complexity: 13 Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:40:50,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:40:50,149 INFO L93 Difference]: Finished difference Result 41 states and 52 transitions. [2021-12-06 23:40:50,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 23:40:50,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 52 transitions. [2021-12-06 23:40:50,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:40:50,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 35 states and 45 transitions. [2021-12-06 23:40:50,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:40:50,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:40:50,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 45 transitions. [2021-12-06 23:40:50,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:40:50,150 INFO L681 BuchiCegarLoop]: Abstraction has 35 states and 45 transitions. [2021-12-06 23:40:50,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 45 transitions. [2021-12-06 23:40:50,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2021-12-06 23:40:50,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2580645161290323) internal successors, (39), 30 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:40:50,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 39 transitions. [2021-12-06 23:40:50,152 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 39 transitions. [2021-12-06 23:40:50,152 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 39 transitions. [2021-12-06 23:40:50,152 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 23:40:50,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 39 transitions. [2021-12-06 23:40:50,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:40:50,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:40:50,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:40:50,153 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:40:50,153 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:40:50,153 INFO L791 eck$LassoCheckResult]: Stem: 1654#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1665#L367 assume !(main_~length~0#1 < 1); 1656#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1657#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1658#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1666#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1668#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1672#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1671#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1659#L370-4 main_~j~0#1 := 0; 1660#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1663#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1661#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1662#L378-2 [2021-12-06 23:40:50,153 INFO L793 eck$LassoCheckResult]: Loop: 1662#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1674#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1662#L378-2 [2021-12-06 23:40:50,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:40:50,153 INFO L85 PathProgramCache]: Analyzing trace with hash 2023500642, now seen corresponding path program 3 times [2021-12-06 23:40:50,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:40:50,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178683781] [2021-12-06 23:40:50,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:40:50,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:40:50,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:40:50,220 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:40:50,220 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:40:50,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178683781] [2021-12-06 23:40:50,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178683781] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:40:50,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1327123460] [2021-12-06 23:40:50,220 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:40:50,220 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:40:50,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:40:50,221 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:40:50,222 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-12-06 23:40:50,255 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-12-06 23:40:50,255 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:40:50,256 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 18 conjunts are in the unsatisfiable core [2021-12-06 23:40:50,257 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:40:50,273 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:40:50,311 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:40:50,311 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:40:50,344 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:40:50,345 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:40:50,345 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:42:38,463 WARN L227 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 23 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 23:42:38,475 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2021-12-06 23:42:38,478 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 80 [2021-12-06 23:42:38,501 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:38,501 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1327123460] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:42:38,501 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:42:38,501 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 17 [2021-12-06 23:42:38,502 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150099289] [2021-12-06 23:42:38,502 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:42:38,502 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:42:38,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:38,502 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2021-12-06 23:42:38,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:38,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967477178] [2021-12-06 23:42:38,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:38,502 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:38,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:38,505 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:42:38,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:38,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:42:38,534 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:42:38,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 23:42:38,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=242, Unknown=7, NotChecked=0, Total=306 [2021-12-06 23:42:38,535 INFO L87 Difference]: Start difference. First operand 31 states and 39 transitions. cyclomatic complexity: 12 Second operand has 18 states, 17 states have (on average 2.0588235294117645) internal successors, (35), 18 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:38,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:42:38,602 INFO L93 Difference]: Finished difference Result 45 states and 57 transitions. [2021-12-06 23:42:38,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 23:42:38,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 57 transitions. [2021-12-06 23:42:38,603 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:42:38,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 56 transitions. [2021-12-06 23:42:38,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 23:42:38,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 23:42:38,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2021-12-06 23:42:38,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:42:38,603 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 56 transitions. [2021-12-06 23:42:38,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2021-12-06 23:42:38,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 34. [2021-12-06 23:42:38,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2941176470588236) internal successors, (44), 33 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:38,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 44 transitions. [2021-12-06 23:42:38,605 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 44 transitions. [2021-12-06 23:42:38,605 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 44 transitions. [2021-12-06 23:42:38,605 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 23:42:38,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 44 transitions. [2021-12-06 23:42:38,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:38,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:42:38,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:42:38,606 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:42:38,606 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:42:38,606 INFO L791 eck$LassoCheckResult]: Stem: 1867#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1878#L367 assume !(main_~length~0#1 < 1); 1869#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1870#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1871#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1879#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1885#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1880#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1881#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1888#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1899#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1897#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1876#L370-4 main_~j~0#1 := 0; 1877#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1874#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1875#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1872#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1873#L378-2 [2021-12-06 23:42:38,606 INFO L793 eck$LassoCheckResult]: Loop: 1873#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1894#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1873#L378-2 [2021-12-06 23:42:38,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:38,607 INFO L85 PathProgramCache]: Analyzing trace with hash -761055450, now seen corresponding path program 4 times [2021-12-06 23:42:38,607 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:38,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582718288] [2021-12-06 23:42:38,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:38,607 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:38,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:38,717 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:38,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:42:38,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582718288] [2021-12-06 23:42:38,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582718288] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:42:38,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1475763812] [2021-12-06 23:42:38,718 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 23:42:38,718 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:42:38,718 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:42:38,719 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:42:38,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-12-06 23:42:38,749 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 23:42:38,749 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:42:38,750 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 22 conjunts are in the unsatisfiable core [2021-12-06 23:42:38,751 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:42:38,768 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:42:38,828 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:42:38,829 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:42:38,849 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:42:38,849 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:42:38,893 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:42:38,895 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:38,895 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:42:39,003 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:42:39,005 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:42:39,017 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:39,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1475763812] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:42:39,017 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:42:39,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2021-12-06 23:42:39,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894748035] [2021-12-06 23:42:39,018 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:42:39,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:42:39,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:39,018 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2021-12-06 23:42:39,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:39,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451294751] [2021-12-06 23:42:39,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:39,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:39,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:39,021 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:42:39,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:39,024 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:42:39,061 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:42:39,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-12-06 23:42:39,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2021-12-06 23:42:39,062 INFO L87 Difference]: Start difference. First operand 34 states and 44 transitions. cyclomatic complexity: 14 Second operand has 17 states, 16 states have (on average 2.0625) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:39,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:42:39,221 INFO L93 Difference]: Finished difference Result 71 states and 92 transitions. [2021-12-06 23:42:39,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 23:42:39,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 92 transitions. [2021-12-06 23:42:39,222 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 23:42:39,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 91 transitions. [2021-12-06 23:42:39,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 23:42:39,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 23:42:39,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 91 transitions. [2021-12-06 23:42:39,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:42:39,223 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 91 transitions. [2021-12-06 23:42:39,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 91 transitions. [2021-12-06 23:42:39,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 41. [2021-12-06 23:42:39,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3658536585365855) internal successors, (56), 40 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:39,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 56 transitions. [2021-12-06 23:42:39,225 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 56 transitions. [2021-12-06 23:42:39,225 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 56 transitions. [2021-12-06 23:42:39,225 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 23:42:39,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 56 transitions. [2021-12-06 23:42:39,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:39,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:42:39,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:42:39,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:42:39,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:42:39,226 INFO L791 eck$LassoCheckResult]: Stem: 2114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2125#L367 assume !(main_~length~0#1 < 1); 2116#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2117#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2118#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2126#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2141#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2138#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2139#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2153#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2130#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2149#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2119#L370-4 main_~j~0#1 := 0; 2120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2123#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2124#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2132#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2121#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2122#L378-2 [2021-12-06 23:42:39,226 INFO L793 eck$LassoCheckResult]: Loop: 2122#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2136#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2122#L378-2 [2021-12-06 23:42:39,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:39,226 INFO L85 PathProgramCache]: Analyzing trace with hash -643041689, now seen corresponding path program 5 times [2021-12-06 23:42:39,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:39,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640760771] [2021-12-06 23:42:39,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:39,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:39,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:39,301 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:39,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:42:39,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640760771] [2021-12-06 23:42:39,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640760771] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:42:39,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1996344177] [2021-12-06 23:42:39,302 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 23:42:39,302 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:42:39,302 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:42:39,302 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:42:39,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-12-06 23:42:39,346 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-12-06 23:42:39,346 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:42:39,347 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 29 conjunts are in the unsatisfiable core [2021-12-06 23:42:39,349 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:42:39,363 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:42:39,392 INFO L354 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2021-12-06 23:42:39,392 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-12-06 23:42:39,405 INFO L354 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2021-12-06 23:42:39,405 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-12-06 23:42:39,610 INFO L354 Elim1Store]: treesize reduction 48, result has 5.9 percent of original size [2021-12-06 23:42:39,610 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2021-12-06 23:42:39,612 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:39,612 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:42:40,521 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~j~0#1_90| Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0)) (.cse1 (* |v_ULTIMATE.start_main_~j~0#1_90| 4))) (or (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 8)) 2) 0) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 4)) 2) 0)) (< 0 |v_ULTIMATE.start_main_~j~0#1_90|) (< |v_ULTIMATE.start_main_~j~0#1_90| 0)))) is different from false [2021-12-06 23:42:48,905 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 56 [2021-12-06 23:42:48,909 INFO L354 Elim1Store]: treesize reduction 17, result has 5.6 percent of original size [2021-12-06 23:42:48,909 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 137 treesize of output 123 [2021-12-06 23:42:48,958 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 5 not checked. [2021-12-06 23:42:48,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1996344177] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:42:48,958 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:42:48,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12, 12] total 29 [2021-12-06 23:42:48,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970930462] [2021-12-06 23:42:48,958 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:42:48,958 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:42:48,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:48,959 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2021-12-06 23:42:48,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:48,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969303394] [2021-12-06 23:42:48,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:48,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:48,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:48,961 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:42:48,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:48,963 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:42:48,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:42:48,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-12-06 23:42:48,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=677, Unknown=8, NotChecked=54, Total=870 [2021-12-06 23:42:48,993 INFO L87 Difference]: Start difference. First operand 41 states and 56 transitions. cyclomatic complexity: 19 Second operand has 30 states, 29 states have (on average 1.793103448275862) internal successors, (52), 30 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:49,880 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((|v_ULTIMATE.start_main_~j~0#1_90| Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0)) (.cse1 (* |v_ULTIMATE.start_main_~j~0#1_90| 4))) (or (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 8)) 2) 0) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 4)) 2) 0)) (< 0 |v_ULTIMATE.start_main_~j~0#1_90|) (< |v_ULTIMATE.start_main_~j~0#1_90| 0)))) (exists ((|ULTIMATE.start_main_~i~0#1| Int)) (let ((.cse2 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|)) (.cse3 (* |ULTIMATE.start_main_~i~0#1| 4))) (and (<= |ULTIMATE.start_main_~i~0#1| 2) (<= 2 |ULTIMATE.start_main_~i~0#1|) (= 0 (select .cse2 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse3))) (= (select .cse2 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (- 4) .cse3)) 0))))) is different from false [2021-12-06 23:42:50,684 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((|v_ULTIMATE.start_main_~j~0#1_90| Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0)) (.cse1 (* |v_ULTIMATE.start_main_~j~0#1_90| 4))) (or (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 8)) 2) 0) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 4)) 2) 0)) (< 0 |v_ULTIMATE.start_main_~j~0#1_90|) (< |v_ULTIMATE.start_main_~j~0#1_90| 0)))) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 8)) 0)) is different from false [2021-12-06 23:42:50,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:42:50,739 INFO L93 Difference]: Finished difference Result 71 states and 92 transitions. [2021-12-06 23:42:50,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-12-06 23:42:50,740 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 92 transitions. [2021-12-06 23:42:50,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:50,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 69 states and 89 transitions. [2021-12-06 23:42:50,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-12-06 23:42:50,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-12-06 23:42:50,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 89 transitions. [2021-12-06 23:42:50,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:42:50,742 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 89 transitions. [2021-12-06 23:42:50,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 89 transitions. [2021-12-06 23:42:50,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 54. [2021-12-06 23:42:50,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.3518518518518519) internal successors, (73), 53 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:50,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 73 transitions. [2021-12-06 23:42:50,745 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 73 transitions. [2021-12-06 23:42:50,745 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 73 transitions. [2021-12-06 23:42:50,745 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 23:42:50,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 73 transitions. [2021-12-06 23:42:50,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:50,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:42:50,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:42:50,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:42:50,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:42:50,747 INFO L791 eck$LassoCheckResult]: Stem: 2396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2407#L367 assume !(main_~length~0#1 < 1); 2398#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2399#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2400#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2408#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2411#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2409#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2410#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2440#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2439#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2438#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2401#L370-4 main_~j~0#1 := 0; 2402#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2405#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2415#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2416#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2403#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2404#L378-2 [2021-12-06 23:42:50,747 INFO L793 eck$LassoCheckResult]: Loop: 2404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2414#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2404#L378-2 [2021-12-06 23:42:50,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:50,747 INFO L85 PathProgramCache]: Analyzing trace with hash -1036068699, now seen corresponding path program 6 times [2021-12-06 23:42:50,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:50,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143967073] [2021-12-06 23:42:50,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:50,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:50,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:50,866 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:50,866 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:42:50,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143967073] [2021-12-06 23:42:50,866 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143967073] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:42:50,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [246115224] [2021-12-06 23:42:50,866 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 23:42:50,866 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:42:50,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:42:50,867 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:42:50,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-12-06 23:42:50,909 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2021-12-06 23:42:50,909 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:42:50,910 INFO L263 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 18 conjunts are in the unsatisfiable core [2021-12-06 23:42:50,911 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:42:50,944 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:42:51,137 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 23:42:51,137 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2021-12-06 23:42:51,146 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:51,146 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:42:51,402 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2021-12-06 23:42:51,404 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 32 [2021-12-06 23:42:51,415 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:51,415 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [246115224] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:42:51,415 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:42:51,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 12] total 28 [2021-12-06 23:42:51,415 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657410883] [2021-12-06 23:42:51,415 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:42:51,416 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:42:51,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:51,416 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2021-12-06 23:42:51,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:51,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741765391] [2021-12-06 23:42:51,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:51,416 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:51,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:51,419 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:42:51,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:51,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:42:51,448 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:42:51,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-12-06 23:42:51,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=695, Unknown=0, NotChecked=0, Total=812 [2021-12-06 23:42:51,449 INFO L87 Difference]: Start difference. First operand 54 states and 73 transitions. cyclomatic complexity: 23 Second operand has 29 states, 28 states have (on average 1.75) internal successors, (49), 29 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:51,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:42:51,732 INFO L93 Difference]: Finished difference Result 84 states and 110 transitions. [2021-12-06 23:42:51,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-12-06 23:42:51,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 110 transitions. [2021-12-06 23:42:51,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:51,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 69 states and 91 transitions. [2021-12-06 23:42:51,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 23:42:51,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 23:42:51,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 91 transitions. [2021-12-06 23:42:51,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:42:51,734 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 91 transitions. [2021-12-06 23:42:51,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 91 transitions. [2021-12-06 23:42:51,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2021-12-06 23:42:51,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.318840579710145) internal successors, (91), 68 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:51,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 91 transitions. [2021-12-06 23:42:51,738 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 91 transitions. [2021-12-06 23:42:51,738 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 91 transitions. [2021-12-06 23:42:51,738 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 23:42:51,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 91 transitions. [2021-12-06 23:42:51,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:42:51,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:42:51,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:42:51,739 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:42:51,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:42:51,739 INFO L791 eck$LassoCheckResult]: Stem: 2720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2731#L367 assume !(main_~length~0#1 < 1); 2722#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2723#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2732#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2786#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2784#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2781#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2788#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2767#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2768#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2761#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2725#L370-4 main_~j~0#1 := 0; 2726#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2744#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2737#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2729#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2730#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2727#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2728#L378-2 [2021-12-06 23:42:51,740 INFO L793 eck$LassoCheckResult]: Loop: 2728#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2741#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2728#L378-2 [2021-12-06 23:42:51,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:51,740 INFO L85 PathProgramCache]: Analyzing trace with hash -15000345, now seen corresponding path program 7 times [2021-12-06 23:42:51,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:51,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059929771] [2021-12-06 23:42:51,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:51,740 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:51,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:51,877 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:51,877 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:42:51,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059929771] [2021-12-06 23:42:51,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059929771] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:42:51,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [921791508] [2021-12-06 23:42:51,877 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 23:42:51,878 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:42:51,878 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:42:51,878 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:42:51,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-12-06 23:42:51,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:51,923 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 25 conjunts are in the unsatisfiable core [2021-12-06 23:42:51,924 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:42:51,985 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-12-06 23:42:52,088 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-12-06 23:42:52,097 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:52,097 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:42:52,156 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:42:52,157 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:42:52,172 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:52,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [921791508] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:42:52,172 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:42:52,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 10] total 22 [2021-12-06 23:42:52,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398858784] [2021-12-06 23:42:52,173 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:42:52,173 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:42:52,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:52,173 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2021-12-06 23:42:52,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:52,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6310504] [2021-12-06 23:42:52,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:52,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:52,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:52,176 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:42:52,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:42:52,178 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:42:52,206 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:42:52,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 23:42:52,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=428, Unknown=0, NotChecked=0, Total=506 [2021-12-06 23:42:52,207 INFO L87 Difference]: Start difference. First operand 69 states and 91 transitions. cyclomatic complexity: 26 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:52,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:42:52,420 INFO L93 Difference]: Finished difference Result 100 states and 130 transitions. [2021-12-06 23:42:52,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 23:42:52,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 130 transitions. [2021-12-06 23:42:52,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8 [2021-12-06 23:42:52,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 99 states and 129 transitions. [2021-12-06 23:42:52,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-12-06 23:42:52,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-12-06 23:42:52,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 129 transitions. [2021-12-06 23:42:52,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:42:52,422 INFO L681 BuchiCegarLoop]: Abstraction has 99 states and 129 transitions. [2021-12-06 23:42:52,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 129 transitions. [2021-12-06 23:42:52,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 85. [2021-12-06 23:42:52,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.3294117647058823) internal successors, (113), 84 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:42:52,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 113 transitions. [2021-12-06 23:42:52,425 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 113 transitions. [2021-12-06 23:42:52,425 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 113 transitions. [2021-12-06 23:42:52,425 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 23:42:52,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 113 transitions. [2021-12-06 23:42:52,425 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 23:42:52,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:42:52,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:42:52,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:42:52,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:42:52,426 INFO L791 eck$LassoCheckResult]: Stem: 3049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3060#L367 assume !(main_~length~0#1 < 1); 3051#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3052#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3053#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3061#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3127#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3124#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3125#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3132#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3131#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3118#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3103#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3100#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3097#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3092#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3089#L370-4 main_~j~0#1 := 0; 3087#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3085#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3071#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3056#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3057#L378-2 [2021-12-06 23:42:52,426 INFO L793 eck$LassoCheckResult]: Loop: 3057#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3076#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3057#L378-2 [2021-12-06 23:42:52,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:42:52,426 INFO L85 PathProgramCache]: Analyzing trace with hash -920370722, now seen corresponding path program 1 times [2021-12-06 23:42:52,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:42:52,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976998771] [2021-12-06 23:42:52,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:52,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:42:52,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:52,519 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:52,519 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:42:52,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976998771] [2021-12-06 23:42:52,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976998771] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:42:52,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872424208] [2021-12-06 23:42:52,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:42:52,519 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:42:52,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:42:52,520 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:42:52,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-12-06 23:42:52,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:42:52,557 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 46 conjunts are in the unsatisfiable core [2021-12-06 23:42:52,560 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:42:52,566 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2021-12-06 23:42:52,582 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2021-12-06 23:42:52,587 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:42:52,616 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,617 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-12-06 23:42:52,624 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,624 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-12-06 23:42:52,661 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,662 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,662 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,664 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:42:52,664 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 34 [2021-12-06 23:42:52,675 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,676 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,677 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,678 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:42:52,678 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 34 [2021-12-06 23:42:52,705 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,706 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,707 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,708 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:42:52,708 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 34 [2021-12-06 23:42:52,721 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,722 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,723 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:42:52,724 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:42:52,724 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 34 [2021-12-06 23:42:52,803 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 23:42:52,804 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2021-12-06 23:42:52,805 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:42:52,805 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:43:04,930 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) is different from false [2021-12-06 23:43:32,601 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) is different from false [2021-12-06 23:43:33,871 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (|v_ULTIMATE.start_main_~i~0#1_111| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1))))) is different from false [2021-12-06 23:43:43,261 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 76 [2021-12-06 23:43:43,271 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-12-06 23:43:43,271 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 4024 treesize of output 3988 [2021-12-06 23:43:45,988 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 12 not checked. [2021-12-06 23:43:45,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1872424208] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:43:45,989 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:43:45,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 13, 14] total 34 [2021-12-06 23:43:45,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727379236] [2021-12-06 23:43:45,989 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:43:45,989 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:43:45,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:43:45,989 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2021-12-06 23:43:45,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:43:45,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738281896] [2021-12-06 23:43:45,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:43:45,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:43:45,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:43:45,992 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:43:45,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:43:45,994 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:43:46,024 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:43:46,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-12-06 23:43:46,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=813, Unknown=19, NotChecked=186, Total=1190 [2021-12-06 23:43:46,025 INFO L87 Difference]: Start difference. First operand 85 states and 113 transitions. cyclomatic complexity: 34 Second operand has 35 states, 34 states have (on average 1.7941176470588236) internal successors, (61), 35 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:44:03,756 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= |c_ULTIMATE.start_main_~i~0#1| 1) (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (= 0 (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))))) is different from false [2021-12-06 23:44:15,763 WARN L838 $PredicateComparison]: unable to prove that (and (<= 1 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= |c_ULTIMATE.start_main_~i~0#1| 1)) is different from false [2021-12-06 23:44:22,650 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (|v_ULTIMATE.start_main_~i~0#1_111| Int) (v_ArrVal_338 Int)) (let ((.cse1 (store (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1))))) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|))) is different from false [2021-12-06 23:44:24,166 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (|v_ULTIMATE.start_main_~i~0#1_111| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1))))) (<= 2 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-12-06 23:44:36,173 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse1 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse2 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse2 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse2 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|))) is different from false [2021-12-06 23:44:48,179 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse1 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (<= 2 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-12-06 23:45:33,210 WARN L227 SmtUtils]: Spent 7.21s on a formula simplification that was a NOOP. DAG size: 36 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 23:45:45,244 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse1 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|))) is different from false [2021-12-06 23:45:57,252 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0))))))) is different from false [2021-12-06 23:46:05,764 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (|v_ULTIMATE.start_main_~i~0#1_111| Int) (v_ArrVal_338 Int)) (let ((.cse1 (store (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1))))) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (<= 3 |c_ULTIMATE.start_main_~i~0#1|) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0))) is different from false [2021-12-06 23:46:21,682 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_111| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_111| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse1 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_111| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |v_ULTIMATE.start_main_~i~0#1_111| 1)) (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0))) is different from false [2021-12-06 23:46:24,462 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (forall ((v_ArrVal_343 Int) (|v_ULTIMATE.start_main_~i~0#1_110| Int) (v_ArrVal_338 Int)) (let ((.cse1 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) v_ArrVal_338) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0))))))) is different from false [2021-12-06 23:46:39,700 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((|v_ULTIMATE.start_main_~i~0#1_110| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_110| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_343 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_110| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_343))) (or (not (= (mod (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))))) (let ((.cse1 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (or (not (= (mod (select .cse1 |c_ULTIMATE.start_main_~arr~0#1.offset|) 2) 0)) (= (mod (select .cse1 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))) is different from false [2021-12-06 23:47:00,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:00,378 INFO L93 Difference]: Finished difference Result 232 states and 302 transitions. [2021-12-06 23:47:00,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-12-06 23:47:00,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232 states and 302 transitions. [2021-12-06 23:47:00,381 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20 [2021-12-06 23:47:00,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232 states to 226 states and 295 transitions. [2021-12-06 23:47:00,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76 [2021-12-06 23:47:00,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76 [2021-12-06 23:47:00,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226 states and 295 transitions. [2021-12-06 23:47:00,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:00,384 INFO L681 BuchiCegarLoop]: Abstraction has 226 states and 295 transitions. [2021-12-06 23:47:00,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states and 295 transitions. [2021-12-06 23:47:00,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 110. [2021-12-06 23:47:00,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.3909090909090909) internal successors, (153), 109 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:00,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 153 transitions. [2021-12-06 23:47:00,389 INFO L704 BuchiCegarLoop]: Abstraction has 110 states and 153 transitions. [2021-12-06 23:47:00,389 INFO L587 BuchiCegarLoop]: Abstraction has 110 states and 153 transitions. [2021-12-06 23:47:00,389 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 23:47:00,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 153 transitions. [2021-12-06 23:47:00,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 23:47:00,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:00,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:00,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:00,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:00,390 INFO L791 eck$LassoCheckResult]: Stem: 3604#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3615#L367 assume !(main_~length~0#1 < 1); 3606#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3607#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3616#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3669#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3663#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3664#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3704#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3648#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3693#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3691#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3688#L370-4 main_~j~0#1 := 0; 3686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3685#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3609#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3610#L378-2 [2021-12-06 23:47:00,391 INFO L793 eck$LassoCheckResult]: Loop: 3610#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3627#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3610#L378-2 [2021-12-06 23:47:00,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:00,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1931487972, now seen corresponding path program 8 times [2021-12-06 23:47:00,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:00,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228959510] [2021-12-06 23:47:00,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:00,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:00,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:00,541 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:00,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:00,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228959510] [2021-12-06 23:47:00,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228959510] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:00,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2004131225] [2021-12-06 23:47:00,541 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:47:00,541 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:00,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:00,542 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:00,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-12-06 23:47:00,579 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:47:00,579 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:00,579 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 27 conjunts are in the unsatisfiable core [2021-12-06 23:47:00,581 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:00,594 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:00,643 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:00,643 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:00,653 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:00,653 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:00,678 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:00,678 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:00,689 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:00,689 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:00,715 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:00,717 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:00,717 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:00,856 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:00,858 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:00,868 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 23:47:00,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2004131225] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:00,869 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:00,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2021-12-06 23:47:00,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439334265] [2021-12-06 23:47:00,869 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:00,869 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:00,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:00,869 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2021-12-06 23:47:00,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:00,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895606602] [2021-12-06 23:47:00,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:00,870 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:00,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:00,872 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:00,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:00,874 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:00,903 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:00,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 23:47:00,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2021-12-06 23:47:00,904 INFO L87 Difference]: Start difference. First operand 110 states and 153 transitions. cyclomatic complexity: 50 Second operand has 18 states, 17 states have (on average 2.235294117647059) internal successors, (38), 18 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:01,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:01,063 INFO L93 Difference]: Finished difference Result 110 states and 150 transitions. [2021-12-06 23:47:01,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-12-06 23:47:01,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 150 transitions. [2021-12-06 23:47:01,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:01,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 108 states and 147 transitions. [2021-12-06 23:47:01,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-12-06 23:47:01,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-12-06 23:47:01,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 147 transitions. [2021-12-06 23:47:01,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:01,065 INFO L681 BuchiCegarLoop]: Abstraction has 108 states and 147 transitions. [2021-12-06 23:47:01,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 147 transitions. [2021-12-06 23:47:01,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 47. [2021-12-06 23:47:01,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.297872340425532) internal successors, (61), 46 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:01,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 61 transitions. [2021-12-06 23:47:01,067 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 61 transitions. [2021-12-06 23:47:01,067 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 61 transitions. [2021-12-06 23:47:01,067 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 23:47:01,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 61 transitions. [2021-12-06 23:47:01,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:01,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:01,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:01,068 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:01,068 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:01,068 INFO L791 eck$LassoCheckResult]: Stem: 3983#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3994#L367 assume !(main_~length~0#1 < 1); 3985#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3986#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3987#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3995#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3998#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3999#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4023#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4021#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4016#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3988#L370-4 main_~j~0#1 := 0; 3989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4007#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3992#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4005#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3990#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3991#L378-2 [2021-12-06 23:47:01,068 INFO L793 eck$LassoCheckResult]: Loop: 3991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4006#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3991#L378-2 [2021-12-06 23:47:01,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:01,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1226507950, now seen corresponding path program 9 times [2021-12-06 23:47:01,068 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:01,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360945846] [2021-12-06 23:47:01,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:01,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:01,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:01,189 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:01,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:01,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360945846] [2021-12-06 23:47:01,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360945846] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:01,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [309538538] [2021-12-06 23:47:01,189 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:47:01,190 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:01,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:01,190 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:01,191 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-12-06 23:47:01,240 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-12-06 23:47:01,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:01,241 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 10 conjunts are in the unsatisfiable core [2021-12-06 23:47:01,242 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:01,325 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:01,325 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:01,372 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:01,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [309538538] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:01,373 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:01,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11] total 25 [2021-12-06 23:47:01,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303244790] [2021-12-06 23:47:01,373 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:01,373 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:01,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:01,374 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2021-12-06 23:47:01,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:01,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412249681] [2021-12-06 23:47:01,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:01,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:01,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:01,376 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:01,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:01,378 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:01,409 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:01,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-12-06 23:47:01,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=479, Unknown=0, NotChecked=0, Total=600 [2021-12-06 23:47:01,409 INFO L87 Difference]: Start difference. First operand 47 states and 61 transitions. cyclomatic complexity: 18 Second operand has 25 states, 25 states have (on average 2.08) internal successors, (52), 25 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:01,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:01,549 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2021-12-06 23:47:01,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-12-06 23:47:01,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2021-12-06 23:47:01,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:01,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 52 states and 66 transitions. [2021-12-06 23:47:01,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:47:01,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:47:01,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 66 transitions. [2021-12-06 23:47:01,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:01,551 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 66 transitions. [2021-12-06 23:47:01,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 66 transitions. [2021-12-06 23:47:01,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 39. [2021-12-06 23:47:01,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2820512820512822) internal successors, (50), 38 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:01,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 50 transitions. [2021-12-06 23:47:01,552 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 50 transitions. [2021-12-06 23:47:01,552 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 50 transitions. [2021-12-06 23:47:01,552 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 23:47:01,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 50 transitions. [2021-12-06 23:47:01,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:01,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:01,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:01,553 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:01,553 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:01,553 INFO L791 eck$LassoCheckResult]: Stem: 4266#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4277#L367 assume !(main_~length~0#1 < 1); 4268#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4269#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4270#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4278#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4279#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4280#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4302#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4299#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4292#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4293#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4284#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4271#L370-4 main_~j~0#1 := 0; 4272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4283#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4289#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4287#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4286#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4274#L378-2 [2021-12-06 23:47:01,553 INFO L793 eck$LassoCheckResult]: Loop: 4274#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4288#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4274#L378-2 [2021-12-06 23:47:01,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:01,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1285147747, now seen corresponding path program 10 times [2021-12-06 23:47:01,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:01,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654297504] [2021-12-06 23:47:01,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:01,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:01,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:01,689 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:01,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:01,689 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1654297504] [2021-12-06 23:47:01,689 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1654297504] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:01,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [228362191] [2021-12-06 23:47:01,690 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 23:47:01,690 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:01,690 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:01,691 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:01,691 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-12-06 23:47:01,728 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 23:47:01,728 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:01,729 INFO L263 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 26 conjunts are in the unsatisfiable core [2021-12-06 23:47:01,731 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:01,754 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:01,823 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:01,824 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:47:01,843 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:01,843 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:47:01,913 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:01,915 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:01,915 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:02,038 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:02,040 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:02,057 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:02,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [228362191] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:02,057 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:02,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2021-12-06 23:47:02,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659227487] [2021-12-06 23:47:02,057 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:02,058 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:02,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:02,058 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2021-12-06 23:47:02,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:02,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274434560] [2021-12-06 23:47:02,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:02,058 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:02,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:02,060 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:02,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:02,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:02,092 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:02,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-12-06 23:47:02,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=322, Unknown=0, NotChecked=0, Total=380 [2021-12-06 23:47:02,093 INFO L87 Difference]: Start difference. First operand 39 states and 50 transitions. cyclomatic complexity: 15 Second operand has 20 states, 19 states have (on average 2.1052631578947367) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:02,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:02,332 INFO L93 Difference]: Finished difference Result 79 states and 99 transitions. [2021-12-06 23:47:02,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 23:47:02,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 99 transitions. [2021-12-06 23:47:02,333 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 23:47:02,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 78 states and 98 transitions. [2021-12-06 23:47:02,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 23:47:02,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 23:47:02,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 98 transitions. [2021-12-06 23:47:02,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:02,335 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 98 transitions. [2021-12-06 23:47:02,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 98 transitions. [2021-12-06 23:47:02,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 40. [2021-12-06 23:47:02,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.325) internal successors, (53), 39 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:02,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 53 transitions. [2021-12-06 23:47:02,336 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 53 transitions. [2021-12-06 23:47:02,336 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 53 transitions. [2021-12-06 23:47:02,337 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 23:47:02,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 53 transitions. [2021-12-06 23:47:02,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:02,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:02,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:02,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:02,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:02,338 INFO L791 eck$LassoCheckResult]: Stem: 4561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4572#L367 assume !(main_~length~0#1 < 1); 4563#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4564#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4565#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4573#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4588#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4589#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4584#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4585#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4586#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4587#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4574#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4575#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4600#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4566#L370-4 main_~j~0#1 := 0; 4567#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4570#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4578#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4582#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4581#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4568#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4569#L378-2 [2021-12-06 23:47:02,338 INFO L793 eck$LassoCheckResult]: Loop: 4569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4583#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4569#L378-2 [2021-12-06 23:47:02,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:02,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1923596954, now seen corresponding path program 11 times [2021-12-06 23:47:02,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:02,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801903262] [2021-12-06 23:47:02,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:02,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:02,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:02,443 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:02,443 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:02,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801903262] [2021-12-06 23:47:02,443 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801903262] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:02,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [70587174] [2021-12-06 23:47:02,443 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 23:47:02,443 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:02,443 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:02,444 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:02,445 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-12-06 23:47:02,502 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2021-12-06 23:47:02,502 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:02,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 23 conjunts are in the unsatisfiable core [2021-12-06 23:47:02,504 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:02,532 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:02,606 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:47:02,607 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:02,607 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:02,734 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2021-12-06 23:47:02,736 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 32 [2021-12-06 23:47:02,759 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:02,759 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [70587174] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:02,759 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:02,759 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 23 [2021-12-06 23:47:02,760 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312712158] [2021-12-06 23:47:02,760 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:02,760 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:02,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:02,760 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2021-12-06 23:47:02,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:02,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043326893] [2021-12-06 23:47:02,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:02,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:02,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:02,762 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:02,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:02,765 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:02,793 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:02,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-12-06 23:47:02,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=478, Unknown=0, NotChecked=0, Total=552 [2021-12-06 23:47:02,794 INFO L87 Difference]: Start difference. First operand 40 states and 53 transitions. cyclomatic complexity: 17 Second operand has 24 states, 23 states have (on average 2.130434782608696) internal successors, (49), 24 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:02,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:02,974 INFO L93 Difference]: Finished difference Result 52 states and 66 transitions. [2021-12-06 23:47:02,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-12-06 23:47:02,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 66 transitions. [2021-12-06 23:47:02,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:02,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 51 states and 65 transitions. [2021-12-06 23:47:02,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-12-06 23:47:02,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-12-06 23:47:02,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 65 transitions. [2021-12-06 23:47:02,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:02,976 INFO L681 BuchiCegarLoop]: Abstraction has 51 states and 65 transitions. [2021-12-06 23:47:02,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 65 transitions. [2021-12-06 23:47:02,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 46. [2021-12-06 23:47:02,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.3043478260869565) internal successors, (60), 45 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:02,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 60 transitions. [2021-12-06 23:47:02,977 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 60 transitions. [2021-12-06 23:47:02,977 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 60 transitions. [2021-12-06 23:47:02,977 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 23:47:02,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 60 transitions. [2021-12-06 23:47:02,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:02,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:02,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:02,978 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:02,978 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:02,978 INFO L791 eck$LassoCheckResult]: Stem: 4838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4849#L367 assume !(main_~length~0#1 < 1); 4840#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4841#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4842#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4850#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4853#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4851#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4852#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4882#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4881#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4880#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4879#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4876#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4877#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4869#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4843#L370-4 main_~j~0#1 := 0; 4844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4847#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4848#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4859#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4857#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4845#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4846#L378-2 [2021-12-06 23:47:02,978 INFO L793 eck$LassoCheckResult]: Loop: 4846#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4855#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4846#L378-2 [2021-12-06 23:47:02,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:02,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1665431516, now seen corresponding path program 3 times [2021-12-06 23:47:02,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:02,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338611893] [2021-12-06 23:47:02,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:02,979 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:02,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:03,141 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:03,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:03,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338611893] [2021-12-06 23:47:03,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338611893] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:03,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1698848128] [2021-12-06 23:47:03,141 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:47:03,141 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:03,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:03,142 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:03,143 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-12-06 23:47:03,198 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-12-06 23:47:03,198 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:03,199 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 20 conjunts are in the unsatisfiable core [2021-12-06 23:47:03,200 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:03,261 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:03,522 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-12-06 23:47:03,522 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2021-12-06 23:47:03,533 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:03,533 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:03,911 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2021-12-06 23:47:03,914 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 32 [2021-12-06 23:47:03,930 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 6 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:03,930 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1698848128] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:03,930 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:03,930 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 14] total 33 [2021-12-06 23:47:03,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415069788] [2021-12-06 23:47:03,930 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:03,931 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:03,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:03,931 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2021-12-06 23:47:03,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:03,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970833645] [2021-12-06 23:47:03,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:03,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:03,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:03,934 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:03,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:03,937 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:03,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:03,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-12-06 23:47:03,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=151, Invalid=971, Unknown=0, NotChecked=0, Total=1122 [2021-12-06 23:47:03,969 INFO L87 Difference]: Start difference. First operand 46 states and 60 transitions. cyclomatic complexity: 18 Second operand has 34 states, 33 states have (on average 1.8484848484848484) internal successors, (61), 34 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:04,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:04,438 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2021-12-06 23:47:04,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-12-06 23:47:04,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 76 transitions. [2021-12-06 23:47:04,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:04,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 42 states and 54 transitions. [2021-12-06 23:47:04,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:47:04,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:47:04,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 54 transitions. [2021-12-06 23:47:04,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:04,439 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 54 transitions. [2021-12-06 23:47:04,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 54 transitions. [2021-12-06 23:47:04,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2021-12-06 23:47:04,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2857142857142858) internal successors, (54), 41 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:04,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 54 transitions. [2021-12-06 23:47:04,440 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 54 transitions. [2021-12-06 23:47:04,440 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 54 transitions. [2021-12-06 23:47:04,440 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 23:47:04,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 54 transitions. [2021-12-06 23:47:04,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:04,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:04,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:04,441 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:04,441 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:04,441 INFO L791 eck$LassoCheckResult]: Stem: 5178#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5189#L367 assume !(main_~length~0#1 < 1); 5180#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5181#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5182#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5190#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5191#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5192#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5219#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5218#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5217#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5216#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5214#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5211#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5209#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5197#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5196#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5183#L370-4 main_~j~0#1 := 0; 5184#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5195#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5201#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5199#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5198#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5185#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5186#L378-2 [2021-12-06 23:47:04,441 INFO L793 eck$LassoCheckResult]: Loop: 5186#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5200#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5186#L378-2 [2021-12-06 23:47:04,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:04,442 INFO L85 PathProgramCache]: Analyzing trace with hash 3898981, now seen corresponding path program 12 times [2021-12-06 23:47:04,442 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:04,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40790187] [2021-12-06 23:47:04,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:04,442 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:04,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:04,604 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:04,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:04,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40790187] [2021-12-06 23:47:04,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40790187] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:04,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [124917488] [2021-12-06 23:47:04,604 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 23:47:04,604 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:04,605 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:04,605 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:04,606 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-12-06 23:47:04,660 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2021-12-06 23:47:04,660 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:04,661 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 32 conjunts are in the unsatisfiable core [2021-12-06 23:47:04,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:04,762 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:04,837 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:47:04,837 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:47:04,845 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:47:04,846 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:47:04,880 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 23:47:04,880 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:47:05,006 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2021-12-06 23:47:05,018 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:05,018 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:05,201 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:05,202 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:05,270 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 23:47:05,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [124917488] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:05,270 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:05,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 15, 14] total 31 [2021-12-06 23:47:05,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487430141] [2021-12-06 23:47:05,270 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:05,271 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:05,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:05,271 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2021-12-06 23:47:05,271 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:05,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576330700] [2021-12-06 23:47:05,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:05,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:05,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:05,274 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:05,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:05,276 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:05,304 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:05,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-12-06 23:47:05,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=860, Unknown=0, NotChecked=0, Total=992 [2021-12-06 23:47:05,305 INFO L87 Difference]: Start difference. First operand 42 states and 54 transitions. cyclomatic complexity: 16 Second operand has 32 states, 31 states have (on average 2.096774193548387) internal successors, (65), 32 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:05,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:05,599 INFO L93 Difference]: Finished difference Result 48 states and 60 transitions. [2021-12-06 23:47:05,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 23:47:05,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 60 transitions. [2021-12-06 23:47:05,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:05,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 47 states and 59 transitions. [2021-12-06 23:47:05,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:47:05,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:47:05,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2021-12-06 23:47:05,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:05,601 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2021-12-06 23:47:05,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2021-12-06 23:47:05,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 32. [2021-12-06 23:47:05,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.25) internal successors, (40), 31 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:05,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 40 transitions. [2021-12-06 23:47:05,602 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2021-12-06 23:47:05,602 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2021-12-06 23:47:05,602 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 23:47:05,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 40 transitions. [2021-12-06 23:47:05,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:05,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:05,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:05,603 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:05,603 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:05,603 INFO L791 eck$LassoCheckResult]: Stem: 5473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5484#L367 assume !(main_~length~0#1 < 1); 5475#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5476#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5485#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5488#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5487#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5504#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5502#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5499#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5491#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5496#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5490#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5478#L370-4 main_~j~0#1 := 0; 5479#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5482#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5483#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5489#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5495#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5493#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5492#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5480#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5481#L378-2 [2021-12-06 23:47:05,603 INFO L793 eck$LassoCheckResult]: Loop: 5481#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5494#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5481#L378-2 [2021-12-06 23:47:05,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:05,603 INFO L85 PathProgramCache]: Analyzing trace with hash -1827910806, now seen corresponding path program 4 times [2021-12-06 23:47:05,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:05,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879634510] [2021-12-06 23:47:05,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:05,603 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:05,789 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:05,789 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:05,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879634510] [2021-12-06 23:47:05,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879634510] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:05,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1874359275] [2021-12-06 23:47:05,790 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 23:47:05,790 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:05,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:05,790 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:05,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-12-06 23:47:05,832 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 23:47:05,832 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:05,833 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 28 conjunts are in the unsatisfiable core [2021-12-06 23:47:05,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:05,862 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:05,930 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:05,930 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:47:06,026 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:06,028 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:06,028 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:06,142 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:06,144 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:06,170 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:06,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1874359275] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:06,171 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:06,171 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2021-12-06 23:47:06,171 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395665772] [2021-12-06 23:47:06,171 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:06,171 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:06,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:06,171 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2021-12-06 23:47:06,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:06,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022767663] [2021-12-06 23:47:06,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:06,171 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:06,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:06,174 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:06,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:06,175 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:06,208 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:06,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 23:47:06,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=440, Unknown=0, NotChecked=0, Total=506 [2021-12-06 23:47:06,209 INFO L87 Difference]: Start difference. First operand 32 states and 40 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:06,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:06,434 INFO L93 Difference]: Finished difference Result 50 states and 62 transitions. [2021-12-06 23:47:06,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 23:47:06,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50 states and 62 transitions. [2021-12-06 23:47:06,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:47:06,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50 states to 49 states and 61 transitions. [2021-12-06 23:47:06,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-12-06 23:47:06,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-12-06 23:47:06,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 61 transitions. [2021-12-06 23:47:06,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:06,436 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2021-12-06 23:47:06,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 61 transitions. [2021-12-06 23:47:06,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 39. [2021-12-06 23:47:06,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2564102564102564) internal successors, (49), 38 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:06,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2021-12-06 23:47:06,436 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-12-06 23:47:06,437 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-12-06 23:47:06,437 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 23:47:06,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 49 transitions. [2021-12-06 23:47:06,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:06,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:06,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:06,437 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:06,437 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:06,437 INFO L791 eck$LassoCheckResult]: Stem: 5757#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5768#L367 assume !(main_~length~0#1 < 1); 5759#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5760#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5761#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5769#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5786#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5770#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5771#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5775#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5785#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5784#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5783#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5782#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5781#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5780#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5779#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5778#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5776#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5762#L370-4 main_~j~0#1 := 0; 5763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5792#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5774#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5766#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5791#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5790#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5789#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5764#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5765#L378-2 [2021-12-06 23:47:06,437 INFO L793 eck$LassoCheckResult]: Loop: 5765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5765#L378-2 [2021-12-06 23:47:06,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:06,438 INFO L85 PathProgramCache]: Analyzing trace with hash 19338925, now seen corresponding path program 5 times [2021-12-06 23:47:06,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:06,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247664604] [2021-12-06 23:47:06,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:06,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:06,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:06,610 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:06,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:06,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247664604] [2021-12-06 23:47:06,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247664604] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:06,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1727558185] [2021-12-06 23:47:06,610 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 23:47:06,610 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:06,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:06,611 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:06,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-12-06 23:47:06,688 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-12-06 23:47:06,688 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:06,689 INFO L263 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 29 conjunts are in the unsatisfiable core [2021-12-06 23:47:06,690 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:06,722 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:06,901 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:06,903 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:06,903 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:07,032 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:07,034 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:07,070 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:07,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1727558185] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:07,070 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:07,070 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 24 [2021-12-06 23:47:07,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572522118] [2021-12-06 23:47:07,071 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:07,071 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:07,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:07,071 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2021-12-06 23:47:07,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:07,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449962463] [2021-12-06 23:47:07,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:07,071 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:07,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:07,073 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:07,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:07,075 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:07,105 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:07,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-12-06 23:47:07,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=526, Unknown=0, NotChecked=0, Total=600 [2021-12-06 23:47:07,106 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. cyclomatic complexity: 13 Second operand has 25 states, 24 states have (on average 2.0833333333333335) internal successors, (50), 25 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:07,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:07,419 INFO L93 Difference]: Finished difference Result 81 states and 101 transitions. [2021-12-06 23:47:07,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 23:47:07,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 101 transitions. [2021-12-06 23:47:07,420 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13 [2021-12-06 23:47:07,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 100 transitions. [2021-12-06 23:47:07,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2021-12-06 23:47:07,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2021-12-06 23:47:07,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 100 transitions. [2021-12-06 23:47:07,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:07,421 INFO L681 BuchiCegarLoop]: Abstraction has 80 states and 100 transitions. [2021-12-06 23:47:07,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 100 transitions. [2021-12-06 23:47:07,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 67. [2021-12-06 23:47:07,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2686567164179106) internal successors, (85), 66 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:07,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 85 transitions. [2021-12-06 23:47:07,423 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 85 transitions. [2021-12-06 23:47:07,423 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 85 transitions. [2021-12-06 23:47:07,423 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 23:47:07,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 85 transitions. [2021-12-06 23:47:07,423 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2021-12-06 23:47:07,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:07,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:07,423 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:07,423 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:07,424 INFO L791 eck$LassoCheckResult]: Stem: 6095#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6106#L367 assume !(main_~length~0#1 < 1); 6097#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6098#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6099#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6107#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6110#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6109#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6112#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6113#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6125#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6123#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6122#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6121#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6119#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6120#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6114#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6115#L370-4 main_~j~0#1 := 0; 6151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6111#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6146#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6129#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6132#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6130#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6102#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6103#L378-2 [2021-12-06 23:47:07,424 INFO L793 eck$LassoCheckResult]: Loop: 6103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6126#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6103#L378-2 [2021-12-06 23:47:07,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:07,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1030456175, now seen corresponding path program 13 times [2021-12-06 23:47:07,424 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:07,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297731683] [2021-12-06 23:47:07,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:07,424 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:07,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:07,537 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:07,537 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:07,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297731683] [2021-12-06 23:47:07,537 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297731683] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:07,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [7179364] [2021-12-06 23:47:07,537 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 23:47:07,538 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:07,538 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:07,538 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:07,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-12-06 23:47:07,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:07,586 INFO L263 TraceCheckSpWp]: Trace formula consists of 174 conjuncts, 27 conjunts are in the unsatisfiable core [2021-12-06 23:47:07,587 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:07,623 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:07,701 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:47:07,702 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:07,702 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:07,813 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-12-06 23:47:07,814 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 26 [2021-12-06 23:47:07,848 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:07,848 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [7179364] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:07,849 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:07,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 25 [2021-12-06 23:47:07,849 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385299825] [2021-12-06 23:47:07,849 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:07,849 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:07,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:07,849 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2021-12-06 23:47:07,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:07,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156524796] [2021-12-06 23:47:07,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:07,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:07,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:07,851 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:07,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:07,853 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:07,885 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:07,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-12-06 23:47:07,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=573, Unknown=0, NotChecked=0, Total=650 [2021-12-06 23:47:07,885 INFO L87 Difference]: Start difference. First operand 67 states and 85 transitions. cyclomatic complexity: 23 Second operand has 26 states, 25 states have (on average 2.24) internal successors, (56), 26 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:08,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:08,099 INFO L93 Difference]: Finished difference Result 82 states and 102 transitions. [2021-12-06 23:47:08,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 23:47:08,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 102 transitions. [2021-12-06 23:47:08,100 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2021-12-06 23:47:08,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 81 states and 101 transitions. [2021-12-06 23:47:08,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-12-06 23:47:08,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-12-06 23:47:08,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 101 transitions. [2021-12-06 23:47:08,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:08,101 INFO L681 BuchiCegarLoop]: Abstraction has 81 states and 101 transitions. [2021-12-06 23:47:08,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 101 transitions. [2021-12-06 23:47:08,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 65. [2021-12-06 23:47:08,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.2769230769230768) internal successors, (83), 64 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:08,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 83 transitions. [2021-12-06 23:47:08,102 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 83 transitions. [2021-12-06 23:47:08,102 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 83 transitions. [2021-12-06 23:47:08,102 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 23:47:08,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 83 transitions. [2021-12-06 23:47:08,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2021-12-06 23:47:08,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:08,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:08,103 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:08,103 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:08,103 INFO L791 eck$LassoCheckResult]: Stem: 6461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6472#L367 assume !(main_~length~0#1 < 1); 6463#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6464#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6465#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6473#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6476#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6474#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6475#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6479#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6480#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6491#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6488#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6487#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6485#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6486#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6511#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6481#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6482#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6483#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6484#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6515#L370-4 main_~j~0#1 := 0; 6514#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6513#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6512#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6495#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6498#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6496#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6497#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6468#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6469#L378-2 [2021-12-06 23:47:08,103 INFO L793 eck$LassoCheckResult]: Loop: 6469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6492#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6469#L378-2 [2021-12-06 23:47:08,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:08,104 INFO L85 PathProgramCache]: Analyzing trace with hash -540432926, now seen corresponding path program 14 times [2021-12-06 23:47:08,104 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:08,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097475959] [2021-12-06 23:47:08,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:08,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:08,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:08,285 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:08,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:08,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097475959] [2021-12-06 23:47:08,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097475959] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:08,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [922039326] [2021-12-06 23:47:08,286 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:47:08,286 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:08,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:08,287 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:08,288 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-12-06 23:47:08,337 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:47:08,337 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:08,338 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 33 conjunts are in the unsatisfiable core [2021-12-06 23:47:08,339 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:08,364 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:08,424 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:08,425 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:08,436 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:08,436 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:08,474 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:08,475 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:47:08,575 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:08,577 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:08,577 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:08,762 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:08,764 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:08,788 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 23:47:08,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [922039326] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:08,788 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:08,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2021-12-06 23:47:08,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724312686] [2021-12-06 23:47:08,788 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:08,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:08,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:08,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2021-12-06 23:47:08,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:08,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352652046] [2021-12-06 23:47:08,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:08,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:08,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:08,791 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:08,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:08,793 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:08,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:08,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-12-06 23:47:08,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=479, Unknown=0, NotChecked=0, Total=552 [2021-12-06 23:47:08,823 INFO L87 Difference]: Start difference. First operand 65 states and 83 transitions. cyclomatic complexity: 23 Second operand has 24 states, 23 states have (on average 2.217391304347826) internal successors, (51), 24 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:09,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:09,097 INFO L93 Difference]: Finished difference Result 63 states and 76 transitions. [2021-12-06 23:47:09,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-12-06 23:47:09,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 76 transitions. [2021-12-06 23:47:09,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:09,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 61 states and 74 transitions. [2021-12-06 23:47:09,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-12-06 23:47:09,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-12-06 23:47:09,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 74 transitions. [2021-12-06 23:47:09,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:09,098 INFO L681 BuchiCegarLoop]: Abstraction has 61 states and 74 transitions. [2021-12-06 23:47:09,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 74 transitions. [2021-12-06 23:47:09,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 44. [2021-12-06 23:47:09,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 43 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:09,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 56 transitions. [2021-12-06 23:47:09,099 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 56 transitions. [2021-12-06 23:47:09,099 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 56 transitions. [2021-12-06 23:47:09,099 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 23:47:09,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 56 transitions. [2021-12-06 23:47:09,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:09,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:09,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:09,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:09,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:09,100 INFO L791 eck$LassoCheckResult]: Stem: 6818#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6819#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6829#L367 assume !(main_~length~0#1 < 1); 6820#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6821#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6822#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6830#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6832#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6860#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6859#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6856#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6855#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6853#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6852#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6843#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6827#L370-4 main_~j~0#1 := 0; 6828#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6825#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6826#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6833#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6846#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6845#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6841#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6840#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6839#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6838#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6823#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6824#L378-2 [2021-12-06 23:47:09,100 INFO L793 eck$LassoCheckResult]: Loop: 6824#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6837#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6824#L378-2 [2021-12-06 23:47:09,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:09,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1869061774, now seen corresponding path program 15 times [2021-12-06 23:47:09,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:09,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221555296] [2021-12-06 23:47:09,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:09,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:09,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:09,252 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:09,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:09,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221555296] [2021-12-06 23:47:09,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221555296] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:09,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1078854893] [2021-12-06 23:47:09,252 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:47:09,252 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:09,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:09,253 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:09,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-12-06 23:47:09,336 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2021-12-06 23:47:09,336 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:09,337 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 14 conjunts are in the unsatisfiable core [2021-12-06 23:47:09,338 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:09,495 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:09,495 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:09,590 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:09,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1078854893] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:09,590 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:09,590 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15] total 35 [2021-12-06 23:47:09,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544089800] [2021-12-06 23:47:09,591 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:09,591 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:09,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:09,591 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2021-12-06 23:47:09,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:09,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055812906] [2021-12-06 23:47:09,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:09,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:09,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:09,595 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:09,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:09,598 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:09,626 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:09,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-12-06 23:47:09,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=1018, Unknown=0, NotChecked=0, Total=1190 [2021-12-06 23:47:09,627 INFO L87 Difference]: Start difference. First operand 44 states and 56 transitions. cyclomatic complexity: 16 Second operand has 35 states, 35 states have (on average 2.1714285714285713) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:09,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:09,933 INFO L93 Difference]: Finished difference Result 62 states and 76 transitions. [2021-12-06 23:47:09,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-12-06 23:47:09,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 76 transitions. [2021-12-06 23:47:09,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:09,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 50 states and 63 transitions. [2021-12-06 23:47:09,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:47:09,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:47:09,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 63 transitions. [2021-12-06 23:47:09,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:09,934 INFO L681 BuchiCegarLoop]: Abstraction has 50 states and 63 transitions. [2021-12-06 23:47:09,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 63 transitions. [2021-12-06 23:47:09,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 46. [2021-12-06 23:47:09,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.2391304347826086) internal successors, (57), 45 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:09,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 57 transitions. [2021-12-06 23:47:09,935 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 57 transitions. [2021-12-06 23:47:09,935 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 57 transitions. [2021-12-06 23:47:09,935 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 23:47:09,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 57 transitions. [2021-12-06 23:47:09,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:09,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:09,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:09,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:09,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:09,936 INFO L791 eck$LassoCheckResult]: Stem: 7184#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7185#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7195#L367 assume !(main_~length~0#1 < 1); 7186#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7187#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7188#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7196#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7201#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7202#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7229#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7228#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7226#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7224#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7223#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7222#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7221#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7219#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7197#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7198#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7216#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7214#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7213#L370-4 main_~j~0#1 := 0; 7199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7191#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7192#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7209#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7208#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7207#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7206#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7204#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7203#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7189#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7190#L378-2 [2021-12-06 23:47:09,936 INFO L793 eck$LassoCheckResult]: Loop: 7190#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7205#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7190#L378-2 [2021-12-06 23:47:09,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:09,936 INFO L85 PathProgramCache]: Analyzing trace with hash 335000357, now seen corresponding path program 16 times [2021-12-06 23:47:09,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:09,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359755418] [2021-12-06 23:47:09,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:09,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:09,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:10,070 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:10,070 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:10,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359755418] [2021-12-06 23:47:10,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359755418] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:10,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [344385978] [2021-12-06 23:47:10,070 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 23:47:10,071 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:10,071 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:10,071 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:10,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-12-06 23:47:10,125 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 23:47:10,125 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:10,126 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 30 conjunts are in the unsatisfiable core [2021-12-06 23:47:10,127 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:10,158 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:10,201 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:10,202 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:47:10,289 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:47:10,291 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:10,291 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:22,467 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_223| Int)) (or (forall ((v_ArrVal_710 Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_223| 4)) v_ArrVal_710) (+ 16 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_223| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2021-12-06 23:47:22,476 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2021-12-06 23:47:22,479 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 190 treesize of output 182 [2021-12-06 23:47:22,547 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 5 not checked. [2021-12-06 23:47:22,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [344385978] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:22,547 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:22,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 29 [2021-12-06 23:47:22,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705388866] [2021-12-06 23:47:22,547 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:22,547 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:22,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:22,548 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2021-12-06 23:47:22,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:22,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356824429] [2021-12-06 23:47:22,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:22,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:22,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:22,550 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:22,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:22,552 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:22,581 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:22,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-12-06 23:47:22,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=722, Unknown=1, NotChecked=54, Total=870 [2021-12-06 23:47:22,581 INFO L87 Difference]: Start difference. First operand 46 states and 57 transitions. cyclomatic complexity: 15 Second operand has 30 states, 29 states have (on average 2.1379310344827585) internal successors, (62), 30 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:34,691 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((|v_ULTIMATE.start_main_~i~0#1_223| Int)) (or (forall ((v_ArrVal_710 Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_223| 4)) v_ArrVal_710) (+ 16 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 2) 0)) (< |v_ULTIMATE.start_main_~i~0#1_223| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) (<= |c_ULTIMATE.start_main_~i~0#1| 4) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= 4 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-12-06 23:47:34,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:34,824 INFO L93 Difference]: Finished difference Result 66 states and 81 transitions. [2021-12-06 23:47:34,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-12-06 23:47:34,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 81 transitions. [2021-12-06 23:47:34,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:47:34,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 65 states and 80 transitions. [2021-12-06 23:47:34,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 23:47:34,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 23:47:34,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 80 transitions. [2021-12-06 23:47:34,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:34,826 INFO L681 BuchiCegarLoop]: Abstraction has 65 states and 80 transitions. [2021-12-06 23:47:34,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 80 transitions. [2021-12-06 23:47:34,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 49. [2021-12-06 23:47:34,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2653061224489797) internal successors, (62), 48 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:34,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 62 transitions. [2021-12-06 23:47:34,828 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 62 transitions. [2021-12-06 23:47:34,828 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 62 transitions. [2021-12-06 23:47:34,828 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 23:47:34,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 62 transitions. [2021-12-06 23:47:34,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:34,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:34,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:34,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:34,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:34,829 INFO L791 eck$LassoCheckResult]: Stem: 7537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7548#L367 assume !(main_~length~0#1 < 1); 7539#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7540#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7541#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7549#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7572#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7551#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7552#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7555#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7571#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7570#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7569#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7568#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7564#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7561#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7557#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7584#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7582#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7581#L370-4 main_~j~0#1 := 0; 7553#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7546#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7547#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7579#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7577#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7574#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7544#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7545#L378-2 [2021-12-06 23:47:34,829 INFO L793 eck$LassoCheckResult]: Loop: 7545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7575#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7545#L378-2 [2021-12-06 23:47:34,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:34,830 INFO L85 PathProgramCache]: Analyzing trace with hash -242230295, now seen corresponding path program 17 times [2021-12-06 23:47:34,830 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:34,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100934118] [2021-12-06 23:47:34,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:34,830 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:34,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:35,038 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:35,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:35,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100934118] [2021-12-06 23:47:35,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100934118] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:35,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2041507353] [2021-12-06 23:47:35,038 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 23:47:35,038 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:35,039 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:35,039 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:35,041 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-12-06 23:47:35,103 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2021-12-06 23:47:35,103 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:35,104 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 34 conjunts are in the unsatisfiable core [2021-12-06 23:47:35,105 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:35,137 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:35,212 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:35,212 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:47:35,230 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:47:35,230 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:47:35,396 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:35,398 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:35,398 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:35,581 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:35,583 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:35,612 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:35,612 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2041507353] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:35,612 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:35,612 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 17] total 27 [2021-12-06 23:47:35,613 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100543997] [2021-12-06 23:47:35,613 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:35,613 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:35,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:35,613 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2021-12-06 23:47:35,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:35,613 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140870075] [2021-12-06 23:47:35,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:35,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:35,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:35,615 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:35,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:35,617 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:35,646 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:35,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-12-06 23:47:35,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=673, Unknown=0, NotChecked=0, Total=756 [2021-12-06 23:47:35,647 INFO L87 Difference]: Start difference. First operand 49 states and 62 transitions. cyclomatic complexity: 17 Second operand has 28 states, 27 states have (on average 2.074074074074074) internal successors, (56), 28 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:36,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:36,087 INFO L93 Difference]: Finished difference Result 104 states and 128 transitions. [2021-12-06 23:47:36,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-12-06 23:47:36,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104 states and 128 transitions. [2021-12-06 23:47:36,088 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 23:47:36,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104 states to 103 states and 127 transitions. [2021-12-06 23:47:36,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 23:47:36,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 23:47:36,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 127 transitions. [2021-12-06 23:47:36,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:36,089 INFO L681 BuchiCegarLoop]: Abstraction has 103 states and 127 transitions. [2021-12-06 23:47:36,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 127 transitions. [2021-12-06 23:47:36,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 56. [2021-12-06 23:47:36,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 55 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:36,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 74 transitions. [2021-12-06 23:47:36,090 INFO L704 BuchiCegarLoop]: Abstraction has 56 states and 74 transitions. [2021-12-06 23:47:36,090 INFO L587 BuchiCegarLoop]: Abstraction has 56 states and 74 transitions. [2021-12-06 23:47:36,090 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 23:47:36,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 74 transitions. [2021-12-06 23:47:36,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:36,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:36,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:36,091 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:36,091 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:36,091 INFO L791 eck$LassoCheckResult]: Stem: 7939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7940#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7950#L367 assume !(main_~length~0#1 < 1); 7941#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7942#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7951#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7994#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7993#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7992#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7991#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7989#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7988#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7987#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7986#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7985#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7984#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7983#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7967#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7952#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7953#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7955#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7976#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7948#L370-4 main_~j~0#1 := 0; 7949#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7946#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7954#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7966#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7965#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7963#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7962#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7961#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7960#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7944#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7945#L378-2 [2021-12-06 23:47:36,091 INFO L793 eck$LassoCheckResult]: Loop: 7945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7959#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7945#L378-2 [2021-12-06 23:47:36,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:36,091 INFO L85 PathProgramCache]: Analyzing trace with hash 833863658, now seen corresponding path program 18 times [2021-12-06 23:47:36,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:36,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920911273] [2021-12-06 23:47:36,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:36,092 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:36,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:36,255 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:36,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:36,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920911273] [2021-12-06 23:47:36,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920911273] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:36,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [157835666] [2021-12-06 23:47:36,255 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 23:47:36,255 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:36,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:36,256 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:36,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-12-06 23:47:36,356 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-12-06 23:47:36,357 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:36,358 INFO L263 TraceCheckSpWp]: Trace formula consists of 208 conjuncts, 42 conjunts are in the unsatisfiable core [2021-12-06 23:47:36,360 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:36,397 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:36,452 INFO L354 Elim1Store]: treesize reduction 29, result has 39.6 percent of original size [2021-12-06 23:47:36,452 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2021-12-06 23:47:36,506 INFO L354 Elim1Store]: treesize reduction 29, result has 39.6 percent of original size [2021-12-06 23:47:36,506 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 42 [2021-12-06 23:47:37,170 INFO L354 Elim1Store]: treesize reduction 46, result has 6.1 percent of original size [2021-12-06 23:47:37,170 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 13 [2021-12-06 23:47:37,173 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:37,173 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:45,531 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 50 [2021-12-06 23:47:45,536 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-12-06 23:47:45,537 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 113 treesize of output 103 [2021-12-06 23:47:45,683 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 2 proven. 79 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:45,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [157835666] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:45,683 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:45,684 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 20, 19] total 47 [2021-12-06 23:47:45,684 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579310453] [2021-12-06 23:47:45,684 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:45,684 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:45,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:45,684 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2021-12-06 23:47:45,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:45,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329757097] [2021-12-06 23:47:45,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:45,685 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:45,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:45,687 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:45,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:45,689 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:45,722 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:45,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-12-06 23:47:45,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=267, Invalid=1985, Unknown=4, NotChecked=0, Total=2256 [2021-12-06 23:47:45,723 INFO L87 Difference]: Start difference. First operand 56 states and 74 transitions. cyclomatic complexity: 22 Second operand has 48 states, 47 states have (on average 1.872340425531915) internal successors, (88), 48 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:46,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:46,898 INFO L93 Difference]: Finished difference Result 110 states and 133 transitions. [2021-12-06 23:47:46,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-12-06 23:47:46,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 133 transitions. [2021-12-06 23:47:46,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:46,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 91 states and 113 transitions. [2021-12-06 23:47:46,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-12-06 23:47:46,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-12-06 23:47:46,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 113 transitions. [2021-12-06 23:47:46,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:46,900 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 113 transitions. [2021-12-06 23:47:46,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 113 transitions. [2021-12-06 23:47:46,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 77. [2021-12-06 23:47:46,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.2857142857142858) internal successors, (99), 76 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:46,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 99 transitions. [2021-12-06 23:47:46,901 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 99 transitions. [2021-12-06 23:47:46,901 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 99 transitions. [2021-12-06 23:47:46,901 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 23:47:46,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 99 transitions. [2021-12-06 23:47:46,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:47:46,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:46,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:46,902 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:46,902 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:46,902 INFO L791 eck$LassoCheckResult]: Stem: 8425#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8436#L367 assume !(main_~length~0#1 < 1); 8427#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8428#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8429#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8437#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8483#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8482#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8481#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8480#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8479#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8478#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8476#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8474#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8472#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8471#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8466#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8443#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8438#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8439#L370-4 main_~j~0#1 := 0; 8495#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8441#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8490#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8489#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8488#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8487#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8486#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8446#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8447#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8448#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8430#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8431#L378-2 [2021-12-06 23:47:46,902 INFO L793 eck$LassoCheckResult]: Loop: 8431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8444#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8431#L378-2 [2021-12-06 23:47:46,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:46,903 INFO L85 PathProgramCache]: Analyzing trace with hash -187204696, now seen corresponding path program 19 times [2021-12-06 23:47:46,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:46,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277126816] [2021-12-06 23:47:46,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:46,903 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:46,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:47,151 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:47,152 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:47,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277126816] [2021-12-06 23:47:47,152 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277126816] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:47,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998854163] [2021-12-06 23:47:47,152 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 23:47:47,152 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:47,152 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:47,153 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:47,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-12-06 23:47:47,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:47,214 INFO L263 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 33 conjunts are in the unsatisfiable core [2021-12-06 23:47:47,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:47,267 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:47,472 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:47:47,474 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:47,474 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:47:47,561 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:47:47,562 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:47:47,598 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:47,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998854163] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:47:47,598 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:47:47,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16] total 25 [2021-12-06 23:47:47,599 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114844478] [2021-12-06 23:47:47,599 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:47:47,599 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:47:47,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:47,599 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2021-12-06 23:47:47,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:47,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970725152] [2021-12-06 23:47:47,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:47,599 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:47,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:47,602 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:47:47,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:47:47,604 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:47:47,638 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:47:47,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-12-06 23:47:47,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=577, Unknown=0, NotChecked=0, Total=650 [2021-12-06 23:47:47,639 INFO L87 Difference]: Start difference. First operand 77 states and 99 transitions. cyclomatic complexity: 27 Second operand has 26 states, 25 states have (on average 2.2) internal successors, (55), 26 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:48,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:47:48,014 INFO L93 Difference]: Finished difference Result 124 states and 157 transitions. [2021-12-06 23:47:48,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-12-06 23:47:48,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 157 transitions. [2021-12-06 23:47:48,015 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14 [2021-12-06 23:47:48,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 123 states and 156 transitions. [2021-12-06 23:47:48,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-12-06 23:47:48,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-12-06 23:47:48,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 156 transitions. [2021-12-06 23:47:48,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:47:48,016 INFO L681 BuchiCegarLoop]: Abstraction has 123 states and 156 transitions. [2021-12-06 23:47:48,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 156 transitions. [2021-12-06 23:47:48,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 105. [2021-12-06 23:47:48,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.2952380952380953) internal successors, (136), 104 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:47:48,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 136 transitions. [2021-12-06 23:47:48,018 INFO L704 BuchiCegarLoop]: Abstraction has 105 states and 136 transitions. [2021-12-06 23:47:48,018 INFO L587 BuchiCegarLoop]: Abstraction has 105 states and 136 transitions. [2021-12-06 23:47:48,018 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-06 23:47:48,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 136 transitions. [2021-12-06 23:47:48,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2021-12-06 23:47:48,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:47:48,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:47:48,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:47:48,019 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:47:48,019 INFO L791 eck$LassoCheckResult]: Stem: 8875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8886#L367 assume !(main_~length~0#1 < 1); 8877#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8878#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8879#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8887#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8949#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8947#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8945#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8944#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8943#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8942#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8941#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8940#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8938#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8937#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8936#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8934#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8932#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8929#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8925#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8926#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8950#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8958#L370-4 main_~j~0#1 := 0; 8952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8953#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8915#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8908#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8909#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8977#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8898#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8882#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8883#L378-2 [2021-12-06 23:47:48,019 INFO L793 eck$LassoCheckResult]: Loop: 8883#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8897#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8883#L378-2 [2021-12-06 23:47:48,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:47:48,020 INFO L85 PathProgramCache]: Analyzing trace with hash -762539921, now seen corresponding path program 20 times [2021-12-06 23:47:48,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:47:48,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579138992] [2021-12-06 23:47:48,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:47:48,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:47:48,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:47:48,180 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:48,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:47:48,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579138992] [2021-12-06 23:47:48,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579138992] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:47:48,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [738257979] [2021-12-06 23:47:48,181 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:47:48,181 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:47:48,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:47:48,182 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:47:48,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-12-06 23:47:48,240 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:47:48,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:47:48,242 INFO L263 TraceCheckSpWp]: Trace formula consists of 218 conjuncts, 37 conjunts are in the unsatisfiable core [2021-12-06 23:47:48,243 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:47:48,276 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:47:48,308 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:48,308 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:47:48,319 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:48,319 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:47:48,345 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:48,346 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:47:48,358 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:47:48,358 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:47:48,440 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:47:48,442 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:47:48,442 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:51:36,678 WARN L227 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 24 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 23:51:52,315 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_274| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_274| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|v_ULTIMATE.start_main_~i~0#1_273| Int) (v_ArrVal_879 Int) (v_ArrVal_875 Int)) (or (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_274| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_875) (+ (* |v_ULTIMATE.start_main_~i~0#1_273| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_879) (+ 16 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 2) 0) (< |v_ULTIMATE.start_main_~i~0#1_273| (+ |v_ULTIMATE.start_main_~i~0#1_274| 1)))))) is different from false [2021-12-06 23:51:52,332 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 30 [2021-12-06 23:51:52,336 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 834 treesize of output 818 [2021-12-06 23:51:52,700 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 80 refuted. 4 times theorem prover too weak. 0 trivial. 6 not checked. [2021-12-06 23:51:52,700 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [738257979] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:51:52,700 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:51:52,700 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 17] total 32 [2021-12-06 23:51:52,700 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601618813] [2021-12-06 23:51:52,700 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:51:52,701 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:51:52,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:51:52,701 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2021-12-06 23:51:52,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:51:52,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812495227] [2021-12-06 23:51:52,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:51:52,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:51:52,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:51:52,703 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:51:52,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:51:52,705 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:51:52,736 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:51:52,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-12-06 23:51:52,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=861, Unknown=23, NotChecked=60, Total=1056 [2021-12-06 23:51:52,737 INFO L87 Difference]: Start difference. First operand 105 states and 136 transitions. cyclomatic complexity: 38 Second operand has 33 states, 32 states have (on average 2.15625) internal successors, (69), 33 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:04,830 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((|v_ULTIMATE.start_main_~i~0#1_274| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_274| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|v_ULTIMATE.start_main_~i~0#1_273| Int) (v_ArrVal_879 Int) (v_ArrVal_875 Int)) (or (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_274| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_875) (+ (* |v_ULTIMATE.start_main_~i~0#1_273| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_879) (+ 16 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 2) 0) (< |v_ULTIMATE.start_main_~i~0#1_273| (+ |v_ULTIMATE.start_main_~i~0#1_274| 1)))))) (<= |c_ULTIMATE.start_main_~i~0#1| 4) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= 4 |c_ULTIMATE.start_main_~i~0#1|)) is different from false [2021-12-06 23:52:05,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:05,067 INFO L93 Difference]: Finished difference Result 151 states and 184 transitions. [2021-12-06 23:52:05,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-12-06 23:52:05,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 184 transitions. [2021-12-06 23:52:05,068 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-12-06 23:52:05,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 149 states and 181 transitions. [2021-12-06 23:52:05,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2021-12-06 23:52:05,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2021-12-06 23:52:05,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 149 states and 181 transitions. [2021-12-06 23:52:05,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:05,069 INFO L681 BuchiCegarLoop]: Abstraction has 149 states and 181 transitions. [2021-12-06 23:52:05,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states and 181 transitions. [2021-12-06 23:52:05,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 83. [2021-12-06 23:52:05,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.3132530120481927) internal successors, (109), 82 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:05,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 109 transitions. [2021-12-06 23:52:05,071 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 109 transitions. [2021-12-06 23:52:05,071 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 109 transitions. [2021-12-06 23:52:05,071 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-12-06 23:52:05,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 109 transitions. [2021-12-06 23:52:05,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:05,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:05,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:05,071 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:05,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:05,072 INFO L791 eck$LassoCheckResult]: Stem: 9403#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9414#L367 assume !(main_~length~0#1 < 1); 9405#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9406#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9407#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9415#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9459#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9458#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9457#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9456#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9455#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9454#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9453#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9451#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9450#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9449#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9447#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9446#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9445#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9443#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9441#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9438#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9439#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9437#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9436#L370-4 main_~j~0#1 := 0; 9435#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9434#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9432#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9430#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9428#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9422#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9410#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9411#L378-2 [2021-12-06 23:52:05,072 INFO L793 eck$LassoCheckResult]: Loop: 9411#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9424#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9411#L378-2 [2021-12-06 23:52:05,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:05,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1580188371, now seen corresponding path program 21 times [2021-12-06 23:52:05,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:05,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259434217] [2021-12-06 23:52:05,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:05,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:05,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:05,317 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:05,317 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:05,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259434217] [2021-12-06 23:52:05,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259434217] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:05,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1742613234] [2021-12-06 23:52:05,317 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:52:05,317 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:05,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:05,318 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:05,319 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-12-06 23:52:05,439 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-12-06 23:52:05,439 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:05,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 39 conjunts are in the unsatisfiable core [2021-12-06 23:52:05,443 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:05,479 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:05,521 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:05,522 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:52:05,533 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:05,533 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:52:05,561 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:05,561 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:52:05,571 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:05,571 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-12-06 23:52:05,667 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:52:05,669 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:05,669 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:05,878 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:52:05,880 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:52:05,909 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 1 proven. 88 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 23:52:05,909 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1742613234] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:05,909 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:05,909 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 25 [2021-12-06 23:52:05,909 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756161891] [2021-12-06 23:52:05,909 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:05,909 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:05,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:05,910 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2021-12-06 23:52:05,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:05,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104577164] [2021-12-06 23:52:05,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:05,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:05,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:05,912 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:05,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:05,914 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:05,943 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:05,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-12-06 23:52:05,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=573, Unknown=0, NotChecked=0, Total=650 [2021-12-06 23:52:05,944 INFO L87 Difference]: Start difference. First operand 83 states and 109 transitions. cyclomatic complexity: 34 Second operand has 26 states, 25 states have (on average 2.28) internal successors, (57), 26 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:06,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:06,310 INFO L93 Difference]: Finished difference Result 102 states and 128 transitions. [2021-12-06 23:52:06,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-12-06 23:52:06,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 128 transitions. [2021-12-06 23:52:06,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:06,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 101 states and 126 transitions. [2021-12-06 23:52:06,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-12-06 23:52:06,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-12-06 23:52:06,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 126 transitions. [2021-12-06 23:52:06,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:06,312 INFO L681 BuchiCegarLoop]: Abstraction has 101 states and 126 transitions. [2021-12-06 23:52:06,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 126 transitions. [2021-12-06 23:52:06,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 55. [2021-12-06 23:52:06,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.2727272727272727) internal successors, (70), 54 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:06,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 70 transitions. [2021-12-06 23:52:06,314 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 70 transitions. [2021-12-06 23:52:06,314 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 70 transitions. [2021-12-06 23:52:06,314 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-12-06 23:52:06,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 70 transitions. [2021-12-06 23:52:06,314 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:06,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:06,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:06,314 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:06,314 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:06,314 INFO L791 eck$LassoCheckResult]: Stem: 9851#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9862#L367 assume !(main_~length~0#1 < 1); 9853#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9854#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9863#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9904#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9903#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9901#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9900#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9899#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9898#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9897#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9896#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9895#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9893#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9890#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9884#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9856#L370-4 main_~j~0#1 := 0; 9857#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9883#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9869#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9860#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9861#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9882#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9881#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9880#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9876#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9875#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9874#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9872#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9871#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9858#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9859#L378-2 [2021-12-06 23:52:06,314 INFO L793 eck$LassoCheckResult]: Loop: 9859#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9873#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9859#L378-2 [2021-12-06 23:52:06,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:06,315 INFO L85 PathProgramCache]: Analyzing trace with hash 484913003, now seen corresponding path program 22 times [2021-12-06 23:52:06,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:06,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40523400] [2021-12-06 23:52:06,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:06,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:06,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:06,478 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:06,478 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:06,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40523400] [2021-12-06 23:52:06,478 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40523400] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:06,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1062659272] [2021-12-06 23:52:06,478 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 23:52:06,478 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:06,478 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:06,479 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:06,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-12-06 23:52:06,534 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 23:52:06,534 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:06,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 23:52:06,536 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:06,737 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:06,737 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:06,853 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:06,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1062659272] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:06,854 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:06,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 40 [2021-12-06 23:52:06,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318472878] [2021-12-06 23:52:06,854 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:06,854 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:06,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:06,854 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2021-12-06 23:52:06,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:06,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769447870] [2021-12-06 23:52:06,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:06,854 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:06,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:06,857 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:06,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:06,859 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:06,886 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:06,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-12-06 23:52:06,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=220, Invalid=1340, Unknown=0, NotChecked=0, Total=1560 [2021-12-06 23:52:06,888 INFO L87 Difference]: Start difference. First operand 55 states and 70 transitions. cyclomatic complexity: 20 Second operand has 40 states, 40 states have (on average 2.2) internal successors, (88), 40 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:07,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:07,272 INFO L93 Difference]: Finished difference Result 78 states and 96 transitions. [2021-12-06 23:52:07,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 23:52:07,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 96 transitions. [2021-12-06 23:52:07,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:07,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 64 states and 81 transitions. [2021-12-06 23:52:07,273 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-12-06 23:52:07,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-12-06 23:52:07,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 81 transitions. [2021-12-06 23:52:07,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:07,274 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 81 transitions. [2021-12-06 23:52:07,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 81 transitions. [2021-12-06 23:52:07,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 54. [2021-12-06 23:52:07,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2592592592592593) internal successors, (68), 53 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:07,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 68 transitions. [2021-12-06 23:52:07,275 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 68 transitions. [2021-12-06 23:52:07,275 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 68 transitions. [2021-12-06 23:52:07,275 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-12-06 23:52:07,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 68 transitions. [2021-12-06 23:52:07,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:07,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:07,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:07,275 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:07,275 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:07,276 INFO L791 eck$LassoCheckResult]: Stem: 10283#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10284#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10294#L367 assume !(main_~length~0#1 < 1); 10285#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10286#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10287#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10295#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10298#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10297#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10334#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10331#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10328#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10323#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10322#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10321#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10320#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10316#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10314#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10311#L370-4 main_~j~0#1 := 0; 10310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10299#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10309#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10308#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10307#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10306#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10305#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10304#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10301#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10300#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10288#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10289#L378-2 [2021-12-06 23:52:07,276 INFO L793 eck$LassoCheckResult]: Loop: 10289#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10302#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10289#L378-2 [2021-12-06 23:52:07,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:07,276 INFO L85 PathProgramCache]: Analyzing trace with hash 836329326, now seen corresponding path program 23 times [2021-12-06 23:52:07,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:07,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087043557] [2021-12-06 23:52:07,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:07,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:07,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:07,446 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:07,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:07,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087043557] [2021-12-06 23:52:07,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087043557] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:07,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [936993001] [2021-12-06 23:52:07,447 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 23:52:07,447 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:07,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:07,448 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:07,449 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-12-06 23:52:07,575 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-12-06 23:52:07,575 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:07,577 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 34 conjunts are in the unsatisfiable core [2021-12-06 23:52:07,578 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:07,616 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:07,659 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:52:07,659 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2021-12-06 23:52:07,795 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-12-06 23:52:07,797 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:07,797 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:36,074 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_314| Int)) (or (forall ((v_ArrVal_1001 Int) (|v_ULTIMATE.start_main_~j~0#1_328| Int)) (or (< 0 |v_ULTIMATE.start_main_~j~0#1_328|) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_314| 4)) v_ArrVal_1001) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~j~0#1_328| 4) 20)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_328| 0))) (< |v_ULTIMATE.start_main_~i~0#1_314| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2021-12-06 23:52:36,087 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 26 [2021-12-06 23:52:36,090 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 105 treesize of output 98 [2021-12-06 23:52:36,156 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 94 refuted. 0 times theorem prover too weak. 0 trivial. 6 not checked. [2021-12-06 23:52:36,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [936993001] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:36,156 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:36,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 35 [2021-12-06 23:52:36,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310797277] [2021-12-06 23:52:36,157 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:36,157 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:36,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:36,157 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2021-12-06 23:52:36,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:36,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150428295] [2021-12-06 23:52:36,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:36,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:36,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:36,159 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:36,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:36,161 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:36,193 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:36,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-12-06 23:52:36,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=1056, Unknown=22, NotChecked=66, Total=1260 [2021-12-06 23:52:36,193 INFO L87 Difference]: Start difference. First operand 54 states and 68 transitions. cyclomatic complexity: 19 Second operand has 36 states, 35 states have (on average 2.085714285714286) internal successors, (73), 36 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:48,359 WARN L838 $PredicateComparison]: unable to prove that (and (<= 5 |c_ULTIMATE.start_main_~i~0#1|) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= |c_ULTIMATE.start_main_~i~0#1| 5) (forall ((|v_ULTIMATE.start_main_~i~0#1_314| Int)) (or (forall ((v_ArrVal_1001 Int) (|v_ULTIMATE.start_main_~j~0#1_328| Int)) (or (< 0 |v_ULTIMATE.start_main_~j~0#1_328|) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_314| 4)) v_ArrVal_1001) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~j~0#1_328| 4) 20)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_328| 0))) (< |v_ULTIMATE.start_main_~i~0#1_314| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from false [2021-12-06 23:52:48,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:48,517 INFO L93 Difference]: Finished difference Result 71 states and 87 transitions. [2021-12-06 23:52:48,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-12-06 23:52:48,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 87 transitions. [2021-12-06 23:52:48,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:48,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 86 transitions. [2021-12-06 23:52:48,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-12-06 23:52:48,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-12-06 23:52:48,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 86 transitions. [2021-12-06 23:52:48,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:48,519 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 86 transitions. [2021-12-06 23:52:48,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 86 transitions. [2021-12-06 23:52:48,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 57. [2021-12-06 23:52:48,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.280701754385965) internal successors, (73), 56 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:48,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 73 transitions. [2021-12-06 23:52:48,520 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2021-12-06 23:52:48,520 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2021-12-06 23:52:48,520 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-12-06 23:52:48,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 73 transitions. [2021-12-06 23:52:48,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:48,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:48,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:48,521 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:48,521 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:48,521 INFO L791 eck$LassoCheckResult]: Stem: 10685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10696#L367 assume !(main_~length~0#1 < 1); 10687#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10688#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10689#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10697#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10698#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10699#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10738#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10737#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10736#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10735#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10732#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10731#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10730#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10728#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10722#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10717#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10716#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10714#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10713#L370-4 main_~j~0#1 := 0; 10712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10701#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10710#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10709#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10708#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10707#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10706#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10703#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10692#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10693#L378-2 [2021-12-06 23:52:48,521 INFO L793 eck$LassoCheckResult]: Loop: 10693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10704#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10693#L378-2 [2021-12-06 23:52:48,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:48,521 INFO L85 PathProgramCache]: Analyzing trace with hash 168453938, now seen corresponding path program 24 times [2021-12-06 23:52:48,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:48,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792276209] [2021-12-06 23:52:48,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:48,521 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:48,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:48,754 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:48,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:48,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792276209] [2021-12-06 23:52:48,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792276209] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:48,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [442554618] [2021-12-06 23:52:48,754 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 23:52:48,754 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:48,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:48,755 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:48,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-12-06 23:52:48,861 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-12-06 23:52:48,861 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:48,863 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 38 conjunts are in the unsatisfiable core [2021-12-06 23:52:48,865 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:48,904 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:48,987 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:52:48,987 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:52:49,005 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-12-06 23:52:49,005 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2021-12-06 23:52:49,161 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:52:49,162 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:49,162 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:49,310 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:52:49,312 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:52:49,351 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:49,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [442554618] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:49,351 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:49,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2021-12-06 23:52:49,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215973543] [2021-12-06 23:52:49,351 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:49,351 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:49,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:49,351 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2021-12-06 23:52:49,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:49,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586989144] [2021-12-06 23:52:49,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:49,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:49,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:49,354 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:49,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:49,356 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:49,389 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:49,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-12-06 23:52:49,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=730, Unknown=0, NotChecked=0, Total=812 [2021-12-06 23:52:49,390 INFO L87 Difference]: Start difference. First operand 57 states and 73 transitions. cyclomatic complexity: 21 Second operand has 29 states, 28 states have (on average 2.1785714285714284) internal successors, (61), 29 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:49,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:49,943 INFO L93 Difference]: Finished difference Result 118 states and 145 transitions. [2021-12-06 23:52:49,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-12-06 23:52:49,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 145 transitions. [2021-12-06 23:52:49,944 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2021-12-06 23:52:49,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 117 states and 144 transitions. [2021-12-06 23:52:49,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-12-06 23:52:49,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-12-06 23:52:49,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 144 transitions. [2021-12-06 23:52:49,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:49,945 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 144 transitions. [2021-12-06 23:52:49,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 144 transitions. [2021-12-06 23:52:49,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 64. [2021-12-06 23:52:49,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.328125) internal successors, (85), 63 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:49,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 85 transitions. [2021-12-06 23:52:49,946 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 85 transitions. [2021-12-06 23:52:49,946 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 85 transitions. [2021-12-06 23:52:49,946 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-12-06 23:52:49,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 85 transitions. [2021-12-06 23:52:49,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:49,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:49,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:49,947 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:49,947 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:49,947 INFO L791 eck$LassoCheckResult]: Stem: 11142#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11153#L367 assume !(main_~length~0#1 < 1); 11144#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11145#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11146#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11154#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11155#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11156#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11204#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11203#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11202#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11200#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11198#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11197#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11194#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11192#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11188#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11181#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11147#L370-4 main_~j~0#1 := 0; 11148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11151#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11158#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11170#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11169#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11168#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11167#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11165#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11164#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11163#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11149#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 11150#L378-2 [2021-12-06 23:52:49,947 INFO L793 eck$LassoCheckResult]: Loop: 11150#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11161#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11150#L378-2 [2021-12-06 23:52:49,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:49,947 INFO L85 PathProgramCache]: Analyzing trace with hash -1747225229, now seen corresponding path program 25 times [2021-12-06 23:52:49,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:49,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144288482] [2021-12-06 23:52:49,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:49,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:49,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:50,122 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:50,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:50,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144288482] [2021-12-06 23:52:50,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144288482] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:50,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1242941507] [2021-12-06 23:52:50,123 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 23:52:50,123 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:50,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:50,124 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:50,124 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-12-06 23:52:50,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:50,192 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 45 conjunts are in the unsatisfiable core [2021-12-06 23:52:50,193 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:50,238 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:50,290 INFO L354 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2021-12-06 23:52:50,291 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-12-06 23:52:50,305 INFO L354 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2021-12-06 23:52:50,305 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-12-06 23:52:50,693 INFO L354 Elim1Store]: treesize reduction 44, result has 6.4 percent of original size [2021-12-06 23:52:50,693 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 33 treesize of output 13 [2021-12-06 23:52:50,695 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:50,695 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:51,116 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 50 [2021-12-06 23:52:51,120 INFO L354 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2021-12-06 23:52:51,120 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 107 treesize of output 99 [2021-12-06 23:52:51,306 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:51,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1242941507] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:51,307 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:51,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 47 [2021-12-06 23:52:51,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923214150] [2021-12-06 23:52:51,307 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:51,307 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:51,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:51,307 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2021-12-06 23:52:51,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:51,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539413189] [2021-12-06 23:52:51,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:51,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:51,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:51,310 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:51,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:51,313 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:51,345 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:51,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-12-06 23:52:51,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=216, Invalid=2040, Unknown=0, NotChecked=0, Total=2256 [2021-12-06 23:52:51,346 INFO L87 Difference]: Start difference. First operand 64 states and 85 transitions. cyclomatic complexity: 26 Second operand has 48 states, 47 states have (on average 2.127659574468085) internal successors, (100), 48 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:51,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:51,657 INFO L93 Difference]: Finished difference Result 134 states and 163 transitions. [2021-12-06 23:52:51,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-12-06 23:52:51,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 163 transitions. [2021-12-06 23:52:51,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:51,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 132 states and 160 transitions. [2021-12-06 23:52:51,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-12-06 23:52:51,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-12-06 23:52:51,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 160 transitions. [2021-12-06 23:52:51,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:51,659 INFO L681 BuchiCegarLoop]: Abstraction has 132 states and 160 transitions. [2021-12-06 23:52:51,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 160 transitions. [2021-12-06 23:52:51,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 90. [2021-12-06 23:52:51,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.3111111111111111) internal successors, (118), 89 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:51,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 118 transitions. [2021-12-06 23:52:51,661 INFO L704 BuchiCegarLoop]: Abstraction has 90 states and 118 transitions. [2021-12-06 23:52:51,661 INFO L587 BuchiCegarLoop]: Abstraction has 90 states and 118 transitions. [2021-12-06 23:52:51,661 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-12-06 23:52:51,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 118 transitions. [2021-12-06 23:52:51,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-12-06 23:52:51,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:51,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:51,661 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:51,661 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 23:52:51,662 INFO L791 eck$LassoCheckResult]: Stem: 11641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11652#L367 assume !(main_~length~0#1 < 1); 11643#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11644#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11645#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11653#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11701#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11698#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11696#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11695#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11694#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11693#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11692#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11690#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11689#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11655#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11657#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11723#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11646#L370-4 main_~j~0#1 := 0; 11647#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11650#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11651#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11709#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11707#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11705#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11661#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11663#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11648#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 11649#L378-2 [2021-12-06 23:52:51,662 INFO L793 eck$LassoCheckResult]: Loop: 11649#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11662#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11649#L378-2 [2021-12-06 23:52:51,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:51,662 INFO L85 PathProgramCache]: Analyzing trace with hash 553597361, now seen corresponding path program 26 times [2021-12-06 23:52:51,662 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:51,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161781369] [2021-12-06 23:52:51,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:51,662 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:51,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:51,901 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:51,901 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:51,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161781369] [2021-12-06 23:52:51,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161781369] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:51,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1535545262] [2021-12-06 23:52:51,902 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 23:52:51,902 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:51,902 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:51,903 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:51,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-12-06 23:52:51,963 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 23:52:51,963 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:51,964 INFO L263 TraceCheckSpWp]: Trace formula consists of 228 conjuncts, 37 conjunts are in the unsatisfiable core [2021-12-06 23:52:51,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:52,009 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:52,218 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-12-06 23:52:52,220 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:52,220 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:52:52,305 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-12-06 23:52:52,306 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-12-06 23:52:52,349 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:52,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1535545262] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 23:52:52,350 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 23:52:52,350 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18] total 28 [2021-12-06 23:52:52,350 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96255846] [2021-12-06 23:52:52,350 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 23:52:52,350 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 23:52:52,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:52,350 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2021-12-06 23:52:52,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:52,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675602006] [2021-12-06 23:52:52,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:52,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:52,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:52,353 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 23:52:52,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 23:52:52,355 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 23:52:52,386 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 23:52:52,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-12-06 23:52:52,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=728, Unknown=0, NotChecked=0, Total=812 [2021-12-06 23:52:52,386 INFO L87 Difference]: Start difference. First operand 90 states and 118 transitions. cyclomatic complexity: 33 Second operand has 29 states, 28 states have (on average 2.2142857142857144) internal successors, (62), 29 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:52,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 23:52:52,814 INFO L93 Difference]: Finished difference Result 157 states and 197 transitions. [2021-12-06 23:52:52,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-12-06 23:52:52,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157 states and 197 transitions. [2021-12-06 23:52:52,815 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2021-12-06 23:52:52,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157 states to 156 states and 196 transitions. [2021-12-06 23:52:52,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-12-06 23:52:52,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-12-06 23:52:52,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156 states and 196 transitions. [2021-12-06 23:52:52,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-06 23:52:52,816 INFO L681 BuchiCegarLoop]: Abstraction has 156 states and 196 transitions. [2021-12-06 23:52:52,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states and 196 transitions. [2021-12-06 23:52:52,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 122. [2021-12-06 23:52:52,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.3114754098360655) internal successors, (160), 121 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 23:52:52,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 160 transitions. [2021-12-06 23:52:52,818 INFO L704 BuchiCegarLoop]: Abstraction has 122 states and 160 transitions. [2021-12-06 23:52:52,818 INFO L587 BuchiCegarLoop]: Abstraction has 122 states and 160 transitions. [2021-12-06 23:52:52,818 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-12-06 23:52:52,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 160 transitions. [2021-12-06 23:52:52,819 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2021-12-06 23:52:52,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 23:52:52,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 23:52:52,819 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 23:52:52,819 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-12-06 23:52:52,819 INFO L791 eck$LassoCheckResult]: Stem: 12168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12179#L367 assume !(main_~length~0#1 < 1); 12170#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12171#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12172#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12180#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12244#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12243#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12242#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12241#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12240#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12239#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12238#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12237#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12236#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12234#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12233#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12231#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12229#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12182#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12248#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12222#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12218#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12219#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12213#L370-4 main_~j~0#1 := 0; 12214#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12209#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12205#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12206#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12201#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12202#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12198#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12197#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12195#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12196#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12282#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12276#L378-2 [2021-12-06 23:52:52,819 INFO L793 eck$LassoCheckResult]: Loop: 12276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12278#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12277#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12275#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12276#L378-2 [2021-12-06 23:52:52,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 23:52:52,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1548277590, now seen corresponding path program 27 times [2021-12-06 23:52:52,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 23:52:52,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268953688] [2021-12-06 23:52:52,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 23:52:52,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 23:52:52,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 23:52:52,996 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:52,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 23:52:52,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268953688] [2021-12-06 23:52:52,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268953688] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 23:52:52,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [503949593] [2021-12-06 23:52:52,997 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 23:52:52,997 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 23:52:52,997 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 23:52:52,998 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 23:52:52,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21432d86-6902-416d-8111-8e43c566305f/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-12-06 23:52:53,146 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2021-12-06 23:52:53,147 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 23:52:53,148 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 41 conjunts are in the unsatisfiable core [2021-12-06 23:52:53,150 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 23:52:53,188 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-12-06 23:52:53,216 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:53,216 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:52:53,226 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-12-06 23:52:53,226 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-12-06 23:52:53,293 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-12-06 23:52:53,293 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 36 treesize of output 38 [2021-12-06 23:52:53,544 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-12-06 23:52:53,544 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 10 [2021-12-06 23:52:53,546 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 23:52:53,546 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 23:53:05,772 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_371| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_371| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((v_ArrVal_1178 Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_371| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_1178) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 2) 0)))) is different from false [2021-12-06 23:53:06,641 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1178 Int) (|v_ULTIMATE.start_main_~i~0#1_371| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_371| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ (* |v_ULTIMATE.start_main_~i~0#1_371| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) v_ArrVal_1178) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 2) 0))) is different from false