./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_3-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_3-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42bdab47928922c9249a376933fe7b7a33d855d426cfe04eb271066ef5c44d0a --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 17:16:06,009 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 17:16:06,011 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 17:16:06,039 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 17:16:06,039 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 17:16:06,040 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 17:16:06,042 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 17:16:06,043 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 17:16:06,045 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 17:16:06,046 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 17:16:06,047 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 17:16:06,048 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 17:16:06,048 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 17:16:06,049 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 17:16:06,050 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 17:16:06,051 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 17:16:06,052 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 17:16:06,053 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 17:16:06,054 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 17:16:06,056 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 17:16:06,058 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 17:16:06,059 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 17:16:06,061 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 17:16:06,061 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 17:16:06,065 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 17:16:06,066 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 17:16:06,066 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 17:16:06,067 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 17:16:06,068 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 17:16:06,069 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 17:16:06,069 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 17:16:06,070 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 17:16:06,071 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 17:16:06,071 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 17:16:06,072 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 17:16:06,073 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 17:16:06,073 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 17:16:06,073 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 17:16:06,074 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 17:16:06,074 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 17:16:06,075 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 17:16:06,076 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 17:16:06,101 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 17:16:06,101 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 17:16:06,102 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 17:16:06,102 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 17:16:06,103 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 17:16:06,103 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 17:16:06,103 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 17:16:06,103 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 17:16:06,103 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 17:16:06,103 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 17:16:06,104 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 17:16:06,104 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 17:16:06,104 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 17:16:06,104 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 17:16:06,104 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 17:16:06,104 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 17:16:06,105 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 17:16:06,106 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 17:16:06,106 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 17:16:06,106 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 17:16:06,106 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 17:16:06,106 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 17:16:06,106 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 17:16:06,107 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 17:16:06,107 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 17:16:06,107 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 17:16:06,108 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42bdab47928922c9249a376933fe7b7a33d855d426cfe04eb271066ef5c44d0a [2021-12-06 17:16:06,283 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 17:16:06,298 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 17:16:06,300 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 17:16:06,301 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 17:16:06,301 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 17:16:06,302 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/loop-acceleration/array_3-2.i [2021-12-06 17:16:06,344 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/data/70a848ae9/5fd418ef80ba4619891a094df61b6af9/FLAG11c07a1cd [2021-12-06 17:16:06,727 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 17:16:06,727 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/sv-benchmarks/c/loop-acceleration/array_3-2.i [2021-12-06 17:16:06,732 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/data/70a848ae9/5fd418ef80ba4619891a094df61b6af9/FLAG11c07a1cd [2021-12-06 17:16:06,741 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/data/70a848ae9/5fd418ef80ba4619891a094df61b6af9 [2021-12-06 17:16:06,743 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 17:16:06,744 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 17:16:06,745 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:06,745 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 17:16:06,747 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 17:16:06,748 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,749 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@225929c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06, skipping insertion in model container [2021-12-06 17:16:06,749 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,756 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 17:16:06,769 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 17:16:06,884 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/sv-benchmarks/c/loop-acceleration/array_3-2.i[809,822] [2021-12-06 17:16:06,891 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:06,897 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 17:16:06,905 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/sv-benchmarks/c/loop-acceleration/array_3-2.i[809,822] [2021-12-06 17:16:06,908 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:06,917 INFO L208 MainTranslator]: Completed translation [2021-12-06 17:16:06,918 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06 WrapperNode [2021-12-06 17:16:06,918 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:06,919 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:06,919 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 17:16:06,919 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 17:16:06,924 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,928 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,941 INFO L137 Inliner]: procedures = 16, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 46 [2021-12-06 17:16:06,941 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:06,942 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 17:16:06,942 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 17:16:06,942 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 17:16:06,947 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,948 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,949 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,949 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,952 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,955 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,956 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,957 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 17:16:06,958 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 17:16:06,958 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 17:16:06,958 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 17:16:06,959 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,965 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:06,973 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:06,982 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:06,984 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 17:16:07,011 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 17:16:07,011 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 17:16:07,011 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 17:16:07,011 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 17:16:07,011 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 17:16:07,011 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 17:16:07,012 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-12-06 17:16:07,012 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 17:16:07,057 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 17:16:07,059 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 17:16:07,127 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 17:16:07,131 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 17:16:07,132 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 17:16:07,133 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:07 BoogieIcfgContainer [2021-12-06 17:16:07,133 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 17:16:07,134 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 17:16:07,134 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 17:16:07,136 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 17:16:07,137 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,137 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 05:16:06" (1/3) ... [2021-12-06 17:16:07,137 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@515c5ac6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:07, skipping insertion in model container [2021-12-06 17:16:07,138 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,138 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (2/3) ... [2021-12-06 17:16:07,138 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@515c5ac6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:07, skipping insertion in model container [2021-12-06 17:16:07,138 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,138 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:07" (3/3) ... [2021-12-06 17:16:07,139 INFO L388 chiAutomizerObserver]: Analyzing ICFG array_3-2.i [2021-12-06 17:16:07,170 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 17:16:07,171 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 17:16:07,171 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 17:16:07,171 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 17:16:07,171 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 17:16:07,171 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 17:16:07,171 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 17:16:07,171 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 17:16:07,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,194 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 17:16:07,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:07,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:07,199 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-12-06 17:16:07,199 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 17:16:07,199 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 17:16:07,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,201 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-12-06 17:16:07,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:07,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:07,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-12-06 17:16:07,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-12-06 17:16:07,206 INFO L791 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 14#L23-3true [2021-12-06 17:16:07,206 INFO L793 eck$LassoCheckResult]: Loop: 14#L23-3true assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12#L23-2true main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 14#L23-3true [2021-12-06 17:16:07,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,211 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-12-06 17:16:07,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084209428] [2021-12-06 17:16:07,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,218 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,289 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:07,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,309 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:07,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2021-12-06 17:16:07,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602082345] [2021-12-06 17:16:07,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,313 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,321 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:07,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,328 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:07,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,329 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2021-12-06 17:16:07,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737371449] [2021-12-06 17:16:07,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,347 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:07,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:07,362 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:07,580 INFO L210 LassoAnalysis]: Preferences: [2021-12-06 17:16:07,581 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-06 17:16:07,581 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-06 17:16:07,581 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-06 17:16:07,582 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-06 17:16:07,582 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:07,582 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-06 17:16:07,582 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-06 17:16:07,582 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_3-2.i_Iteration1_Lasso [2021-12-06 17:16:07,582 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-06 17:16:07,583 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-06 17:16:07,602 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,607 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,610 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,719 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,720 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,722 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-06 17:16:07,863 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-06 17:16:07,866 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-06 17:16:07,868 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:07,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:07,869 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:07,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-06 17:16:07,871 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:07,880 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:07,881 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 17:16:07,881 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:07,881 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:07,881 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:07,883 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 17:16:07,883 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 17:16:07,885 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 17:16:07,905 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-06 17:16:07,905 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:07,906 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:07,907 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:07,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-06 17:16:07,908 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:07,915 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:07,916 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:07,916 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:07,916 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:07,919 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 17:16:07,919 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 17:16:07,922 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 17:16:07,941 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2021-12-06 17:16:07,941 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:07,942 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:07,942 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:07,943 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-06 17:16:07,944 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:07,952 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:07,952 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:07,952 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:07,952 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:07,955 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 17:16:07,955 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 17:16:07,958 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 17:16:07,990 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2021-12-06 17:16:07,991 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:07,991 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:07,991 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:07,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-06 17:16:07,993 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:08,000 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:08,000 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-06 17:16:08,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:08,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:08,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:08,001 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-06 17:16:08,001 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-06 17:16:08,002 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 17:16:08,020 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2021-12-06 17:16:08,020 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:08,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:08,021 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:08,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-06 17:16:08,022 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:08,030 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:08,030 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:08,030 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:08,030 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:08,033 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 17:16:08,033 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 17:16:08,036 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-06 17:16:08,055 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2021-12-06 17:16:08,055 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:08,056 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:08,056 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:08,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-06 17:16:08,058 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-06 17:16:08,065 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-06 17:16:08,066 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-06 17:16:08,066 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-06 17:16:08,066 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-06 17:16:08,070 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-12-06 17:16:08,070 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-12-06 17:16:08,079 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-06 17:16:08,107 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2021-12-06 17:16:08,107 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2021-12-06 17:16:08,109 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:08,109 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:08,110 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:08,111 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-06 17:16:08,111 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-06 17:16:08,120 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-12-06 17:16:08,120 INFO L513 LassoAnalysis]: Proved termination. [2021-12-06 17:16:08,120 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1) = -8*ULTIMATE.start_main_~i~0#1 + 2047*v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1 Supporting invariants [] [2021-12-06 17:16:08,140 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2021-12-06 17:16:08,151 INFO L297 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2021-12-06 17:16:08,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,183 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-06 17:16:08,183 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:08,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,194 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 17:16:08,195 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:08,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,255 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-12-06 17:16:08,256 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,287 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 31 states and 43 transitions. Complement of second has 8 states. [2021-12-06 17:16:08,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-12-06 17:16:08,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 21 transitions. [2021-12-06 17:16:08,293 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 2 letters. Loop has 2 letters. [2021-12-06 17:16:08,293 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 17:16:08,293 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 4 letters. Loop has 2 letters. [2021-12-06 17:16:08,293 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 17:16:08,293 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 2 letters. Loop has 4 letters. [2021-12-06 17:16:08,294 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-06 17:16:08,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 43 transitions. [2021-12-06 17:16:08,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 10 states and 13 transitions. [2021-12-06 17:16:08,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-12-06 17:16:08,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-12-06 17:16:08,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 13 transitions. [2021-12-06 17:16:08,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,300 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-12-06 17:16:08,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 13 transitions. [2021-12-06 17:16:08,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-12-06 17:16:08,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2021-12-06 17:16:08,319 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-12-06 17:16:08,319 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-12-06 17:16:08,319 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 17:16:08,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2021-12-06 17:16:08,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-12-06 17:16:08,320 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:08,320 INFO L791 eck$LassoCheckResult]: Stem: 109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 116#L23-3 assume !(main_~i~0#1 < 1024); 115#L23-4 main_~i~0#1 := 0; 107#L26-6 [2021-12-06 17:16:08,321 INFO L793 eck$LassoCheckResult]: Loop: 107#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 108#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 113#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 114#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 107#L26-6 [2021-12-06 17:16:08,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,321 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2021-12-06 17:16:08,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96963634] [2021-12-06 17:16:08,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96963634] [2021-12-06 17:16:08,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96963634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101463698] [2021-12-06 17:16:08,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,354 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 1 times [2021-12-06 17:16:08,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187586678] [2021-12-06 17:16:08,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,355 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,360 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:08,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,366 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:08,418 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:08,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:08,422 INFO L87 Difference]: Start difference. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,438 INFO L93 Difference]: Finished difference Result 15 states and 18 transitions. [2021-12-06 17:16:08,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:08,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 18 transitions. [2021-12-06 17:16:08,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 18 transitions. [2021-12-06 17:16:08,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-12-06 17:16:08,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-12-06 17:16:08,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 18 transitions. [2021-12-06 17:16:08,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,441 INFO L681 BuchiCegarLoop]: Abstraction has 15 states and 18 transitions. [2021-12-06 17:16:08,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 18 transitions. [2021-12-06 17:16:08,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 10. [2021-12-06 17:16:08,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.2) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 12 transitions. [2021-12-06 17:16:08,443 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2021-12-06 17:16:08,443 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2021-12-06 17:16:08,443 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 17:16:08,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 12 transitions. [2021-12-06 17:16:08,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,444 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:08,444 INFO L791 eck$LassoCheckResult]: Stem: 140#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 147#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 142#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 143#L23-3 assume !(main_~i~0#1 < 1024); 146#L23-4 main_~i~0#1 := 0; 138#L26-6 [2021-12-06 17:16:08,445 INFO L793 eck$LassoCheckResult]: Loop: 138#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 139#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 144#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 145#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 138#L26-6 [2021-12-06 17:16:08,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,445 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2021-12-06 17:16:08,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487035647] [2021-12-06 17:16:08,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,474 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487035647] [2021-12-06 17:16:08,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487035647] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:08,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [105387404] [2021-12-06 17:16:08,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,475 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:08,475 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:08,476 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:08,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-12-06 17:16:08,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,502 INFO L263 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 3 conjunts are in the unsatisfiable core [2021-12-06 17:16:08,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:08,517 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,517 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 17:16:08,535 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [105387404] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 17:16:08,535 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 17:16:08,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2021-12-06 17:16:08,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366095015] [2021-12-06 17:16:08,536 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,536 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 2 times [2021-12-06 17:16:08,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041584889] [2021-12-06 17:16:08,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,543 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:08,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,549 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:08,597 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-12-06 17:16:08,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-12-06 17:16:08,598 INFO L87 Difference]: Start difference. First operand 10 states and 12 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,633 INFO L93 Difference]: Finished difference Result 32 states and 38 transitions. [2021-12-06 17:16:08,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:16:08,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 38 transitions. [2021-12-06 17:16:08,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 32 states and 38 transitions. [2021-12-06 17:16:08,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2021-12-06 17:16:08,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24 [2021-12-06 17:16:08,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2021-12-06 17:16:08,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,637 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 38 transitions. [2021-12-06 17:16:08,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2021-12-06 17:16:08,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 16. [2021-12-06 17:16:08,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.125) internal successors, (18), 15 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 18 transitions. [2021-12-06 17:16:08,638 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2021-12-06 17:16:08,639 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2021-12-06 17:16:08,639 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 17:16:08,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 18 transitions. [2021-12-06 17:16:08,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2021-12-06 17:16:08,640 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:08,640 INFO L791 eck$LassoCheckResult]: Stem: 222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 229#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 224#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 225#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 230#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 235#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 234#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 233#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 232#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 231#L23-3 assume !(main_~i~0#1 < 1024); 228#L23-4 main_~i~0#1 := 0; 220#L26-6 [2021-12-06 17:16:08,640 INFO L793 eck$LassoCheckResult]: Loop: 220#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 221#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 226#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 227#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 220#L26-6 [2021-12-06 17:16:08,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,640 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 2 times [2021-12-06 17:16:08,640 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411447110] [2021-12-06 17:16:08,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,693 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,693 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411447110] [2021-12-06 17:16:08,693 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411447110] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:08,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [961554534] [2021-12-06 17:16:08,693 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 17:16:08,693 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:08,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:08,717 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:08,718 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-12-06 17:16:08,748 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 17:16:08,749 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 17:16:08,749 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 17:16:08,750 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:08,774 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,774 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 17:16:08,832 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-12-06 17:16:08,834 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [961554534] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 17:16:08,834 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 17:16:08,834 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2021-12-06 17:16:08,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473923389] [2021-12-06 17:16:08,835 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,835 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 3 times [2021-12-06 17:16:08,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902733809] [2021-12-06 17:16:08,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,841 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:08,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:08,847 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:08,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-12-06 17:16:08,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-12-06 17:16:08,893 INFO L87 Difference]: Start difference. First operand 16 states and 18 transitions. cyclomatic complexity: 4 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,963 INFO L93 Difference]: Finished difference Result 68 states and 80 transitions. [2021-12-06 17:16:08,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-12-06 17:16:08,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 80 transitions. [2021-12-06 17:16:08,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 68 states and 80 transitions. [2021-12-06 17:16:08,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48 [2021-12-06 17:16:08,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48 [2021-12-06 17:16:08,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 80 transitions. [2021-12-06 17:16:08,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,970 INFO L681 BuchiCegarLoop]: Abstraction has 68 states and 80 transitions. [2021-12-06 17:16:08,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 80 transitions. [2021-12-06 17:16:08,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 28. [2021-12-06 17:16:08,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0714285714285714) internal successors, (30), 27 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 30 transitions. [2021-12-06 17:16:08,973 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2021-12-06 17:16:08,973 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2021-12-06 17:16:08,973 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 17:16:08,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 30 transitions. [2021-12-06 17:16:08,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:08,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,975 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2021-12-06 17:16:08,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:08,976 INFO L791 eck$LassoCheckResult]: Stem: 388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 395#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 390#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 391#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 396#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 413#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 412#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 411#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 410#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 409#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 408#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 407#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 406#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 405#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 404#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 403#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 402#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 401#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 400#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 399#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 398#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 397#L23-3 assume !(main_~i~0#1 < 1024); 394#L23-4 main_~i~0#1 := 0; 386#L26-6 [2021-12-06 17:16:08,976 INFO L793 eck$LassoCheckResult]: Loop: 386#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 387#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 392#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 393#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 386#L26-6 [2021-12-06 17:16:08,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,976 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 3 times [2021-12-06 17:16:08,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899703227] [2021-12-06 17:16:08,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,066 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,066 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899703227] [2021-12-06 17:16:09,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899703227] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:09,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [145123336] [2021-12-06 17:16:09,067 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 17:16:09,067 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:09,067 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:09,067 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:09,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-12-06 17:16:09,153 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2021-12-06 17:16:09,153 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 17:16:09,154 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 12 conjunts are in the unsatisfiable core [2021-12-06 17:16:09,156 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:09,200 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,200 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 17:16:09,331 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [145123336] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 17:16:09,331 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 17:16:09,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2021-12-06 17:16:09,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657127713] [2021-12-06 17:16:09,332 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,332 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:09,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 4 times [2021-12-06 17:16:09,333 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341489832] [2021-12-06 17:16:09,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,333 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:09,338 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:09,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:09,343 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:09,381 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:09,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-12-06 17:16:09,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-12-06 17:16:09,382 INFO L87 Difference]: Start difference. First operand 28 states and 30 transitions. cyclomatic complexity: 4 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:09,534 INFO L93 Difference]: Finished difference Result 140 states and 164 transitions. [2021-12-06 17:16:09,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-12-06 17:16:09,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 164 transitions. [2021-12-06 17:16:09,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:09,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 140 states and 164 transitions. [2021-12-06 17:16:09,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96 [2021-12-06 17:16:09,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96 [2021-12-06 17:16:09,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 164 transitions. [2021-12-06 17:16:09,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:09,542 INFO L681 BuchiCegarLoop]: Abstraction has 140 states and 164 transitions. [2021-12-06 17:16:09,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 164 transitions. [2021-12-06 17:16:09,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 52. [2021-12-06 17:16:09,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0384615384615385) internal successors, (54), 51 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 54 transitions. [2021-12-06 17:16:09,547 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2021-12-06 17:16:09,547 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2021-12-06 17:16:09,547 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 17:16:09,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 54 transitions. [2021-12-06 17:16:09,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:09,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:09,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:09,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2021-12-06 17:16:09,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:09,550 INFO L791 eck$LassoCheckResult]: Stem: 722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 729#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 724#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 725#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 730#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 771#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 770#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 769#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 768#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 767#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 766#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 765#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 764#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 763#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 762#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 761#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 760#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 759#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 758#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 757#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 756#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 755#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 754#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 753#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 752#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 751#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 750#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 749#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 748#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 747#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 746#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 745#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 744#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 743#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 742#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 741#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 740#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 739#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 738#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 737#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 736#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 735#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 734#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 733#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 732#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 731#L23-3 assume !(main_~i~0#1 < 1024); 728#L23-4 main_~i~0#1 := 0; 720#L26-6 [2021-12-06 17:16:09,550 INFO L793 eck$LassoCheckResult]: Loop: 720#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 721#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 726#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 727#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 720#L26-6 [2021-12-06 17:16:09,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,551 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 4 times [2021-12-06 17:16:09,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126399737] [2021-12-06 17:16:09,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,799 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126399737] [2021-12-06 17:16:09,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126399737] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:09,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [640105526] [2021-12-06 17:16:09,800 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 17:16:09,800 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:09,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:09,801 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:09,801 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-12-06 17:16:09,854 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 17:16:09,854 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 17:16:09,856 INFO L263 TraceCheckSpWp]: Trace formula consists of 280 conjuncts, 24 conjunts are in the unsatisfiable core [2021-12-06 17:16:09,858 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:09,938 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,939 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 17:16:10,361 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,362 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [640105526] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 17:16:10,362 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 17:16:10,362 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2021-12-06 17:16:10,362 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130524585] [2021-12-06 17:16:10,362 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,363 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:10,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 5 times [2021-12-06 17:16:10,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874363936] [2021-12-06 17:16:10,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:10,367 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:10,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:10,370 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:10,406 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:10,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-12-06 17:16:10,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-12-06 17:16:10,408 INFO L87 Difference]: Start difference. First operand 52 states and 54 transitions. cyclomatic complexity: 4 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:10,750 INFO L93 Difference]: Finished difference Result 284 states and 332 transitions. [2021-12-06 17:16:10,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-12-06 17:16:10,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 332 transitions. [2021-12-06 17:16:10,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:10,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 332 transitions. [2021-12-06 17:16:10,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192 [2021-12-06 17:16:10,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192 [2021-12-06 17:16:10,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 332 transitions. [2021-12-06 17:16:10,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:10,758 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 332 transitions. [2021-12-06 17:16:10,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 332 transitions. [2021-12-06 17:16:10,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 100. [2021-12-06 17:16:10,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.02) internal successors, (102), 99 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 102 transitions. [2021-12-06 17:16:10,765 INFO L704 BuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2021-12-06 17:16:10,765 INFO L587 BuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2021-12-06 17:16:10,765 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 17:16:10,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 102 transitions. [2021-12-06 17:16:10,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:10,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:10,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:10,768 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2021-12-06 17:16:10,768 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:10,769 INFO L791 eck$LassoCheckResult]: Stem: 1392#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 1393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 1399#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1394#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1395#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1400#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1489#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1488#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1487#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1486#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1485#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1484#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1483#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1482#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1481#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1480#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1479#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1478#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1477#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1476#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1475#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1474#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1473#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1472#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1471#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1470#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1469#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1468#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1467#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1466#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1465#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1464#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1463#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1462#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1461#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1460#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1459#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1458#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1457#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1456#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1455#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1454#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1453#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1452#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1451#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1450#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1449#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1448#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1447#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1446#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1445#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1444#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1443#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1442#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1441#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1440#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1439#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1438#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1437#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1436#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1435#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1434#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1433#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1432#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1431#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1430#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1429#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1428#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1427#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1426#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1425#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1424#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1423#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1422#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1421#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1420#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1419#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1418#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1417#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1416#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1415#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1414#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1413#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1412#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1411#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1410#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1409#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1408#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1407#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1406#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1405#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1404#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1403#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1402#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1401#L23-3 assume !(main_~i~0#1 < 1024); 1398#L23-4 main_~i~0#1 := 0; 1390#L26-6 [2021-12-06 17:16:10,769 INFO L793 eck$LassoCheckResult]: Loop: 1390#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 1391#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 1396#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 1397#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1390#L26-6 [2021-12-06 17:16:10,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,769 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 5 times [2021-12-06 17:16:10,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026749719] [2021-12-06 17:16:10,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,770 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:11,418 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:11,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:11,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026749719] [2021-12-06 17:16:11,419 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026749719] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:11,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1718962731] [2021-12-06 17:16:11,419 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 17:16:11,419 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:11,419 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:11,420 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:11,421 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-12-06 17:16:20,317 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2021-12-06 17:16:20,317 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 17:16:20,336 INFO L263 TraceCheckSpWp]: Trace formula consists of 544 conjuncts, 48 conjunts are in the unsatisfiable core [2021-12-06 17:16:20,339 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 17:16:20,460 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:20,460 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 17:16:21,887 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:21,887 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1718962731] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 17:16:21,887 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 17:16:21,887 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2021-12-06 17:16:21,887 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869786726] [2021-12-06 17:16:21,887 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 17:16:21,888 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:21,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:21,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 6 times [2021-12-06 17:16:21,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:21,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473330615] [2021-12-06 17:16:21,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:21,889 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:21,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:21,892 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:21,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:21,895 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:21,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:21,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2021-12-06 17:16:21,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2021-12-06 17:16:21,937 INFO L87 Difference]: Start difference. First operand 100 states and 102 transitions. cyclomatic complexity: 4 Second operand has 97 states, 97 states have (on average 1.9896907216494846) internal successors, (193), 97 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:23,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:23,550 INFO L93 Difference]: Finished difference Result 572 states and 668 transitions. [2021-12-06 17:16:23,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2021-12-06 17:16:23,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 572 states and 668 transitions. [2021-12-06 17:16:23,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:23,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 572 states to 572 states and 668 transitions. [2021-12-06 17:16:23,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 17:16:23,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 17:16:23,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 572 states and 668 transitions. [2021-12-06 17:16:23,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:23,564 INFO L681 BuchiCegarLoop]: Abstraction has 572 states and 668 transitions. [2021-12-06 17:16:23,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states and 668 transitions. [2021-12-06 17:16:23,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 196. [2021-12-06 17:16:23,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.010204081632653) internal successors, (198), 195 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:23,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 198 transitions. [2021-12-06 17:16:23,576 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 198 transitions. [2021-12-06 17:16:23,576 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 198 transitions. [2021-12-06 17:16:23,576 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 17:16:23,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 198 transitions. [2021-12-06 17:16:23,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-12-06 17:16:23,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:23,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:23,580 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1] [2021-12-06 17:16:23,580 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-12-06 17:16:23,581 INFO L791 eck$LassoCheckResult]: Stem: 2734#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 2735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 2741#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2736#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2737#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2742#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2927#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2926#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2925#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2924#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2923#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2922#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2921#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2920#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2919#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2918#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2917#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2916#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2915#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2914#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2913#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2912#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2911#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2910#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2909#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2908#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2907#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2906#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2905#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2904#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2903#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2902#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2901#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2900#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2899#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2898#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2897#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2896#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2895#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2894#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2893#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2892#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2891#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2890#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2889#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2888#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2887#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2886#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2885#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2884#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2883#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2882#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2881#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2880#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2879#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2878#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2877#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2876#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2875#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2874#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2873#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2872#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2871#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2870#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2869#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2868#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2867#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2866#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2865#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2864#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2863#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2862#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2861#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2860#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2859#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2858#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2857#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2856#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2855#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2854#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2853#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2852#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2851#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2850#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2849#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2848#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2847#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2846#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2845#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2844#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2843#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2842#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2841#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2840#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2839#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2838#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2837#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2836#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2835#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2834#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2833#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2832#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2831#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2830#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2829#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2828#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2827#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2826#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2825#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2824#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2823#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2822#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2821#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2820#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2819#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2818#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2817#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2816#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2815#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2814#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2813#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2812#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2811#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2810#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2809#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2808#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2807#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2806#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2805#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2804#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2803#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2802#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2801#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2800#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2799#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2798#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2797#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2796#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2795#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2794#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2793#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2792#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2791#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2790#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2789#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2788#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2787#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2786#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2785#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2784#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2783#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2782#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2781#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2780#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2779#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2778#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2777#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2776#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2775#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2774#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2773#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2772#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2771#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2770#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2769#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2768#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2767#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2766#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2765#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2764#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2763#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2762#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2761#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2760#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2759#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2758#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2757#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2756#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2755#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2754#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2753#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2752#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2751#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2750#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2749#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2748#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2747#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2746#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2745#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2744#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2743#L23-3 assume !(main_~i~0#1 < 1024); 2740#L23-4 main_~i~0#1 := 0; 2732#L26-6 [2021-12-06 17:16:23,581 INFO L793 eck$LassoCheckResult]: Loop: 2732#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 2733#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 2738#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 2739#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2732#L26-6 [2021-12-06 17:16:23,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:23,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1165371207, now seen corresponding path program 6 times [2021-12-06 17:16:23,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:23,582 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480931142] [2021-12-06 17:16:23,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:23,582 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:23,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:25,609 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:25,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:25,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480931142] [2021-12-06 17:16:25,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480931142] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 17:16:25,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [918057450] [2021-12-06 17:16:25,609 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 17:16:25,610 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 17:16:25,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:25,610 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 17:16:25,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3768b678-9de9-41e9-83d9-0e4b2f10fc18/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process