./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/bitvector/byte_add_1-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/bitvector/byte_add_1-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0ba3e3db8f44a5e9ad151b8422bee8deebac1dcf47a42cba5485daeafd8d8e80 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 19:07:20,330 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 19:07:20,332 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 19:07:20,362 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 19:07:20,363 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 19:07:20,364 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 19:07:20,365 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 19:07:20,368 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 19:07:20,370 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 19:07:20,371 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 19:07:20,372 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 19:07:20,373 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 19:07:20,374 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 19:07:20,375 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 19:07:20,376 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 19:07:20,378 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 19:07:20,378 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 19:07:20,380 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 19:07:20,382 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 19:07:20,384 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 19:07:20,386 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 19:07:20,387 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 19:07:20,389 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 19:07:20,390 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 19:07:20,393 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 19:07:20,393 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 19:07:20,394 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 19:07:20,395 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 19:07:20,395 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 19:07:20,397 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 19:07:20,397 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 19:07:20,398 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 19:07:20,398 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 19:07:20,399 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 19:07:20,400 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 19:07:20,400 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 19:07:20,400 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 19:07:20,401 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 19:07:20,401 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 19:07:20,401 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 19:07:20,402 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 19:07:20,402 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 19:07:20,426 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 19:07:20,426 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 19:07:20,427 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 19:07:20,427 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 19:07:20,428 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 19:07:20,428 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 19:07:20,428 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 19:07:20,429 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 19:07:20,429 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 19:07:20,429 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 19:07:20,429 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 19:07:20,429 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 19:07:20,429 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 19:07:20,430 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 19:07:20,431 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 19:07:20,431 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 19:07:20,431 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 19:07:20,431 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 19:07:20,431 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 19:07:20,432 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 19:07:20,433 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0ba3e3db8f44a5e9ad151b8422bee8deebac1dcf47a42cba5485daeafd8d8e80 [2021-12-06 19:07:20,618 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 19:07:20,633 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 19:07:20,635 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 19:07:20,635 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 19:07:20,636 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 19:07:20,637 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/bitvector/byte_add_1-1.i [2021-12-06 19:07:20,683 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/data/a82200f44/844071aed9204539b267548066ccda5c/FLAGcf0766513 [2021-12-06 19:07:21,046 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 19:07:21,046 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/sv-benchmarks/c/bitvector/byte_add_1-1.i [2021-12-06 19:07:21,052 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/data/a82200f44/844071aed9204539b267548066ccda5c/FLAGcf0766513 [2021-12-06 19:07:21,062 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/data/a82200f44/844071aed9204539b267548066ccda5c [2021-12-06 19:07:21,065 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 19:07:21,066 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 19:07:21,067 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 19:07:21,067 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 19:07:21,070 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 19:07:21,070 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,071 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7745c27d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21, skipping insertion in model container [2021-12-06 19:07:21,071 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,076 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 19:07:21,092 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 19:07:21,206 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/sv-benchmarks/c/bitvector/byte_add_1-1.i[1168,1181] [2021-12-06 19:07:21,234 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:07:21,240 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 19:07:21,248 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/sv-benchmarks/c/bitvector/byte_add_1-1.i[1168,1181] [2021-12-06 19:07:21,262 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:07:21,272 INFO L208 MainTranslator]: Completed translation [2021-12-06 19:07:21,272 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21 WrapperNode [2021-12-06 19:07:21,272 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 19:07:21,273 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 19:07:21,273 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 19:07:21,273 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 19:07:21,279 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,285 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,302 INFO L137 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 123 [2021-12-06 19:07:21,302 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 19:07:21,303 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 19:07:21,303 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 19:07:21,303 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 19:07:21,309 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,310 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,312 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,312 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,317 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,322 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,324 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,326 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 19:07:21,327 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 19:07:21,327 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 19:07:21,328 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 19:07:21,329 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (1/1) ... [2021-12-06 19:07:21,336 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 19:07:21,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:21,355 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 19:07:21,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 19:07:21,384 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 19:07:21,384 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 19:07:21,385 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 19:07:21,385 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 19:07:21,433 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 19:07:21,434 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 19:07:21,566 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 19:07:21,571 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 19:07:21,571 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 19:07:21,573 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:07:21 BoogieIcfgContainer [2021-12-06 19:07:21,573 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 19:07:21,574 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 19:07:21,574 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 19:07:21,576 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 19:07:21,577 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:07:21,577 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 07:07:21" (1/3) ... [2021-12-06 19:07:21,578 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1bb88c0f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 07:07:21, skipping insertion in model container [2021-12-06 19:07:21,578 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:07:21,578 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:21" (2/3) ... [2021-12-06 19:07:21,578 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1bb88c0f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 07:07:21, skipping insertion in model container [2021-12-06 19:07:21,578 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:07:21,578 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:07:21" (3/3) ... [2021-12-06 19:07:21,579 INFO L388 chiAutomizerObserver]: Analyzing ICFG byte_add_1-1.i [2021-12-06 19:07:21,611 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 19:07:21,611 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 19:07:21,611 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 19:07:21,612 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 19:07:21,612 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 19:07:21,612 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 19:07:21,612 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 19:07:21,612 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 19:07:21,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 41 states, 40 states have (on average 1.75) internal successors, (70), 40 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:21,642 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 23 [2021-12-06 19:07:21,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:21,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:21,648 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-12-06 19:07:21,648 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:21,648 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 19:07:21,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 41 states, 40 states have (on average 1.75) internal successors, (70), 40 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:21,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 23 [2021-12-06 19:07:21,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:21,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:21,656 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-12-06 19:07:21,656 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:21,663 INFO L791 eck$LassoCheckResult]: Stem: 21#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 13#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 5#L59true assume !(0 == mp_add_~a3~0#1 % 256); 16#L59-1true mp_add_~nb~0#1 := 4; 18#L69true assume !(0 == mp_add_~b3~0#1 % 256); 36#L69-1true mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 23#L80-2true [2021-12-06 19:07:21,663 INFO L793 eck$LassoCheckResult]: Loop: 23#L80-2true assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 33#L83true assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 42#L83-1true assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 8#L89true assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 40#L95-1true assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 17#L99-1true assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 12#L100-1true assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 28#L101-1true assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 31#L102-1true mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 23#L80-2true [2021-12-06 19:07:21,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:21,668 INFO L85 PathProgramCache]: Analyzing trace with hash 889938151, now seen corresponding path program 1 times [2021-12-06 19:07:21,675 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:21,675 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339189503] [2021-12-06 19:07:21,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:21,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:21,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:21,761 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:21,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:21,797 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:21,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:21,799 INFO L85 PathProgramCache]: Analyzing trace with hash 318197182, now seen corresponding path program 1 times [2021-12-06 19:07:21,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:21,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75959330] [2021-12-06 19:07:21,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:21,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:21,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:21,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:21,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:21,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75959330] [2021-12-06 19:07:21,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75959330] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:21,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:21,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:21,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143741922] [2021-12-06 19:07:21,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:21,861 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:21,861 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:21,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:21,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:21,887 INFO L87 Difference]: Start difference. First operand has 41 states, 40 states have (on average 1.75) internal successors, (70), 40 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:21,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:22,000 INFO L93 Difference]: Finished difference Result 64 states and 94 transitions. [2021-12-06 19:07:22,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:22,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 94 transitions. [2021-12-06 19:07:22,011 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41 [2021-12-06 19:07:22,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 56 states and 86 transitions. [2021-12-06 19:07:22,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2021-12-06 19:07:22,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2021-12-06 19:07:22,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 86 transitions. [2021-12-06 19:07:22,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:22,018 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 86 transitions. [2021-12-06 19:07:22,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 86 transitions. [2021-12-06 19:07:22,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 54. [2021-12-06 19:07:22,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.5555555555555556) internal successors, (84), 53 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 84 transitions. [2021-12-06 19:07:22,043 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 84 transitions. [2021-12-06 19:07:22,043 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 84 transitions. [2021-12-06 19:07:22,043 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 19:07:22,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 84 transitions. [2021-12-06 19:07:22,046 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 39 [2021-12-06 19:07:22,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:22,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:22,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,047 INFO L791 eck$LassoCheckResult]: Stem: 136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 114#L59 assume !(0 == mp_add_~a3~0#1 % 256); 115#L59-1 mp_add_~nb~0#1 := 4; 132#L69 assume !(0 == mp_add_~b3~0#1 % 256); 123#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 138#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 139#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 129#L83-1 [2021-12-06 19:07:22,048 INFO L793 eck$LassoCheckResult]: Loop: 129#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 118#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 119#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 133#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 125#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 126#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 144#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 147#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 159#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 160#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 135#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 141#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 128#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 129#L83-1 [2021-12-06 19:07:22,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,049 INFO L85 PathProgramCache]: Analyzing trace with hash 532072804, now seen corresponding path program 1 times [2021-12-06 19:07:22,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778660343] [2021-12-06 19:07:22,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778660343] [2021-12-06 19:07:22,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778660343] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,187 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:22,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699061256] [2021-12-06 19:07:22,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,188 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:22,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1939143242, now seen corresponding path program 1 times [2021-12-06 19:07:22,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388288075] [2021-12-06 19:07:22,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,189 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388288075] [2021-12-06 19:07:22,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388288075] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,241 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:22,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615725567] [2021-12-06 19:07:22,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,241 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:22,242 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:22,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:07:22,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:07:22,243 INFO L87 Difference]: Start difference. First operand 54 states and 84 transitions. cyclomatic complexity: 32 Second operand has 5 states, 4 states have (on average 2.0) internal successors, (8), 5 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:22,457 INFO L93 Difference]: Finished difference Result 149 states and 228 transitions. [2021-12-06 19:07:22,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:07:22,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 228 transitions. [2021-12-06 19:07:22,462 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108 [2021-12-06 19:07:22,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 149 states and 228 transitions. [2021-12-06 19:07:22,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2021-12-06 19:07:22,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2021-12-06 19:07:22,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 149 states and 228 transitions. [2021-12-06 19:07:22,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:22,467 INFO L681 BuchiCegarLoop]: Abstraction has 149 states and 228 transitions. [2021-12-06 19:07:22,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states and 228 transitions. [2021-12-06 19:07:22,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 78. [2021-12-06 19:07:22,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.4487179487179487) internal successors, (113), 77 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 113 transitions. [2021-12-06 19:07:22,475 INFO L704 BuchiCegarLoop]: Abstraction has 78 states and 113 transitions. [2021-12-06 19:07:22,475 INFO L587 BuchiCegarLoop]: Abstraction has 78 states and 113 transitions. [2021-12-06 19:07:22,475 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 19:07:22,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 113 transitions. [2021-12-06 19:07:22,477 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 39 [2021-12-06 19:07:22,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:22,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:22,478 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,478 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,478 INFO L791 eck$LassoCheckResult]: Stem: 354#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 333#L59 assume 0 == mp_add_~a3~0#1 % 256;mp_add_~na~0#1 := mp_add_~na~0#1 % 256 - 1; 335#L61 assume !(0 == mp_add_~a2~0#1 % 256); 336#L59-1 mp_add_~nb~0#1 := 4; 350#L69 assume !(0 == mp_add_~b3~0#1 % 256); 341#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 380#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 381#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 402#L83-1 [2021-12-06 19:07:22,479 INFO L793 eck$LassoCheckResult]: Loop: 402#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 404#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 372#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 373#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 403#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 362#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 363#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 364#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 378#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 368#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 352#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 357#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 358#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 402#L83-1 [2021-12-06 19:07:22,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,479 INFO L85 PathProgramCache]: Analyzing trace with hash -384676570, now seen corresponding path program 1 times [2021-12-06 19:07:22,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221994868] [2021-12-06 19:07:22,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,480 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221994868] [2021-12-06 19:07:22,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221994868] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,528 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,528 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:22,528 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347509203] [2021-12-06 19:07:22,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,529 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:22,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1939143242, now seen corresponding path program 2 times [2021-12-06 19:07:22,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456677316] [2021-12-06 19:07:22,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456677316] [2021-12-06 19:07:22,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456677316] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:22,578 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114832160] [2021-12-06 19:07:22,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,578 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:22,578 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:22,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:22,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:22,579 INFO L87 Difference]: Start difference. First operand 78 states and 113 transitions. cyclomatic complexity: 37 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:22,584 INFO L93 Difference]: Finished difference Result 66 states and 93 transitions. [2021-12-06 19:07:22,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:22,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 93 transitions. [2021-12-06 19:07:22,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 39 [2021-12-06 19:07:22,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 66 states and 93 transitions. [2021-12-06 19:07:22,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2021-12-06 19:07:22,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2021-12-06 19:07:22,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 93 transitions. [2021-12-06 19:07:22,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:22,588 INFO L681 BuchiCegarLoop]: Abstraction has 66 states and 93 transitions. [2021-12-06 19:07:22,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 93 transitions. [2021-12-06 19:07:22,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2021-12-06 19:07:22,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.4090909090909092) internal successors, (93), 65 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 93 transitions. [2021-12-06 19:07:22,592 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 93 transitions. [2021-12-06 19:07:22,592 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 93 transitions. [2021-12-06 19:07:22,592 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 19:07:22,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 93 transitions. [2021-12-06 19:07:22,593 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 39 [2021-12-06 19:07:22,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:22,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:22,593 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,593 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,593 INFO L791 eck$LassoCheckResult]: Stem: 502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 481#L59 assume !(0 == mp_add_~a3~0#1 % 256); 482#L59-1 mp_add_~nb~0#1 := 4; 497#L69 assume !(0 == mp_add_~b3~0#1 % 256); 488#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 514#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 543#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 542#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 541#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 539#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 537#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 535#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 532#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 484#L95-1 [2021-12-06 19:07:22,594 INFO L793 eck$LassoCheckResult]: Loop: 484#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 525#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 523#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 522#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 520#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 517#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 518#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 530#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 531#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 511#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 485#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 486#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 483#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 484#L95-1 [2021-12-06 19:07:22,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1874592092, now seen corresponding path program 1 times [2021-12-06 19:07:22,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477161284] [2021-12-06 19:07:22,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,676 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477161284] [2021-12-06 19:07:22,676 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [477161284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,676 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,676 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:22,677 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018786912] [2021-12-06 19:07:22,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,677 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:22,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1213684438, now seen corresponding path program 1 times [2021-12-06 19:07:22,678 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774780315] [2021-12-06 19:07:22,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,678 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774780315] [2021-12-06 19:07:22,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774780315] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:22,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964706565] [2021-12-06 19:07:22,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,713 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:22,714 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:22,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:22,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:07:22,714 INFO L87 Difference]: Start difference. First operand 66 states and 93 transitions. cyclomatic complexity: 29 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:22,798 INFO L93 Difference]: Finished difference Result 91 states and 134 transitions. [2021-12-06 19:07:22,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:07:22,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 134 transitions. [2021-12-06 19:07:22,800 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 64 [2021-12-06 19:07:22,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 91 states and 134 transitions. [2021-12-06 19:07:22,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2021-12-06 19:07:22,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2021-12-06 19:07:22,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 134 transitions. [2021-12-06 19:07:22,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:22,802 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 134 transitions. [2021-12-06 19:07:22,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 134 transitions. [2021-12-06 19:07:22,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 83. [2021-12-06 19:07:22,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.4457831325301205) internal successors, (120), 82 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 120 transitions. [2021-12-06 19:07:22,808 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 120 transitions. [2021-12-06 19:07:22,808 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 120 transitions. [2021-12-06 19:07:22,808 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 19:07:22,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 120 transitions. [2021-12-06 19:07:22,809 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56 [2021-12-06 19:07:22,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:22,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:22,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:22,810 INFO L791 eck$LassoCheckResult]: Stem: 667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 650#L59 assume !(0 == mp_add_~a3~0#1 % 256); 651#L59-1 mp_add_~nb~0#1 := 4; 663#L69 assume !(0 == mp_add_~b3~0#1 % 256); 656#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 684#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 712#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 711#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 710#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 708#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 705#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 701#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 698#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 649#L95-1 [2021-12-06 19:07:22,810 INFO L793 eck$LassoCheckResult]: Loop: 649#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 709#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 706#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 703#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 699#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 689#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 690#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 724#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 725#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 687#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 664#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 653#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 654#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 676#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 691#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 696#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 720#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 685#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 671#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 659#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 660#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 648#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 649#L95-1 [2021-12-06 19:07:22,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1874592092, now seen corresponding path program 2 times [2021-12-06 19:07:22,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066265699] [2021-12-06 19:07:22,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,811 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:22,879 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066265699] [2021-12-06 19:07:22,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066265699] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,880 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,880 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:22,880 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506707866] [2021-12-06 19:07:22,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,880 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:22,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:22,881 INFO L85 PathProgramCache]: Analyzing trace with hash 857385497, now seen corresponding path program 1 times [2021-12-06 19:07:22,881 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:22,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156313477] [2021-12-06 19:07:22,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:22,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:22,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:22,895 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:22,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:22,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156313477] [2021-12-06 19:07:22,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156313477] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:22,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:22,896 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:22,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584750827] [2021-12-06 19:07:22,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:22,896 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:22,896 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:22,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:22,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:07:22,897 INFO L87 Difference]: Start difference. First operand 83 states and 120 transitions. cyclomatic complexity: 39 Second operand has 4 states, 4 states have (on average 3.5) internal successors, (14), 4 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:22,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:22,990 INFO L93 Difference]: Finished difference Result 164 states and 234 transitions. [2021-12-06 19:07:22,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:07:22,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 164 states and 234 transitions. [2021-12-06 19:07:22,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 112 [2021-12-06 19:07:22,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 164 states to 164 states and 234 transitions. [2021-12-06 19:07:22,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 164 [2021-12-06 19:07:22,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 164 [2021-12-06 19:07:22,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 164 states and 234 transitions. [2021-12-06 19:07:22,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:22,997 INFO L681 BuchiCegarLoop]: Abstraction has 164 states and 234 transitions. [2021-12-06 19:07:22,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states and 234 transitions. [2021-12-06 19:07:23,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 91. [2021-12-06 19:07:23,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.4065934065934067) internal successors, (128), 90 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 128 transitions. [2021-12-06 19:07:23,003 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 128 transitions. [2021-12-06 19:07:23,003 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 128 transitions. [2021-12-06 19:07:23,003 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 19:07:23,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 128 transitions. [2021-12-06 19:07:23,004 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56 [2021-12-06 19:07:23,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,005 INFO L791 eck$LassoCheckResult]: Stem: 928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 910#L59 assume !(0 == mp_add_~a3~0#1 % 256); 911#L59-1 mp_add_~nb~0#1 := 4; 922#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 914#L71 assume !(0 == mp_add_~b2~0#1 % 256); 915#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 969#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 968#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 967#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 966#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 965#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 964#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 962#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 960#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 909#L95-1 [2021-12-06 19:07:23,006 INFO L793 eck$LassoCheckResult]: Loop: 909#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 923#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 912#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 913#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 935#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 944#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 945#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 919#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 905#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 958#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 956#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 954#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 952#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 951#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 949#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 950#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 981#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 982#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 938#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 906#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 907#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 908#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 909#L95-1 [2021-12-06 19:07:23,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,006 INFO L85 PathProgramCache]: Analyzing trace with hash -2095675795, now seen corresponding path program 1 times [2021-12-06 19:07:23,006 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856400680] [2021-12-06 19:07:23,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:23,079 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856400680] [2021-12-06 19:07:23,079 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856400680] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,079 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,079 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:07:23,080 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018064988] [2021-12-06 19:07:23,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,080 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:23,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1043280079, now seen corresponding path program 1 times [2021-12-06 19:07:23,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229590993] [2021-12-06 19:07:23,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,098 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:23,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229590993] [2021-12-06 19:07:23,099 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229590993] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:23,099 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929369371] [2021-12-06 19:07:23,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,100 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:23,100 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:23,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:07:23,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:07:23,101 INFO L87 Difference]: Start difference. First operand 91 states and 128 transitions. cyclomatic complexity: 39 Second operand has 5 states, 5 states have (on average 3.0) internal successors, (15), 5 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:23,310 INFO L93 Difference]: Finished difference Result 245 states and 348 transitions. [2021-12-06 19:07:23,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:07:23,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 348 transitions. [2021-12-06 19:07:23,314 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 168 [2021-12-06 19:07:23,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 245 states and 348 transitions. [2021-12-06 19:07:23,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2021-12-06 19:07:23,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2021-12-06 19:07:23,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245 states and 348 transitions. [2021-12-06 19:07:23,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:23,317 INFO L681 BuchiCegarLoop]: Abstraction has 245 states and 348 transitions. [2021-12-06 19:07:23,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states and 348 transitions. [2021-12-06 19:07:23,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 91. [2021-12-06 19:07:23,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.4065934065934067) internal successors, (128), 90 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 128 transitions. [2021-12-06 19:07:23,323 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 128 transitions. [2021-12-06 19:07:23,323 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 128 transitions. [2021-12-06 19:07:23,323 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 19:07:23,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 128 transitions. [2021-12-06 19:07:23,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56 [2021-12-06 19:07:23,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,325 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,325 INFO L791 eck$LassoCheckResult]: Stem: 1274#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 1264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 1257#L59 assume !(0 == mp_add_~a3~0#1 % 256); 1258#L59-1 mp_add_~nb~0#1 := 4; 1269#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 1261#L71 assume 0 == mp_add_~b2~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 1263#L73 assume 0 == mp_add_~b1~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 1289#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 1316#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1315#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 1314#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 1313#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 1312#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 1311#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 1309#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 1307#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1256#L95-1 [2021-12-06 19:07:23,325 INFO L793 eck$LassoCheckResult]: Loop: 1256#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 1270#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 1259#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 1260#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 1298#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1291#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1292#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 1266#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 1337#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1305#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 1303#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 1301#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 1300#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 1299#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1296#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1297#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 1328#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 1329#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 1284#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 1253#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 1254#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 1255#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1256#L95-1 [2021-12-06 19:07:23,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1829134745, now seen corresponding path program 1 times [2021-12-06 19:07:23,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849468939] [2021-12-06 19:07:23,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:23,363 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849468939] [2021-12-06 19:07:23,363 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849468939] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,363 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,363 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:23,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780342642] [2021-12-06 19:07:23,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,364 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:23,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1043280079, now seen corresponding path program 2 times [2021-12-06 19:07:23,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594864120] [2021-12-06 19:07:23,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,364 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,376 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:23,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594864120] [2021-12-06 19:07:23,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594864120] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:23,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648850877] [2021-12-06 19:07:23,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,377 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:23,378 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:23,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:07:23,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:07:23,378 INFO L87 Difference]: Start difference. First operand 91 states and 128 transitions. cyclomatic complexity: 39 Second operand has 5 states, 4 states have (on average 4.0) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:23,441 INFO L93 Difference]: Finished difference Result 219 states and 318 transitions. [2021-12-06 19:07:23,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 19:07:23,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 318 transitions. [2021-12-06 19:07:23,443 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 177 [2021-12-06 19:07:23,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 219 states and 318 transitions. [2021-12-06 19:07:23,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219 [2021-12-06 19:07:23,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2021-12-06 19:07:23,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219 states and 318 transitions. [2021-12-06 19:07:23,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:23,446 INFO L681 BuchiCegarLoop]: Abstraction has 219 states and 318 transitions. [2021-12-06 19:07:23,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states and 318 transitions. [2021-12-06 19:07:23,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 149. [2021-12-06 19:07:23,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.5033557046979866) internal successors, (224), 148 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 224 transitions. [2021-12-06 19:07:23,450 INFO L704 BuchiCegarLoop]: Abstraction has 149 states and 224 transitions. [2021-12-06 19:07:23,450 INFO L587 BuchiCegarLoop]: Abstraction has 149 states and 224 transitions. [2021-12-06 19:07:23,450 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 19:07:23,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 224 transitions. [2021-12-06 19:07:23,451 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 113 [2021-12-06 19:07:23,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,452 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,452 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,452 INFO L791 eck$LassoCheckResult]: Stem: 1599#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 1589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 1578#L59 assume !(0 == mp_add_~a3~0#1 % 256); 1579#L59-1 mp_add_~nb~0#1 := 4; 1594#L69 assume !(0 == mp_add_~b3~0#1 % 256); 1587#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 1722#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1723#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 1596#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 1597#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 1602#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 1603#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 1697#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 1691#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 1685#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 1682#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 1678#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 1641#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1642#L95-1 [2021-12-06 19:07:23,452 INFO L793 eck$LassoCheckResult]: Loop: 1642#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 1680#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 1715#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 1706#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 1703#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1700#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1695#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 1690#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 1684#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1681#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 1677#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 1676#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 1675#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 1673#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1670#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1667#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 1668#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 1687#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 1654#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 1650#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 1645#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 1643#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1642#L95-1 [2021-12-06 19:07:23,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,452 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 1 times [2021-12-06 19:07:23,452 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989062960] [2021-12-06 19:07:23,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,467 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:23,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:23,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,486 INFO L85 PathProgramCache]: Analyzing trace with hash -1043280079, now seen corresponding path program 3 times [2021-12-06 19:07:23,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148227652] [2021-12-06 19:07:23,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,499 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:23,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148227652] [2021-12-06 19:07:23,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148227652] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,499 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:23,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557171877] [2021-12-06 19:07:23,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,499 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:23,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:23,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:23,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:23,500 INFO L87 Difference]: Start difference. First operand 149 states and 224 transitions. cyclomatic complexity: 77 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:23,551 INFO L93 Difference]: Finished difference Result 194 states and 283 transitions. [2021-12-06 19:07:23,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:23,552 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 283 transitions. [2021-12-06 19:07:23,553 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 158 [2021-12-06 19:07:23,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 194 states and 283 transitions. [2021-12-06 19:07:23,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 194 [2021-12-06 19:07:23,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194 [2021-12-06 19:07:23,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 194 states and 283 transitions. [2021-12-06 19:07:23,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:23,555 INFO L681 BuchiCegarLoop]: Abstraction has 194 states and 283 transitions. [2021-12-06 19:07:23,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states and 283 transitions. [2021-12-06 19:07:23,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 191. [2021-12-06 19:07:23,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4659685863874345) internal successors, (280), 190 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 280 transitions. [2021-12-06 19:07:23,559 INFO L704 BuchiCegarLoop]: Abstraction has 191 states and 280 transitions. [2021-12-06 19:07:23,559 INFO L587 BuchiCegarLoop]: Abstraction has 191 states and 280 transitions. [2021-12-06 19:07:23,559 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 19:07:23,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 280 transitions. [2021-12-06 19:07:23,560 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 155 [2021-12-06 19:07:23,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,561 INFO L791 eck$LassoCheckResult]: Stem: 1948#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 1938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 1925#L59 assume !(0 == mp_add_~a3~0#1 % 256); 1926#L59-1 mp_add_~nb~0#1 := 4; 1943#L69 assume !(0 == mp_add_~b3~0#1 % 256); 1934#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 1967#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 2009#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 2008#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 2007#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 2005#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 2003#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 2001#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 1995#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 1998#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 1996#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 1992#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 1993#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 2012#L95-1 [2021-12-06 19:07:23,562 INFO L793 eck$LassoCheckResult]: Loop: 2012#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 2011#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 2010#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 1991#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 1985#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1976#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1964#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 1965#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 2069#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 1972#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 1973#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 2016#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 1957#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 1958#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 1978#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 1979#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 2049#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 2050#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 2115#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 2114#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 2073#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 2072#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 2012#L95-1 [2021-12-06 19:07:23,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,562 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 2 times [2021-12-06 19:07:23,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321128310] [2021-12-06 19:07:23,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,575 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:23,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,590 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:23,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1165423065, now seen corresponding path program 1 times [2021-12-06 19:07:23,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763624298] [2021-12-06 19:07:23,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,649 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:23,649 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763624298] [2021-12-06 19:07:23,649 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763624298] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,649 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,650 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:07:23,650 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733870480] [2021-12-06 19:07:23,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:23,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:23,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:07:23,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:07:23,651 INFO L87 Difference]: Start difference. First operand 191 states and 280 transitions. cyclomatic complexity: 91 Second operand has 5 states, 5 states have (on average 4.4) internal successors, (22), 5 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:23,816 INFO L93 Difference]: Finished difference Result 367 states and 532 transitions. [2021-12-06 19:07:23,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:07:23,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 367 states and 532 transitions. [2021-12-06 19:07:23,819 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 311 [2021-12-06 19:07:23,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 367 states to 367 states and 532 transitions. [2021-12-06 19:07:23,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 367 [2021-12-06 19:07:23,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 367 [2021-12-06 19:07:23,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 367 states and 532 transitions. [2021-12-06 19:07:23,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:23,823 INFO L681 BuchiCegarLoop]: Abstraction has 367 states and 532 transitions. [2021-12-06 19:07:23,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states and 532 transitions. [2021-12-06 19:07:23,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 288. [2021-12-06 19:07:23,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4548611111111112) internal successors, (419), 287 states have internal predecessors, (419), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 419 transitions. [2021-12-06 19:07:23,829 INFO L704 BuchiCegarLoop]: Abstraction has 288 states and 419 transitions. [2021-12-06 19:07:23,829 INFO L587 BuchiCegarLoop]: Abstraction has 288 states and 419 transitions. [2021-12-06 19:07:23,829 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 19:07:23,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 419 transitions. [2021-12-06 19:07:23,830 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 249 [2021-12-06 19:07:23,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,831 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,831 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,832 INFO L791 eck$LassoCheckResult]: Stem: 2516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 2507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 2494#L59 assume !(0 == mp_add_~a3~0#1 % 256); 2495#L59-1 mp_add_~nb~0#1 := 4; 2512#L69 assume !(0 == mp_add_~b3~0#1 % 256); 2503#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 2532#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 2582#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 2581#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 2580#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 2578#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 2576#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 2574#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 2568#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 2571#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 2569#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 2565#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 2566#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 2595#L95-1 [2021-12-06 19:07:23,832 INFO L793 eck$LassoCheckResult]: Loop: 2595#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 2596#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 2591#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 2592#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 2587#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 2588#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 2583#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 2584#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 2722#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 2721#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 2719#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 2713#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 2710#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 2545#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 2542#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 2543#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 2662#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 2533#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 2520#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 2521#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 2715#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 2714#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 2595#L95-1 [2021-12-06 19:07:23,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,832 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 3 times [2021-12-06 19:07:23,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655060731] [2021-12-06 19:07:23,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,846 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:23,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,861 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:23,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1115550935, now seen corresponding path program 1 times [2021-12-06 19:07:23,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867750023] [2021-12-06 19:07:23,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:23,874 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 19:07:23,874 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:23,874 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867750023] [2021-12-06 19:07:23,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867750023] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:23,874 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:23,874 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:23,874 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113597887] [2021-12-06 19:07:23,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:23,875 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:23,875 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:23,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:23,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:23,875 INFO L87 Difference]: Start difference. First operand 288 states and 419 transitions. cyclomatic complexity: 134 Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:23,931 INFO L93 Difference]: Finished difference Result 340 states and 495 transitions. [2021-12-06 19:07:23,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:23,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 340 states and 495 transitions. [2021-12-06 19:07:23,934 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 301 [2021-12-06 19:07:23,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 340 states to 340 states and 495 transitions. [2021-12-06 19:07:23,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 340 [2021-12-06 19:07:23,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 340 [2021-12-06 19:07:23,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 495 transitions. [2021-12-06 19:07:23,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:23,939 INFO L681 BuchiCegarLoop]: Abstraction has 340 states and 495 transitions. [2021-12-06 19:07:23,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 495 transitions. [2021-12-06 19:07:23,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 334. [2021-12-06 19:07:23,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 334 states, 334 states have (on average 1.464071856287425) internal successors, (489), 333 states have internal predecessors, (489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:23,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 489 transitions. [2021-12-06 19:07:23,947 INFO L704 BuchiCegarLoop]: Abstraction has 334 states and 489 transitions. [2021-12-06 19:07:23,947 INFO L587 BuchiCegarLoop]: Abstraction has 334 states and 489 transitions. [2021-12-06 19:07:23,948 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 19:07:23,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 334 states and 489 transitions. [2021-12-06 19:07:23,950 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 295 [2021-12-06 19:07:23,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:23,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:23,951 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,951 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:23,951 INFO L791 eck$LassoCheckResult]: Stem: 3152#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 3141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 3134#L59 assume !(0 == mp_add_~a3~0#1 % 256); 3135#L59-1 mp_add_~nb~0#1 := 4; 3146#L69 assume !(0 == mp_add_~b3~0#1 % 256); 3139#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 3173#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 3212#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 3211#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 3210#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 3208#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 3206#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 3204#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 3198#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 3201#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 3199#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 3195#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 3196#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 3331#L95-1 [2021-12-06 19:07:23,951 INFO L793 eck$LassoCheckResult]: Loop: 3331#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 3238#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 3239#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 3235#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 3231#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 3232#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 3285#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 3286#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 3402#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 3387#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 3233#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 3234#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 3223#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 3224#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 3179#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 3180#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 3308#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 3309#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 3382#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 3380#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 3378#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 3376#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 3331#L95-1 [2021-12-06 19:07:23,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,952 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 4 times [2021-12-06 19:07:23,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102267018] [2021-12-06 19:07:23,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,952 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,967 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:23,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:23,985 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:23,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:23,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1816615513, now seen corresponding path program 1 times [2021-12-06 19:07:23,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:23,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717222549] [2021-12-06 19:07:23,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:23,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:23,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:24,064 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 8 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:24,064 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:24,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717222549] [2021-12-06 19:07:24,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717222549] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:24,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [518004783] [2021-12-06 19:07:24,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,065 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:24,065 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:24,072 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:24,073 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-12-06 19:07:24,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:24,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 5 conjunts are in the unsatisfiable core [2021-12-06 19:07:24,105 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:24,265 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:24,265 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:24,314 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:24,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [518004783] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:24,314 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:24,314 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 7 [2021-12-06 19:07:24,315 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849297842] [2021-12-06 19:07:24,315 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:24,315 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:24,315 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:24,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-12-06 19:07:24,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=32, Unknown=0, NotChecked=0, Total=56 [2021-12-06 19:07:24,316 INFO L87 Difference]: Start difference. First operand 334 states and 489 transitions. cyclomatic complexity: 158 Second operand has 8 states, 8 states have (on average 5.5) internal successors, (44), 7 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:24,571 INFO L93 Difference]: Finished difference Result 448 states and 627 transitions. [2021-12-06 19:07:24,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-12-06 19:07:24,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 448 states and 627 transitions. [2021-12-06 19:07:24,575 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 392 [2021-12-06 19:07:24,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 448 states to 448 states and 627 transitions. [2021-12-06 19:07:24,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2021-12-06 19:07:24,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2021-12-06 19:07:24,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 448 states and 627 transitions. [2021-12-06 19:07:24,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:24,578 INFO L681 BuchiCegarLoop]: Abstraction has 448 states and 627 transitions. [2021-12-06 19:07:24,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 448 states and 627 transitions. [2021-12-06 19:07:24,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 448 to 347. [2021-12-06 19:07:24,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 347 states, 347 states have (on average 1.440922190201729) internal successors, (500), 346 states have internal predecessors, (500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 500 transitions. [2021-12-06 19:07:24,584 INFO L704 BuchiCegarLoop]: Abstraction has 347 states and 500 transitions. [2021-12-06 19:07:24,584 INFO L587 BuchiCegarLoop]: Abstraction has 347 states and 500 transitions. [2021-12-06 19:07:24,584 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 19:07:24,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 347 states and 500 transitions. [2021-12-06 19:07:24,586 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 299 [2021-12-06 19:07:24,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:24,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:24,587 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,587 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,587 INFO L791 eck$LassoCheckResult]: Stem: 4072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 4062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 4051#L59 assume !(0 == mp_add_~a3~0#1 % 256); 4052#L59-1 mp_add_~nb~0#1 := 4; 4067#L69 assume !(0 == mp_add_~b3~0#1 % 256); 4058#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 4092#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 4179#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 4178#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 4177#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 4175#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 4173#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 4171#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 4165#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 4168#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 4166#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 4162#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 4163#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 4327#L95-1 [2021-12-06 19:07:24,587 INFO L793 eck$LassoCheckResult]: Loop: 4327#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 4210#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 4325#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 4081#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 4082#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 4150#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 4354#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 4070#L84 assume !(0 == mp_add_~i~0#1 % 256); 4071#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 4352#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 4349#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 4346#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 4342#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 4341#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 4068#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 4069#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 4130#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 4142#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 4143#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 4236#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 4232#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 4233#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 4376#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 4373#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 4370#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 4368#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 4327#L95-1 [2021-12-06 19:07:24,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,587 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 5 times [2021-12-06 19:07:24,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337828001] [2021-12-06 19:07:24,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,598 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:24,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,610 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:24,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1570645289, now seen corresponding path program 1 times [2021-12-06 19:07:24,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043255637] [2021-12-06 19:07:24,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:24,640 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:24,640 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:24,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043255637] [2021-12-06 19:07:24,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043255637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:24,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:24,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:24,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372816889] [2021-12-06 19:07:24,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:24,641 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:24,641 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:24,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:24,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:07:24,642 INFO L87 Difference]: Start difference. First operand 347 states and 500 transitions. cyclomatic complexity: 156 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:24,748 INFO L93 Difference]: Finished difference Result 515 states and 722 transitions. [2021-12-06 19:07:24,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 19:07:24,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 515 states and 722 transitions. [2021-12-06 19:07:24,752 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 461 [2021-12-06 19:07:24,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 515 states to 515 states and 722 transitions. [2021-12-06 19:07:24,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 515 [2021-12-06 19:07:24,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 515 [2021-12-06 19:07:24,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 515 states and 722 transitions. [2021-12-06 19:07:24,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:24,757 INFO L681 BuchiCegarLoop]: Abstraction has 515 states and 722 transitions. [2021-12-06 19:07:24,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 515 states and 722 transitions. [2021-12-06 19:07:24,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 515 to 396. [2021-12-06 19:07:24,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 396 states, 396 states have (on average 1.446969696969697) internal successors, (573), 395 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 573 transitions. [2021-12-06 19:07:24,764 INFO L704 BuchiCegarLoop]: Abstraction has 396 states and 573 transitions. [2021-12-06 19:07:24,764 INFO L587 BuchiCegarLoop]: Abstraction has 396 states and 573 transitions. [2021-12-06 19:07:24,764 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 19:07:24,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 396 states and 573 transitions. [2021-12-06 19:07:24,765 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2021-12-06 19:07:24,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:24,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:24,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,767 INFO L791 eck$LassoCheckResult]: Stem: 4943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 4934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 4923#L59 assume !(0 == mp_add_~a3~0#1 % 256); 4924#L59-1 mp_add_~nb~0#1 := 4; 4939#L69 assume !(0 == mp_add_~b3~0#1 % 256); 4930#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 4964#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 5004#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 5003#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 5002#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 5000#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 4998#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 4996#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 4990#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 4993#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 4991#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 4987#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 4988#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 5287#L95-1 [2021-12-06 19:07:24,767 INFO L793 eck$LassoCheckResult]: Loop: 5287#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 5052#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 5286#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 5013#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 5014#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 4978#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 4979#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 4961#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 5312#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 5311#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 4940#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 4932#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 4933#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 4953#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 5012#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 5218#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 5210#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 5204#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 5185#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 5180#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 5173#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 5041#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 5040#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 4970#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 4971#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 5114#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 5078#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 5294#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 5292#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 5290#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 5288#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 5287#L95-1 [2021-12-06 19:07:24,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,767 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 6 times [2021-12-06 19:07:24,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606713979] [2021-12-06 19:07:24,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,777 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:24,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:24,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1557912240, now seen corresponding path program 2 times [2021-12-06 19:07:24,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666538893] [2021-12-06 19:07:24,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:24,816 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:24,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:24,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666538893] [2021-12-06 19:07:24,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666538893] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:24,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:24,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 19:07:24,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805181888] [2021-12-06 19:07:24,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:24,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:24,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:24,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:24,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:07:24,818 INFO L87 Difference]: Start difference. First operand 396 states and 573 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.75) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:24,869 INFO L93 Difference]: Finished difference Result 463 states and 650 transitions. [2021-12-06 19:07:24,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:07:24,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463 states and 650 transitions. [2021-12-06 19:07:24,873 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 427 [2021-12-06 19:07:24,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463 states to 463 states and 650 transitions. [2021-12-06 19:07:24,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463 [2021-12-06 19:07:24,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463 [2021-12-06 19:07:24,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463 states and 650 transitions. [2021-12-06 19:07:24,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:24,878 INFO L681 BuchiCegarLoop]: Abstraction has 463 states and 650 transitions. [2021-12-06 19:07:24,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states and 650 transitions. [2021-12-06 19:07:24,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 383. [2021-12-06 19:07:24,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 383 states, 383 states have (on average 1.4255874673629243) internal successors, (546), 382 states have internal predecessors, (546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 383 states to 383 states and 546 transitions. [2021-12-06 19:07:24,888 INFO L704 BuchiCegarLoop]: Abstraction has 383 states and 546 transitions. [2021-12-06 19:07:24,888 INFO L587 BuchiCegarLoop]: Abstraction has 383 states and 546 transitions. [2021-12-06 19:07:24,888 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 19:07:24,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 383 states and 546 transitions. [2021-12-06 19:07:24,890 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 347 [2021-12-06 19:07:24,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:24,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:24,891 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,891 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:24,891 INFO L791 eck$LassoCheckResult]: Stem: 5812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 5802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 5789#L59 assume !(0 == mp_add_~a3~0#1 % 256); 5790#L59-1 mp_add_~nb~0#1 := 4; 5807#L69 assume !(0 == mp_add_~b3~0#1 % 256); 5798#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 5830#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6155#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 5810#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 5811#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 5816#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 5817#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 6075#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 6076#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 6064#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 6065#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 6045#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 6046#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 6012#L95-1 [2021-12-06 19:07:24,891 INFO L793 eck$LassoCheckResult]: Loop: 6012#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 5958#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 6009#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 6008#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 6007#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 6006#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6004#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 6005#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 6157#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 6152#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 5909#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 5868#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 5900#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 5891#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 5859#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 5860#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 5835#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 5836#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 5936#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 5931#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 5850#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 5848#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 5846#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 5844#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 5845#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 5880#L84 assume !(0 == mp_add_~i~0#1 % 256); 5947#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 5943#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 5944#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 6041#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 6040#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 5925#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 6060#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 6061#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 6029#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 6012#L95-1 [2021-12-06 19:07:24,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,892 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 7 times [2021-12-06 19:07:24,892 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254564736] [2021-12-06 19:07:24,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,904 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:24,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:24,920 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:24,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:24,920 INFO L85 PathProgramCache]: Analyzing trace with hash -1270880006, now seen corresponding path program 1 times [2021-12-06 19:07:24,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:24,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146370999] [2021-12-06 19:07:24,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:24,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:24,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:24,946 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2021-12-06 19:07:24,946 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:24,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146370999] [2021-12-06 19:07:24,946 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146370999] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:24,946 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:24,947 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:24,947 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053293737] [2021-12-06 19:07:24,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:24,947 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:24,947 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:24,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:24,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:24,948 INFO L87 Difference]: Start difference. First operand 383 states and 546 transitions. cyclomatic complexity: 165 Second operand has 3 states, 3 states have (on average 7.666666666666667) internal successors, (23), 3 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:24,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:24,992 INFO L93 Difference]: Finished difference Result 386 states and 527 transitions. [2021-12-06 19:07:24,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:24,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 386 states and 527 transitions. [2021-12-06 19:07:24,994 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 350 [2021-12-06 19:07:24,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 386 states to 386 states and 527 transitions. [2021-12-06 19:07:24,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 386 [2021-12-06 19:07:24,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 386 [2021-12-06 19:07:24,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386 states and 527 transitions. [2021-12-06 19:07:24,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:24,997 INFO L681 BuchiCegarLoop]: Abstraction has 386 states and 527 transitions. [2021-12-06 19:07:24,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386 states and 527 transitions. [2021-12-06 19:07:25,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386 to 357. [2021-12-06 19:07:25,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 357 states, 357 states have (on average 1.3753501400560224) internal successors, (491), 356 states have internal predecessors, (491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:25,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 357 states to 357 states and 491 transitions. [2021-12-06 19:07:25,002 INFO L704 BuchiCegarLoop]: Abstraction has 357 states and 491 transitions. [2021-12-06 19:07:25,003 INFO L587 BuchiCegarLoop]: Abstraction has 357 states and 491 transitions. [2021-12-06 19:07:25,003 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 19:07:25,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 357 states and 491 transitions. [2021-12-06 19:07:25,004 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 321 [2021-12-06 19:07:25,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:25,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:25,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:25,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:25,005 INFO L791 eck$LassoCheckResult]: Stem: 6585#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 6576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 6564#L59 assume !(0 == mp_add_~a3~0#1 % 256); 6565#L59-1 mp_add_~nb~0#1 := 4; 6581#L69 assume !(0 == mp_add_~b3~0#1 % 256); 6572#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 6842#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6843#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 6834#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 6835#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 6828#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 6829#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 6810#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 6809#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 6807#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 6805#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 6801#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 6799#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 6797#L95-1 [2021-12-06 19:07:25,005 INFO L793 eck$LassoCheckResult]: Loop: 6797#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 6796#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 6795#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 6794#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 6793#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 6792#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6790#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 6791#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 6861#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 6857#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 6674#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 6643#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 6659#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 6660#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 6634#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6600#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 6601#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 6568#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 6569#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 6678#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 6624#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 6625#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 6637#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 6635#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 6636#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 6695#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 6746#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 6823#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 6822#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 6819#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 6804#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 6814#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 6812#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 6802#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 6798#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 6797#L95-1 [2021-12-06 19:07:25,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:25,005 INFO L85 PathProgramCache]: Analyzing trace with hash 389365736, now seen corresponding path program 8 times [2021-12-06 19:07:25,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:25,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873917992] [2021-12-06 19:07:25,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:25,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:25,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:25,014 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:25,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:25,024 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:25,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:25,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1327903996, now seen corresponding path program 1 times [2021-12-06 19:07:25,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:25,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233227067] [2021-12-06 19:07:25,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:25,025 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:25,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:25,062 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 24 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 19:07:25,063 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:25,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233227067] [2021-12-06 19:07:25,063 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233227067] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:25,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [9290142] [2021-12-06 19:07:25,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:25,063 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:25,063 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:25,064 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:25,065 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-12-06 19:07:25,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:25,094 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 7 conjunts are in the unsatisfiable core [2021-12-06 19:07:25,095 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:25,235 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 20 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:25,235 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:25,323 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 20 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 19:07:25,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [9290142] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:25,323 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:25,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2021-12-06 19:07:25,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145975677] [2021-12-06 19:07:25,324 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:25,324 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:25,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:25,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-12-06 19:07:25,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2021-12-06 19:07:25,325 INFO L87 Difference]: Start difference. First operand 357 states and 491 transitions. cyclomatic complexity: 136 Second operand has 11 states, 11 states have (on average 6.545454545454546) internal successors, (72), 11 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:26,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:26,288 INFO L93 Difference]: Finished difference Result 526 states and 669 transitions. [2021-12-06 19:07:26,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-12-06 19:07:26,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 526 states and 669 transitions. [2021-12-06 19:07:26,291 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 439 [2021-12-06 19:07:26,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 526 states to 526 states and 669 transitions. [2021-12-06 19:07:26,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 526 [2021-12-06 19:07:26,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 526 [2021-12-06 19:07:26,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 526 states and 669 transitions. [2021-12-06 19:07:26,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:26,297 INFO L681 BuchiCegarLoop]: Abstraction has 526 states and 669 transitions. [2021-12-06 19:07:26,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states and 669 transitions. [2021-12-06 19:07:26,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 317. [2021-12-06 19:07:26,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 317 states, 317 states have (on average 1.2996845425867507) internal successors, (412), 316 states have internal predecessors, (412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:26,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 412 transitions. [2021-12-06 19:07:26,305 INFO L704 BuchiCegarLoop]: Abstraction has 317 states and 412 transitions. [2021-12-06 19:07:26,305 INFO L587 BuchiCegarLoop]: Abstraction has 317 states and 412 transitions. [2021-12-06 19:07:26,305 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 19:07:26,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 317 states and 412 transitions. [2021-12-06 19:07:26,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 267 [2021-12-06 19:07:26,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:26,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:26,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:26,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:26,308 INFO L791 eck$LassoCheckResult]: Stem: 7775#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 7764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 7757#L59 assume !(0 == mp_add_~a3~0#1 % 256); 7758#L59-1 mp_add_~nb~0#1 := 4; 7769#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 7761#L71 assume 0 == mp_add_~b2~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 7763#L73 assume 0 == mp_add_~b1~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 7794#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 7795#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 7956#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 7957#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 7948#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 7949#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 7938#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 7939#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 7977#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 7929#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 7976#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 7974#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 7970#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 7971#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 7776#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 7777#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 7772#L84 assume !(0 == mp_add_~i~0#1 % 256); 7773#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 7778#L85-1 [2021-12-06 19:07:26,309 INFO L793 eck$LassoCheckResult]: Loop: 7778#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 7765#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 7766#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 7799#L90 assume !(0 == mp_add_~i~0#1 % 256); 8050#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 7883#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 8047#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 8041#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 8040#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 7870#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 7869#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 7868#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 7864#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 7853#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 7854#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 7859#L84 assume !(0 == mp_add_~i~0#1 % 256); 7860#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 7851#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 7852#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 7845#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 7844#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 7978#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 7975#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 7972#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 7973#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 7784#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 7785#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 8030#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 8031#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 8034#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 8022#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 7770#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 7771#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 8061#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 7783#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 7827#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 7828#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 7966#L84 assume !(0 == mp_add_~i~0#1 % 256); 7964#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 7778#L85-1 [2021-12-06 19:07:26,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:26,309 INFO L85 PathProgramCache]: Analyzing trace with hash -311032260, now seen corresponding path program 1 times [2021-12-06 19:07:26,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:26,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361275111] [2021-12-06 19:07:26,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:26,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:26,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:26,379 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:26,380 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:26,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361275111] [2021-12-06 19:07:26,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361275111] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:26,380 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:26,380 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-12-06 19:07:26,380 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507661921] [2021-12-06 19:07:26,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:26,380 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:26,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:26,380 INFO L85 PathProgramCache]: Analyzing trace with hash -976224508, now seen corresponding path program 1 times [2021-12-06 19:07:26,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:26,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079443985] [2021-12-06 19:07:26,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:26,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:26,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:26,424 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:26,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:26,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079443985] [2021-12-06 19:07:26,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079443985] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:26,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [271623966] [2021-12-06 19:07:26,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:26,424 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:26,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:26,464 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:26,465 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-12-06 19:07:26,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:26,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 19:07:26,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:26,545 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2021-12-06 19:07:26,545 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:26,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [271623966] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:26,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:26,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 7 [2021-12-06 19:07:26,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880529091] [2021-12-06 19:07:26,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:26,546 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:26,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:26,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-12-06 19:07:26,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-12-06 19:07:26,547 INFO L87 Difference]: Start difference. First operand 317 states and 412 transitions. cyclomatic complexity: 97 Second operand has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:26,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:26,932 INFO L93 Difference]: Finished difference Result 1211 states and 1578 transitions. [2021-12-06 19:07:26,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 19:07:26,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1211 states and 1578 transitions. [2021-12-06 19:07:26,938 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1068 [2021-12-06 19:07:26,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1211 states to 1211 states and 1578 transitions. [2021-12-06 19:07:26,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1211 [2021-12-06 19:07:26,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1211 [2021-12-06 19:07:26,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1211 states and 1578 transitions. [2021-12-06 19:07:26,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:26,946 INFO L681 BuchiCegarLoop]: Abstraction has 1211 states and 1578 transitions. [2021-12-06 19:07:26,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1211 states and 1578 transitions. [2021-12-06 19:07:26,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1211 to 308. [2021-12-06 19:07:26,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.3051948051948052) internal successors, (402), 307 states have internal predecessors, (402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:26,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 402 transitions. [2021-12-06 19:07:26,953 INFO L704 BuchiCegarLoop]: Abstraction has 308 states and 402 transitions. [2021-12-06 19:07:26,953 INFO L587 BuchiCegarLoop]: Abstraction has 308 states and 402 transitions. [2021-12-06 19:07:26,953 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 19:07:26,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 402 transitions. [2021-12-06 19:07:26,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 267 [2021-12-06 19:07:26,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:26,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:26,955 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:26,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:26,956 INFO L791 eck$LassoCheckResult]: Stem: 9440#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 9431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 9418#L59 assume !(0 == mp_add_~a3~0#1 % 256); 9419#L59-1 mp_add_~nb~0#1 := 4; 9436#L69 assume !(0 == mp_add_~b3~0#1 % 256); 9427#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 9455#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 9452#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 9453#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 9713#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 9444#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 9432#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 9433#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 9719#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 9717#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 9716#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 9715#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 9423#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 9424#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 9437#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 9429#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 9430#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 9448#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 9442#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 9443#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 9721#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 9422#L89 [2021-12-06 19:07:26,956 INFO L793 eck$LassoCheckResult]: Loop: 9422#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 9599#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 9595#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 9509#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 9586#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 9501#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 9491#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 9492#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 9567#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 9575#L90 assume !(0 == mp_add_~i~0#1 % 256); 9573#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 9572#L91-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b2~0#1 % 256; 9568#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 9493#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 9489#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 9487#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 9485#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 9482#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 9479#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 9473#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 9474#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 9460#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 9449#L90 assume !(0 == mp_add_~i~0#1 % 256); 9450#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 9457#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 9530#L92-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b3~0#1 % 256; 9522#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 9519#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 9515#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 9511#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 9499#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 9498#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 9494#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 9495#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 9671#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 9669#L90 assume !(0 == mp_add_~i~0#1 % 256); 9667#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 9420#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 9421#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 9422#L89 [2021-12-06 19:07:26,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:26,956 INFO L85 PathProgramCache]: Analyzing trace with hash 465531897, now seen corresponding path program 1 times [2021-12-06 19:07:26,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:26,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159182404] [2021-12-06 19:07:26,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:26,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:26,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,010 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:27,011 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:27,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159182404] [2021-12-06 19:07:27,011 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159182404] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:27,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [98628652] [2021-12-06 19:07:27,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,011 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:27,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:27,012 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:27,013 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-12-06 19:07:27,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,071 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 7 conjunts are in the unsatisfiable core [2021-12-06 19:07:27,072 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:27,258 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:27,258 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:27,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [98628652] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:27,258 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:27,258 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2021-12-06 19:07:27,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369283723] [2021-12-06 19:07:27,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:27,259 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:27,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:27,259 INFO L85 PathProgramCache]: Analyzing trace with hash 956487534, now seen corresponding path program 1 times [2021-12-06 19:07:27,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:27,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181358129] [2021-12-06 19:07:27,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,259 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:27,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,307 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 10 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:27,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:27,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181358129] [2021-12-06 19:07:27,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181358129] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:27,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [570947772] [2021-12-06 19:07:27,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,308 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:27,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:27,309 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:27,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2021-12-06 19:07:27,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,334 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 19:07:27,335 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:27,383 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2021-12-06 19:07:27,384 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:27,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [570947772] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:27,384 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:27,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [6] total 8 [2021-12-06 19:07:27,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471532566] [2021-12-06 19:07:27,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:27,384 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:27,384 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:27,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-12-06 19:07:27,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2021-12-06 19:07:27,385 INFO L87 Difference]: Start difference. First operand 308 states and 402 transitions. cyclomatic complexity: 96 Second operand has 6 states, 6 states have (on average 4.333333333333333) internal successors, (26), 6 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:27,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:27,492 INFO L93 Difference]: Finished difference Result 357 states and 457 transitions. [2021-12-06 19:07:27,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:07:27,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 357 states and 457 transitions. [2021-12-06 19:07:27,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 293 [2021-12-06 19:07:27,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 357 states to 357 states and 457 transitions. [2021-12-06 19:07:27,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 357 [2021-12-06 19:07:27,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 357 [2021-12-06 19:07:27,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 357 states and 457 transitions. [2021-12-06 19:07:27,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:27,497 INFO L681 BuchiCegarLoop]: Abstraction has 357 states and 457 transitions. [2021-12-06 19:07:27,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states and 457 transitions. [2021-12-06 19:07:27,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 331. [2021-12-06 19:07:27,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 331 states, 331 states have (on average 1.2870090634441087) internal successors, (426), 330 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:27,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 426 transitions. [2021-12-06 19:07:27,502 INFO L704 BuchiCegarLoop]: Abstraction has 331 states and 426 transitions. [2021-12-06 19:07:27,502 INFO L587 BuchiCegarLoop]: Abstraction has 331 states and 426 transitions. [2021-12-06 19:07:27,502 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 19:07:27,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 331 states and 426 transitions. [2021-12-06 19:07:27,503 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 267 [2021-12-06 19:07:27,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:27,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:27,504 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:27,504 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:27,504 INFO L791 eck$LassoCheckResult]: Stem: 10312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 10303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 10296#L59 assume !(0 == mp_add_~a3~0#1 % 256); 10297#L59-1 mp_add_~nb~0#1 := 4; 10308#L69 assume !(0 == mp_add_~b3~0#1 % 256); 10301#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 10331#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10601#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 10595#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 10594#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 10592#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 10591#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 10589#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 10588#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 10587#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 10586#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 10290#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 10291#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 10292#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 10620#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 10619#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 10618#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 10617#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 10616#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10327#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 10310#L84 assume !(0 == mp_add_~i~0#1 % 256); 10311#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 10614#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 10613#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 10558#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 10557#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 10612#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 10309#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 10298#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 10299#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 10471#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 10472#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10467#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 10466#L84 [2021-12-06 19:07:27,504 INFO L793 eck$LassoCheckResult]: Loop: 10466#L84 assume !(0 == mp_add_~i~0#1 % 256); 10465#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 10464#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 10463#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 10460#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 10458#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 10457#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 10456#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 10455#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 10454#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 10453#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 10452#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10451#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 10305#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 10417#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 10405#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 10401#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 10398#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 10379#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 10375#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 10337#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10338#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 10547#L84 assume !(0 == mp_add_~i~0#1 % 256); 10549#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 10548#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 10546#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 10544#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 10323#L90 assume !(0 == mp_add_~i~0#1 % 256); 10324#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 10503#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 10499#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 10495#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 10493#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 10491#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 10397#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 10487#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 10486#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 10469#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 10470#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 10466#L84 [2021-12-06 19:07:27,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:27,504 INFO L85 PathProgramCache]: Analyzing trace with hash 149180734, now seen corresponding path program 1 times [2021-12-06 19:07:27,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:27,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533696432] [2021-12-06 19:07:27,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:27,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,578 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:27,578 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:27,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533696432] [2021-12-06 19:07:27,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533696432] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:27,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1762368302] [2021-12-06 19:07:27,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,579 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:27,579 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:27,580 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:27,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2021-12-06 19:07:27,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,645 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 5 conjunts are in the unsatisfiable core [2021-12-06 19:07:27,646 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:27,730 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2021-12-06 19:07:27,731 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:27,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1762368302] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:27,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:27,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [6] total 7 [2021-12-06 19:07:27,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168838560] [2021-12-06 19:07:27,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:27,731 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:27,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:27,731 INFO L85 PathProgramCache]: Analyzing trace with hash 1135149264, now seen corresponding path program 2 times [2021-12-06 19:07:27,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:27,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548283316] [2021-12-06 19:07:27,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:27,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:27,804 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 23 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:27,804 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:27,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548283316] [2021-12-06 19:07:27,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548283316] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:27,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [236842858] [2021-12-06 19:07:27,804 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 19:07:27,804 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:27,804 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:27,805 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:27,806 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2021-12-06 19:07:27,834 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 19:07:27,834 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:27,835 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 19:07:27,836 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:27,877 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-12-06 19:07:27,878 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:27,878 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [236842858] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:27,878 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:27,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [8] total 10 [2021-12-06 19:07:27,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531824526] [2021-12-06 19:07:27,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:27,878 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:27,878 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:27,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:27,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 19:07:27,879 INFO L87 Difference]: Start difference. First operand 331 states and 426 transitions. cyclomatic complexity: 97 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 4 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:27,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:27,939 INFO L93 Difference]: Finished difference Result 654 states and 837 transitions. [2021-12-06 19:07:27,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:07:27,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 654 states and 837 transitions. [2021-12-06 19:07:27,942 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 534 [2021-12-06 19:07:27,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 654 states to 654 states and 837 transitions. [2021-12-06 19:07:27,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 654 [2021-12-06 19:07:27,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 654 [2021-12-06 19:07:27,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 654 states and 837 transitions. [2021-12-06 19:07:27,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:27,946 INFO L681 BuchiCegarLoop]: Abstraction has 654 states and 837 transitions. [2021-12-06 19:07:27,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states and 837 transitions. [2021-12-06 19:07:27,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 612. [2021-12-06 19:07:27,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 612 states, 612 states have (on average 1.2908496732026145) internal successors, (790), 611 states have internal predecessors, (790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:27,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 612 states to 612 states and 790 transitions. [2021-12-06 19:07:27,955 INFO L704 BuchiCegarLoop]: Abstraction has 612 states and 790 transitions. [2021-12-06 19:07:27,955 INFO L587 BuchiCegarLoop]: Abstraction has 612 states and 790 transitions. [2021-12-06 19:07:27,955 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 19:07:27,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 612 states and 790 transitions. [2021-12-06 19:07:27,957 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 504 [2021-12-06 19:07:27,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:27,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:27,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:27,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:27,958 INFO L791 eck$LassoCheckResult]: Stem: 11543#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 11531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 11524#L59 assume !(0 == mp_add_~a3~0#1 % 256); 11525#L59-1 mp_add_~nb~0#1 := 4; 11536#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 11528#L71 assume !(0 == mp_add_~b2~0#1 % 256); 11529#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 11834#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11833#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 11832#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 11831#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 11830#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 11829#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 11828#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 11827#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 11826#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 11825#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 11824#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 11822#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 11821#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 11820#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 11819#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 11818#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 11817#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 11816#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11815#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 11814#L84 assume !(0 == mp_add_~i~0#1 % 256); 11813#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 11812#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 11811#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 11809#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 11805#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 11801#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 11797#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 11795#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 11793#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 11791#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 11789#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11787#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 11784#L84 [2021-12-06 19:07:27,958 INFO L793 eck$LassoCheckResult]: Loop: 11784#L84 assume !(0 == mp_add_~i~0#1 % 256); 11785#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 12019#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 12017#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 11668#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 11667#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 11770#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 11767#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 11766#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 11765#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 11764#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 11763#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11758#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 11760#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 11626#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 11623#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 11617#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 11618#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 11604#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 11603#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 11598#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11599#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 12069#L84 assume !(0 == mp_add_~i~0#1 % 256); 12068#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 12066#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 11939#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 11994#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 11993#L90 assume !(0 == mp_add_~i~0#1 % 256); 11992#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 11989#L91-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b2~0#1 % 256; 11835#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 11650#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 11651#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 11802#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 11692#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 11740#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 11741#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 11733#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 11734#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 11784#L84 [2021-12-06 19:07:27,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:27,958 INFO L85 PathProgramCache]: Analyzing trace with hash 225768271, now seen corresponding path program 1 times [2021-12-06 19:07:27,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:27,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899911977] [2021-12-06 19:07:27,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:27,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:27,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:28,021 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:28,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:28,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899911977] [2021-12-06 19:07:28,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899911977] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:28,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1382852718] [2021-12-06 19:07:28,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:28,021 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:28,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:28,022 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:28,023 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-12-06 19:07:28,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:28,097 INFO L263 TraceCheckSpWp]: Trace formula consists of 126 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 19:07:28,099 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:28,331 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 19:07:28,331 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:28,464 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 14 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:28,464 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1382852718] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:28,465 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:28,465 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 7] total 15 [2021-12-06 19:07:28,465 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103731809] [2021-12-06 19:07:28,465 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:28,465 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:28,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:28,466 INFO L85 PathProgramCache]: Analyzing trace with hash -1806931120, now seen corresponding path program 1 times [2021-12-06 19:07:28,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:28,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412991020] [2021-12-06 19:07:28,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:28,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:28,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:28,485 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2021-12-06 19:07:28,485 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:28,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412991020] [2021-12-06 19:07:28,485 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412991020] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:28,485 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:28,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:28,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459001664] [2021-12-06 19:07:28,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:28,486 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:28,486 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:28,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:28,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:28,487 INFO L87 Difference]: Start difference. First operand 612 states and 790 transitions. cyclomatic complexity: 181 Second operand has 3 states, 3 states have (on average 11.0) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:28,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:28,529 INFO L93 Difference]: Finished difference Result 637 states and 787 transitions. [2021-12-06 19:07:28,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:28,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 637 states and 787 transitions. [2021-12-06 19:07:28,533 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 529 [2021-12-06 19:07:28,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 637 states to 637 states and 787 transitions. [2021-12-06 19:07:28,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 637 [2021-12-06 19:07:28,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 637 [2021-12-06 19:07:28,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 637 states and 787 transitions. [2021-12-06 19:07:28,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:28,539 INFO L681 BuchiCegarLoop]: Abstraction has 637 states and 787 transitions. [2021-12-06 19:07:28,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states and 787 transitions. [2021-12-06 19:07:28,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 567. [2021-12-06 19:07:28,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 567 states, 567 states have (on average 1.2398589065255732) internal successors, (703), 566 states have internal predecessors, (703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:28,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 703 transitions. [2021-12-06 19:07:28,551 INFO L704 BuchiCegarLoop]: Abstraction has 567 states and 703 transitions. [2021-12-06 19:07:28,551 INFO L587 BuchiCegarLoop]: Abstraction has 567 states and 703 transitions. [2021-12-06 19:07:28,551 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 19:07:28,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567 states and 703 transitions. [2021-12-06 19:07:28,553 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 459 [2021-12-06 19:07:28,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:28,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:28,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:28,554 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:28,554 INFO L791 eck$LassoCheckResult]: Stem: 13037#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 13026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 13014#L59 assume !(0 == mp_add_~a3~0#1 % 256); 13015#L59-1 mp_add_~nb~0#1 := 4; 13031#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 13021#L71 assume !(0 == mp_add_~b2~0#1 % 256); 13022#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 13052#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13474#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 13473#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 13472#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 13471#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 13470#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 13469#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 13467#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 13465#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 13463#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 13461#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 13458#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 13456#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 13454#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 13452#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 13450#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 13448#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 13445#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13444#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 13442#L84 assume !(0 == mp_add_~i~0#1 % 256); 13440#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 13439#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 13438#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 13435#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 13429#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 13428#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 13424#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 13423#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 13422#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 13420#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 13419#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13248#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 13249#L84 [2021-12-06 19:07:28,554 INFO L793 eck$LassoCheckResult]: Loop: 13249#L84 assume !(0 == mp_add_~i~0#1 % 256); 13244#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 13245#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 13238#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 13239#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 13336#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 13335#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 13334#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 13333#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 13332#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 13331#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 13330#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13328#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 13329#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 13475#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 13321#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 13417#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 13105#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 13106#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 13086#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 13087#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13409#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 13400#L84 assume !(0 == mp_add_~i~0#1 % 256); 13401#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 13396#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 13395#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 13393#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 13309#L90 assume !(0 == mp_add_~i~0#1 % 256); 13392#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 13391#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 13306#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 13307#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 13297#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 13298#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 13285#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 13286#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 13276#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 13277#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 13268#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 13249#L84 [2021-12-06 19:07:28,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:28,555 INFO L85 PathProgramCache]: Analyzing trace with hash 225768271, now seen corresponding path program 2 times [2021-12-06 19:07:28,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:28,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157151351] [2021-12-06 19:07:28,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:28,555 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:28,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:28,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:28,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157151351] [2021-12-06 19:07:28,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157151351] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:28,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [574108505] [2021-12-06 19:07:28,627 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 19:07:28,627 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:28,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:28,629 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:28,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-12-06 19:07:28,735 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 19:07:28,735 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:28,736 INFO L263 TraceCheckSpWp]: Trace formula consists of 126 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 19:07:28,738 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:28,969 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 19:07:28,969 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:29,085 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 14 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:29,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [574108505] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:29,085 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:29,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 7] total 15 [2021-12-06 19:07:29,086 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439805867] [2021-12-06 19:07:29,086 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:29,086 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:29,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:29,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1135149264, now seen corresponding path program 3 times [2021-12-06 19:07:29,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:29,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738109262] [2021-12-06 19:07:29,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:29,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:29,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:29,150 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 23 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:29,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:29,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738109262] [2021-12-06 19:07:29,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738109262] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:29,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [637912283] [2021-12-06 19:07:29,150 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 19:07:29,150 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:29,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:29,151 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:29,152 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-12-06 19:07:29,176 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2021-12-06 19:07:29,176 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:29,176 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 19:07:29,177 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:29,224 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-12-06 19:07:29,224 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 19:07:29,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [637912283] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:29,225 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 19:07:29,225 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [8] total 10 [2021-12-06 19:07:29,225 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672835071] [2021-12-06 19:07:29,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:29,225 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:29,225 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:29,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:07:29,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2021-12-06 19:07:29,226 INFO L87 Difference]: Start difference. First operand 567 states and 703 transitions. cyclomatic complexity: 139 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 4 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:29,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:29,311 INFO L93 Difference]: Finished difference Result 665 states and 808 transitions. [2021-12-06 19:07:29,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:07:29,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 808 transitions. [2021-12-06 19:07:29,315 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 541 [2021-12-06 19:07:29,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 649 states and 782 transitions. [2021-12-06 19:07:29,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 649 [2021-12-06 19:07:29,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 649 [2021-12-06 19:07:29,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 649 states and 782 transitions. [2021-12-06 19:07:29,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:29,320 INFO L681 BuchiCegarLoop]: Abstraction has 649 states and 782 transitions. [2021-12-06 19:07:29,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states and 782 transitions. [2021-12-06 19:07:29,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 530. [2021-12-06 19:07:29,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 530 states, 530 states have (on average 1.2264150943396226) internal successors, (650), 529 states have internal predecessors, (650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:29,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 650 transitions. [2021-12-06 19:07:29,328 INFO L704 BuchiCegarLoop]: Abstraction has 530 states and 650 transitions. [2021-12-06 19:07:29,328 INFO L587 BuchiCegarLoop]: Abstraction has 530 states and 650 transitions. [2021-12-06 19:07:29,328 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 19:07:29,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 530 states and 650 transitions. [2021-12-06 19:07:29,330 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 422 [2021-12-06 19:07:29,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:29,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:29,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:29,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:29,331 INFO L791 eck$LassoCheckResult]: Stem: 14637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 14626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 14619#L59 assume !(0 == mp_add_~a3~0#1 % 256); 14620#L59-1 mp_add_~nb~0#1 := 4; 14631#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 14623#L71 assume !(0 == mp_add_~b2~0#1 % 256); 14624#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 14983#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14982#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14981#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 14980#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 14979#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 14978#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 14977#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 14976#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 14975#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 14974#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 14973#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 14971#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 14970#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 14969#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 14968#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 14967#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 14966#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14965#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14964#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14963#L84 assume !(0 == mp_add_~i~0#1 % 256); 14962#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 14961#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 14960#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 14958#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 14951#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 14952#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 14941#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 14942#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 14929#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 14930#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14917#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14918#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14835#L84 [2021-12-06 19:07:29,331 INFO L793 eck$LassoCheckResult]: Loop: 14835#L84 assume !(0 == mp_add_~i~0#1 % 256); 14836#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 14827#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 14828#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 14819#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 14818#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 14812#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 14813#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 14808#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 14809#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 14804#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14805#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14800#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14801#L84 assume !(0 == mp_add_~i~0#1 % 256); 14794#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 14795#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 14789#L86-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a3~0#1 % 256; 14790#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 14700#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 14701#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 14696#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 14697#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 14692#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 14693#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14688#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14689#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 14685#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 14684#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 14763#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 15031#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 14665#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 14664#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 14913#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14914#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14783#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14784#L84 assume !(0 == mp_add_~i~0#1 % 256); 14908#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 14772#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 14943#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 14944#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 14877#L90 assume !(0 == mp_add_~i~0#1 % 256); 14931#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 14919#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 14920#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 14869#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 14870#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 14861#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 14862#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 14853#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 14854#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 14845#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 14846#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 14835#L84 [2021-12-06 19:07:29,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:29,331 INFO L85 PathProgramCache]: Analyzing trace with hash 225768271, now seen corresponding path program 3 times [2021-12-06 19:07:29,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:29,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032185110] [2021-12-06 19:07:29,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:29,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:29,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:29,394 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:29,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:29,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032185110] [2021-12-06 19:07:29,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032185110] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:29,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1365222991] [2021-12-06 19:07:29,395 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 19:07:29,395 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:29,395 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:29,395 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:29,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-12-06 19:07:29,481 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2021-12-06 19:07:29,482 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:29,482 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 7 conjunts are in the unsatisfiable core [2021-12-06 19:07:29,483 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:29,655 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-12-06 19:07:29,655 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:29,711 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-12-06 19:07:29,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1365222991] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:29,711 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:29,711 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 12 [2021-12-06 19:07:29,711 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779209106] [2021-12-06 19:07:29,711 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:29,711 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:29,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:29,712 INFO L85 PathProgramCache]: Analyzing trace with hash -152111539, now seen corresponding path program 1 times [2021-12-06 19:07:29,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:29,712 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204621275] [2021-12-06 19:07:29,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:29,712 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:29,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:29,770 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 30 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:29,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:29,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204621275] [2021-12-06 19:07:29,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204621275] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:29,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1486147407] [2021-12-06 19:07:29,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:29,771 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:29,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:29,772 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:29,772 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-12-06 19:07:29,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:29,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 19:07:29,805 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:29,955 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:29,955 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:30,081 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:30,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1486147407] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:30,081 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:30,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 15 [2021-12-06 19:07:30,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102360389] [2021-12-06 19:07:30,082 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:30,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:30,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:30,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-12-06 19:07:30,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2021-12-06 19:07:30,083 INFO L87 Difference]: Start difference. First operand 530 states and 650 transitions. cyclomatic complexity: 123 Second operand has 12 states, 12 states have (on average 7.666666666666667) internal successors, (92), 12 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:30,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:30,780 INFO L93 Difference]: Finished difference Result 1481 states and 1776 transitions. [2021-12-06 19:07:30,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-12-06 19:07:30,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1481 states and 1776 transitions. [2021-12-06 19:07:30,788 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1199 [2021-12-06 19:07:30,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1481 states to 1449 states and 1738 transitions. [2021-12-06 19:07:30,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1449 [2021-12-06 19:07:30,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1449 [2021-12-06 19:07:30,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1449 states and 1738 transitions. [2021-12-06 19:07:30,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:30,798 INFO L681 BuchiCegarLoop]: Abstraction has 1449 states and 1738 transitions. [2021-12-06 19:07:30,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1449 states and 1738 transitions. [2021-12-06 19:07:30,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1449 to 1261. [2021-12-06 19:07:30,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1261 states, 1261 states have (on average 1.2204599524187154) internal successors, (1539), 1260 states have internal predecessors, (1539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:30,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1261 states to 1261 states and 1539 transitions. [2021-12-06 19:07:30,819 INFO L704 BuchiCegarLoop]: Abstraction has 1261 states and 1539 transitions. [2021-12-06 19:07:30,819 INFO L587 BuchiCegarLoop]: Abstraction has 1261 states and 1539 transitions. [2021-12-06 19:07:30,819 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 19:07:30,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1261 states and 1539 transitions. [2021-12-06 19:07:30,824 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1075 [2021-12-06 19:07:30,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:30,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:30,825 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:30,825 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:30,825 INFO L791 eck$LassoCheckResult]: Stem: 17240#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 17229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 17222#L59 assume !(0 == mp_add_~a3~0#1 % 256); 17223#L59-1 mp_add_~nb~0#1 := 4; 17234#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 17226#L71 assume 0 == mp_add_~b2~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 17228#L73 assume 0 == mp_add_~b1~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 17255#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 17627#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17626#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17625#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 17624#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 17622#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 17620#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 17618#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 17616#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 17614#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 17612#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 17610#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 17607#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 17604#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 17601#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 17597#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 17594#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 17593#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17592#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17590#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17588#L84 assume !(0 == mp_add_~i~0#1 % 256); 17586#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 17584#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 17578#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 17576#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 17561#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 17562#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 17552#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 17553#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 17571#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 17570#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17472#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17473#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17402#L84 [2021-12-06 19:07:30,825 INFO L793 eck$LassoCheckResult]: Loop: 17402#L84 assume !(0 == mp_add_~i~0#1 % 256); 17403#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 17396#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 17397#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 17382#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 17381#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 17370#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 17371#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 17361#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 17362#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 17353#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17354#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17344#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17345#L84 assume !(0 == mp_add_~i~0#1 % 256); 17330#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 17331#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 17314#L86-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a3~0#1 % 256; 17315#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 17302#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 17303#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 17298#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 17299#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 17294#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 17295#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17290#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17291#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 17283#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 17285#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 17274#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 17275#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 17271#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 17267#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 17268#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17263#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17264#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17633#L84 assume !(0 == mp_add_~i~0#1 % 256); 17634#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 17603#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 17600#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 17595#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 17505#L90 assume !(0 == mp_add_~i~0#1 % 256); 17536#L90-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b1~0#1 % 256; 17581#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 17580#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 17497#L89 assume mp_add_~partial_sum~0#1 % 65536 > 255;mp_add_~partial_sum~0#1 := ~bitwiseAnd(mp_add_~partial_sum~0#1 % 65536, 255);mp_add_~carry~0#1 := 1; 17498#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 17489#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 17490#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 17481#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 17482#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 17431#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 17432#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 17402#L84 [2021-12-06 19:07:30,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:30,825 INFO L85 PathProgramCache]: Analyzing trace with hash -764527287, now seen corresponding path program 1 times [2021-12-06 19:07:30,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:30,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295972408] [2021-12-06 19:07:30,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:30,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:30,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:30,905 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:30,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:30,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295972408] [2021-12-06 19:07:30,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295972408] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:30,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1093637298] [2021-12-06 19:07:30,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:30,906 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:30,906 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:30,906 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:30,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-12-06 19:07:30,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:30,995 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 15 conjunts are in the unsatisfiable core [2021-12-06 19:07:30,996 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:31,128 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,128 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:31,196 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,197 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1093637298] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:31,197 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:31,197 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2021-12-06 19:07:31,197 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356122632] [2021-12-06 19:07:31,197 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:31,197 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:07:31,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:31,198 INFO L85 PathProgramCache]: Analyzing trace with hash -152111539, now seen corresponding path program 2 times [2021-12-06 19:07:31,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:31,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549002138] [2021-12-06 19:07:31,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:31,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:31,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:31,263 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 30 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:31,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549002138] [2021-12-06 19:07:31,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549002138] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:31,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2131144450] [2021-12-06 19:07:31,264 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 19:07:31,264 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:31,264 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:31,265 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:31,266 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-12-06 19:07:31,310 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 19:07:31,310 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:31,311 INFO L263 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 19:07:31,312 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:31,467 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,467 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:31,600 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2131144450] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:31,601 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:31,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 15 [2021-12-06 19:07:31,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710676590] [2021-12-06 19:07:31,601 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:31,601 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:07:31,601 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:31,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-12-06 19:07:31,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2021-12-06 19:07:31,602 INFO L87 Difference]: Start difference. First operand 1261 states and 1539 transitions. cyclomatic complexity: 284 Second operand has 11 states, 11 states have (on average 7.0) internal successors, (77), 11 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:31,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:07:31,811 INFO L93 Difference]: Finished difference Result 1644 states and 1959 transitions. [2021-12-06 19:07:31,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-12-06 19:07:31,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1644 states and 1959 transitions. [2021-12-06 19:07:31,818 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1385 [2021-12-06 19:07:31,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1644 states to 1644 states and 1959 transitions. [2021-12-06 19:07:31,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1644 [2021-12-06 19:07:31,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1644 [2021-12-06 19:07:31,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1644 states and 1959 transitions. [2021-12-06 19:07:31,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:31,827 INFO L681 BuchiCegarLoop]: Abstraction has 1644 states and 1959 transitions. [2021-12-06 19:07:31,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1644 states and 1959 transitions. [2021-12-06 19:07:31,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1644 to 1246. [2021-12-06 19:07:31,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1246 states, 1246 states have (on average 1.2215088282504012) internal successors, (1522), 1245 states have internal predecessors, (1522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:31,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1246 states to 1246 states and 1522 transitions. [2021-12-06 19:07:31,845 INFO L704 BuchiCegarLoop]: Abstraction has 1246 states and 1522 transitions. [2021-12-06 19:07:31,845 INFO L587 BuchiCegarLoop]: Abstraction has 1246 states and 1522 transitions. [2021-12-06 19:07:31,845 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 19:07:31,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1246 states and 1522 transitions. [2021-12-06 19:07:31,849 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1072 [2021-12-06 19:07:31,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:07:31,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:07:31,850 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:31,850 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:31,850 INFO L791 eck$LassoCheckResult]: Stem: 20723#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(15, 2); 20713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~ret2#1, main_~a~0#1, main_~b~0#1, main_~r~1#1;havoc main_~a~0#1;havoc main_~b~0#1;havoc main_~r~1#1;main_~b~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~a~0#1 := 234770789;assume { :begin_inline_mp_add } true;mp_add_#in~a#1, mp_add_#in~b#1 := main_~a~0#1, main_~b~0#1;havoc mp_add_#res#1;havoc mp_add_~a#1, mp_add_~b#1, mp_add_~a0~0#1, mp_add_~a1~0#1, mp_add_~a2~0#1, mp_add_~a3~0#1, mp_add_~b0~0#1, mp_add_~b1~0#1, mp_add_~b2~0#1, mp_add_~b3~0#1, mp_add_~r0~0#1, mp_add_~r1~0#1, mp_add_~r2~0#1, mp_add_~r3~0#1, mp_add_~carry~0#1, mp_add_~partial_sum~0#1, mp_add_~r~0#1, mp_add_~i~0#1, mp_add_~na~0#1, mp_add_~nb~0#1;mp_add_~a#1 := mp_add_#in~a#1;mp_add_~b#1 := mp_add_#in~b#1;havoc mp_add_~a0~0#1;havoc mp_add_~a1~0#1;havoc mp_add_~a2~0#1;havoc mp_add_~a3~0#1;havoc mp_add_~b0~0#1;havoc mp_add_~b1~0#1;havoc mp_add_~b2~0#1;havoc mp_add_~b3~0#1;havoc mp_add_~r0~0#1;havoc mp_add_~r1~0#1;havoc mp_add_~r2~0#1;havoc mp_add_~r3~0#1;havoc mp_add_~carry~0#1;havoc mp_add_~partial_sum~0#1;havoc mp_add_~r~0#1;havoc mp_add_~i~0#1;havoc mp_add_~na~0#1;havoc mp_add_~nb~0#1;mp_add_~a0~0#1 := mp_add_~a#1;mp_add_~a1~0#1 := mp_add_~a#1 / 256;mp_add_~a2~0#1 := mp_add_~a#1 / 65536;mp_add_~a3~0#1 := mp_add_~a#1 / 16777216;mp_add_~b0~0#1 := mp_add_~b#1;mp_add_~b1~0#1 := mp_add_~b#1 / 256;mp_add_~b2~0#1 := mp_add_~b#1 / 65536;mp_add_~b3~0#1 := mp_add_~b#1 / 16777216;mp_add_~na~0#1 := 4; 20706#L59 assume !(0 == mp_add_~a3~0#1 % 256); 20707#L59-1 mp_add_~nb~0#1 := 4; 20718#L69 assume 0 == mp_add_~b3~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 20710#L71 assume 0 == mp_add_~b2~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 20712#L73 assume 0 == mp_add_~b1~0#1 % 256;mp_add_~nb~0#1 := mp_add_~nb~0#1 % 256 - 1; 20741#L69-1 mp_add_~carry~0#1 := 0;mp_add_~i~0#1 := 0; 21071#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21072#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 21067#L84 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a0~0#1 % 256; 21068#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 21063#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 21064#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 21059#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 21060#L90 assume 0 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~b0~0#1 % 256; 21055#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 21056#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 21051#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 21052#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 21047#L95-1 assume 0 == mp_add_~i~0#1 % 256;mp_add_~r0~0#1 := mp_add_~partial_sum~0#1; 21048#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 21043#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 21044#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 21039#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21040#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21035#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 21036#L84 assume !(0 == mp_add_~i~0#1 % 256); 21031#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 21032#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 21027#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 21028#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 21212#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 21210#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 21207#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 21182#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 21179#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 21176#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21173#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21174#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 20984#L84 [2021-12-06 19:07:31,850 INFO L793 eck$LassoCheckResult]: Loop: 20984#L84 assume !(0 == mp_add_~i~0#1 % 256); 20985#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 20944#L85-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a2~0#1 % 256; 20945#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 20942#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 21159#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 20863#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 21156#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 21152#L100-1 assume 2 == mp_add_~i~0#1 % 256;mp_add_~r2~0#1 := mp_add_~partial_sum~0#1; 21153#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 21146#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21147#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21139#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 21140#L84 assume !(0 == mp_add_~i~0#1 % 256); 21129#L84-2 assume !(1 == mp_add_~i~0#1 % 256); 21130#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 21108#L86-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a3~0#1 % 256; 21109#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 20824#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 20787#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 21096#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 21097#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 21084#L101-1 assume 3 == mp_add_~i~0#1 % 256;mp_add_~r3~0#1 := mp_add_~partial_sum~0#1; 21085#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21080#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21081#L83 assume !(mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256); 21240#L83-1 assume mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256; 21215#L90 assume !(0 == mp_add_~i~0#1 % 256); 21248#L90-2 assume !(1 == mp_add_~i~0#1 % 256); 21247#L91-1 assume !(2 == mp_add_~i~0#1 % 256); 20772#L92-1 assume !(3 == mp_add_~i~0#1 % 256); 21214#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 20762#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 20763#L99-1 assume !(1 == mp_add_~i~0#1 % 256); 21211#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 20756#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 21204#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21195#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21119#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 21120#L84 assume !(0 == mp_add_~i~0#1 % 256); 21131#L84-2 assume 1 == mp_add_~i~0#1 % 256;mp_add_~partial_sum~0#1 := mp_add_~partial_sum~0#1 % 65536 + mp_add_~a1~0#1 % 256; 20815#L85-1 assume !(2 == mp_add_~i~0#1 % 256); 21018#L86-1 assume !(3 == mp_add_~i~0#1 % 256); 21019#L83-1 assume !(mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256); 21208#L89 assume !(mp_add_~partial_sum~0#1 % 65536 > 255); 21206#L95-1 assume !(0 == mp_add_~i~0#1 % 256); 21205#L99-1 assume 1 == mp_add_~i~0#1 % 256;mp_add_~r1~0#1 := mp_add_~partial_sum~0#1; 21183#L100-1 assume !(2 == mp_add_~i~0#1 % 256); 21180#L101-1 assume !(3 == mp_add_~i~0#1 % 256); 21177#L102-1 mp_add_~i~0#1 := 1 + mp_add_~i~0#1 % 256; 21014#L80-2 assume !!((mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256 || mp_add_~i~0#1 % 256 < mp_add_~nb~0#1 % 256) || 0 != mp_add_~carry~0#1 % 65536);mp_add_~partial_sum~0#1 := mp_add_~carry~0#1;mp_add_~carry~0#1 := 0; 21015#L83 assume mp_add_~i~0#1 % 256 < mp_add_~na~0#1 % 256; 20984#L84 [2021-12-06 19:07:31,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:31,851 INFO L85 PathProgramCache]: Analyzing trace with hash -1151172087, now seen corresponding path program 1 times [2021-12-06 19:07:31,851 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:31,851 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119375417] [2021-12-06 19:07:31,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:31,851 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:31,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:31,868 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:07:31,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:07:31,882 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:07:31,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:31,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1060317865, now seen corresponding path program 1 times [2021-12-06 19:07:31,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:31,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716672724] [2021-12-06 19:07:31,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:31,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:31,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:31,915 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 51 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:31,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:31,916 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716672724] [2021-12-06 19:07:31,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716672724] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:31,916 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [542960003] [2021-12-06 19:07:31,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:31,916 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:31,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:31,917 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:31,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-12-06 19:07:31,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:31,943 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 6 conjunts are in the unsatisfiable core [2021-12-06 19:07:31,943 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:32,128 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 54 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2021-12-06 19:07:32,129 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:09:54,319 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 46 proven. 12 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2021-12-06 19:09:54,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [542960003] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:09:54,319 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:09:54,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7, 7] total 16 [2021-12-06 19:09:54,319 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585995065] [2021-12-06 19:09:54,319 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:09:54,320 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:09:54,320 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:09:54,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-12-06 19:09:54,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=183, Unknown=11, NotChecked=0, Total=240 [2021-12-06 19:09:54,321 INFO L87 Difference]: Start difference. First operand 1246 states and 1522 transitions. cyclomatic complexity: 282 Second operand has 16 states, 16 states have (on average 7.0) internal successors, (112), 16 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:12:08,038 WARN L228 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) stderr output: (error "out of memory") [2021-12-06 19:12:08,039 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 101 [2021-12-06 19:12:08,039 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:241) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:260) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.smtlibutils.ManagedScript.checkSat(ManagedScript.java:139) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:85) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:934) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:773) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:345) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:388) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:229) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.getOrConstructPredicate(DeterministicInterpolantAutomaton.java:282) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.constructSuccessorsAndTransitions(DeterministicInterpolantAutomaton.java:304) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:79) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:233) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:213) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:216) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:208) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1058) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:960) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:182) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.refineFinite(BuchiCegarLoop.java:950) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:530) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1465) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:658) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:237) ... 40 more [2021-12-06 19:12:08,041 INFO L158 Benchmark]: Toolchain (without parser) took 286975.12ms. Allocated memory was 132.1MB in the beginning and 192.9MB in the end (delta: 60.8MB). Free memory was 98.4MB in the beginning and 52.9MB in the end (delta: 45.5MB). Peak memory consumption was 105.7MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,042 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 77.6MB. Free memory was 53.2MB in the beginning and 53.2MB in the end (delta: 30.2kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-06 19:12:08,042 INFO L158 Benchmark]: CACSL2BoogieTranslator took 205.50ms. Allocated memory is still 132.1MB. Free memory was 98.1MB in the beginning and 107.0MB in the end (delta: -9.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,042 INFO L158 Benchmark]: Boogie Procedure Inliner took 29.43ms. Allocated memory is still 132.1MB. Free memory was 107.0MB in the beginning and 105.0MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,042 INFO L158 Benchmark]: Boogie Preprocessor took 23.55ms. Allocated memory is still 132.1MB. Free memory was 105.0MB in the beginning and 103.7MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,042 INFO L158 Benchmark]: RCFGBuilder took 245.76ms. Allocated memory is still 132.1MB. Free memory was 103.7MB in the beginning and 91.1MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,043 INFO L158 Benchmark]: BuchiAutomizer took 286466.92ms. Allocated memory was 132.1MB in the beginning and 192.9MB in the end (delta: 60.8MB). Free memory was 91.1MB in the beginning and 52.9MB in the end (delta: 38.3MB). Peak memory consumption was 100.0MB. Max. memory is 16.1GB. [2021-12-06 19:12:08,044 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 77.6MB. Free memory was 53.2MB in the beginning and 53.2MB in the end (delta: 30.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 205.50ms. Allocated memory is still 132.1MB. Free memory was 98.1MB in the beginning and 107.0MB in the end (delta: -9.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 29.43ms. Allocated memory is still 132.1MB. Free memory was 107.0MB in the beginning and 105.0MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 23.55ms. Allocated memory is still 132.1MB. Free memory was 105.0MB in the beginning and 103.7MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 245.76ms. Allocated memory is still 132.1MB. Free memory was 103.7MB in the beginning and 91.1MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 286466.92ms. Allocated memory was 132.1MB in the beginning and 192.9MB in the end (delta: 60.8MB). Free memory was 91.1MB in the beginning and 52.9MB in the end (delta: 38.3MB). Peak memory consumption was 100.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:241) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-06 19:12:08,069 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2021-12-06 19:12:08,288 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2021-12-06 19:12:08,506 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2021-12-06 19:12:08,710 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2021-12-06 19:12:08,861 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2021-12-06 19:12:09,106 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2021-12-06 19:12:09,259 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2021-12-06 19:12:09,507 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2021-12-06 19:12:09,680 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2021-12-06 19:12:09,881 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2021-12-06 19:12:10,080 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2021-12-06 19:12:10,307 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2021-12-06 19:12:10,481 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-12-06 19:12:10,682 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2021-12-06 19:12:10,910 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9c5ad11-5a09-49e0-ae44-10443d747400/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory")