./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-07 01:23:13,203 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-07 01:23:13,205 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-07 01:23:13,236 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-07 01:23:13,237 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-07 01:23:13,238 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-07 01:23:13,240 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-07 01:23:13,242 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-07 01:23:13,244 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-07 01:23:13,245 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-07 01:23:13,246 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-07 01:23:13,248 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-07 01:23:13,248 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-07 01:23:13,249 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-07 01:23:13,251 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-07 01:23:13,252 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-07 01:23:13,253 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-07 01:23:13,254 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-07 01:23:13,256 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-07 01:23:13,259 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-07 01:23:13,260 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-07 01:23:13,262 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-07 01:23:13,263 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-07 01:23:13,264 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-07 01:23:13,267 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-07 01:23:13,268 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-07 01:23:13,268 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-07 01:23:13,269 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-07 01:23:13,270 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-07 01:23:13,271 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-07 01:23:13,271 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-07 01:23:13,272 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-07 01:23:13,273 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-07 01:23:13,273 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-07 01:23:13,274 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-07 01:23:13,275 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-07 01:23:13,275 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-07 01:23:13,275 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-07 01:23:13,276 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-07 01:23:13,276 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-07 01:23:13,277 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-07 01:23:13,278 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-07 01:23:13,301 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-07 01:23:13,302 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-07 01:23:13,302 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-07 01:23:13,302 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-07 01:23:13,303 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-07 01:23:13,304 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-07 01:23:13,304 INFO L138 SettingsManager]: * Use SBE=true [2021-12-07 01:23:13,304 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-07 01:23:13,304 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-07 01:23:13,304 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-07 01:23:13,304 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-07 01:23:13,305 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-07 01:23:13,305 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-07 01:23:13,305 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-07 01:23:13,305 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-07 01:23:13,305 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-07 01:23:13,306 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-07 01:23:13,307 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-07 01:23:13,307 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-07 01:23:13,307 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-07 01:23:13,307 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-07 01:23:13,307 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-07 01:23:13,308 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-07 01:23:13,308 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-07 01:23:13,308 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-07 01:23:13,308 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-07 01:23:13,308 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-07 01:23:13,309 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-07 01:23:13,309 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 [2021-12-07 01:23:13,483 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-07 01:23:13,501 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-07 01:23:13,503 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-07 01:23:13,504 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-07 01:23:13,504 INFO L275 PluginConnector]: CDTParser initialized [2021-12-07 01:23:13,505 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/pipeline.cil-1.c [2021-12-07 01:23:13,549 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/data/bdb470448/ac899e9d47d549eba094da278ac87200/FLAGacb07fd0e [2021-12-07 01:23:13,949 INFO L306 CDTParser]: Found 1 translation units. [2021-12-07 01:23:13,950 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/sv-benchmarks/c/systemc/pipeline.cil-1.c [2021-12-07 01:23:13,957 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/data/bdb470448/ac899e9d47d549eba094da278ac87200/FLAGacb07fd0e [2021-12-07 01:23:13,967 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/data/bdb470448/ac899e9d47d549eba094da278ac87200 [2021-12-07 01:23:13,969 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-07 01:23:13,970 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-07 01:23:13,971 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-07 01:23:13,971 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-07 01:23:13,974 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-07 01:23:13,975 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:23:13" (1/1) ... [2021-12-07 01:23:13,976 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37b1de1e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:13, skipping insertion in model container [2021-12-07 01:23:13,976 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:23:13" (1/1) ... [2021-12-07 01:23:13,983 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-07 01:23:14,014 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-07 01:23:14,130 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2021-12-07 01:23:14,181 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 01:23:14,188 INFO L203 MainTranslator]: Completed pre-run [2021-12-07 01:23:14,196 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2021-12-07 01:23:14,225 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 01:23:14,236 INFO L208 MainTranslator]: Completed translation [2021-12-07 01:23:14,236 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14 WrapperNode [2021-12-07 01:23:14,237 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-07 01:23:14,237 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-07 01:23:14,237 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-07 01:23:14,238 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-07 01:23:14,243 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,250 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,281 INFO L137 Inliner]: procedures = 20, calls = 17, calls flagged for inlining = 12, calls inlined = 24, statements flattened = 1037 [2021-12-07 01:23:14,281 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-07 01:23:14,282 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-07 01:23:14,282 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-07 01:23:14,282 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-07 01:23:14,288 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,289 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,293 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,293 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,306 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,320 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,323 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,330 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-07 01:23:14,330 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-07 01:23:14,330 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-07 01:23:14,330 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-07 01:23:14,331 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (1/1) ... [2021-12-07 01:23:14,338 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-07 01:23:14,349 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/z3 [2021-12-07 01:23:14,359 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-07 01:23:14,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e23f160f-4bcb-440e-89bc-ce4a3f7bfb8b/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-07 01:23:14,387 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-07 01:23:14,388 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-07 01:23:14,388 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-07 01:23:14,388 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-07 01:23:14,449 INFO L236 CfgBuilder]: Building ICFG [2021-12-07 01:23:14,450 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-07 01:23:15,058 INFO L277 CfgBuilder]: Performing block encoding [2021-12-07 01:23:15,067 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-07 01:23:15,067 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-07 01:23:15,069 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:23:15 BoogieIcfgContainer [2021-12-07 01:23:15,069 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-07 01:23:15,070 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-07 01:23:15,070 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-07 01:23:15,073 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-07 01:23:15,073 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:23:15,073 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 01:23:13" (1/3) ... [2021-12-07 01:23:15,074 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53ab279f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:23:15, skipping insertion in model container [2021-12-07 01:23:15,074 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:23:15,074 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:14" (2/3) ... [2021-12-07 01:23:15,075 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53ab279f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:23:15, skipping insertion in model container [2021-12-07 01:23:15,075 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:23:15,075 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:23:15" (3/3) ... [2021-12-07 01:23:15,076 INFO L388 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-1.c [2021-12-07 01:23:15,106 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-07 01:23:15,106 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-07 01:23:15,107 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-07 01:23:15,107 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-07 01:23:15,107 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-07 01:23:15,107 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-07 01:23:15,107 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-07 01:23:15,107 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-07 01:23:15,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2021-12-07 01:23:15,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:15,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:15,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,168 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-07 01:23:15,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,181 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2021-12-07 01:23:15,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:15,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:15,183 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,183 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,189 INFO L791 eck$LassoCheckResult]: Stem: 414#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 359#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 31#L256true assume !(1 == ~main_in1_req_up~0); 10#L256-2true assume !(1 == ~main_in2_req_up~0); 25#L267-1true assume !(1 == ~main_sum_req_up~0); 303#L278-1true assume !(1 == ~main_diff_req_up~0); 3#L289-1true assume !(1 == ~main_pres_req_up~0); 255#L300-1true assume !(1 == ~main_dbl_req_up~0); 149#L311-1true assume !(1 == ~main_zero_req_up~0); 328#L322-1true assume !(1 == ~main_clk_req_up~0); 194#L333-1true assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 125#L351-1true assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 19#L356-1true assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 119#L361-1true assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 341#L366-1true assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 113#L371-1true assume !(0 == ~main_in1_ev~0); 44#L376-1true assume !(0 == ~main_in2_ev~0); 305#L381-1true assume !(0 == ~main_sum_ev~0); 133#L386-1true assume !(0 == ~main_diff_ev~0); 323#L391-1true assume !(0 == ~main_pres_ev~0); 229#L396-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 81#L401-1true assume !(0 == ~main_zero_ev~0); 87#L406-1true assume !(0 == ~main_clk_ev~0); 354#L411-1true assume !(0 == ~main_clk_pos_edge~0); 338#L416-1true assume !(0 == ~main_clk_neg_edge~0); 394#L421-1true assume !(1 == ~main_clk_pos_edge~0); 291#L426-1true assume !(1 == ~main_clk_pos_edge~0); 106#L431-1true assume !(1 == ~main_clk_pos_edge~0); 234#L436-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 95#L441-1true assume !(1 == ~main_clk_pos_edge~0); 386#L446-1true assume !(1 == ~main_in1_ev~0); 277#L451-1true assume !(1 == ~main_in2_ev~0); 395#L456-1true assume !(1 == ~main_sum_ev~0); 138#L461-1true assume !(1 == ~main_diff_ev~0); 381#L466-1true assume !(1 == ~main_pres_ev~0); 406#L471-1true assume !(1 == ~main_dbl_ev~0); 26#L476-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 195#L481-1true assume !(1 == ~main_clk_ev~0); 92#L486-1true assume !(1 == ~main_clk_pos_edge~0); 28#L491-1true assume !(1 == ~main_clk_neg_edge~0); 250#L742-1true [2021-12-07 01:23:15,190 INFO L793 eck$LassoCheckResult]: Loop: 250#L742-1true assume !false; 376#L503true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 206#L229true assume false; 239#L245true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 256#L509true assume !(1 == ~main_in1_req_up~0); 173#L509-2true assume !(1 == ~main_in2_req_up~0); 339#L520-1true assume !(1 == ~main_sum_req_up~0); 220#L531-1true assume !(1 == ~main_diff_req_up~0); 144#L542-1true assume !(1 == ~main_pres_req_up~0); 393#L553-1true assume !(1 == ~main_dbl_req_up~0); 159#L564-1true assume !(1 == ~main_zero_req_up~0); 245#L575-1true assume !(1 == ~main_clk_req_up~0); 343#L586-1true start_simulation_~kernel_st~0#1 := 3; 369#L605true assume !(0 == ~main_in1_ev~0); 287#L605-2true assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 17#L610-1true assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 193#L615-1true assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 190#L620-1true assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 186#L625-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 270#L630-1true assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 329#L635-1true assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 327#L640-1true assume !(0 == ~main_clk_pos_edge~0); 85#L645-1true assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 112#L650-1true assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 132#L655-1true assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 204#L660-1true assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 240#L665-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 290#L670-1true assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 182#L675-1true assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 237#L680-1true assume !(1 == ~main_in2_ev~0); 312#L685-1true assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 215#L690-1true assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 405#L695-1true assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 275#L700-1true assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 268#L705-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 375#L710-1true assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 178#L715-1true assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 135#L720-1true assume !(1 == ~main_clk_neg_edge~0); 165#L725-1true assume 0 == ~N_generate_st~0; 250#L742-1true [2021-12-07 01:23:15,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2021-12-07 01:23:15,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406784200] [2021-12-07 01:23:15,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406784200] [2021-12-07 01:23:15,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406784200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,356 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:15,358 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644839648] [2021-12-07 01:23:15,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,361 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:15,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,362 INFO L85 PathProgramCache]: Analyzing trace with hash -727719859, now seen corresponding path program 1 times [2021-12-07 01:23:15,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312837098] [2021-12-07 01:23:15,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312837098] [2021-12-07 01:23:15,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312837098] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:15,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743747520] [2021-12-07 01:23:15,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:15,380 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:15,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-07 01:23:15,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-07 01:23:15,406 INFO L87 Difference]: Start difference. First operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:15,435 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2021-12-07 01:23:15,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-07 01:23:15,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2021-12-07 01:23:15,445 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2021-12-07 01:23:15,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2021-12-07 01:23:15,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2021-12-07 01:23:15,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2021-12-07 01:23:15,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2021-12-07 01:23:15,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:15,459 INFO L681 BuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2021-12-07 01:23:15,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2021-12-07 01:23:15,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2021-12-07 01:23:15,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2021-12-07 01:23:15,503 INFO L704 BuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2021-12-07 01:23:15,503 INFO L587 BuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2021-12-07 01:23:15,503 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-07 01:23:15,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2021-12-07 01:23:15,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2021-12-07 01:23:15,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:15,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:15,510 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,510 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,510 INFO L791 eck$LassoCheckResult]: Stem: 1264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 909#L256 assume !(1 == ~main_in1_req_up~0); 866#L256-2 assume !(1 == ~main_in2_req_up~0); 868#L267-1 assume !(1 == ~main_sum_req_up~0); 897#L278-1 assume !(1 == ~main_diff_req_up~0); 849#L289-1 assume !(1 == ~main_pres_req_up~0); 850#L300-1 assume !(1 == ~main_dbl_req_up~0); 957#L311-1 assume !(1 == ~main_zero_req_up~0); 1102#L322-1 assume !(1 == ~main_clk_req_up~0); 1076#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1067#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 886#L356-1 assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 887#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1061#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1055#L371-1 assume !(0 == ~main_in1_ev~0); 937#L376-1 assume !(0 == ~main_in2_ev~0); 938#L381-1 assume !(0 == ~main_sum_ev~0); 1078#L386-1 assume !(0 == ~main_diff_ev~0); 1079#L391-1 assume !(0 == ~main_pres_ev~0); 1186#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1006#L401-1 assume !(0 == ~main_zero_ev~0); 1007#L406-1 assume !(0 == ~main_clk_ev~0); 1016#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1247#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1248#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1233#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1044#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1045#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1025#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1026#L446-1 assume !(1 == ~main_in1_ev~0); 1225#L451-1 assume !(1 == ~main_in2_ev~0); 1226#L456-1 assume !(1 == ~main_sum_ev~0); 1087#L461-1 assume !(1 == ~main_diff_ev~0); 1088#L466-1 assume !(1 == ~main_pres_ev~0); 1261#L471-1 assume !(1 == ~main_dbl_ev~0); 899#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 900#L481-1 assume !(1 == ~main_clk_ev~0); 1023#L486-1 assume !(1 == ~main_clk_pos_edge~0); 904#L491-1 assume !(1 == ~main_clk_neg_edge~0); 905#L742-1 [2021-12-07 01:23:15,510 INFO L793 eck$LassoCheckResult]: Loop: 905#L742-1 assume !false; 1205#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 941#L229 assume !false; 1164#L147 assume !(0 == ~N_generate_st~0); 969#L151 assume !(0 == ~S1_addsub_st~0); 970#L154 assume !(0 == ~S2_presdbl_st~0); 859#L157 assume !(0 == ~S3_zero_st~0); 861#L160 assume !(0 == ~D_print_st~0); 1195#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1196#L509 assume !(1 == ~main_in1_req_up~0); 863#L509-2 assume !(1 == ~main_in2_req_up~0); 1132#L520-1 assume !(1 == ~main_sum_req_up~0); 1178#L531-1 assume !(1 == ~main_diff_req_up~0); 1096#L542-1 assume !(1 == ~main_pres_req_up~0); 870#L553-1 assume !(1 == ~main_dbl_req_up~0); 1105#L564-1 assume !(1 == ~main_zero_req_up~0); 1115#L575-1 assume !(1 == ~main_clk_req_up~0); 1200#L586-1 start_simulation_~kernel_st~0#1 := 3; 1249#L605 assume !(0 == ~main_in1_ev~0); 1232#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 883#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 884#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1155#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1150#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1151#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 1220#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1243#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1014#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1015#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1054#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1077#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1163#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1197#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 1143#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 1144#L680-1 assume !(1 == ~main_in2_ev~0); 1193#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1173#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1174#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1221#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 1218#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 1219#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1139#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 1083#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1084#L725-1 assume 0 == ~N_generate_st~0; 905#L742-1 [2021-12-07 01:23:15,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2021-12-07 01:23:15,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764760332] [2021-12-07 01:23:15,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,511 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764760332] [2021-12-07 01:23:15,563 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764760332] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,563 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:15,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203194241] [2021-12-07 01:23:15,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,564 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:15,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,564 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 1 times [2021-12-07 01:23:15,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338015869] [2021-12-07 01:23:15,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,565 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338015869] [2021-12-07 01:23:15,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338015869] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,598 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:15,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344663847] [2021-12-07 01:23:15,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,598 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:15,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:15,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:15,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:15,599 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:15,693 INFO L93 Difference]: Finished difference Result 760 states and 1352 transitions. [2021-12-07 01:23:15,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:15,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 760 states and 1352 transitions. [2021-12-07 01:23:15,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2021-12-07 01:23:15,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 760 states to 760 states and 1352 transitions. [2021-12-07 01:23:15,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2021-12-07 01:23:15,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2021-12-07 01:23:15,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 760 states and 1352 transitions. [2021-12-07 01:23:15,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:15,713 INFO L681 BuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2021-12-07 01:23:15,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states and 1352 transitions. [2021-12-07 01:23:15,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2021-12-07 01:23:15,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.7789473684210526) internal successors, (1352), 759 states have internal predecessors, (1352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1352 transitions. [2021-12-07 01:23:15,750 INFO L704 BuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2021-12-07 01:23:15,750 INFO L587 BuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2021-12-07 01:23:15,750 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-07 01:23:15,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 1352 transitions. [2021-12-07 01:23:15,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2021-12-07 01:23:15,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:15,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:15,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:15,758 INFO L791 eck$LassoCheckResult]: Stem: 2461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2096#L256 assume !(1 == ~main_in1_req_up~0); 2053#L256-2 assume !(1 == ~main_in2_req_up~0); 2055#L267-1 assume !(1 == ~main_sum_req_up~0); 2084#L278-1 assume !(1 == ~main_diff_req_up~0); 2036#L289-1 assume !(1 == ~main_pres_req_up~0); 2037#L300-1 assume !(1 == ~main_dbl_req_up~0); 2142#L311-1 assume !(1 == ~main_zero_req_up~0); 2290#L322-1 assume !(1 == ~main_clk_req_up~0); 2263#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2254#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2073#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2074#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2248#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2242#L371-1 assume !(0 == ~main_in1_ev~0); 2122#L376-1 assume !(0 == ~main_in2_ev~0); 2123#L381-1 assume !(0 == ~main_sum_ev~0); 2265#L386-1 assume !(0 == ~main_diff_ev~0); 2266#L391-1 assume !(0 == ~main_pres_ev~0); 2377#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2193#L401-1 assume !(0 == ~main_zero_ev~0); 2194#L406-1 assume !(0 == ~main_clk_ev~0); 2203#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2444#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2445#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2428#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2231#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2232#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2211#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2212#L446-1 assume !(1 == ~main_in1_ev~0); 2420#L451-1 assume !(1 == ~main_in2_ev~0); 2421#L456-1 assume !(1 == ~main_sum_ev~0); 2275#L461-1 assume !(1 == ~main_diff_ev~0); 2276#L466-1 assume !(1 == ~main_pres_ev~0); 2457#L471-1 assume !(1 == ~main_dbl_ev~0); 2086#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2087#L481-1 assume !(1 == ~main_clk_ev~0); 2210#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2091#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2092#L742-1 [2021-12-07 01:23:15,758 INFO L793 eck$LassoCheckResult]: Loop: 2092#L742-1 assume !false; 2744#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2739#L229 assume !false; 2737#L147 assume !(0 == ~N_generate_st~0); 2735#L151 assume !(0 == ~S1_addsub_st~0); 2733#L154 assume !(0 == ~S2_presdbl_st~0); 2046#L157 assume !(0 == ~S3_zero_st~0); 2048#L160 assume !(0 == ~D_print_st~0); 2387#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2388#L509 assume !(1 == ~main_in1_req_up~0); 2321#L509-2 assume !(1 == ~main_in2_req_up~0); 2322#L520-1 assume !(1 == ~main_sum_req_up~0); 2369#L531-1 assume !(1 == ~main_diff_req_up~0); 2284#L542-1 assume !(1 == ~main_pres_req_up~0); 2057#L553-1 assume !(1 == ~main_dbl_req_up~0); 2293#L564-1 assume !(1 == ~main_zero_req_up~0); 2304#L575-1 assume !(1 == ~main_clk_req_up~0); 2393#L586-1 start_simulation_~kernel_st~0#1 := 3; 2446#L605 assume !(0 == ~main_in1_ev~0); 2427#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2070#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2071#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2346#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2340#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2341#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 2415#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2440#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2201#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2202#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2241#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2264#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2354#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2389#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 2333#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 2334#L680-1 assume !(1 == ~main_in2_ev~0); 2385#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2364#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2365#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2416#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 2413#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2414#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2329#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 2270#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2271#L725-1 assume 0 == ~N_generate_st~0; 2092#L742-1 [2021-12-07 01:23:15,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,759 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2021-12-07 01:23:15,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868097802] [2021-12-07 01:23:15,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868097802] [2021-12-07 01:23:15,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868097802] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:15,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944970162] [2021-12-07 01:23:15,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,818 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:15,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:15,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 2 times [2021-12-07 01:23:15,819 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:15,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673873911] [2021-12-07 01:23:15,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:15,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:15,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:15,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:15,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:15,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673873911] [2021-12-07 01:23:15,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673873911] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:15,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:15,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:15,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149459831] [2021-12-07 01:23:15,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:15,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:15,854 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:15,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:15,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:15,855 INFO L87 Difference]: Start difference. First operand 760 states and 1352 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:15,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:15,984 INFO L93 Difference]: Finished difference Result 1669 states and 2937 transitions. [2021-12-07 01:23:15,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:15,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2937 transitions. [2021-12-07 01:23:16,000 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2021-12-07 01:23:16,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2937 transitions. [2021-12-07 01:23:16,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2021-12-07 01:23:16,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2021-12-07 01:23:16,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2937 transitions. [2021-12-07 01:23:16,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:16,021 INFO L681 BuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2021-12-07 01:23:16,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2937 transitions. [2021-12-07 01:23:16,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1669. [2021-12-07 01:23:16,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1669 states, 1669 states have (on average 1.7597363690832835) internal successors, (2937), 1668 states have internal predecessors, (2937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:16,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 1669 states and 2937 transitions. [2021-12-07 01:23:16,062 INFO L704 BuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2021-12-07 01:23:16,062 INFO L587 BuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2021-12-07 01:23:16,062 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-07 01:23:16,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1669 states and 2937 transitions. [2021-12-07 01:23:16,069 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2021-12-07 01:23:16,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:16,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:16,071 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,071 INFO L791 eck$LassoCheckResult]: Stem: 4958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4535#L256 assume !(1 == ~main_in1_req_up~0); 4492#L256-2 assume !(1 == ~main_in2_req_up~0); 4494#L267-1 assume !(1 == ~main_sum_req_up~0); 4523#L278-1 assume !(1 == ~main_diff_req_up~0); 4475#L289-1 assume !(1 == ~main_pres_req_up~0); 4476#L300-1 assume !(1 == ~main_dbl_req_up~0); 4745#L311-1 assume !(1 == ~main_zero_req_up~0); 4744#L322-1 assume !(1 == ~main_clk_req_up~0); 4972#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4971#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4512#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4513#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4697#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4691#L371-1 assume !(0 == ~main_in1_ev~0); 4562#L376-1 assume !(0 == ~main_in2_ev~0); 4563#L381-1 assume !(0 == ~main_sum_ev~0); 4966#L386-1 assume !(0 == ~main_diff_ev~0); 4917#L391-1 assume !(0 == ~main_pres_ev~0); 4845#L396-1 assume !(0 == ~main_dbl_ev~0); 4846#L401-1 assume !(0 == ~main_zero_ev~0); 5814#L406-1 assume !(0 == ~main_clk_ev~0); 5813#L411-1 assume !(0 == ~main_clk_pos_edge~0); 5812#L416-1 assume !(0 == ~main_clk_neg_edge~0); 5811#L421-1 assume !(1 == ~main_clk_pos_edge~0); 5810#L426-1 assume !(1 == ~main_clk_pos_edge~0); 5809#L431-1 assume !(1 == ~main_clk_pos_edge~0); 5808#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 5804#L441-1 assume !(1 == ~main_clk_pos_edge~0); 5800#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4889#L451-1 assume !(1 == ~main_in2_ev~0); 4890#L456-1 assume !(1 == ~main_sum_ev~0); 4725#L461-1 assume !(1 == ~main_diff_ev~0); 4726#L466-1 assume !(1 == ~main_pres_ev~0); 4946#L471-1 assume !(1 == ~main_dbl_ev~0); 4525#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4526#L481-1 assume !(1 == ~main_clk_ev~0); 4656#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4530#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4531#L742-1 [2021-12-07 01:23:16,071 INFO L793 eck$LassoCheckResult]: Loop: 4531#L742-1 assume !false; 4868#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4566#L229 assume !false; 4817#L147 assume !(0 == ~N_generate_st~0); 4596#L151 assume !(0 == ~S1_addsub_st~0); 4597#L154 assume !(0 == ~S2_presdbl_st~0); 4485#L157 assume !(0 == ~S3_zero_st~0); 4487#L160 assume !(0 == ~D_print_st~0); 4856#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4857#L509 assume !(1 == ~main_in1_req_up~0); 4777#L509-2 assume !(1 == ~main_in2_req_up~0); 4778#L520-1 assume !(1 == ~main_sum_req_up~0); 5113#L531-1 assume !(1 == ~main_diff_req_up~0); 5111#L542-1 assume !(1 == ~main_pres_req_up~0); 4952#L553-1 assume !(1 == ~main_dbl_req_up~0); 4953#L564-1 assume !(1 == ~main_zero_req_up~0); 5944#L575-1 assume !(1 == ~main_clk_req_up~0); 5942#L586-1 start_simulation_~kernel_st~0#1 := 3; 5941#L605 assume !(0 == ~main_in1_ev~0); 5940#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 5939#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 5938#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 5937#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 4799#L625-1 assume !(0 == ~main_dbl_ev~0); 4800#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 4884#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 4918#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4643#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 4644#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 4690#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 4715#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 4816#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4858#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 4792#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4793#L680-1 assume !(1 == ~main_in2_ev~0); 4854#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 4829#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 4830#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 4885#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 4882#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4883#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 4786#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 4723#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4724#L725-1 assume 0 == ~N_generate_st~0; 4531#L742-1 [2021-12-07 01:23:16,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,072 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2021-12-07 01:23:16,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199013044] [2021-12-07 01:23:16,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,109 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199013044] [2021-12-07 01:23:16,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199013044] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,109 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:16,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102700408] [2021-12-07 01:23:16,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:16,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,111 INFO L85 PathProgramCache]: Analyzing trace with hash -2069491216, now seen corresponding path program 1 times [2021-12-07 01:23:16,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43965016] [2021-12-07 01:23:16,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43965016] [2021-12-07 01:23:16,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [43965016] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,138 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:16,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701993734] [2021-12-07 01:23:16,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,138 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:16,138 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:16,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:16,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:16,139 INFO L87 Difference]: Start difference. First operand 1669 states and 2937 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:16,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:16,280 INFO L93 Difference]: Finished difference Result 1999 states and 3465 transitions. [2021-12-07 01:23:16,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:16,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1999 states and 3465 transitions. [2021-12-07 01:23:16,297 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2021-12-07 01:23:16,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1999 states to 1999 states and 3465 transitions. [2021-12-07 01:23:16,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1999 [2021-12-07 01:23:16,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1999 [2021-12-07 01:23:16,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1999 states and 3465 transitions. [2021-12-07 01:23:16,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:16,318 INFO L681 BuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2021-12-07 01:23:16,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states and 3465 transitions. [2021-12-07 01:23:16,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1999. [2021-12-07 01:23:16,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1999 states, 1999 states have (on average 1.7333666833416708) internal successors, (3465), 1998 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:16,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1999 states to 1999 states and 3465 transitions. [2021-12-07 01:23:16,355 INFO L704 BuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2021-12-07 01:23:16,355 INFO L587 BuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2021-12-07 01:23:16,355 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-07 01:23:16,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1999 states and 3465 transitions. [2021-12-07 01:23:16,363 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2021-12-07 01:23:16,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:16,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:16,364 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,364 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,365 INFO L791 eck$LassoCheckResult]: Stem: 8642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 8618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 8211#L256 assume !(1 == ~main_in1_req_up~0); 8167#L256-2 assume !(1 == ~main_in2_req_up~0); 8169#L267-1 assume !(1 == ~main_sum_req_up~0); 8198#L278-1 assume !(1 == ~main_diff_req_up~0); 8150#L289-1 assume !(1 == ~main_pres_req_up~0); 8151#L300-1 assume !(1 == ~main_dbl_req_up~0); 8258#L311-1 assume !(1 == ~main_zero_req_up~0); 8598#L322-1 assume !(1 == ~main_clk_req_up~0); 8389#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 8378#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 8379#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 8653#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 8606#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 8366#L371-1 assume !(0 == ~main_in1_ev~0); 8238#L376-1 assume !(0 == ~main_in2_ev~0); 8239#L381-1 assume !(0 == ~main_sum_ev~0); 8650#L386-1 assume !(0 == ~main_diff_ev~0); 8595#L391-1 assume !(0 == ~main_pres_ev~0); 8520#L396-1 assume !(0 == ~main_dbl_ev~0); 8312#L401-1 assume !(0 == ~main_zero_ev~0); 8313#L406-1 assume !(0 == ~main_clk_ev~0); 8324#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 8614#L416-1 assume !(0 == ~main_clk_neg_edge~0); 10148#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 10122#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 10121#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 10120#L436-1 assume !(1 == ~main_clk_pos_edge~0); 8333#L441-1 assume !(1 == ~main_clk_pos_edge~0); 8334#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 9017#L451-1 assume !(1 == ~main_in2_ev~0); 10027#L456-1 assume !(1 == ~main_sum_ev~0); 10026#L461-1 assume !(1 == ~main_diff_ev~0); 10025#L466-1 assume !(1 == ~main_pres_ev~0); 10024#L471-1 assume !(1 == ~main_dbl_ev~0); 9006#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 10023#L481-1 assume !(1 == ~main_clk_ev~0); 10022#L486-1 assume !(1 == ~main_clk_pos_edge~0); 10020#L491-1 assume !(1 == ~main_clk_neg_edge~0); 8293#L742-1 [2021-12-07 01:23:16,365 INFO L793 eck$LassoCheckResult]: Loop: 8293#L742-1 assume !false; 10019#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 10015#L229 assume !false; 10014#L147 assume !(0 == ~N_generate_st~0); 10013#L151 assume !(0 == ~S1_addsub_st~0); 10012#L154 assume !(0 == ~S2_presdbl_st~0); 10011#L157 assume !(0 == ~S3_zero_st~0); 10009#L160 assume !(0 == ~D_print_st~0); 10008#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 10007#L509 assume !(1 == ~main_in1_req_up~0); 10005#L509-2 assume !(1 == ~main_in2_req_up~0); 10002#L520-1 assume !(1 == ~main_sum_req_up~0); 9998#L531-1 assume !(1 == ~main_diff_req_up~0); 9994#L542-1 assume !(1 == ~main_pres_req_up~0); 9990#L553-1 assume !(1 == ~main_dbl_req_up~0); 9984#L564-1 assume !(1 == ~main_zero_req_up~0); 9978#L575-1 assume !(1 == ~main_clk_req_up~0); 9975#L586-1 start_simulation_~kernel_st~0#1 := 3; 9973#L605 assume !(0 == ~main_in1_ev~0); 9971#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 9969#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 9967#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 9965#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 9964#L625-1 assume !(0 == ~main_dbl_ev~0); 9962#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 9961#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 9959#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 9958#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 9957#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 9956#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 9954#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 9953#L665-1 assume !(1 == ~main_clk_pos_edge~0); 8532#L670-1 assume !(1 == ~main_clk_pos_edge~0); 8471#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 8472#L680-1 assume !(1 == ~main_in2_ev~0); 8528#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 8505#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 8506#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 8564#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 8560#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 8561#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 8466#L715-1 assume !(1 == ~main_clk_pos_edge~0); 8397#L720-1 assume !(1 == ~main_clk_neg_edge~0); 8398#L725-1 assume 0 == ~N_generate_st~0; 8293#L742-1 [2021-12-07 01:23:16,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,365 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2021-12-07 01:23:16,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086301903] [2021-12-07 01:23:16,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086301903] [2021-12-07 01:23:16,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086301903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:16,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438349863] [2021-12-07 01:23:16,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,400 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:16,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,401 INFO L85 PathProgramCache]: Analyzing trace with hash -403985164, now seen corresponding path program 1 times [2021-12-07 01:23:16,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [98385863] [2021-12-07 01:23:16,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,401 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,421 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [98385863] [2021-12-07 01:23:16,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [98385863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,422 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,422 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:16,422 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830545515] [2021-12-07 01:23:16,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,423 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:16,423 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:16,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:16,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:16,423 INFO L87 Difference]: Start difference. First operand 1999 states and 3465 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:16,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:16,613 INFO L93 Difference]: Finished difference Result 4015 states and 6814 transitions. [2021-12-07 01:23:16,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:16,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4015 states and 6814 transitions. [2021-12-07 01:23:16,645 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2021-12-07 01:23:16,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4015 states to 4015 states and 6814 transitions. [2021-12-07 01:23:16,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4015 [2021-12-07 01:23:16,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4015 [2021-12-07 01:23:16,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4015 states and 6814 transitions. [2021-12-07 01:23:16,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:16,683 INFO L681 BuchiCegarLoop]: Abstraction has 4015 states and 6814 transitions. [2021-12-07 01:23:16,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4015 states and 6814 transitions. [2021-12-07 01:23:16,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4015 to 3985. [2021-12-07 01:23:16,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3985 states, 3985 states have (on average 1.6948557089084064) internal successors, (6754), 3984 states have internal predecessors, (6754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:16,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 6754 transitions. [2021-12-07 01:23:16,768 INFO L704 BuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2021-12-07 01:23:16,768 INFO L587 BuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2021-12-07 01:23:16,768 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-07 01:23:16,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3985 states and 6754 transitions. [2021-12-07 01:23:16,784 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2021-12-07 01:23:16,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:16,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:16,785 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,785 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:16,785 INFO L791 eck$LassoCheckResult]: Stem: 14698#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 14672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 14235#L256 assume !(1 == ~main_in1_req_up~0); 14191#L256-2 assume !(1 == ~main_in2_req_up~0); 14193#L267-1 assume !(1 == ~main_sum_req_up~0); 14222#L278-1 assume !(1 == ~main_diff_req_up~0); 14174#L289-1 assume !(1 == ~main_pres_req_up~0); 14175#L300-1 assume !(1 == ~main_dbl_req_up~0); 14449#L311-1 assume !(1 == ~main_zero_req_up~0); 14446#L322-1 assume !(1 == ~main_clk_req_up~0); 14519#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 14405#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 14406#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 15390#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 14658#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 14391#L371-1 assume !(0 == ~main_in1_ev~0); 14392#L376-1 assume !(0 == ~main_in2_ev~0); 14785#L381-1 assume !(0 == ~main_sum_ev~0); 14786#L386-1 assume !(0 == ~main_diff_ev~0); 14645#L391-1 assume !(0 == ~main_pres_ev~0); 14557#L396-1 assume !(0 == ~main_dbl_ev~0); 14336#L401-1 assume !(0 == ~main_zero_ev~0); 14337#L406-1 assume !(0 == ~main_clk_ev~0); 14346#L411-1 assume !(0 == ~main_clk_pos_edge~0); 14655#L416-1 assume !(0 == ~main_clk_neg_edge~0); 14656#L421-1 assume !(1 == ~main_clk_pos_edge~0); 14623#L426-1 assume !(1 == ~main_clk_pos_edge~0); 14378#L431-1 assume !(1 == ~main_clk_pos_edge~0); 14379#L436-1 assume !(1 == ~main_clk_pos_edge~0); 14357#L441-1 assume !(1 == ~main_clk_pos_edge~0); 14358#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 14688#L451-1 assume !(1 == ~main_in2_ev~0); 15332#L456-1 assume !(1 == ~main_sum_ev~0); 15330#L461-1 assume !(1 == ~main_diff_ev~0); 15291#L466-1 assume !(1 == ~main_pres_ev~0); 15283#L471-1 assume !(1 == ~main_dbl_ev~0); 14224#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 14225#L481-1 assume !(1 == ~main_clk_ev~0); 15093#L486-1 assume !(1 == ~main_clk_pos_edge~0); 15092#L491-1 assume !(1 == ~main_clk_neg_edge~0); 15213#L742-1 [2021-12-07 01:23:16,786 INFO L793 eck$LassoCheckResult]: Loop: 15213#L742-1 assume !false; 15212#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 15208#L229 assume !false; 15206#L147 assume !(0 == ~N_generate_st~0); 15202#L151 assume !(0 == ~S1_addsub_st~0); 15203#L154 assume !(0 == ~S2_presdbl_st~0); 15204#L157 assume !(0 == ~S3_zero_st~0); 15205#L160 assume !(0 == ~D_print_st~0); 15207#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 15416#L509 assume !(1 == ~main_in1_req_up~0); 15414#L509-2 assume !(1 == ~main_in2_req_up~0); 15411#L520-1 assume !(1 == ~main_sum_req_up~0); 15407#L531-1 assume !(1 == ~main_diff_req_up~0); 15397#L542-1 assume !(1 == ~main_pres_req_up~0); 15393#L553-1 assume !(1 == ~main_dbl_req_up~0); 15388#L564-1 assume !(1 == ~main_zero_req_up~0); 15382#L575-1 assume !(1 == ~main_clk_req_up~0); 15378#L586-1 start_simulation_~kernel_st~0#1 := 3; 15376#L605 assume !(0 == ~main_in1_ev~0); 15374#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 15371#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 15369#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 15366#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 15362#L625-1 assume !(0 == ~main_dbl_ev~0); 15356#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 15352#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 15350#L640-1 assume !(0 == ~main_clk_pos_edge~0); 15318#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 15344#L650-1 assume !(1 == ~main_clk_pos_edge~0); 15314#L655-1 assume !(1 == ~main_clk_pos_edge~0); 15312#L660-1 assume !(1 == ~main_clk_pos_edge~0); 15309#L665-1 assume !(1 == ~main_clk_pos_edge~0); 15303#L670-1 assume !(1 == ~main_clk_pos_edge~0); 15301#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 15300#L680-1 assume !(1 == ~main_in2_ev~0); 15298#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 15296#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 15295#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 15289#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 15282#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 15280#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 15278#L715-1 assume !(1 == ~main_clk_pos_edge~0); 15276#L720-1 assume !(1 == ~main_clk_neg_edge~0); 15219#L725-1 assume 0 == ~N_generate_st~0; 15213#L742-1 [2021-12-07 01:23:16,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,786 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2021-12-07 01:23:16,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061050221] [2021-12-07 01:23:16,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061050221] [2021-12-07 01:23:16,810 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061050221] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:16,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858909599] [2021-12-07 01:23:16,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,811 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:16,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:16,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 1 times [2021-12-07 01:23:16,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:16,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099885124] [2021-12-07 01:23:16,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:16,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:16,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:16,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:16,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:16,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099885124] [2021-12-07 01:23:16,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099885124] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:16,833 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:16,833 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:16,833 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524158750] [2021-12-07 01:23:16,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:16,833 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:16,834 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:16,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:16,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:16,834 INFO L87 Difference]: Start difference. First operand 3985 states and 6754 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:17,018 INFO L93 Difference]: Finished difference Result 4445 states and 7522 transitions. [2021-12-07 01:23:17,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:17,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 7522 transitions. [2021-12-07 01:23:17,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2021-12-07 01:23:17,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 7522 transitions. [2021-12-07 01:23:17,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2021-12-07 01:23:17,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2021-12-07 01:23:17,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 7522 transitions. [2021-12-07 01:23:17,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:17,098 INFO L681 BuchiCegarLoop]: Abstraction has 4445 states and 7522 transitions. [2021-12-07 01:23:17,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 7522 transitions. [2021-12-07 01:23:17,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4415. [2021-12-07 01:23:17,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4415 states, 4415 states have (on average 1.6901472253680634) internal successors, (7462), 4414 states have internal predecessors, (7462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4415 states to 4415 states and 7462 transitions. [2021-12-07 01:23:17,169 INFO L704 BuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2021-12-07 01:23:17,169 INFO L587 BuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2021-12-07 01:23:17,169 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-07 01:23:17,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4415 states and 7462 transitions. [2021-12-07 01:23:17,181 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2021-12-07 01:23:17,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:17,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:17,182 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:17,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:17,182 INFO L791 eck$LassoCheckResult]: Stem: 23123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 23090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 22676#L256 assume !(1 == ~main_in1_req_up~0); 22632#L256-2 assume !(1 == ~main_in2_req_up~0); 22634#L267-1 assume !(1 == ~main_sum_req_up~0); 22663#L278-1 assume !(1 == ~main_diff_req_up~0); 22615#L289-1 assume !(1 == ~main_pres_req_up~0); 22616#L300-1 assume !(1 == ~main_dbl_req_up~0); 22723#L311-1 assume !(1 == ~main_zero_req_up~0); 23069#L322-1 assume !(1 == ~main_clk_req_up~0); 23071#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 24690#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 24688#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 24686#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 24684#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 24682#L371-1 assume !(0 == ~main_in1_ev~0); 24680#L376-1 assume !(0 == ~main_in2_ev~0); 24678#L381-1 assume !(0 == ~main_sum_ev~0); 24675#L386-1 assume !(0 == ~main_diff_ev~0); 24673#L391-1 assume !(0 == ~main_pres_ev~0); 24671#L396-1 assume !(0 == ~main_dbl_ev~0); 24669#L401-1 assume !(0 == ~main_zero_ev~0); 24667#L406-1 assume !(0 == ~main_clk_ev~0); 24664#L411-1 assume !(0 == ~main_clk_pos_edge~0); 24662#L416-1 assume !(0 == ~main_clk_neg_edge~0); 24660#L421-1 assume !(1 == ~main_clk_pos_edge~0); 24657#L426-1 assume !(1 == ~main_clk_pos_edge~0); 24655#L431-1 assume !(1 == ~main_clk_pos_edge~0); 24652#L436-1 assume !(1 == ~main_clk_pos_edge~0); 24649#L441-1 assume !(1 == ~main_clk_pos_edge~0); 24646#L446-1 assume !(1 == ~main_in1_ev~0); 24643#L451-1 assume !(1 == ~main_in2_ev~0); 24641#L456-1 assume !(1 == ~main_sum_ev~0); 24569#L461-1 assume !(1 == ~main_diff_ev~0); 24564#L466-1 assume !(1 == ~main_pres_ev~0); 24555#L471-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 24556#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 25389#L481-1 assume !(1 == ~main_clk_ev~0); 25387#L486-1 assume !(1 == ~main_clk_pos_edge~0); 25373#L491-1 assume !(1 == ~main_clk_neg_edge~0); 25369#L742-1 [2021-12-07 01:23:17,182 INFO L793 eck$LassoCheckResult]: Loop: 25369#L742-1 assume !false; 25368#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 25364#L229 assume !false; 25362#L147 assume !(0 == ~N_generate_st~0); 25358#L151 assume !(0 == ~S1_addsub_st~0); 25359#L154 assume !(0 == ~S2_presdbl_st~0); 25360#L157 assume !(0 == ~S3_zero_st~0); 25361#L160 assume !(0 == ~D_print_st~0); 25363#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 25459#L509 assume !(1 == ~main_in1_req_up~0); 25457#L509-2 assume !(1 == ~main_in2_req_up~0); 25454#L520-1 assume !(1 == ~main_sum_req_up~0); 25450#L531-1 assume !(1 == ~main_diff_req_up~0); 25448#L542-1 assume !(1 == ~main_pres_req_up~0); 25444#L553-1 assume !(1 == ~main_dbl_req_up~0); 25440#L564-1 assume !(1 == ~main_zero_req_up~0); 25436#L575-1 assume !(1 == ~main_clk_req_up~0); 25433#L586-1 start_simulation_~kernel_st~0#1 := 3; 25431#L605 assume !(0 == ~main_in1_ev~0); 25429#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 25427#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 25425#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 25423#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 25421#L625-1 assume !(0 == ~main_dbl_ev~0); 25418#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 25416#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 25414#L640-1 assume !(0 == ~main_clk_pos_edge~0); 25412#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 25410#L650-1 assume !(1 == ~main_clk_pos_edge~0); 25408#L655-1 assume !(1 == ~main_clk_pos_edge~0); 25406#L660-1 assume !(1 == ~main_clk_pos_edge~0); 25404#L665-1 assume !(1 == ~main_clk_pos_edge~0); 25402#L670-1 assume !(1 == ~main_clk_pos_edge~0); 25400#L675-1 assume !(1 == ~main_in1_ev~0); 25398#L680-1 assume !(1 == ~main_in2_ev~0); 25396#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 25394#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 25392#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 25390#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 24274#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 25388#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 25386#L715-1 assume !(1 == ~main_clk_pos_edge~0); 25385#L720-1 assume !(1 == ~main_clk_neg_edge~0); 25376#L725-1 assume 0 == ~N_generate_st~0; 25369#L742-1 [2021-12-07 01:23:17,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:17,183 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2021-12-07 01:23:17,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:17,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534622519] [2021-12-07 01:23:17,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:17,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:17,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:17,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:17,205 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:17,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534622519] [2021-12-07 01:23:17,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534622519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:17,205 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:17,205 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:17,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237178070] [2021-12-07 01:23:17,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:17,206 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:17,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:17,206 INFO L85 PathProgramCache]: Analyzing trace with hash -714147278, now seen corresponding path program 1 times [2021-12-07 01:23:17,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:17,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891761055] [2021-12-07 01:23:17,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:17,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:17,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:17,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:17,219 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:17,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891761055] [2021-12-07 01:23:17,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1891761055] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:17,220 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:17,220 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:17,220 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794875986] [2021-12-07 01:23:17,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:17,220 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:17,220 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:17,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:17,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:17,221 INFO L87 Difference]: Start difference. First operand 4415 states and 7462 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:17,374 INFO L93 Difference]: Finished difference Result 5574 states and 9318 transitions. [2021-12-07 01:23:17,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:17,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5574 states and 9318 transitions. [2021-12-07 01:23:17,413 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5240 [2021-12-07 01:23:17,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5574 states to 5574 states and 9318 transitions. [2021-12-07 01:23:17,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5574 [2021-12-07 01:23:17,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5574 [2021-12-07 01:23:17,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5574 states and 9318 transitions. [2021-12-07 01:23:17,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:17,455 INFO L681 BuchiCegarLoop]: Abstraction has 5574 states and 9318 transitions. [2021-12-07 01:23:17,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5574 states and 9318 transitions. [2021-12-07 01:23:17,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5574 to 5130. [2021-12-07 01:23:17,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5130 states, 5130 states have (on average 1.6754385964912282) internal successors, (8595), 5129 states have internal predecessors, (8595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 8595 transitions. [2021-12-07 01:23:17,527 INFO L704 BuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2021-12-07 01:23:17,527 INFO L587 BuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2021-12-07 01:23:17,527 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-07 01:23:17,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5130 states and 8595 transitions. [2021-12-07 01:23:17,539 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4812 [2021-12-07 01:23:17,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:17,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:17,540 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:17,540 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:17,540 INFO L791 eck$LassoCheckResult]: Stem: 33094#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 33071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32676#L256 assume !(1 == ~main_in1_req_up~0); 32632#L256-2 assume !(1 == ~main_in2_req_up~0); 32634#L267-1 assume !(1 == ~main_sum_req_up~0); 32663#L278-1 assume !(1 == ~main_diff_req_up~0); 32615#L289-1 assume !(1 == ~main_pres_req_up~0); 32616#L300-1 assume !(1 == ~main_dbl_req_up~0); 32724#L311-1 assume !(1 == ~main_zero_req_up~0); 33048#L322-1 assume !(1 == ~main_clk_req_up~0); 33050#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 36466#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 36465#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 36464#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 36463#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 36462#L371-1 assume !(0 == ~main_in1_ev~0); 36461#L376-1 assume !(0 == ~main_in2_ev~0); 36460#L381-1 assume !(0 == ~main_sum_ev~0); 36459#L386-1 assume !(0 == ~main_diff_ev~0); 36458#L391-1 assume !(0 == ~main_pres_ev~0); 36397#L396-1 assume !(0 == ~main_dbl_ev~0); 35475#L401-1 assume !(0 == ~main_zero_ev~0); 35472#L406-1 assume !(0 == ~main_clk_ev~0); 35470#L411-1 assume !(0 == ~main_clk_pos_edge~0); 35468#L416-1 assume !(0 == ~main_clk_neg_edge~0); 35467#L421-1 assume !(1 == ~main_clk_pos_edge~0); 35465#L426-1 assume !(1 == ~main_clk_pos_edge~0); 35461#L431-1 assume !(1 == ~main_clk_pos_edge~0); 35457#L436-1 assume !(1 == ~main_clk_pos_edge~0); 35453#L441-1 assume !(1 == ~main_clk_pos_edge~0); 35452#L446-1 assume !(1 == ~main_in1_ev~0); 35451#L451-1 assume !(1 == ~main_in2_ev~0); 35450#L456-1 assume !(1 == ~main_sum_ev~0); 35449#L461-1 assume !(1 == ~main_diff_ev~0); 35448#L466-1 assume !(1 == ~main_pres_ev~0); 35447#L471-1 assume !(1 == ~main_dbl_ev~0); 35446#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35445#L481-1 assume !(1 == ~main_clk_ev~0); 35444#L486-1 assume !(1 == ~main_clk_pos_edge~0); 35443#L491-1 assume !(1 == ~main_clk_neg_edge~0); 35390#L742-1 [2021-12-07 01:23:17,540 INFO L793 eck$LassoCheckResult]: Loop: 35390#L742-1 assume !false; 35442#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 35438#L229 assume !false; 35437#L147 assume !(0 == ~N_generate_st~0); 35436#L151 assume !(0 == ~S1_addsub_st~0); 35435#L154 assume !(0 == ~S2_presdbl_st~0); 35434#L157 assume !(0 == ~S3_zero_st~0); 35432#L160 assume !(0 == ~D_print_st~0); 35431#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 35430#L509 assume !(1 == ~main_in1_req_up~0); 35429#L509-2 assume !(1 == ~main_in2_req_up~0); 35428#L520-1 assume !(1 == ~main_sum_req_up~0); 35425#L531-1 assume !(1 == ~main_diff_req_up~0); 35424#L542-1 assume !(1 == ~main_pres_req_up~0); 35423#L553-1 assume !(1 == ~main_dbl_req_up~0); 35422#L564-1 assume !(1 == ~main_zero_req_up~0); 35421#L575-1 assume !(1 == ~main_clk_req_up~0); 35420#L586-1 start_simulation_~kernel_st~0#1 := 3; 35419#L605 assume !(0 == ~main_in1_ev~0); 35418#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 35417#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 35416#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 35415#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 35414#L625-1 assume !(0 == ~main_dbl_ev~0); 35413#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 35412#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 35411#L640-1 assume !(0 == ~main_clk_pos_edge~0); 35410#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 35409#L650-1 assume !(1 == ~main_clk_pos_edge~0); 35408#L655-1 assume !(1 == ~main_clk_pos_edge~0); 35407#L660-1 assume !(1 == ~main_clk_pos_edge~0); 35406#L665-1 assume !(1 == ~main_clk_pos_edge~0); 35405#L670-1 assume !(1 == ~main_clk_pos_edge~0); 35404#L675-1 assume !(1 == ~main_in1_ev~0); 35403#L680-1 assume !(1 == ~main_in2_ev~0); 35402#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 35401#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 35400#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 35399#L700-1 assume !(1 == ~main_dbl_ev~0); 35398#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35397#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 35396#L715-1 assume !(1 == ~main_clk_pos_edge~0); 35395#L720-1 assume !(1 == ~main_clk_neg_edge~0); 35394#L725-1 assume 0 == ~N_generate_st~0; 35390#L742-1 [2021-12-07 01:23:17,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:17,540 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2021-12-07 01:23:17,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:17,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062586462] [2021-12-07 01:23:17,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:17,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:17,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:17,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:17,564 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:17,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062586462] [2021-12-07 01:23:17,565 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2062586462] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:17,565 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:17,565 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:17,565 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287439919] [2021-12-07 01:23:17,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:17,565 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:17,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:17,566 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 1 times [2021-12-07 01:23:17,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:17,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775735404] [2021-12-07 01:23:17,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:17,566 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:17,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:17,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:17,582 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:17,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775735404] [2021-12-07 01:23:17,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775735404] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:17,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:17,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:17,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719704135] [2021-12-07 01:23:17,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:17,583 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:17,584 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:17,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:17,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:17,584 INFO L87 Difference]: Start difference. First operand 5130 states and 8595 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:17,784 INFO L93 Difference]: Finished difference Result 9446 states and 15503 transitions. [2021-12-07 01:23:17,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:17,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9446 states and 15503 transitions. [2021-12-07 01:23:17,817 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8840 [2021-12-07 01:23:17,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9446 states to 9446 states and 15503 transitions. [2021-12-07 01:23:17,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9446 [2021-12-07 01:23:17,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9446 [2021-12-07 01:23:17,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9446 states and 15503 transitions. [2021-12-07 01:23:17,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:17,868 INFO L681 BuchiCegarLoop]: Abstraction has 9446 states and 15503 transitions. [2021-12-07 01:23:17,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9446 states and 15503 transitions. [2021-12-07 01:23:17,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9446 to 6978. [2021-12-07 01:23:17,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6978 states, 6978 states have (on average 1.65262252794497) internal successors, (11532), 6977 states have internal predecessors, (11532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:17,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6978 states to 6978 states and 11532 transitions. [2021-12-07 01:23:17,989 INFO L704 BuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2021-12-07 01:23:17,989 INFO L587 BuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2021-12-07 01:23:17,989 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-07 01:23:17,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6978 states and 11532 transitions. [2021-12-07 01:23:18,006 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6492 [2021-12-07 01:23:18,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:18,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:18,007 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:18,007 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:18,007 INFO L791 eck$LassoCheckResult]: Stem: 47732#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 47702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 47263#L256 assume !(1 == ~main_in1_req_up~0); 47219#L256-2 assume !(1 == ~main_in2_req_up~0); 47221#L267-1 assume !(1 == ~main_sum_req_up~0); 47250#L278-1 assume !(1 == ~main_diff_req_up~0); 47202#L289-1 assume !(1 == ~main_pres_req_up~0); 47203#L300-1 assume !(1 == ~main_dbl_req_up~0); 47310#L311-1 assume !(1 == ~main_zero_req_up~0); 47678#L322-1 assume !(1 == ~main_clk_req_up~0); 47447#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 47435#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 47239#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 47240#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 47428#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 47962#L371-1 assume !(0 == ~main_in1_ev~0); 47290#L376-1 assume !(0 == ~main_in2_ev~0); 47291#L381-1 assume !(0 == ~main_sum_ev~0); 47960#L386-1 assume !(0 == ~main_diff_ev~0); 47674#L391-1 assume !(0 == ~main_pres_ev~0); 47587#L396-1 assume !(0 == ~main_dbl_ev~0); 47588#L401-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 50722#L406-1 assume !(0 == ~main_clk_ev~0); 50721#L411-1 assume !(0 == ~main_clk_pos_edge~0); 50720#L416-1 assume !(0 == ~main_clk_neg_edge~0); 50719#L421-1 assume !(1 == ~main_clk_pos_edge~0); 50718#L426-1 assume !(1 == ~main_clk_pos_edge~0); 50717#L431-1 assume !(1 == ~main_clk_pos_edge~0); 50716#L436-1 assume !(1 == ~main_clk_pos_edge~0); 50715#L441-1 assume !(1 == ~main_clk_pos_edge~0); 50714#L446-1 assume !(1 == ~main_in1_ev~0); 50713#L451-1 assume !(1 == ~main_in2_ev~0); 50712#L456-1 assume !(1 == ~main_sum_ev~0); 50711#L461-1 assume !(1 == ~main_diff_ev~0); 50710#L466-1 assume !(1 == ~main_pres_ev~0); 50709#L471-1 assume !(1 == ~main_dbl_ev~0); 50707#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 50686#L481-1 assume !(1 == ~main_clk_ev~0); 50679#L486-1 assume !(1 == ~main_clk_pos_edge~0); 50671#L491-1 assume !(1 == ~main_clk_neg_edge~0); 50476#L742-1 [2021-12-07 01:23:18,007 INFO L793 eck$LassoCheckResult]: Loop: 50476#L742-1 assume !false; 50656#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 50651#L229 assume !false; 50649#L147 assume !(0 == ~N_generate_st~0); 50647#L151 assume !(0 == ~S1_addsub_st~0); 50645#L154 assume !(0 == ~S2_presdbl_st~0); 50641#L157 assume !(0 == ~S3_zero_st~0); 50637#L160 assume !(0 == ~D_print_st~0); 50635#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 50633#L509 assume !(1 == ~main_in1_req_up~0); 50628#L509-2 assume !(1 == ~main_in2_req_up~0); 50621#L520-1 assume !(1 == ~main_sum_req_up~0); 50612#L531-1 assume !(1 == ~main_diff_req_up~0); 50604#L542-1 assume !(1 == ~main_pres_req_up~0); 50595#L553-1 assume !(1 == ~main_dbl_req_up~0); 50587#L564-1 assume !(1 == ~main_zero_req_up~0); 50579#L575-1 assume !(1 == ~main_clk_req_up~0); 50574#L586-1 start_simulation_~kernel_st~0#1 := 3; 50570#L605 assume !(0 == ~main_in1_ev~0); 50566#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 50562#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 50558#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 50554#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 50550#L625-1 assume !(0 == ~main_dbl_ev~0); 50529#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 50528#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 50527#L640-1 assume !(0 == ~main_clk_pos_edge~0); 50526#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 50525#L650-1 assume !(1 == ~main_clk_pos_edge~0); 50524#L655-1 assume !(1 == ~main_clk_pos_edge~0); 50523#L660-1 assume !(1 == ~main_clk_pos_edge~0); 50522#L665-1 assume !(1 == ~main_clk_pos_edge~0); 50521#L670-1 assume !(1 == ~main_clk_pos_edge~0); 50520#L675-1 assume !(1 == ~main_in1_ev~0); 50519#L680-1 assume !(1 == ~main_in2_ev~0); 50518#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 50517#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 50516#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 50515#L700-1 assume !(1 == ~main_dbl_ev~0); 50513#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 50511#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 50509#L715-1 assume !(1 == ~main_clk_pos_edge~0); 50507#L720-1 assume !(1 == ~main_clk_neg_edge~0); 50503#L725-1 assume 0 == ~N_generate_st~0; 50476#L742-1 [2021-12-07 01:23:18,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:18,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2021-12-07 01:23:18,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:18,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315163815] [2021-12-07 01:23:18,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:18,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:18,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:18,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:18,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:18,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315163815] [2021-12-07 01:23:18,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315163815] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:18,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:18,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:18,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283738807] [2021-12-07 01:23:18,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:18,028 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:18,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:18,029 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 2 times [2021-12-07 01:23:18,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:18,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618886231] [2021-12-07 01:23:18,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:18,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:18,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:18,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:18,045 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:18,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618886231] [2021-12-07 01:23:18,045 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618886231] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:18,045 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:18,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:18,046 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984472943] [2021-12-07 01:23:18,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:18,046 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:18,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:18,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:18,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:18,047 INFO L87 Difference]: Start difference. First operand 6978 states and 11532 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:18,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:18,174 INFO L93 Difference]: Finished difference Result 12839 states and 21043 transitions. [2021-12-07 01:23:18,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:18,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12839 states and 21043 transitions. [2021-12-07 01:23:18,221 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2021-12-07 01:23:18,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12839 states to 12839 states and 21043 transitions. [2021-12-07 01:23:18,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12839 [2021-12-07 01:23:18,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12839 [2021-12-07 01:23:18,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12839 states and 21043 transitions. [2021-12-07 01:23:18,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:18,275 INFO L681 BuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2021-12-07 01:23:18,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12839 states and 21043 transitions. [2021-12-07 01:23:18,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12839 to 12839. [2021-12-07 01:23:18,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12839 states, 12839 states have (on average 1.6389905755899992) internal successors, (21043), 12838 states have internal predecessors, (21043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:18,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12839 states to 12839 states and 21043 transitions. [2021-12-07 01:23:18,441 INFO L704 BuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2021-12-07 01:23:18,441 INFO L587 BuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2021-12-07 01:23:18,441 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-07 01:23:18,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12839 states and 21043 transitions. [2021-12-07 01:23:18,461 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2021-12-07 01:23:18,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:18,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:18,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:18,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:18,463 INFO L791 eck$LassoCheckResult]: Stem: 67576#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 67547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 67091#L256 assume !(1 == ~main_in1_req_up~0); 67047#L256-2 assume !(1 == ~main_in2_req_up~0); 67049#L267-1 assume !(1 == ~main_sum_req_up~0); 67078#L278-1 assume !(1 == ~main_diff_req_up~0); 67029#L289-1 assume !(1 == ~main_pres_req_up~0); 67030#L300-1 assume !(1 == ~main_dbl_req_up~0); 67138#L311-1 assume !(1 == ~main_zero_req_up~0); 67522#L322-1 assume !(1 == ~main_clk_req_up~0); 67524#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 70263#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 70257#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 70256#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 70255#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 70254#L371-1 assume !(0 == ~main_in1_ev~0); 70253#L376-1 assume !(0 == ~main_in2_ev~0); 70252#L381-1 assume !(0 == ~main_sum_ev~0); 70251#L386-1 assume !(0 == ~main_diff_ev~0); 70250#L391-1 assume !(0 == ~main_pres_ev~0); 70249#L396-1 assume !(0 == ~main_dbl_ev~0); 70248#L401-1 assume !(0 == ~main_zero_ev~0); 70247#L406-1 assume !(0 == ~main_clk_ev~0); 70246#L411-1 assume !(0 == ~main_clk_pos_edge~0); 70243#L416-1 assume !(0 == ~main_clk_neg_edge~0); 70240#L421-1 assume !(1 == ~main_clk_pos_edge~0); 70238#L426-1 assume !(1 == ~main_clk_pos_edge~0); 70236#L431-1 assume !(1 == ~main_clk_pos_edge~0); 70234#L436-1 assume !(1 == ~main_clk_pos_edge~0); 70232#L441-1 assume !(1 == ~main_clk_pos_edge~0); 70230#L446-1 assume !(1 == ~main_in1_ev~0); 70228#L451-1 assume !(1 == ~main_in2_ev~0); 70226#L456-1 assume !(1 == ~main_sum_ev~0); 70224#L461-1 assume !(1 == ~main_diff_ev~0); 70222#L466-1 assume !(1 == ~main_pres_ev~0); 70220#L471-1 assume !(1 == ~main_dbl_ev~0); 70217#L476-1 assume !(1 == ~main_zero_ev~0); 70215#L481-1 assume !(1 == ~main_clk_ev~0); 70212#L486-1 assume !(1 == ~main_clk_pos_edge~0); 70170#L491-1 assume !(1 == ~main_clk_neg_edge~0); 70166#L742-1 [2021-12-07 01:23:18,463 INFO L793 eck$LassoCheckResult]: Loop: 70166#L742-1 assume !false; 70165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 70161#L229 assume !false; 70159#L147 assume !(0 == ~N_generate_st~0); 70155#L151 assume !(0 == ~S1_addsub_st~0); 70156#L154 assume !(0 == ~S2_presdbl_st~0); 70157#L157 assume !(0 == ~S3_zero_st~0); 70158#L160 assume !(0 == ~D_print_st~0); 70160#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 70541#L509 assume !(1 == ~main_in1_req_up~0); 70538#L509-2 assume !(1 == ~main_in2_req_up~0); 70534#L520-1 assume !(1 == ~main_sum_req_up~0); 70522#L531-1 assume !(1 == ~main_diff_req_up~0); 70510#L542-1 assume !(1 == ~main_pres_req_up~0); 70506#L553-1 assume !(1 == ~main_dbl_req_up~0); 70502#L564-1 assume !(1 == ~main_zero_req_up~0); 70498#L575-1 assume !(1 == ~main_clk_req_up~0); 70494#L586-1 start_simulation_~kernel_st~0#1 := 3; 70493#L605 assume !(0 == ~main_in1_ev~0); 70491#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 70489#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 70487#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 70485#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 70483#L625-1 assume !(0 == ~main_dbl_ev~0); 70481#L630-1 assume !(0 == ~main_zero_ev~0); 70375#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 70339#L640-1 assume !(0 == ~main_clk_pos_edge~0); 70338#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 70337#L650-1 assume !(1 == ~main_clk_pos_edge~0); 70336#L655-1 assume !(1 == ~main_clk_pos_edge~0); 70335#L660-1 assume !(1 == ~main_clk_pos_edge~0); 70334#L665-1 assume !(1 == ~main_clk_pos_edge~0); 70333#L670-1 assume !(1 == ~main_clk_pos_edge~0); 70332#L675-1 assume !(1 == ~main_in1_ev~0); 70331#L680-1 assume !(1 == ~main_in2_ev~0); 70330#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 70329#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 70328#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 70327#L700-1 assume !(1 == ~main_dbl_ev~0); 70326#L705-1 assume !(1 == ~main_zero_ev~0); 70324#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 70320#L715-1 assume !(1 == ~main_clk_pos_edge~0); 70316#L720-1 assume !(1 == ~main_clk_neg_edge~0); 70173#L725-1 assume 0 == ~N_generate_st~0; 70166#L742-1 [2021-12-07 01:23:18,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:18,463 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2021-12-07 01:23:18,463 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:18,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26953774] [2021-12-07 01:23:18,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:18,464 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:18,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:18,473 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:18,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:18,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:18,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:18,509 INFO L85 PathProgramCache]: Analyzing trace with hash -1472690384, now seen corresponding path program 1 times [2021-12-07 01:23:18,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:18,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164519063] [2021-12-07 01:23:18,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:18,509 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:18,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:18,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:18,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:18,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164519063] [2021-12-07 01:23:18,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164519063] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:18,524 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:18,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:18,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987811303] [2021-12-07 01:23:18,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:18,524 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:18,524 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:18,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:18,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:18,526 INFO L87 Difference]: Start difference. First operand 12839 states and 21043 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:18,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:18,608 INFO L93 Difference]: Finished difference Result 18429 states and 29722 transitions. [2021-12-07 01:23:18,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:18,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18429 states and 29722 transitions. [2021-12-07 01:23:18,693 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2021-12-07 01:23:18,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18429 states to 18429 states and 29722 transitions. [2021-12-07 01:23:18,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18429 [2021-12-07 01:23:18,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18429 [2021-12-07 01:23:18,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18429 states and 29722 transitions. [2021-12-07 01:23:18,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:18,754 INFO L681 BuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2021-12-07 01:23:18,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18429 states and 29722 transitions. [2021-12-07 01:23:18,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18429 to 18429. [2021-12-07 01:23:18,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18429 states, 18429 states have (on average 1.6127841988170817) internal successors, (29722), 18428 states have internal predecessors, (29722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:18,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18429 states to 18429 states and 29722 transitions. [2021-12-07 01:23:18,990 INFO L704 BuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2021-12-07 01:23:18,990 INFO L587 BuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2021-12-07 01:23:18,990 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-07 01:23:18,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18429 states and 29722 transitions. [2021-12-07 01:23:19,024 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2021-12-07 01:23:19,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:19,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:19,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:19,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:19,025 INFO L791 eck$LassoCheckResult]: Stem: 98859#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 98826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 98367#L256 assume !(1 == ~main_in1_req_up~0); 98321#L256-2 assume !(1 == ~main_in2_req_up~0); 98323#L267-1 assume !(1 == ~main_sum_req_up~0); 98353#L278-1 assume !(1 == ~main_diff_req_up~0); 98303#L289-1 assume !(1 == ~main_pres_req_up~0); 98304#L300-1 assume !(1 == ~main_dbl_req_up~0); 98415#L311-1 assume !(1 == ~main_zero_req_up~0); 98794#L322-1 assume !(1 == ~main_clk_req_up~0); 98557#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 99445#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 98342#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 98343#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 98538#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 99442#L371-1 assume !(0 == ~main_in1_ev~0); 98394#L376-1 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 98395#L381-1 assume !(0 == ~main_sum_ev~0); 98560#L386-1 assume !(0 == ~main_diff_ev~0); 98561#L391-1 assume !(0 == ~main_pres_ev~0); 98711#L396-1 assume !(0 == ~main_dbl_ev~0); 98472#L401-1 assume !(0 == ~main_zero_ev~0); 98473#L406-1 assume !(0 == ~main_clk_ev~0); 107850#L411-1 assume !(0 == ~main_clk_pos_edge~0); 107848#L416-1 assume !(0 == ~main_clk_neg_edge~0); 107844#L421-1 assume !(1 == ~main_clk_pos_edge~0); 107840#L426-1 assume !(1 == ~main_clk_pos_edge~0); 107837#L431-1 assume !(1 == ~main_clk_pos_edge~0); 107833#L436-1 assume !(1 == ~main_clk_pos_edge~0); 107796#L441-1 assume !(1 == ~main_clk_pos_edge~0); 107215#L446-1 assume !(1 == ~main_in1_ev~0); 101140#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 101132#L456-1 assume !(1 == ~main_sum_ev~0); 101032#L461-1 assume !(1 == ~main_diff_ev~0); 101029#L466-1 assume !(1 == ~main_pres_ev~0); 101027#L471-1 assume !(1 == ~main_dbl_ev~0); 101025#L476-1 assume !(1 == ~main_zero_ev~0); 101017#L481-1 assume !(1 == ~main_clk_ev~0); 100729#L486-1 assume !(1 == ~main_clk_pos_edge~0); 100724#L491-1 assume !(1 == ~main_clk_neg_edge~0); 100439#L742-1 [2021-12-07 01:23:19,025 INFO L793 eck$LassoCheckResult]: Loop: 100439#L742-1 assume !false; 102441#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 102437#L229 assume !false; 102435#L147 assume !(0 == ~N_generate_st~0); 100706#L151 assume !(0 == ~S1_addsub_st~0); 100705#L154 assume !(0 == ~S2_presdbl_st~0); 100704#L157 assume !(0 == ~S3_zero_st~0); 100702#L160 assume !(0 == ~D_print_st~0); 100700#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 100697#L509 assume !(1 == ~main_in1_req_up~0); 100693#L509-2 assume !(1 == ~main_in2_req_up~0); 100688#L520-1 assume !(1 == ~main_sum_req_up~0); 100679#L531-1 assume !(1 == ~main_diff_req_up~0); 100675#L542-1 assume !(1 == ~main_pres_req_up~0); 100674#L553-1 assume !(1 == ~main_dbl_req_up~0); 102207#L564-1 assume !(1 == ~main_zero_req_up~0); 100506#L575-1 assume !(1 == ~main_clk_req_up~0); 100507#L586-1 start_simulation_~kernel_st~0#1 := 3; 100817#L605 assume !(0 == ~main_in1_ev~0); 100814#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 100812#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 100811#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 100810#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 100809#L625-1 assume !(0 == ~main_dbl_ev~0); 100804#L630-1 assume !(0 == ~main_zero_ev~0); 100802#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 100800#L640-1 assume !(0 == ~main_clk_pos_edge~0); 100798#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 100796#L650-1 assume !(1 == ~main_clk_pos_edge~0); 100794#L655-1 assume !(1 == ~main_clk_pos_edge~0); 100792#L660-1 assume !(1 == ~main_clk_pos_edge~0); 100790#L665-1 assume !(1 == ~main_clk_pos_edge~0); 100787#L670-1 assume !(1 == ~main_clk_pos_edge~0); 100786#L675-1 assume !(1 == ~main_in1_ev~0); 100785#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 100783#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 100780#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 100778#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 100776#L700-1 assume !(1 == ~main_dbl_ev~0); 100773#L705-1 assume !(1 == ~main_zero_ev~0); 100770#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 100449#L715-1 assume !(1 == ~main_clk_pos_edge~0); 100446#L720-1 assume !(1 == ~main_clk_neg_edge~0); 100445#L725-1 assume 0 == ~N_generate_st~0; 100439#L742-1 [2021-12-07 01:23:19,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:19,025 INFO L85 PathProgramCache]: Analyzing trace with hash -323147977, now seen corresponding path program 1 times [2021-12-07 01:23:19,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:19,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842734513] [2021-12-07 01:23:19,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:19,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:19,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:19,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:19,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:19,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842734513] [2021-12-07 01:23:19,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842734513] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:19,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:19,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:19,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431640041] [2021-12-07 01:23:19,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:19,044 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:19,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:19,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1079663374, now seen corresponding path program 1 times [2021-12-07 01:23:19,045 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:19,045 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956887886] [2021-12-07 01:23:19,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:19,045 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:19,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:19,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:19,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:19,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956887886] [2021-12-07 01:23:19,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956887886] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:19,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:19,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:19,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642654173] [2021-12-07 01:23:19,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:19,057 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:19,057 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:19,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:19,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:19,058 INFO L87 Difference]: Start difference. First operand 18429 states and 29722 transitions. cyclomatic complexity: 11325 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:19,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:19,245 INFO L93 Difference]: Finished difference Result 33519 states and 53550 transitions. [2021-12-07 01:23:19,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:19,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33519 states and 53550 transitions. [2021-12-07 01:23:19,339 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2021-12-07 01:23:19,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33519 states to 33519 states and 53550 transitions. [2021-12-07 01:23:19,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33519 [2021-12-07 01:23:19,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33519 [2021-12-07 01:23:19,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33519 states and 53550 transitions. [2021-12-07 01:23:19,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:19,465 INFO L681 BuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2021-12-07 01:23:19,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33519 states and 53550 transitions. [2021-12-07 01:23:19,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33519 to 33519. [2021-12-07 01:23:19,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.597601360422447) internal successors, (53550), 33518 states have internal predecessors, (53550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:19,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 53550 transitions. [2021-12-07 01:23:19,869 INFO L704 BuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2021-12-07 01:23:19,869 INFO L587 BuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2021-12-07 01:23:19,869 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-07 01:23:19,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 53550 transitions. [2021-12-07 01:23:19,929 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2021-12-07 01:23:19,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:19,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:19,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:19,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:19,930 INFO L791 eck$LassoCheckResult]: Stem: 150847#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 150803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 150324#L256 assume !(1 == ~main_in1_req_up~0); 150280#L256-2 assume !(1 == ~main_in2_req_up~0); 150282#L267-1 assume !(1 == ~main_sum_req_up~0); 150311#L278-1 assume !(1 == ~main_diff_req_up~0); 150261#L289-1 assume !(1 == ~main_pres_req_up~0); 150262#L300-1 assume !(1 == ~main_dbl_req_up~0); 150376#L311-1 assume !(1 == ~main_zero_req_up~0); 150771#L322-1 assume !(1 == ~main_clk_req_up~0); 150517#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 154238#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 155631#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 155630#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 155629#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 155628#L371-1 assume !(0 == ~main_in1_ev~0); 155627#L376-1 assume !(0 == ~main_in2_ev~0); 155626#L381-1 assume !(0 == ~main_sum_ev~0); 155625#L386-1 assume !(0 == ~main_diff_ev~0); 155624#L391-1 assume !(0 == ~main_pres_ev~0); 155623#L396-1 assume !(0 == ~main_dbl_ev~0); 155622#L401-1 assume !(0 == ~main_zero_ev~0); 155621#L406-1 assume !(0 == ~main_clk_ev~0); 155620#L411-1 assume !(0 == ~main_clk_pos_edge~0); 155619#L416-1 assume !(0 == ~main_clk_neg_edge~0); 155618#L421-1 assume !(1 == ~main_clk_pos_edge~0); 155617#L426-1 assume !(1 == ~main_clk_pos_edge~0); 155616#L431-1 assume !(1 == ~main_clk_pos_edge~0); 155615#L436-1 assume !(1 == ~main_clk_pos_edge~0); 155614#L441-1 assume !(1 == ~main_clk_pos_edge~0); 155613#L446-1 assume !(1 == ~main_in1_ev~0); 155611#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 155612#L456-1 assume !(1 == ~main_sum_ev~0); 163148#L461-1 assume !(1 == ~main_diff_ev~0); 163147#L466-1 assume !(1 == ~main_pres_ev~0); 163146#L471-1 assume !(1 == ~main_dbl_ev~0); 162653#L476-1 assume !(1 == ~main_zero_ev~0); 162651#L481-1 assume !(1 == ~main_clk_ev~0); 162647#L486-1 assume !(1 == ~main_clk_pos_edge~0); 162643#L491-1 assume !(1 == ~main_clk_neg_edge~0); 156633#L742-1 [2021-12-07 01:23:19,930 INFO L793 eck$LassoCheckResult]: Loop: 156633#L742-1 assume !false; 162639#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 162635#L229 assume !false; 162632#L147 assume !(0 == ~N_generate_st~0); 162631#L151 assume !(0 == ~S1_addsub_st~0); 162630#L154 assume !(0 == ~S2_presdbl_st~0); 162626#L157 assume !(0 == ~S3_zero_st~0); 162621#L160 assume !(0 == ~D_print_st~0); 162617#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 162613#L509 assume !(1 == ~main_in1_req_up~0); 162609#L509-2 assume !(1 == ~main_in2_req_up~0); 162610#L520-1 assume !(1 == ~main_sum_req_up~0); 162627#L531-1 assume !(1 == ~main_diff_req_up~0); 162624#L542-1 assume !(1 == ~main_pres_req_up~0); 162619#L553-1 assume !(1 == ~main_dbl_req_up~0); 162615#L564-1 assume !(1 == ~main_zero_req_up~0); 162611#L575-1 assume !(1 == ~main_clk_req_up~0); 162612#L586-1 start_simulation_~kernel_st~0#1 := 3; 168713#L605 assume !(0 == ~main_in1_ev~0); 168712#L605-2 assume !(0 == ~main_in2_ev~0); 162448#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 168711#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 168710#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 168704#L625-1 assume !(0 == ~main_dbl_ev~0); 168703#L630-1 assume !(0 == ~main_zero_ev~0); 168682#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 168681#L640-1 assume !(0 == ~main_clk_pos_edge~0); 168678#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 168677#L650-1 assume !(1 == ~main_clk_pos_edge~0); 168675#L655-1 assume !(1 == ~main_clk_pos_edge~0); 166943#L660-1 assume !(1 == ~main_clk_pos_edge~0); 166940#L665-1 assume !(1 == ~main_clk_pos_edge~0); 166937#L670-1 assume !(1 == ~main_clk_pos_edge~0); 166934#L675-1 assume !(1 == ~main_in1_ev~0); 156664#L680-1 assume !(1 == ~main_in2_ev~0); 154198#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 156662#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 156658#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 156654#L700-1 assume !(1 == ~main_dbl_ev~0); 156652#L705-1 assume !(1 == ~main_zero_ev~0); 156650#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 156647#L715-1 assume !(1 == ~main_clk_pos_edge~0); 156643#L720-1 assume !(1 == ~main_clk_neg_edge~0); 156641#L725-1 assume 0 == ~N_generate_st~0; 156633#L742-1 [2021-12-07 01:23:19,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:19,931 INFO L85 PathProgramCache]: Analyzing trace with hash -457161483, now seen corresponding path program 1 times [2021-12-07 01:23:19,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:19,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827704470] [2021-12-07 01:23:19,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:19,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:19,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:19,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:19,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:19,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827704470] [2021-12-07 01:23:19,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827704470] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:19,950 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:19,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:19,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039000665] [2021-12-07 01:23:19,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:19,950 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:19,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:19,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 1 times [2021-12-07 01:23:19,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:19,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737166646] [2021-12-07 01:23:19,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:19,951 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:19,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:19,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:19,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:19,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737166646] [2021-12-07 01:23:19,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737166646] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:19,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:19,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:19,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408941764] [2021-12-07 01:23:19,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:19,962 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:19,962 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:19,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:19,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:19,963 INFO L87 Difference]: Start difference. First operand 33519 states and 53550 transitions. cyclomatic complexity: 20095 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:20,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:20,166 INFO L93 Difference]: Finished difference Result 34717 states and 54842 transitions. [2021-12-07 01:23:20,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:20,166 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34717 states and 54842 transitions. [2021-12-07 01:23:20,272 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32815 [2021-12-07 01:23:20,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34717 states to 34717 states and 54842 transitions. [2021-12-07 01:23:20,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34717 [2021-12-07 01:23:20,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34717 [2021-12-07 01:23:20,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34717 states and 54842 transitions. [2021-12-07 01:23:20,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:20,447 INFO L681 BuchiCegarLoop]: Abstraction has 34717 states and 54842 transitions. [2021-12-07 01:23:20,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34717 states and 54842 transitions. [2021-12-07 01:23:20,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34717 to 33519. [2021-12-07 01:23:20,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.5798800680211222) internal successors, (52956), 33518 states have internal predecessors, (52956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:20,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 52956 transitions. [2021-12-07 01:23:20,778 INFO L704 BuchiCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2021-12-07 01:23:20,778 INFO L587 BuchiCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2021-12-07 01:23:20,778 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-07 01:23:20,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 52956 transitions. [2021-12-07 01:23:20,833 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2021-12-07 01:23:20,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:20,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:20,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:20,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:20,833 INFO L791 eck$LassoCheckResult]: Stem: 219031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 219003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 218571#L256 assume !(1 == ~main_in1_req_up~0); 218527#L256-2 assume !(1 == ~main_in2_req_up~0); 218529#L267-1 assume !(1 == ~main_sum_req_up~0); 218558#L278-1 assume !(1 == ~main_diff_req_up~0); 218508#L289-1 assume !(1 == ~main_pres_req_up~0); 218509#L300-1 assume !(1 == ~main_dbl_req_up~0); 218622#L311-1 assume !(1 == ~main_zero_req_up~0); 218981#L322-1 assume !(1 == ~main_clk_req_up~0); 218983#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 223895#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 223893#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 223891#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 223889#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 223887#L371-1 assume !(0 == ~main_in1_ev~0); 223885#L376-1 assume !(0 == ~main_in2_ev~0); 223883#L381-1 assume !(0 == ~main_sum_ev~0); 223881#L386-1 assume !(0 == ~main_diff_ev~0); 223879#L391-1 assume !(0 == ~main_pres_ev~0); 223877#L396-1 assume !(0 == ~main_dbl_ev~0); 223875#L401-1 assume !(0 == ~main_zero_ev~0); 223873#L406-1 assume !(0 == ~main_clk_ev~0); 223871#L411-1 assume !(0 == ~main_clk_pos_edge~0); 223869#L416-1 assume !(0 == ~main_clk_neg_edge~0); 223867#L421-1 assume !(1 == ~main_clk_pos_edge~0); 223865#L426-1 assume !(1 == ~main_clk_pos_edge~0); 223863#L431-1 assume !(1 == ~main_clk_pos_edge~0); 223861#L436-1 assume !(1 == ~main_clk_pos_edge~0); 223859#L441-1 assume !(1 == ~main_clk_pos_edge~0); 223857#L446-1 assume !(1 == ~main_in1_ev~0); 223845#L451-1 assume !(1 == ~main_in2_ev~0); 223839#L456-1 assume !(1 == ~main_sum_ev~0); 223833#L461-1 assume !(1 == ~main_diff_ev~0); 223830#L466-1 assume !(1 == ~main_pres_ev~0); 223827#L471-1 assume !(1 == ~main_dbl_ev~0); 223824#L476-1 assume !(1 == ~main_zero_ev~0); 223819#L481-1 assume !(1 == ~main_clk_ev~0); 223818#L486-1 assume !(1 == ~main_clk_pos_edge~0); 223804#L491-1 assume !(1 == ~main_clk_neg_edge~0); 223799#L742-1 [2021-12-07 01:23:20,834 INFO L793 eck$LassoCheckResult]: Loop: 223799#L742-1 assume !false; 223792#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 223785#L229 assume !false; 223784#L147 assume !(0 == ~N_generate_st~0); 223778#L151 assume !(0 == ~S1_addsub_st~0); 223772#L154 assume !(0 == ~S2_presdbl_st~0); 223765#L157 assume !(0 == ~S3_zero_st~0); 223755#L160 assume !(0 == ~D_print_st~0); 223750#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 223746#L509 assume !(1 == ~main_in1_req_up~0); 223740#L509-2 assume !(1 == ~main_in2_req_up~0); 223741#L520-1 assume !(1 == ~main_sum_req_up~0); 223974#L531-1 assume !(1 == ~main_diff_req_up~0); 223970#L542-1 assume !(1 == ~main_pres_req_up~0); 223947#L553-1 assume !(1 == ~main_dbl_req_up~0); 223900#L564-1 assume !(1 == ~main_zero_req_up~0); 223897#L575-1 assume !(1 == ~main_clk_req_up~0); 223894#L586-1 start_simulation_~kernel_st~0#1 := 3; 223892#L605 assume !(0 == ~main_in1_ev~0); 223890#L605-2 assume !(0 == ~main_in2_ev~0); 223888#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 223886#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 223884#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 223882#L625-1 assume !(0 == ~main_dbl_ev~0); 223880#L630-1 assume !(0 == ~main_zero_ev~0); 223878#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 223876#L640-1 assume !(0 == ~main_clk_pos_edge~0); 223874#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 223872#L650-1 assume !(1 == ~main_clk_pos_edge~0); 223870#L655-1 assume !(1 == ~main_clk_pos_edge~0); 223868#L660-1 assume !(1 == ~main_clk_pos_edge~0); 223866#L665-1 assume !(1 == ~main_clk_pos_edge~0); 223864#L670-1 assume !(1 == ~main_clk_pos_edge~0); 223862#L675-1 assume !(1 == ~main_in1_ev~0); 223860#L680-1 assume !(1 == ~main_in2_ev~0); 223858#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 223846#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 223840#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 223834#L700-1 assume !(1 == ~main_dbl_ev~0); 223831#L705-1 assume !(1 == ~main_zero_ev~0); 223828#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 223825#L715-1 assume !(1 == ~main_clk_pos_edge~0); 223820#L720-1 assume !(1 == ~main_clk_neg_edge~0); 223807#L725-1 assume 0 == ~N_generate_st~0; 223799#L742-1 [2021-12-07 01:23:20,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:20,834 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2021-12-07 01:23:20,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:20,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484270810] [2021-12-07 01:23:20,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:20,834 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:20,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:20,840 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:20,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:20,852 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:20,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:20,852 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 2 times [2021-12-07 01:23:20,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:20,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720301360] [2021-12-07 01:23:20,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:20,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:20,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:20,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:20,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:20,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720301360] [2021-12-07 01:23:20,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720301360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:20,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:20,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:20,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554042279] [2021-12-07 01:23:20,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:20,864 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:20,864 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:20,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:20,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:20,865 INFO L87 Difference]: Start difference. First operand 33519 states and 52956 transitions. cyclomatic complexity: 19501 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:20,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:20,979 INFO L93 Difference]: Finished difference Result 44288 states and 68290 transitions. [2021-12-07 01:23:20,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:20,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44288 states and 68290 transitions. [2021-12-07 01:23:21,175 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2021-12-07 01:23:21,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44288 states to 44288 states and 68290 transitions. [2021-12-07 01:23:21,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44288 [2021-12-07 01:23:21,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44288 [2021-12-07 01:23:21,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44288 states and 68290 transitions. [2021-12-07 01:23:21,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:21,295 INFO L681 BuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2021-12-07 01:23:21,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44288 states and 68290 transitions. [2021-12-07 01:23:21,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44288 to 44288. [2021-12-07 01:23:21,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44288 states, 44288 states have (on average 1.5419526734104045) internal successors, (68290), 44287 states have internal predecessors, (68290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:21,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44288 states to 44288 states and 68290 transitions. [2021-12-07 01:23:21,723 INFO L704 BuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2021-12-07 01:23:21,723 INFO L587 BuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2021-12-07 01:23:21,723 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-07 01:23:21,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44288 states and 68290 transitions. [2021-12-07 01:23:21,835 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2021-12-07 01:23:21,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:21,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:21,836 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:21,836 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:21,837 INFO L791 eck$LassoCheckResult]: Stem: 296891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 296845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 296385#L256 assume !(1 == ~main_in1_req_up~0); 296340#L256-2 assume !(1 == ~main_in2_req_up~0); 296342#L267-1 assume !(1 == ~main_sum_req_up~0); 296372#L278-1 assume !(1 == ~main_diff_req_up~0); 296321#L289-1 assume !(1 == ~main_pres_req_up~0); 296322#L300-1 assume !(1 == ~main_dbl_req_up~0); 300482#L311-1 assume !(1 == ~main_zero_req_up~0); 300479#L322-1 assume !(1 == ~main_clk_req_up~0); 300480#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 304645#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 304644#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 304643#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 304642#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 304641#L371-1 assume !(0 == ~main_in1_ev~0); 304640#L376-1 assume !(0 == ~main_in2_ev~0); 304639#L381-1 assume !(0 == ~main_sum_ev~0); 304638#L386-1 assume !(0 == ~main_diff_ev~0); 304637#L391-1 assume !(0 == ~main_pres_ev~0); 304636#L396-1 assume !(0 == ~main_dbl_ev~0); 304635#L401-1 assume !(0 == ~main_zero_ev~0); 304634#L406-1 assume !(0 == ~main_clk_ev~0); 304633#L411-1 assume !(0 == ~main_clk_pos_edge~0); 304631#L416-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 304630#L421-1 assume !(1 == ~main_clk_pos_edge~0); 304629#L426-1 assume !(1 == ~main_clk_pos_edge~0); 304628#L431-1 assume !(1 == ~main_clk_pos_edge~0); 304627#L436-1 assume !(1 == ~main_clk_pos_edge~0); 304626#L441-1 assume !(1 == ~main_clk_pos_edge~0); 304625#L446-1 assume !(1 == ~main_in1_ev~0); 304624#L451-1 assume !(1 == ~main_in2_ev~0); 304623#L456-1 assume !(1 == ~main_sum_ev~0); 304622#L461-1 assume !(1 == ~main_diff_ev~0); 304621#L466-1 assume !(1 == ~main_pres_ev~0); 304620#L471-1 assume !(1 == ~main_dbl_ev~0); 304619#L476-1 assume !(1 == ~main_zero_ev~0); 304618#L481-1 assume !(1 == ~main_clk_ev~0); 304617#L486-1 assume !(1 == ~main_clk_pos_edge~0); 304546#L491-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 304544#L742-1 [2021-12-07 01:23:21,837 INFO L793 eck$LassoCheckResult]: Loop: 304544#L742-1 assume !false; 304543#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 304539#L229 assume !false; 304538#L147 assume !(0 == ~N_generate_st~0); 304537#L151 assume !(0 == ~S1_addsub_st~0); 304536#L154 assume !(0 == ~S2_presdbl_st~0); 304535#L157 assume !(0 == ~S3_zero_st~0); 304533#L160 assume !(0 == ~D_print_st~0); 304532#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 304531#L509 assume !(1 == ~main_in1_req_up~0); 304529#L509-2 assume !(1 == ~main_in2_req_up~0); 304530#L520-1 assume !(1 == ~main_sum_req_up~0); 304592#L531-1 assume !(1 == ~main_diff_req_up~0); 300234#L542-1 assume !(1 == ~main_pres_req_up~0); 300233#L553-1 assume !(1 == ~main_dbl_req_up~0); 304584#L564-1 assume !(1 == ~main_zero_req_up~0); 304581#L575-1 assume !(1 == ~main_clk_req_up~0); 304579#L586-1 start_simulation_~kernel_st~0#1 := 3; 304578#L605 assume !(0 == ~main_in1_ev~0); 304577#L605-2 assume !(0 == ~main_in2_ev~0); 304576#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 304575#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 304574#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 304573#L625-1 assume !(0 == ~main_dbl_ev~0); 304572#L630-1 assume !(0 == ~main_zero_ev~0); 304571#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 304570#L640-1 assume !(0 == ~main_clk_pos_edge~0); 304568#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 304567#L650-1 assume !(1 == ~main_clk_pos_edge~0); 304566#L655-1 assume !(1 == ~main_clk_pos_edge~0); 304565#L660-1 assume !(1 == ~main_clk_pos_edge~0); 304564#L665-1 assume !(1 == ~main_clk_pos_edge~0); 304563#L670-1 assume !(1 == ~main_clk_pos_edge~0); 304562#L675-1 assume !(1 == ~main_in1_ev~0); 304561#L680-1 assume !(1 == ~main_in2_ev~0); 304560#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 304559#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 304558#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 304557#L700-1 assume !(1 == ~main_dbl_ev~0); 304556#L705-1 assume !(1 == ~main_zero_ev~0); 304555#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 304554#L715-1 assume !(1 == ~main_clk_pos_edge~0); 304553#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 304549#L725-1 assume 0 == ~N_generate_st~0; 304544#L742-1 [2021-12-07 01:23:21,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:21,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1243965239, now seen corresponding path program 1 times [2021-12-07 01:23:21,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:21,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758842641] [2021-12-07 01:23:21,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:21,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:21,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:21,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:21,857 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:21,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758842641] [2021-12-07 01:23:21,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758842641] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:21,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:21,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:21,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733525683] [2021-12-07 01:23:21,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:21,858 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:21,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:21,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141836, now seen corresponding path program 1 times [2021-12-07 01:23:21,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:21,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336892973] [2021-12-07 01:23:21,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:21,858 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:21,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:21,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:21,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:21,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336892973] [2021-12-07 01:23:21,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336892973] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:21,871 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:21,872 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:21,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99925347] [2021-12-07 01:23:21,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:21,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:21,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:21,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:21,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:21,873 INFO L87 Difference]: Start difference. First operand 44288 states and 68290 transitions. cyclomatic complexity: 24066 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:22,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:22,200 INFO L93 Difference]: Finished difference Result 53275 states and 81140 transitions. [2021-12-07 01:23:22,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:22,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53275 states and 81140 transitions. [2021-12-07 01:23:22,384 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 50818 [2021-12-07 01:23:22,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53275 states to 53275 states and 81140 transitions. [2021-12-07 01:23:22,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53275 [2021-12-07 01:23:22,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53275 [2021-12-07 01:23:22,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53275 states and 81140 transitions. [2021-12-07 01:23:22,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:22,543 INFO L681 BuchiCegarLoop]: Abstraction has 53275 states and 81140 transitions. [2021-12-07 01:23:22,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53275 states and 81140 transitions. [2021-12-07 01:23:22,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53275 to 41741. [2021-12-07 01:23:22,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41741 states, 41741 states have (on average 1.5255504180541912) internal successors, (63678), 41740 states have internal predecessors, (63678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:22,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41741 states to 41741 states and 63678 transitions. [2021-12-07 01:23:22,914 INFO L704 BuchiCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2021-12-07 01:23:22,914 INFO L587 BuchiCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2021-12-07 01:23:22,914 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-07 01:23:22,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41741 states and 63678 transitions. [2021-12-07 01:23:23,015 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 39570 [2021-12-07 01:23:23,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:23,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:23,016 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:23,016 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:23,016 INFO L791 eck$LassoCheckResult]: Stem: 394486#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 394442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 393957#L256 assume !(1 == ~main_in1_req_up~0); 393913#L256-2 assume !(1 == ~main_in2_req_up~0); 393915#L267-1 assume !(1 == ~main_sum_req_up~0); 393944#L278-1 assume !(1 == ~main_diff_req_up~0); 393894#L289-1 assume !(1 == ~main_pres_req_up~0); 393895#L300-1 assume !(1 == ~main_dbl_req_up~0); 394006#L311-1 assume !(1 == ~main_zero_req_up~0); 394412#L322-1 assume !(1 == ~main_clk_req_up~0); 394414#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 398208#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 398207#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 398206#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 398205#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 398204#L371-1 assume !(0 == ~main_in1_ev~0); 398203#L376-1 assume !(0 == ~main_in2_ev~0); 398202#L381-1 assume !(0 == ~main_sum_ev~0); 398198#L386-1 assume !(0 == ~main_diff_ev~0); 396759#L391-1 assume !(0 == ~main_pres_ev~0); 396758#L396-1 assume !(0 == ~main_dbl_ev~0); 396756#L401-1 assume !(0 == ~main_zero_ev~0); 396757#L406-1 assume !(0 == ~main_clk_ev~0); 398188#L411-1 assume !(0 == ~main_clk_pos_edge~0); 396752#L416-1 assume !(0 == ~main_clk_neg_edge~0); 396751#L421-1 assume !(1 == ~main_clk_pos_edge~0); 396750#L426-1 assume !(1 == ~main_clk_pos_edge~0); 396749#L431-1 assume !(1 == ~main_clk_pos_edge~0); 396748#L436-1 assume !(1 == ~main_clk_pos_edge~0); 396747#L441-1 assume !(1 == ~main_clk_pos_edge~0); 396746#L446-1 assume !(1 == ~main_in1_ev~0); 396745#L451-1 assume !(1 == ~main_in2_ev~0); 396744#L456-1 assume !(1 == ~main_sum_ev~0); 396743#L461-1 assume !(1 == ~main_diff_ev~0); 396742#L466-1 assume !(1 == ~main_pres_ev~0); 396741#L471-1 assume !(1 == ~main_dbl_ev~0); 396740#L476-1 assume !(1 == ~main_zero_ev~0); 396738#L481-1 assume !(1 == ~main_clk_ev~0); 396739#L486-1 assume !(1 == ~main_clk_pos_edge~0); 396707#L491-1 assume !(1 == ~main_clk_neg_edge~0); 396702#L742-1 [2021-12-07 01:23:23,016 INFO L793 eck$LassoCheckResult]: Loop: 396702#L742-1 assume !false; 396701#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 396697#L229 assume !false; 396696#L147 assume !(0 == ~N_generate_st~0); 396692#L151 assume !(0 == ~S1_addsub_st~0); 396693#L154 assume !(0 == ~S2_presdbl_st~0); 396694#L157 assume !(0 == ~S3_zero_st~0); 396695#L160 assume !(0 == ~D_print_st~0); 394311#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 394312#L509 assume !(1 == ~main_in1_req_up~0); 394221#L509-2 assume !(1 == ~main_in2_req_up~0); 394222#L520-1 assume !(1 == ~main_sum_req_up~0); 401385#L531-1 assume !(1 == ~main_diff_req_up~0); 400988#L542-1 assume !(1 == ~main_pres_req_up~0); 400984#L553-1 assume !(1 == ~main_dbl_req_up~0); 400981#L564-1 assume !(1 == ~main_zero_req_up~0); 400982#L575-1 assume !(1 == ~main_clk_req_up~0); 401428#L586-1 start_simulation_~kernel_st~0#1 := 3; 403178#L605 assume !(0 == ~main_in1_ev~0); 403177#L605-2 assume !(0 == ~main_in2_ev~0); 403176#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 403175#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 403174#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 403173#L625-1 assume !(0 == ~main_dbl_ev~0); 403172#L630-1 assume !(0 == ~main_zero_ev~0); 403171#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 403170#L640-1 assume !(0 == ~main_clk_pos_edge~0); 403169#L645-1 assume !(0 == ~main_clk_neg_edge~0); 403168#L650-1 assume !(1 == ~main_clk_pos_edge~0); 403167#L655-1 assume !(1 == ~main_clk_pos_edge~0); 403166#L660-1 assume !(1 == ~main_clk_pos_edge~0); 403165#L665-1 assume !(1 == ~main_clk_pos_edge~0); 403164#L670-1 assume !(1 == ~main_clk_pos_edge~0); 403163#L675-1 assume !(1 == ~main_in1_ev~0); 403162#L680-1 assume !(1 == ~main_in2_ev~0); 403161#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 403160#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 403159#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 403158#L700-1 assume !(1 == ~main_dbl_ev~0); 403157#L705-1 assume !(1 == ~main_zero_ev~0); 403156#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 394233#L715-1 assume !(1 == ~main_clk_pos_edge~0); 394155#L720-1 assume !(1 == ~main_clk_neg_edge~0); 394156#L725-1 assume 0 == ~N_generate_st~0; 396702#L742-1 [2021-12-07 01:23:23,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:23,017 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2021-12-07 01:23:23,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:23,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584772529] [2021-12-07 01:23:23,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:23,017 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:23,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:23,024 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:23,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:23,036 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:23,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:23,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1374477620, now seen corresponding path program 1 times [2021-12-07 01:23:23,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:23,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235660580] [2021-12-07 01:23:23,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:23,036 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:23,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:23,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:23,047 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:23,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235660580] [2021-12-07 01:23:23,047 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235660580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:23,047 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:23,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:23,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873107362] [2021-12-07 01:23:23,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:23,048 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:23,048 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:23,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:23,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:23,048 INFO L87 Difference]: Start difference. First operand 41741 states and 63678 transitions. cyclomatic complexity: 22001 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:23,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:23,290 INFO L93 Difference]: Finished difference Result 57643 states and 86947 transitions. [2021-12-07 01:23:23,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:23,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57643 states and 86947 transitions. [2021-12-07 01:23:23,468 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2021-12-07 01:23:23,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57643 states to 57643 states and 86947 transitions. [2021-12-07 01:23:23,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57643 [2021-12-07 01:23:23,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57643 [2021-12-07 01:23:23,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57643 states and 86947 transitions. [2021-12-07 01:23:23,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:23,626 INFO L681 BuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2021-12-07 01:23:23,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57643 states and 86947 transitions. [2021-12-07 01:23:23,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57643 to 57643. [2021-12-07 01:23:24,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57643 states, 57643 states have (on average 1.5083704873098207) internal successors, (86947), 57642 states have internal predecessors, (86947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:24,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57643 states to 57643 states and 86947 transitions. [2021-12-07 01:23:24,130 INFO L704 BuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2021-12-07 01:23:24,130 INFO L587 BuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2021-12-07 01:23:24,130 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-07 01:23:24,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57643 states and 86947 transitions. [2021-12-07 01:23:24,266 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2021-12-07 01:23:24,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:24,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:24,267 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:24,267 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:24,267 INFO L791 eck$LassoCheckResult]: Stem: 493890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 493851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 493348#L256 assume !(1 == ~main_in1_req_up~0); 493303#L256-2 assume !(1 == ~main_in2_req_up~0); 493305#L267-1 assume !(1 == ~main_sum_req_up~0); 493793#L278-1 assume !(1 == ~main_diff_req_up~0); 493448#L289-1 assume !(1 == ~main_pres_req_up~0); 493733#L300-1 assume !(1 == ~main_dbl_req_up~0); 493576#L311-1 assume !(1 == ~main_zero_req_up~0); 493577#L322-1 assume !(1 == ~main_clk_req_up~0); 500679#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 500680#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 500678#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 500676#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 500673#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 500670#L371-1 assume !(0 == ~main_in1_ev~0); 500667#L376-1 assume !(0 == ~main_in2_ev~0); 500664#L381-1 assume !(0 == ~main_sum_ev~0); 500661#L386-1 assume !(0 == ~main_diff_ev~0); 500658#L391-1 assume !(0 == ~main_pres_ev~0); 500655#L396-1 assume !(0 == ~main_dbl_ev~0); 500652#L401-1 assume !(0 == ~main_zero_ev~0); 500649#L406-1 assume !(0 == ~main_clk_ev~0); 500646#L411-1 assume !(0 == ~main_clk_pos_edge~0); 500643#L416-1 assume !(0 == ~main_clk_neg_edge~0); 500640#L421-1 assume !(1 == ~main_clk_pos_edge~0); 500637#L426-1 assume !(1 == ~main_clk_pos_edge~0); 500634#L431-1 assume !(1 == ~main_clk_pos_edge~0); 500631#L436-1 assume !(1 == ~main_clk_pos_edge~0); 500628#L441-1 assume !(1 == ~main_clk_pos_edge~0); 500625#L446-1 assume !(1 == ~main_in1_ev~0); 500622#L451-1 assume !(1 == ~main_in2_ev~0); 500619#L456-1 assume !(1 == ~main_sum_ev~0); 500616#L461-1 assume !(1 == ~main_diff_ev~0); 500613#L466-1 assume !(1 == ~main_pres_ev~0); 500610#L471-1 assume !(1 == ~main_dbl_ev~0); 500607#L476-1 assume !(1 == ~main_zero_ev~0); 500604#L481-1 assume !(1 == ~main_clk_ev~0); 500601#L486-1 assume !(1 == ~main_clk_pos_edge~0); 500589#L491-1 assume !(1 == ~main_clk_neg_edge~0); 500585#L742-1 [2021-12-07 01:23:24,268 INFO L793 eck$LassoCheckResult]: Loop: 500585#L742-1 assume !false; 500581#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 500578#L229 assume !false; 497978#L147 assume !(0 == ~N_generate_st~0); 497977#L151 assume !(0 == ~S1_addsub_st~0); 497976#L154 assume !(0 == ~S2_presdbl_st~0); 497975#L157 assume !(0 == ~S3_zero_st~0); 497973#L160 assume !(0 == ~D_print_st~0); 497972#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 497971#L509 assume !(1 == ~main_in1_req_up~0); 497970#L509-2 assume !(1 == ~main_in2_req_up~0); 494920#L520-1 assume !(1 == ~main_sum_req_up~0); 494912#L531-1 assume !(1 == ~main_diff_req_up~0); 494906#L542-1 assume !(1 == ~main_pres_req_up~0); 494899#L553-1 assume !(1 == ~main_dbl_req_up~0); 494900#L564-1 assume !(1 == ~main_zero_req_up~0); 498604#L575-1 assume !(1 == ~main_clk_req_up~0); 500674#L586-1 start_simulation_~kernel_st~0#1 := 3; 500671#L605 assume !(0 == ~main_in1_ev~0); 500668#L605-2 assume !(0 == ~main_in2_ev~0); 500665#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 500662#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 500659#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 500656#L625-1 assume !(0 == ~main_dbl_ev~0); 500653#L630-1 assume !(0 == ~main_zero_ev~0); 500650#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 500647#L640-1 assume !(0 == ~main_clk_pos_edge~0); 500644#L645-1 assume !(0 == ~main_clk_neg_edge~0); 500641#L650-1 assume !(1 == ~main_clk_pos_edge~0); 500638#L655-1 assume !(1 == ~main_clk_pos_edge~0); 500635#L660-1 assume !(1 == ~main_clk_pos_edge~0); 500632#L665-1 assume !(1 == ~main_clk_pos_edge~0); 500629#L670-1 assume !(1 == ~main_clk_pos_edge~0); 500626#L675-1 assume !(1 == ~main_in1_ev~0); 500623#L680-1 assume !(1 == ~main_in2_ev~0); 500620#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 500617#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 500614#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 500611#L700-1 assume !(1 == ~main_dbl_ev~0); 500608#L705-1 assume !(1 == ~main_zero_ev~0); 500605#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 500602#L715-1 assume !(1 == ~main_clk_pos_edge~0); 500596#L720-1 assume !(1 == ~main_clk_neg_edge~0); 500595#L725-1 assume !(0 == ~N_generate_st~0); 500593#L733 assume 0 == ~S1_addsub_st~0; 500585#L742-1 [2021-12-07 01:23:24,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:24,268 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2021-12-07 01:23:24,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:24,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123721007] [2021-12-07 01:23:24,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:24,268 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:24,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:24,274 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:24,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:24,286 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:24,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:24,286 INFO L85 PathProgramCache]: Analyzing trace with hash -340865996, now seen corresponding path program 1 times [2021-12-07 01:23:24,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:24,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888912866] [2021-12-07 01:23:24,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:24,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:24,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:24,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:24,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:24,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888912866] [2021-12-07 01:23:24,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888912866] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:24,297 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:24,297 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:24,297 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076762240] [2021-12-07 01:23:24,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:24,297 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:24,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:24,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:24,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:24,298 INFO L87 Difference]: Start difference. First operand 57643 states and 86947 transitions. cyclomatic complexity: 29376 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:24,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:24,603 INFO L93 Difference]: Finished difference Result 86850 states and 129727 transitions. [2021-12-07 01:23:24,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:24,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86850 states and 129727 transitions. [2021-12-07 01:23:24,845 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2021-12-07 01:23:24,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86850 states to 86850 states and 129727 transitions. [2021-12-07 01:23:24,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86850 [2021-12-07 01:23:25,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86850 [2021-12-07 01:23:25,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86850 states and 129727 transitions. [2021-12-07 01:23:25,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:25,052 INFO L681 BuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2021-12-07 01:23:25,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86850 states and 129727 transitions. [2021-12-07 01:23:25,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86850 to 86850. [2021-12-07 01:23:25,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86850 states, 86850 states have (on average 1.4936902705814623) internal successors, (129727), 86849 states have internal predecessors, (129727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:25,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86850 states to 86850 states and 129727 transitions. [2021-12-07 01:23:25,724 INFO L704 BuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2021-12-07 01:23:25,724 INFO L587 BuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2021-12-07 01:23:25,724 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-07 01:23:25,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86850 states and 129727 transitions. [2021-12-07 01:23:25,943 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2021-12-07 01:23:25,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:25,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:25,944 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:25,944 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:25,944 INFO L791 eck$LassoCheckResult]: Stem: 638405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 638360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 637848#L256 assume !(1 == ~main_in1_req_up~0); 637802#L256-2 assume !(1 == ~main_in2_req_up~0); 637804#L267-1 assume !(1 == ~main_sum_req_up~0); 638297#L278-1 assume !(1 == ~main_diff_req_up~0); 637947#L289-1 assume !(1 == ~main_pres_req_up~0); 638228#L300-1 assume !(1 == ~main_dbl_req_up~0); 637897#L311-1 assume !(1 == ~main_zero_req_up~0); 641657#L322-1 assume !(1 == ~main_clk_req_up~0); 641658#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 649339#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 649368#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 649365#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 649362#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 649359#L371-1 assume !(0 == ~main_in1_ev~0); 649356#L376-1 assume !(0 == ~main_in2_ev~0); 649353#L381-1 assume !(0 == ~main_sum_ev~0); 649350#L386-1 assume !(0 == ~main_diff_ev~0); 649347#L391-1 assume !(0 == ~main_pres_ev~0); 649344#L396-1 assume !(0 == ~main_dbl_ev~0); 649341#L401-1 assume !(0 == ~main_zero_ev~0); 649337#L406-1 assume !(0 == ~main_clk_ev~0); 649332#L411-1 assume !(0 == ~main_clk_pos_edge~0); 649328#L416-1 assume !(0 == ~main_clk_neg_edge~0); 649324#L421-1 assume !(1 == ~main_clk_pos_edge~0); 649320#L426-1 assume !(1 == ~main_clk_pos_edge~0); 649316#L431-1 assume !(1 == ~main_clk_pos_edge~0); 649312#L436-1 assume !(1 == ~main_clk_pos_edge~0); 649308#L441-1 assume !(1 == ~main_clk_pos_edge~0); 649304#L446-1 assume !(1 == ~main_in1_ev~0); 649300#L451-1 assume !(1 == ~main_in2_ev~0); 649296#L456-1 assume !(1 == ~main_sum_ev~0); 649292#L461-1 assume !(1 == ~main_diff_ev~0); 649288#L466-1 assume !(1 == ~main_pres_ev~0); 649284#L471-1 assume !(1 == ~main_dbl_ev~0); 649281#L476-1 assume !(1 == ~main_zero_ev~0); 649278#L481-1 assume !(1 == ~main_clk_ev~0); 649276#L486-1 assume !(1 == ~main_clk_pos_edge~0); 649274#L491-1 assume !(1 == ~main_clk_neg_edge~0); 648472#L742-1 [2021-12-07 01:23:25,944 INFO L793 eck$LassoCheckResult]: Loop: 648472#L742-1 assume !false; 648460#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 645391#L229 assume !false; 645392#L147 assume !(0 == ~N_generate_st~0); 640131#L151 assume !(0 == ~S1_addsub_st~0); 640129#L154 assume !(0 == ~S2_presdbl_st~0); 640127#L157 assume !(0 == ~S3_zero_st~0); 640124#L160 assume !(0 == ~D_print_st~0); 640121#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 640119#L509 assume !(1 == ~main_in1_req_up~0); 640116#L509-2 assume !(1 == ~main_in2_req_up~0); 640117#L520-1 assume !(1 == ~main_sum_req_up~0); 641819#L531-1 assume !(1 == ~main_diff_req_up~0); 641815#L542-1 assume !(1 == ~main_pres_req_up~0); 641809#L553-1 assume !(1 == ~main_dbl_req_up~0); 641802#L564-1 assume !(1 == ~main_zero_req_up~0); 641796#L575-1 assume !(1 == ~main_clk_req_up~0); 641797#L586-1 start_simulation_~kernel_st~0#1 := 3; 648516#L605 assume !(0 == ~main_in1_ev~0); 648515#L605-2 assume !(0 == ~main_in2_ev~0); 648514#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 648513#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 648512#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 648511#L625-1 assume !(0 == ~main_dbl_ev~0); 648510#L630-1 assume !(0 == ~main_zero_ev~0); 648509#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 648508#L640-1 assume !(0 == ~main_clk_pos_edge~0); 648507#L645-1 assume !(0 == ~main_clk_neg_edge~0); 648506#L650-1 assume !(1 == ~main_clk_pos_edge~0); 648505#L655-1 assume !(1 == ~main_clk_pos_edge~0); 648504#L660-1 assume !(1 == ~main_clk_pos_edge~0); 648503#L665-1 assume !(1 == ~main_clk_pos_edge~0); 648502#L670-1 assume !(1 == ~main_clk_pos_edge~0); 648501#L675-1 assume !(1 == ~main_in1_ev~0); 648500#L680-1 assume !(1 == ~main_in2_ev~0); 648499#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 648498#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 648497#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 648496#L700-1 assume !(1 == ~main_dbl_ev~0); 648495#L705-1 assume !(1 == ~main_zero_ev~0); 648494#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 648493#L715-1 assume !(1 == ~main_clk_pos_edge~0); 648492#L720-1 assume !(1 == ~main_clk_neg_edge~0); 648491#L725-1 assume !(0 == ~N_generate_st~0); 648490#L733 assume !(0 == ~S1_addsub_st~0); 648489#L736 assume 0 == ~S2_presdbl_st~0; 648472#L742-1 [2021-12-07 01:23:25,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:25,945 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2021-12-07 01:23:25,945 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:25,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695649780] [2021-12-07 01:23:25,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:25,945 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:25,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:25,951 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:26,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:26,087 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:26,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:26,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1976910535, now seen corresponding path program 1 times [2021-12-07 01:23:26,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:26,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624167272] [2021-12-07 01:23:26,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:26,094 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:26,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:26,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:26,108 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:26,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624167272] [2021-12-07 01:23:26,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624167272] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:26,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:26,109 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:26,109 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821206268] [2021-12-07 01:23:26,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:26,109 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:26,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:26,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:26,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:26,110 INFO L87 Difference]: Start difference. First operand 86850 states and 129727 transitions. cyclomatic complexity: 42973 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:26,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:26,385 INFO L93 Difference]: Finished difference Result 91777 states and 136566 transitions. [2021-12-07 01:23:26,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:26,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91777 states and 136566 transitions. [2021-12-07 01:23:26,715 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2021-12-07 01:23:26,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91777 states to 91777 states and 136566 transitions. [2021-12-07 01:23:26,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91777 [2021-12-07 01:23:26,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91777 [2021-12-07 01:23:26,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91777 states and 136566 transitions. [2021-12-07 01:23:27,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:27,016 INFO L681 BuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2021-12-07 01:23:27,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91777 states and 136566 transitions. [2021-12-07 01:23:27,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91777 to 91777. [2021-12-07 01:23:27,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91777 states, 91777 states have (on average 1.4880198742604356) internal successors, (136566), 91776 states have internal predecessors, (136566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:27,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91777 states to 91777 states and 136566 transitions. [2021-12-07 01:23:27,990 INFO L704 BuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2021-12-07 01:23:27,990 INFO L587 BuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2021-12-07 01:23:27,990 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-07 01:23:27,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91777 states and 136566 transitions. [2021-12-07 01:23:28,293 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2021-12-07 01:23:28,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:28,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:28,294 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:28,294 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:28,294 INFO L791 eck$LassoCheckResult]: Stem: 817069#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 817009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 816479#L256 assume !(1 == ~main_in1_req_up~0); 816435#L256-2 assume !(1 == ~main_in2_req_up~0); 816437#L267-1 assume !(1 == ~main_sum_req_up~0); 816466#L278-1 assume !(1 == ~main_diff_req_up~0); 816416#L289-1 assume !(1 == ~main_pres_req_up~0); 816417#L300-1 assume !(1 == ~main_dbl_req_up~0); 821976#L311-1 assume !(1 == ~main_zero_req_up~0); 826853#L322-1 assume !(1 == ~main_clk_req_up~0); 826847#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 826848#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 828550#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 828561#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 828560#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 828559#L371-1 assume !(0 == ~main_in1_ev~0); 828558#L376-1 assume !(0 == ~main_in2_ev~0); 828557#L381-1 assume !(0 == ~main_sum_ev~0); 828556#L386-1 assume !(0 == ~main_diff_ev~0); 828555#L391-1 assume !(0 == ~main_pres_ev~0); 828554#L396-1 assume !(0 == ~main_dbl_ev~0); 828553#L401-1 assume !(0 == ~main_zero_ev~0); 828552#L406-1 assume !(0 == ~main_clk_ev~0); 828551#L411-1 assume !(0 == ~main_clk_pos_edge~0); 828536#L416-1 assume !(0 == ~main_clk_neg_edge~0); 828533#L421-1 assume !(1 == ~main_clk_pos_edge~0); 828530#L426-1 assume !(1 == ~main_clk_pos_edge~0); 828527#L431-1 assume !(1 == ~main_clk_pos_edge~0); 828524#L436-1 assume !(1 == ~main_clk_pos_edge~0); 828521#L441-1 assume !(1 == ~main_clk_pos_edge~0); 828518#L446-1 assume !(1 == ~main_in1_ev~0); 828515#L451-1 assume !(1 == ~main_in2_ev~0); 828512#L456-1 assume !(1 == ~main_sum_ev~0); 828509#L461-1 assume !(1 == ~main_diff_ev~0); 828506#L466-1 assume !(1 == ~main_pres_ev~0); 828503#L471-1 assume !(1 == ~main_dbl_ev~0); 828500#L476-1 assume !(1 == ~main_zero_ev~0); 828497#L481-1 assume !(1 == ~main_clk_ev~0); 828494#L486-1 assume !(1 == ~main_clk_pos_edge~0); 828445#L491-1 assume !(1 == ~main_clk_neg_edge~0); 828341#L742-1 [2021-12-07 01:23:28,294 INFO L793 eck$LassoCheckResult]: Loop: 828341#L742-1 assume !false; 828342#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 828330#L229 assume !false; 828331#L147 assume !(0 == ~N_generate_st~0); 821912#L151 assume !(0 == ~S1_addsub_st~0); 821909#L154 assume !(0 == ~S2_presdbl_st~0); 821908#L157 assume !(0 == ~S3_zero_st~0); 821905#L160 assume !(0 == ~D_print_st~0); 821903#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 821900#L509 assume !(1 == ~main_in1_req_up~0); 821896#L509-2 assume !(1 == ~main_in2_req_up~0); 821897#L520-1 assume !(1 == ~main_sum_req_up~0); 828325#L531-1 assume !(1 == ~main_diff_req_up~0); 828323#L542-1 assume !(1 == ~main_pres_req_up~0); 828319#L553-1 assume !(1 == ~main_dbl_req_up~0); 828315#L564-1 assume !(1 == ~main_zero_req_up~0); 828312#L575-1 assume !(1 == ~main_clk_req_up~0); 828313#L586-1 start_simulation_~kernel_st~0#1 := 3; 828565#L605 assume !(0 == ~main_in1_ev~0); 828564#L605-2 assume !(0 == ~main_in2_ev~0); 828563#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 828562#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 828537#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 828534#L625-1 assume !(0 == ~main_dbl_ev~0); 828531#L630-1 assume !(0 == ~main_zero_ev~0); 828528#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 828525#L640-1 assume !(0 == ~main_clk_pos_edge~0); 828522#L645-1 assume !(0 == ~main_clk_neg_edge~0); 828519#L650-1 assume !(1 == ~main_clk_pos_edge~0); 828516#L655-1 assume !(1 == ~main_clk_pos_edge~0); 828513#L660-1 assume !(1 == ~main_clk_pos_edge~0); 828510#L665-1 assume !(1 == ~main_clk_pos_edge~0); 828507#L670-1 assume !(1 == ~main_clk_pos_edge~0); 828504#L675-1 assume !(1 == ~main_in1_ev~0); 828501#L680-1 assume !(1 == ~main_in2_ev~0); 828498#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 828495#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 828448#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 828444#L700-1 assume !(1 == ~main_dbl_ev~0); 828441#L705-1 assume !(1 == ~main_zero_ev~0); 828437#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 828436#L715-1 assume !(1 == ~main_clk_pos_edge~0); 828403#L720-1 assume !(1 == ~main_clk_neg_edge~0); 828400#L725-1 assume !(0 == ~N_generate_st~0); 828397#L733 assume !(0 == ~S1_addsub_st~0); 828394#L736 assume !(0 == ~S2_presdbl_st~0); 828387#L739 assume 0 == ~S3_zero_st~0; 828341#L742-1 [2021-12-07 01:23:28,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:28,294 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2021-12-07 01:23:28,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:28,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163347728] [2021-12-07 01:23:28,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:28,295 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:28,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:28,299 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:28,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:28,307 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:28,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:28,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1154683687, now seen corresponding path program 1 times [2021-12-07 01:23:28,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:28,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092196646] [2021-12-07 01:23:28,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:28,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:28,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:28,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:28,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:28,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092196646] [2021-12-07 01:23:28,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092196646] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:28,319 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:28,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:28,319 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229617670] [2021-12-07 01:23:28,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:28,319 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:28,319 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:28,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:28,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:28,320 INFO L87 Difference]: Start difference. First operand 91777 states and 136566 transitions. cyclomatic complexity: 44885 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:28,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:28,634 INFO L93 Difference]: Finished difference Result 147978 states and 218783 transitions. [2021-12-07 01:23:28,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:28,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147978 states and 218783 transitions. [2021-12-07 01:23:29,122 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2021-12-07 01:23:29,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147978 states to 147978 states and 218783 transitions. [2021-12-07 01:23:29,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147978 [2021-12-07 01:23:29,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147978 [2021-12-07 01:23:29,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147978 states and 218783 transitions. [2021-12-07 01:23:29,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:29,567 INFO L681 BuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2021-12-07 01:23:29,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147978 states and 218783 transitions. [2021-12-07 01:23:30,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147978 to 147978. [2021-12-07 01:23:30,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147978 states, 147978 states have (on average 1.4784832880563328) internal successors, (218783), 147977 states have internal predecessors, (218783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:30,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147978 states to 147978 states and 218783 transitions. [2021-12-07 01:23:30,997 INFO L704 BuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2021-12-07 01:23:30,997 INFO L587 BuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2021-12-07 01:23:30,997 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-07 01:23:30,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147978 states and 218783 transitions. [2021-12-07 01:23:31,401 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2021-12-07 01:23:31,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:31,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:31,402 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:31,402 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:31,402 INFO L791 eck$LassoCheckResult]: Stem: 1056893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1056824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1056239#L256 assume !(1 == ~main_in1_req_up~0); 1056195#L256-2 assume !(1 == ~main_in2_req_up~0); 1056197#L267-1 assume !(1 == ~main_sum_req_up~0); 1056226#L278-1 assume !(1 == ~main_diff_req_up~0); 1056177#L289-1 assume !(1 == ~main_pres_req_up~0); 1056178#L300-1 assume !(1 == ~main_dbl_req_up~0); 1058333#L311-1 assume !(1 == ~main_zero_req_up~0); 1058334#L322-1 assume !(1 == ~main_clk_req_up~0); 1061675#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1061676#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1061680#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1061800#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1061801#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1061946#L371-1 assume !(0 == ~main_in1_ev~0); 1061944#L376-1 assume !(0 == ~main_in2_ev~0); 1061942#L381-1 assume !(0 == ~main_sum_ev~0); 1061940#L386-1 assume !(0 == ~main_diff_ev~0); 1061938#L391-1 assume !(0 == ~main_pres_ev~0); 1061936#L396-1 assume !(0 == ~main_dbl_ev~0); 1061934#L401-1 assume !(0 == ~main_zero_ev~0); 1061932#L406-1 assume !(0 == ~main_clk_ev~0); 1061930#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1061928#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1061926#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1061924#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1061922#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1061920#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1061918#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1061916#L446-1 assume !(1 == ~main_in1_ev~0); 1061914#L451-1 assume !(1 == ~main_in2_ev~0); 1061912#L456-1 assume !(1 == ~main_sum_ev~0); 1061910#L461-1 assume !(1 == ~main_diff_ev~0); 1061908#L466-1 assume !(1 == ~main_pres_ev~0); 1061906#L471-1 assume !(1 == ~main_dbl_ev~0); 1061904#L476-1 assume !(1 == ~main_zero_ev~0); 1061902#L481-1 assume !(1 == ~main_clk_ev~0); 1061900#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1061897#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1061896#L742-1 [2021-12-07 01:23:31,402 INFO L793 eck$LassoCheckResult]: Loop: 1061896#L742-1 assume !false; 1061476#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1061466#L229 assume !false; 1060898#L147 assume !(0 == ~N_generate_st~0); 1060726#L151 assume !(0 == ~S1_addsub_st~0); 1060719#L154 assume !(0 == ~S2_presdbl_st~0); 1056188#L157 assume !(0 == ~S3_zero_st~0); 1056189#L160 assume !(0 == ~D_print_st~0); 1056637#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1056638#L509 assume !(1 == ~main_in1_req_up~0); 1056665#L509-2 assume !(1 == ~main_in2_req_up~0); 1057380#L520-1 assume !(1 == ~main_sum_req_up~0); 1058129#L531-1 assume !(1 == ~main_diff_req_up~0); 1058122#L542-1 assume !(1 == ~main_pres_req_up~0); 1058121#L553-1 assume !(1 == ~main_dbl_req_up~0); 1058097#L564-1 assume !(1 == ~main_zero_req_up~0); 1058098#L575-1 assume !(1 == ~main_clk_req_up~0); 1061953#L586-1 start_simulation_~kernel_st~0#1 := 3; 1061952#L605 assume !(0 == ~main_in1_ev~0); 1061951#L605-2 assume !(0 == ~main_in2_ev~0); 1061950#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 1061949#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1061948#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1061947#L625-1 assume !(0 == ~main_dbl_ev~0); 1061945#L630-1 assume !(0 == ~main_zero_ev~0); 1061943#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1061941#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1061939#L645-1 assume !(0 == ~main_clk_neg_edge~0); 1061937#L650-1 assume !(1 == ~main_clk_pos_edge~0); 1061935#L655-1 assume !(1 == ~main_clk_pos_edge~0); 1061933#L660-1 assume !(1 == ~main_clk_pos_edge~0); 1061931#L665-1 assume !(1 == ~main_clk_pos_edge~0); 1061929#L670-1 assume !(1 == ~main_clk_pos_edge~0); 1061927#L675-1 assume !(1 == ~main_in1_ev~0); 1061925#L680-1 assume !(1 == ~main_in2_ev~0); 1061923#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1061921#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1061919#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1061917#L700-1 assume !(1 == ~main_dbl_ev~0); 1061915#L705-1 assume !(1 == ~main_zero_ev~0); 1061913#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1061911#L715-1 assume !(1 == ~main_clk_pos_edge~0); 1061909#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1061907#L725-1 assume !(0 == ~N_generate_st~0); 1061905#L733 assume !(0 == ~S1_addsub_st~0); 1061903#L736 assume !(0 == ~S2_presdbl_st~0); 1061901#L739 assume !(0 == ~S3_zero_st~0); 1061898#L742 assume 0 == ~D_print_st~0; 1061896#L742-1 [2021-12-07 01:23:31,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:31,403 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 7 times [2021-12-07 01:23:31,403 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:31,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721505083] [2021-12-07 01:23:31,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:31,403 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:31,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:31,410 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:31,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:31,423 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:31,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:31,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1435455170, now seen corresponding path program 1 times [2021-12-07 01:23:31,424 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:31,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439800603] [2021-12-07 01:23:31,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:31,424 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:31,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:31,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:31,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:31,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439800603] [2021-12-07 01:23:31,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439800603] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:31,436 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:31,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:23:31,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769421329] [2021-12-07 01:23:31,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:31,436 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:31,436 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:31,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:31,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:31,437 INFO L87 Difference]: Start difference. First operand 147978 states and 218783 transitions. cyclomatic complexity: 70949 Second operand has 3 states, 2 states have (on average 24.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:32,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:32,106 INFO L93 Difference]: Finished difference Result 253411 states and 370695 transitions. [2021-12-07 01:23:32,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:32,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253411 states and 370695 transitions. [2021-12-07 01:23:33,115 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2021-12-07 01:23:33,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253411 states to 253411 states and 370695 transitions. [2021-12-07 01:23:33,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253411 [2021-12-07 01:23:33,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253411 [2021-12-07 01:23:33,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253411 states and 370695 transitions. [2021-12-07 01:23:33,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:33,992 INFO L681 BuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2021-12-07 01:23:34,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253411 states and 370695 transitions. [2021-12-07 01:23:36,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253411 to 253411. [2021-12-07 01:23:36,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253411 states, 253411 states have (on average 1.4628212666379912) internal successors, (370695), 253410 states have internal predecessors, (370695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:37,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253411 states to 253411 states and 370695 transitions. [2021-12-07 01:23:37,400 INFO L704 BuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2021-12-07 01:23:37,400 INFO L587 BuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2021-12-07 01:23:37,400 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-07 01:23:37,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253411 states and 370695 transitions. [2021-12-07 01:23:38,030 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2021-12-07 01:23:38,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:38,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:38,031 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:38,031 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:38,031 INFO L791 eck$LassoCheckResult]: Stem: 1458266#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1458195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1457634#L256 assume !(1 == ~main_in1_req_up~0); 1457590#L256-2 assume !(1 == ~main_in2_req_up~0); 1457592#L267-1 assume !(1 == ~main_sum_req_up~0); 1457621#L278-1 assume !(1 == ~main_diff_req_up~0); 1457572#L289-1 assume !(1 == ~main_pres_req_up~0); 1457573#L300-1 assume !(1 == ~main_dbl_req_up~0); 1462589#L311-1 assume !(1 == ~main_zero_req_up~0); 1467522#L322-1 assume !(1 == ~main_clk_req_up~0); 1485585#L333-1 assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0; 1486049#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1486050#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1486074#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1486075#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1486094#L371-1 assume !(0 == ~main_in1_ev~0); 1486093#L376-1 assume !(0 == ~main_in2_ev~0); 1486092#L381-1 assume !(0 == ~main_sum_ev~0); 1486091#L386-1 assume !(0 == ~main_diff_ev~0); 1486090#L391-1 assume !(0 == ~main_pres_ev~0); 1486089#L396-1 assume !(0 == ~main_dbl_ev~0); 1486088#L401-1 assume !(0 == ~main_zero_ev~0); 1486087#L406-1 assume !(0 == ~main_clk_ev~0); 1486086#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1486085#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1486077#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1486076#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1486055#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1486054#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1486053#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1486051#L446-1 assume !(1 == ~main_in1_ev~0); 1486048#L451-1 assume !(1 == ~main_in2_ev~0); 1485923#L456-1 assume !(1 == ~main_sum_ev~0); 1485920#L461-1 assume !(1 == ~main_diff_ev~0); 1485918#L466-1 assume !(1 == ~main_pres_ev~0); 1485916#L471-1 assume !(1 == ~main_dbl_ev~0); 1485914#L476-1 assume !(1 == ~main_zero_ev~0); 1485912#L481-1 assume !(1 == ~main_clk_ev~0); 1485910#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1485908#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1485905#L742-1 assume !false; 1485776#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1485705#L229 [2021-12-07 01:23:38,031 INFO L793 eck$LassoCheckResult]: Loop: 1485705#L229 assume !false; 1485696#L147 assume 0 == ~N_generate_st~0; 1485682#L160-1 assume 0 == ~N_generate_st~0;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1; 1485670#L173 assume !(0 != eval_~tmp~0#1); 1485671#L169 assume 0 == ~S1_addsub_st~0;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1485849#L188 assume !(0 != eval_~tmp___0~0#1); 1485840#L184 assume !(0 == ~S2_presdbl_st~0); 1485836#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1485831#L218 assume !(0 != eval_~tmp___2~0#1); 1485828#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1485774#L233 assume !(0 != eval_~tmp___3~0#1); 1485705#L229 [2021-12-07 01:23:38,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:38,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1897430713, now seen corresponding path program 1 times [2021-12-07 01:23:38,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:38,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317946548] [2021-12-07 01:23:38,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:38,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:38,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:38,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:38,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:38,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317946548] [2021-12-07 01:23:38,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317946548] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:38,046 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:38,046 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:38,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124450239] [2021-12-07 01:23:38,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:38,047 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:38,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:38,047 INFO L85 PathProgramCache]: Analyzing trace with hash 263530038, now seen corresponding path program 1 times [2021-12-07 01:23:38,047 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:38,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699194644] [2021-12-07 01:23:38,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:38,047 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:38,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:38,049 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:38,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:38,052 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:38,117 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:38,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:38,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:38,118 INFO L87 Difference]: Start difference. First operand 253411 states and 370695 transitions. cyclomatic complexity: 117508 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:38,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:38,568 INFO L93 Difference]: Finished difference Result 152871 states and 223090 transitions. [2021-12-07 01:23:38,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:38,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152871 states and 223090 transitions. [2021-12-07 01:23:39,046 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2021-12-07 01:23:39,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152871 states to 152871 states and 223090 transitions. [2021-12-07 01:23:39,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152871 [2021-12-07 01:23:39,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152871 [2021-12-07 01:23:39,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152871 states and 223090 transitions. [2021-12-07 01:23:39,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:39,541 INFO L681 BuchiCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2021-12-07 01:23:39,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152871 states and 223090 transitions. [2021-12-07 01:23:40,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152871 to 152871. [2021-12-07 01:23:40,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152871 states, 152871 states have (on average 1.4593349948649514) internal successors, (223090), 152870 states have internal predecessors, (223090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:40,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152871 states to 152871 states and 223090 transitions. [2021-12-07 01:23:40,777 INFO L704 BuchiCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2021-12-07 01:23:40,777 INFO L587 BuchiCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2021-12-07 01:23:40,777 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-07 01:23:40,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152871 states and 223090 transitions. [2021-12-07 01:23:41,225 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2021-12-07 01:23:41,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:41,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:41,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:41,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:41,226 INFO L791 eck$LassoCheckResult]: Stem: 1864555#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1864493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1863927#L256 assume !(1 == ~main_in1_req_up~0); 1863882#L256-2 assume !(1 == ~main_in2_req_up~0); 1863884#L267-1 assume !(1 == ~main_sum_req_up~0); 1864416#L278-1 assume !(1 == ~main_diff_req_up~0); 1864026#L289-1 assume !(1 == ~main_pres_req_up~0); 1864343#L300-1 assume !(1 == ~main_dbl_req_up~0); 1863977#L311-1 assume !(1 == ~main_zero_req_up~0); 1864166#L322-1 assume !(1 == ~main_clk_req_up~0); 1904030#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1904027#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1904025#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1904022#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1904023#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1904039#L371-1 assume !(0 == ~main_in1_ev~0); 1904038#L376-1 assume !(0 == ~main_in2_ev~0); 1904037#L381-1 assume !(0 == ~main_sum_ev~0); 1904035#L386-1 assume !(0 == ~main_diff_ev~0); 1904034#L391-1 assume !(0 == ~main_pres_ev~0); 1904031#L396-1 assume !(0 == ~main_dbl_ev~0); 1904029#L401-1 assume !(0 == ~main_zero_ev~0); 1904026#L406-1 assume !(0 == ~main_clk_ev~0); 1904024#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1904021#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1904018#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1904016#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1904014#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1904012#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1904010#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1904008#L446-1 assume !(1 == ~main_in1_ev~0); 1904006#L451-1 assume !(1 == ~main_in2_ev~0); 1904004#L456-1 assume !(1 == ~main_sum_ev~0); 1904002#L461-1 assume !(1 == ~main_diff_ev~0); 1904000#L466-1 assume !(1 == ~main_pres_ev~0); 1903998#L471-1 assume !(1 == ~main_dbl_ev~0); 1903996#L476-1 assume !(1 == ~main_zero_ev~0); 1903994#L481-1 assume !(1 == ~main_clk_ev~0); 1903992#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1903990#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1903988#L742-1 assume !false; 1903986#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1903982#L229 [2021-12-07 01:23:41,226 INFO L793 eck$LassoCheckResult]: Loop: 1903982#L229 assume !false; 1903980#L147 assume !(0 == ~N_generate_st~0); 1903977#L151 assume 0 == ~S1_addsub_st~0; 1903975#L160-1 assume !(0 == ~N_generate_st~0); 1903972#L169 assume 0 == ~S1_addsub_st~0;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1903969#L188 assume !(0 != eval_~tmp___0~0#1); 1903967#L184 assume !(0 == ~S2_presdbl_st~0); 1903965#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1903963#L218 assume !(0 != eval_~tmp___2~0#1); 1903964#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1903984#L233 assume !(0 != eval_~tmp___3~0#1); 1903982#L229 [2021-12-07 01:23:41,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:41,226 INFO L85 PathProgramCache]: Analyzing trace with hash -2122776969, now seen corresponding path program 1 times [2021-12-07 01:23:41,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:41,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9580546] [2021-12-07 01:23:41,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:41,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:41,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:41,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:41,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:41,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9580546] [2021-12-07 01:23:41,241 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9580546] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:41,241 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:41,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:41,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617970389] [2021-12-07 01:23:41,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:41,241 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:41,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:41,241 INFO L85 PathProgramCache]: Analyzing trace with hash 105804796, now seen corresponding path program 1 times [2021-12-07 01:23:41,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:41,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4546989] [2021-12-07 01:23:41,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:41,241 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:41,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:41,243 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:41,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:41,245 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:41,282 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:41,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:41,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:41,283 INFO L87 Difference]: Start difference. First operand 152871 states and 223090 transitions. cyclomatic complexity: 70315 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:41,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:41,565 INFO L93 Difference]: Finished difference Result 109199 states and 158994 transitions. [2021-12-07 01:23:41,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:41,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109199 states and 158994 transitions. [2021-12-07 01:23:42,027 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2021-12-07 01:23:42,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109199 states to 109199 states and 158994 transitions. [2021-12-07 01:23:42,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109199 [2021-12-07 01:23:42,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109199 [2021-12-07 01:23:42,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109199 states and 158994 transitions. [2021-12-07 01:23:42,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:42,321 INFO L681 BuchiCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2021-12-07 01:23:42,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109199 states and 158994 transitions. [2021-12-07 01:23:43,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109199 to 109199. [2021-12-07 01:23:43,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109199 states, 109199 states have (on average 1.4560023443438126) internal successors, (158994), 109198 states have internal predecessors, (158994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:43,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109199 states to 109199 states and 158994 transitions. [2021-12-07 01:23:43,430 INFO L704 BuchiCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2021-12-07 01:23:43,430 INFO L587 BuchiCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2021-12-07 01:23:43,430 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-07 01:23:43,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109199 states and 158994 transitions. [2021-12-07 01:23:43,801 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2021-12-07 01:23:43,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:43,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:43,801 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:43,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:43,802 INFO L791 eck$LassoCheckResult]: Stem: 2126666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2126597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2126007#L256 assume !(1 == ~main_in1_req_up~0); 2125962#L256-2 assume !(1 == ~main_in2_req_up~0); 2125964#L267-1 assume !(1 == ~main_sum_req_up~0); 2125993#L278-1 assume !(1 == ~main_diff_req_up~0); 2125944#L289-1 assume !(1 == ~main_pres_req_up~0); 2125945#L300-1 assume !(1 == ~main_dbl_req_up~0); 2128392#L311-1 assume !(1 == ~main_zero_req_up~0); 2128383#L322-1 assume !(1 == ~main_clk_req_up~0); 2128384#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2129999#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2129998#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2129996#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 2129994#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 2129995#L371-1 assume !(0 == ~main_in1_ev~0); 2130045#L376-1 assume !(0 == ~main_in2_ev~0); 2130044#L381-1 assume !(0 == ~main_sum_ev~0); 2130043#L386-1 assume !(0 == ~main_diff_ev~0); 2130042#L391-1 assume !(0 == ~main_pres_ev~0); 2130041#L396-1 assume !(0 == ~main_dbl_ev~0); 2130040#L401-1 assume !(0 == ~main_zero_ev~0); 2130039#L406-1 assume !(0 == ~main_clk_ev~0); 2130038#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2130036#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2130032#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2130028#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2130024#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2130020#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2130016#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2130012#L446-1 assume !(1 == ~main_in1_ev~0); 2130008#L451-1 assume !(1 == ~main_in2_ev~0); 2130004#L456-1 assume !(1 == ~main_sum_ev~0); 2130000#L461-1 assume !(1 == ~main_diff_ev~0); 2129980#L466-1 assume !(1 == ~main_pres_ev~0); 2129976#L471-1 assume !(1 == ~main_dbl_ev~0); 2129972#L476-1 assume !(1 == ~main_zero_ev~0); 2129968#L481-1 assume !(1 == ~main_clk_ev~0); 2129915#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2129885#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2129876#L742-1 assume !false; 2129872#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2129615#L229 [2021-12-07 01:23:43,802 INFO L793 eck$LassoCheckResult]: Loop: 2129615#L229 assume !false; 2129865#L147 assume !(0 == ~N_generate_st~0); 2129863#L151 assume !(0 == ~S1_addsub_st~0); 2129861#L154 assume !(0 == ~S2_presdbl_st~0); 2129859#L157 assume 0 == ~S3_zero_st~0; 2129856#L160-1 assume !(0 == ~N_generate_st~0); 2129853#L169 assume !(0 == ~S1_addsub_st~0); 2129810#L184 assume !(0 == ~S2_presdbl_st~0); 2129811#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2129812#L218 assume !(0 != eval_~tmp___2~0#1); 2129804#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2129613#L233 assume !(0 != eval_~tmp___3~0#1); 2129615#L229 [2021-12-07 01:23:43,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:43,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1421177095, now seen corresponding path program 1 times [2021-12-07 01:23:43,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:43,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017987717] [2021-12-07 01:23:43,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:43,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:43,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:43,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:43,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:43,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017987717] [2021-12-07 01:23:43,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017987717] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:43,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:43,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:43,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617781063] [2021-12-07 01:23:43,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:43,820 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:43,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:43,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1118247229, now seen corresponding path program 1 times [2021-12-07 01:23:43,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:43,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112824121] [2021-12-07 01:23:43,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:43,821 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:43,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:43,823 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:43,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:43,826 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:43,859 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:43,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:43,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:43,859 INFO L87 Difference]: Start difference. First operand 109199 states and 158994 transitions. cyclomatic complexity: 49859 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:44,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:44,064 INFO L93 Difference]: Finished difference Result 81667 states and 118838 transitions. [2021-12-07 01:23:44,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:44,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81667 states and 118838 transitions. [2021-12-07 01:23:44,314 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 71796 [2021-12-07 01:23:44,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81667 states to 81667 states and 118838 transitions. [2021-12-07 01:23:44,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81667 [2021-12-07 01:23:44,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81667 [2021-12-07 01:23:44,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81667 states and 118838 transitions. [2021-12-07 01:23:44,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:44,552 INFO L681 BuchiCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2021-12-07 01:23:44,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81667 states and 118838 transitions. [2021-12-07 01:23:45,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81667 to 81667. [2021-12-07 01:23:45,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81667 states, 81667 states have (on average 1.4551532442724724) internal successors, (118838), 81666 states have internal predecessors, (118838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:45,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81667 states to 81667 states and 118838 transitions. [2021-12-07 01:23:45,326 INFO L704 BuchiCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2021-12-07 01:23:45,326 INFO L587 BuchiCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2021-12-07 01:23:45,326 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-07 01:23:45,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81667 states and 118838 transitions. [2021-12-07 01:23:45,513 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 71796 [2021-12-07 01:23:45,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:45,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:45,514 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:45,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:45,514 INFO L791 eck$LassoCheckResult]: Stem: 2317517#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2317458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2316883#L256 assume !(1 == ~main_in1_req_up~0); 2316838#L256-2 assume !(1 == ~main_in2_req_up~0); 2316840#L267-1 assume !(1 == ~main_sum_req_up~0); 2316869#L278-1 assume !(1 == ~main_diff_req_up~0); 2316820#L289-1 assume !(1 == ~main_pres_req_up~0); 2316821#L300-1 assume !(1 == ~main_dbl_req_up~0); 2317113#L311-1 assume !(1 == ~main_zero_req_up~0); 2317115#L322-1 assume !(1 == ~main_clk_req_up~0); 2317412#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2331296#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2331294#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2331292#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2331289#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 2331224#L371-1 assume !(0 == ~main_in1_ev~0); 2331222#L376-1 assume !(0 == ~main_in2_ev~0); 2331219#L381-1 assume !(0 == ~main_sum_ev~0); 2331217#L386-1 assume !(0 == ~main_diff_ev~0); 2331215#L391-1 assume !(0 == ~main_pres_ev~0); 2331213#L396-1 assume !(0 == ~main_dbl_ev~0); 2331211#L401-1 assume !(0 == ~main_zero_ev~0); 2331209#L406-1 assume !(0 == ~main_clk_ev~0); 2331201#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2331199#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2331197#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2331195#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2331192#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2331190#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2331188#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2331186#L446-1 assume !(1 == ~main_in1_ev~0); 2331184#L451-1 assume !(1 == ~main_in2_ev~0); 2331182#L456-1 assume !(1 == ~main_sum_ev~0); 2331180#L461-1 assume !(1 == ~main_diff_ev~0); 2331178#L466-1 assume !(1 == ~main_pres_ev~0); 2331176#L471-1 assume !(1 == ~main_dbl_ev~0); 2331174#L476-1 assume !(1 == ~main_zero_ev~0); 2331172#L481-1 assume !(1 == ~main_clk_ev~0); 2331170#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2331168#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2331166#L742-1 assume !false; 2331165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2331133#L229 [2021-12-07 01:23:45,514 INFO L793 eck$LassoCheckResult]: Loop: 2331133#L229 assume !false; 2331164#L147 assume !(0 == ~N_generate_st~0); 2331163#L151 assume !(0 == ~S1_addsub_st~0); 2331162#L154 assume !(0 == ~S2_presdbl_st~0); 2316831#L157 assume !(0 == ~S3_zero_st~0); 2316832#L160 assume 0 == ~D_print_st~0; 2331151#L160-1 assume !(0 == ~N_generate_st~0); 2331147#L169 assume !(0 == ~S1_addsub_st~0); 2331143#L184 assume !(0 == ~S2_presdbl_st~0); 2331139#L199 assume !(0 == ~S3_zero_st~0); 2331134#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2331132#L233 assume !(0 != eval_~tmp___3~0#1); 2331133#L229 [2021-12-07 01:23:45,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:45,514 INFO L85 PathProgramCache]: Analyzing trace with hash -34973701, now seen corresponding path program 1 times [2021-12-07 01:23:45,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:45,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825137659] [2021-12-07 01:23:45,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:45,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:45,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:45,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:45,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:45,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825137659] [2021-12-07 01:23:45,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825137659] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:45,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:45,530 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:45,530 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674447318] [2021-12-07 01:23:45,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:45,531 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:45,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:45,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1420110094, now seen corresponding path program 1 times [2021-12-07 01:23:45,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:45,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105172114] [2021-12-07 01:23:45,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:45,531 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:45,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:45,533 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:45,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:45,535 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:45,554 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:45,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:45,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:45,555 INFO L87 Difference]: Start difference. First operand 81667 states and 118838 transitions. cyclomatic complexity: 37219 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:45,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:45,722 INFO L93 Difference]: Finished difference Result 66199 states and 96067 transitions. [2021-12-07 01:23:45,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:45,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66199 states and 96067 transitions. [2021-12-07 01:23:46,063 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 59042 [2021-12-07 01:23:46,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66199 states to 66199 states and 96067 transitions. [2021-12-07 01:23:46,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66199 [2021-12-07 01:23:46,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66199 [2021-12-07 01:23:46,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66199 states and 96067 transitions. [2021-12-07 01:23:46,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:46,226 INFO L681 BuchiCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2021-12-07 01:23:46,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66199 states and 96067 transitions. [2021-12-07 01:23:46,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66199 to 66199. [2021-12-07 01:23:46,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66199 states, 66199 states have (on average 1.4511850632184775) internal successors, (96067), 66198 states have internal predecessors, (96067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:46,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66199 states to 66199 states and 96067 transitions. [2021-12-07 01:23:46,924 INFO L704 BuchiCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2021-12-07 01:23:46,924 INFO L587 BuchiCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2021-12-07 01:23:46,924 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-07 01:23:46,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66199 states and 96067 transitions. [2021-12-07 01:23:47,083 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 59042 [2021-12-07 01:23:47,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:47,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:47,085 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:47,085 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:47,085 INFO L791 eck$LassoCheckResult]: Stem: 2465434#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2465356#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2464759#L256 assume !(1 == ~main_in1_req_up~0); 2464714#L256-2 assume !(1 == ~main_in2_req_up~0); 2464716#L267-1 assume !(1 == ~main_sum_req_up~0); 2464745#L278-1 assume !(1 == ~main_diff_req_up~0); 2464696#L289-1 assume !(1 == ~main_pres_req_up~0); 2464697#L300-1 assume !(1 == ~main_dbl_req_up~0); 2464807#L311-1 assume !(1 == ~main_zero_req_up~0); 2464992#L322-1 assume 1 == ~main_clk_req_up~0; 2479114#L334 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 2465026#L337 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 2464957#L334-1 ~main_clk_req_up~0 := 0; 2464958#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2464945#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2464946#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2464936#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2464937#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2465553#L371-1 assume !(0 == ~main_in1_ev~0); 2465554#L376-1 assume !(0 == ~main_in2_ev~0); 2504628#L381-1 assume !(0 == ~main_sum_ev~0); 2504629#L386-1 assume !(0 == ~main_diff_ev~0); 2504624#L391-1 assume !(0 == ~main_pres_ev~0); 2504625#L396-1 assume !(0 == ~main_dbl_ev~0); 2506016#L401-1 assume !(0 == ~main_zero_ev~0); 2506219#L406-1 assume !(0 == ~main_clk_ev~0); 2506217#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 2506216#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2506214#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2506212#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2506210#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2506208#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2506209#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2507419#L446-1 assume !(1 == ~main_in1_ev~0); 2507417#L451-1 assume !(1 == ~main_in2_ev~0); 2507414#L456-1 assume !(1 == ~main_sum_ev~0); 2507411#L461-1 assume !(1 == ~main_diff_ev~0); 2507403#L466-1 assume !(1 == ~main_pres_ev~0); 2507400#L471-1 assume !(1 == ~main_dbl_ev~0); 2507395#L476-1 assume !(1 == ~main_zero_ev~0); 2507390#L481-1 assume !(1 == ~main_clk_ev~0); 2507385#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2507379#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2506142#L742-1 [2021-12-07 01:23:47,085 INFO L793 eck$LassoCheckResult]: Loop: 2506142#L742-1 assume !false; 2507362#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2507358#L229 assume !false; 2507356#L147 assume !(0 == ~N_generate_st~0); 2507354#L151 assume !(0 == ~S1_addsub_st~0); 2507355#L154 assume !(0 == ~S2_presdbl_st~0); 2482892#L157 assume !(0 == ~S3_zero_st~0); 2482891#L160 assume !(0 == ~D_print_st~0); 2482890#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2482889#L509 assume !(1 == ~main_in1_req_up~0); 2482886#L509-2 assume !(1 == ~main_in2_req_up~0); 2482883#L520-1 assume !(1 == ~main_sum_req_up~0); 2482879#L531-1 assume !(1 == ~main_diff_req_up~0); 2482877#L542-1 assume !(1 == ~main_pres_req_up~0); 2482873#L553-1 assume !(1 == ~main_dbl_req_up~0); 2482869#L564-1 assume !(1 == ~main_zero_req_up~0); 2482866#L575-1 assume 1 == ~main_clk_req_up~0; 2482864#L587 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 2479548#L590 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 2482863#L587-1 ~main_clk_req_up~0 := 0; 2482927#L586-1 start_simulation_~kernel_st~0#1 := 3; 2482926#L605 assume !(0 == ~main_in1_ev~0); 2482925#L605-2 assume !(0 == ~main_in2_ev~0); 2482924#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2482923#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2482922#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2482921#L625-1 assume !(0 == ~main_dbl_ev~0); 2482920#L630-1 assume !(0 == ~main_zero_ev~0); 2482919#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2482917#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 2482916#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2482914#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2482912#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2482910#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2482908#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2482909#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2506184#L675-1 assume !(1 == ~main_in1_ev~0); 2506181#L680-1 assume !(1 == ~main_in2_ev~0); 2506177#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2506172#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2506168#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2506164#L700-1 assume !(1 == ~main_dbl_ev~0); 2506162#L705-1 assume !(1 == ~main_zero_ev~0); 2482928#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2482929#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2506144#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2506141#L725-1 assume 0 == ~N_generate_st~0; 2506142#L742-1 [2021-12-07 01:23:47,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:47,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1830128562, now seen corresponding path program 1 times [2021-12-07 01:23:47,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:47,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947571574] [2021-12-07 01:23:47,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:47,086 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:47,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:47,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:47,102 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:47,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947571574] [2021-12-07 01:23:47,103 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947571574] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:47,103 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:47,103 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:47,103 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [441026222] [2021-12-07 01:23:47,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:47,103 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:47,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:47,103 INFO L85 PathProgramCache]: Analyzing trace with hash 744593900, now seen corresponding path program 1 times [2021-12-07 01:23:47,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:47,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170087307] [2021-12-07 01:23:47,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:47,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:47,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:47,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:47,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:47,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170087307] [2021-12-07 01:23:47,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170087307] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:47,116 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:47,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:47,117 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253583742] [2021-12-07 01:23:47,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:47,117 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:47,117 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:47,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:47,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:47,117 INFO L87 Difference]: Start difference. First operand 66199 states and 96067 transitions. cyclomatic complexity: 29908 Second operand has 4 states, 4 states have (on average 10.75) internal successors, (43), 4 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:47,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:47,244 INFO L93 Difference]: Finished difference Result 38411 states and 55018 transitions. [2021-12-07 01:23:47,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:47,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38411 states and 55018 transitions. [2021-12-07 01:23:47,379 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:47,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38411 states to 38411 states and 55018 transitions. [2021-12-07 01:23:47,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38411 [2021-12-07 01:23:47,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38411 [2021-12-07 01:23:47,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38411 states and 55018 transitions. [2021-12-07 01:23:47,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:47,508 INFO L681 BuchiCegarLoop]: Abstraction has 38411 states and 55018 transitions. [2021-12-07 01:23:47,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38411 states and 55018 transitions. [2021-12-07 01:23:47,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38411 to 38395. [2021-12-07 01:23:47,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.4325302773798672) internal successors, (55002), 38394 states have internal predecessors, (55002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:47,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 55002 transitions. [2021-12-07 01:23:47,909 INFO L704 BuchiCegarLoop]: Abstraction has 38395 states and 55002 transitions. [2021-12-07 01:23:47,909 INFO L587 BuchiCegarLoop]: Abstraction has 38395 states and 55002 transitions. [2021-12-07 01:23:47,909 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-07 01:23:47,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 55002 transitions. [2021-12-07 01:23:48,006 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:48,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:48,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:48,008 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:48,008 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:48,008 INFO L791 eck$LassoCheckResult]: Stem: 2569949#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2569888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2569368#L256 assume !(1 == ~main_in1_req_up~0); 2569333#L256-2 assume !(1 == ~main_in2_req_up~0); 2569335#L267-1 assume !(1 == ~main_sum_req_up~0); 2569358#L278-1 assume !(1 == ~main_diff_req_up~0); 2569317#L289-1 assume !(1 == ~main_pres_req_up~0); 2569318#L300-1 assume !(1 == ~main_dbl_req_up~0); 2569413#L311-1 assume !(1 == ~main_zero_req_up~0); 2570221#L322-1 assume !(1 == ~main_clk_req_up~0); 2570265#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2570342#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2570341#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2570340#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2570255#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2570256#L371-1 assume !(0 == ~main_in1_ev~0); 2569396#L376-1 assume !(0 == ~main_in2_ev~0); 2569397#L381-1 assume !(0 == ~main_sum_ev~0); 2569561#L386-1 assume !(0 == ~main_diff_ev~0); 2569562#L391-1 assume !(0 == ~main_pres_ev~0); 2569718#L396-1 assume !(0 == ~main_dbl_ev~0); 2569719#L401-1 assume !(0 == ~main_zero_ev~0); 2578503#L406-1 assume !(0 == ~main_clk_ev~0); 2578502#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2578500#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2578497#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2578495#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2578494#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2578493#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2578490#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2578486#L446-1 assume !(1 == ~main_in1_ev~0); 2578479#L451-1 assume !(1 == ~main_in2_ev~0); 2578472#L456-1 assume !(1 == ~main_sum_ev~0); 2578465#L461-1 assume !(1 == ~main_diff_ev~0); 2578019#L466-1 assume !(1 == ~main_pres_ev~0); 2577945#L471-1 assume !(1 == ~main_dbl_ev~0); 2577941#L476-1 assume !(1 == ~main_zero_ev~0); 2577940#L481-1 assume !(1 == ~main_clk_ev~0); 2577938#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2577935#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2577933#L742-1 assume !false; 2577867#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2577750#L229 assume !false; 2577748#L147 assume !(0 == ~N_generate_st~0); 2577746#L151 assume !(0 == ~S1_addsub_st~0); 2577744#L154 assume !(0 == ~S2_presdbl_st~0); 2577742#L157 assume !(0 == ~S3_zero_st~0); 2577740#L160 assume !(0 == ~D_print_st~0); 2577738#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2577672#L509 assume !(1 == ~main_in1_req_up~0); 2577667#L509-2 assume !(1 == ~main_in2_req_up~0); 2577661#L520-1 assume !(1 == ~main_sum_req_up~0); 2577656#L531-1 assume !(1 == ~main_diff_req_up~0); 2577653#L542-1 assume !(1 == ~main_pres_req_up~0); 2577486#L553-1 assume !(1 == ~main_dbl_req_up~0); 2577385#L564-1 assume !(1 == ~main_zero_req_up~0); 2577380#L575-1 assume !(1 == ~main_clk_req_up~0); 2577379#L586-1 start_simulation_~kernel_st~0#1 := 3; 2577378#L605 assume !(0 == ~main_in1_ev~0); 2577377#L605-2 assume !(0 == ~main_in2_ev~0); 2577376#L610-1 assume !(0 == ~main_sum_ev~0); 2577375#L615-1 assume !(0 == ~main_diff_ev~0); 2577374#L620-1 assume !(0 == ~main_pres_ev~0); 2577373#L625-1 assume !(0 == ~main_dbl_ev~0); 2577371#L630-1 assume !(0 == ~main_zero_ev~0); 2577369#L635-1 assume !(0 == ~main_clk_ev~0); 2577367#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2577365#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2577356#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2577355#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2577354#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2577353#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2577351#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2577350#L675-1 assume !(1 == ~main_in1_ev~0); 2577349#L680-1 assume !(1 == ~main_in2_ev~0); 2577346#L685-1 assume !(1 == ~main_sum_ev~0); 2577344#L690-1 assume !(1 == ~main_diff_ev~0); 2577342#L695-1 assume !(1 == ~main_pres_ev~0); 2577340#L700-1 assume !(1 == ~main_dbl_ev~0); 2577338#L705-1 assume !(1 == ~main_zero_ev~0); 2577337#L710-1 assume !(1 == ~main_clk_ev~0); 2577336#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2577335#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2577334#L725-1 assume !(0 == ~N_generate_st~0); 2577333#L733 assume !(0 == ~S1_addsub_st~0); 2577331#L736 assume !(0 == ~S2_presdbl_st~0); 2577328#L739 assume !(0 == ~S3_zero_st~0); 2577324#L742 assume !(0 == ~D_print_st~0); 2577310#L752 assume { :end_inline_start_simulation } true; 2577308#L795-2 [2021-12-07 01:23:48,009 INFO L793 eck$LassoCheckResult]: Loop: 2577308#L795-2 assume !false; 2577306#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2577304#L256-3 assume !(1 == ~main_in1_req_up~0); 2577300#L256-5 assume !(1 == ~main_in2_req_up~0); 2577301#L267-3 assume !(1 == ~main_sum_req_up~0); 2577326#L278-3 assume !(1 == ~main_diff_req_up~0); 2577241#L289-3 assume !(1 == ~main_pres_req_up~0); 2577237#L300-3 assume !(1 == ~main_dbl_req_up~0); 2577233#L311-3 assume !(1 == ~main_zero_req_up~0); 2577234#L322-3 assume !(1 == ~main_clk_req_up~0); 2577345#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2577343#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2577341#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2577339#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2577243#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2577239#L371-3 assume !(0 == ~main_in1_ev~0); 2577235#L376-3 assume !(0 == ~main_in2_ev~0); 2577209#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2577208#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2577206#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2577205#L396-3 assume !(0 == ~main_dbl_ev~0); 2577204#L401-3 assume !(0 == ~main_zero_ev~0); 2577200#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2577196#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2577152#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2577148#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2577113#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2577111#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2577109#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2577107#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2577103#L446-3 assume !(1 == ~main_in1_ev~0); 2577099#L451-3 assume !(1 == ~main_in2_ev~0); 2577097#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2577086#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2577085#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2577083#L471-3 assume !(1 == ~main_dbl_ev~0); 2577081#L476-3 assume !(1 == ~main_zero_ev~0); 2577079#L481-3 assume !(1 == ~main_clk_ev~0); 2577077#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2577075#L491-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2577061#L742-3 assume !false; 2577055#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2577050#L229-1 assume !false; 2577044#L147-1 assume !(0 == ~N_generate_st~0); 2577037#L151-2 assume !(0 == ~S1_addsub_st~0); 2577014#L154-2 assume !(0 == ~S2_presdbl_st~0); 2576773#L157-2 assume !(0 == ~S3_zero_st~0); 2576774#L160-2 assume !(0 == ~D_print_st~0); 2576764#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2576765#L509-3 assume !(1 == ~main_in1_req_up~0); 2576754#L509-5 assume !(1 == ~main_in2_req_up~0); 2576755#L520-3 assume !(1 == ~main_sum_req_up~0); 2577693#L531-3 assume !(1 == ~main_diff_req_up~0); 2577512#L542-3 assume !(1 == ~main_pres_req_up~0); 2577508#L553-3 assume !(1 == ~main_dbl_req_up~0); 2577504#L564-3 assume !(1 == ~main_zero_req_up~0); 2577505#L575-3 assume !(1 == ~main_clk_req_up~0); 2577633#L586-3 start_simulation_~kernel_st~0#1 := 3; 2577631#L605-3 assume !(0 == ~main_in1_ev~0); 2577629#L605-5 assume !(0 == ~main_in2_ev~0); 2577627#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2577625#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2577622#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2577620#L625-3 assume !(0 == ~main_dbl_ev~0); 2577616#L630-3 assume !(0 == ~main_zero_ev~0); 2577612#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2577607#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2577603#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2577599#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2577597#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2577595#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2577593#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2577590#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2577588#L675-3 assume !(1 == ~main_in1_ev~0); 2577586#L680-3 assume !(1 == ~main_in2_ev~0); 2577584#L685-3 assume !(1 == ~main_sum_ev~0); 2577582#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2577580#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2577578#L700-3 assume !(1 == ~main_dbl_ev~0); 2577576#L705-3 assume !(1 == ~main_zero_ev~0); 2577574#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2577572#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2577570#L720-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2577568#L725-3 assume !(0 == ~N_generate_st~0); 2577566#L733-2 assume !(0 == ~S1_addsub_st~0); 2577564#L736-2 assume !(0 == ~S2_presdbl_st~0); 2577562#L739-2 assume !(0 == ~S3_zero_st~0); 2577561#L742-2 assume !(0 == ~D_print_st~0); 2577560#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2577558#L803 assume !(5 == main_~count~0#1); 2577556#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2577555#L256-6 assume !(1 == ~main_in1_req_up~0); 2577553#L256-8 assume !(1 == ~main_in2_req_up~0); 2577554#L267-5 assume !(1 == ~main_sum_req_up~0); 2578487#L278-5 assume !(1 == ~main_diff_req_up~0); 2578482#L289-5 assume !(1 == ~main_pres_req_up~0); 2578474#L300-5 assume !(1 == ~main_dbl_req_up~0); 2578466#L311-5 assume !(1 == ~main_zero_req_up~0); 2578467#L322-5 assume !(1 == ~main_clk_req_up~0); 2578496#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2578055#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2578053#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2578052#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2578051#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2578050#L371-5 assume !(0 == ~main_in1_ev~0); 2578049#L376-5 assume !(0 == ~main_in2_ev~0); 2578048#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2578047#L386-5 assume !(0 == ~main_diff_ev~0); 2578046#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2578045#L396-5 assume !(0 == ~main_dbl_ev~0); 2578044#L401-5 assume !(0 == ~main_zero_ev~0); 2578043#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2578042#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2578041#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2578040#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2578039#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2578038#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2578037#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2578036#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2578035#L446-5 assume !(1 == ~main_in1_ev~0); 2578034#L451-5 assume !(1 == ~main_in2_ev~0); 2578033#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2578032#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2578031#L466-5 assume !(1 == ~main_pres_ev~0); 2578030#L471-5 assume !(1 == ~main_dbl_ev~0); 2578029#L476-5 assume !(1 == ~main_zero_ev~0); 2578028#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2578027#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2578026#L491-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2578025#L742-5 assume !false; 2578024#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2578023#L229-2 assume !false; 2578022#L147-2 assume !(0 == ~N_generate_st~0); 2578021#L151-4 assume !(0 == ~S1_addsub_st~0); 2578020#L154-4 assume !(0 == ~S2_presdbl_st~0); 2577965#L157-4 assume !(0 == ~S3_zero_st~0); 2577963#L160-4 assume !(0 == ~D_print_st~0); 2577961#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2577959#L509-6 assume !(1 == ~main_in1_req_up~0); 2577951#L509-8 assume !(1 == ~main_in2_req_up~0); 2577890#L520-5 assume !(1 == ~main_sum_req_up~0); 2577886#L531-5 assume !(1 == ~main_diff_req_up~0); 2577882#L542-5 assume !(1 == ~main_pres_req_up~0); 2577878#L553-5 assume !(1 == ~main_dbl_req_up~0); 2577790#L564-5 assume !(1 == ~main_zero_req_up~0); 2577787#L575-5 assume !(1 == ~main_clk_req_up~0); 2577785#L586-5 start_simulation_~kernel_st~0#1 := 3; 2577783#L605-6 assume !(0 == ~main_in1_ev~0); 2577781#L605-8 assume !(0 == ~main_in2_ev~0); 2577779#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2577777#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2577775#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2577773#L625-5 assume !(0 == ~main_dbl_ev~0); 2577771#L630-5 assume !(0 == ~main_zero_ev~0); 2577769#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2577766#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2577764#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2577762#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2577760#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2577758#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2577756#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2577754#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2577677#L675-5 assume !(1 == ~main_in1_ev~0); 2577496#L680-5 assume !(1 == ~main_in2_ev~0); 2577409#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2577407#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2577406#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2577402#L700-5 assume !(1 == ~main_dbl_ev~0); 2577400#L705-5 assume !(1 == ~main_zero_ev~0); 2577398#L710-5 assume !(1 == ~main_clk_ev~0); 2577396#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2577394#L720-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2577393#L725-5 assume !(0 == ~N_generate_st~0); 2577391#L733-4 assume !(0 == ~S1_addsub_st~0); 2577389#L736-4 assume !(0 == ~S2_presdbl_st~0); 2577388#L739-4 assume !(0 == ~S3_zero_st~0); 2577387#L742-4 assume !(0 == ~D_print_st~0); 2577311#L752-2 assume { :end_inline_start_simulation } true; 2577308#L795-2 [2021-12-07 01:23:48,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:48,009 INFO L85 PathProgramCache]: Analyzing trace with hash 1683661513, now seen corresponding path program 1 times [2021-12-07 01:23:48,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:48,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890119848] [2021-12-07 01:23:48,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:48,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:48,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:48,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:48,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:48,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890119848] [2021-12-07 01:23:48,113 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890119848] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:48,113 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:48,113 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:48,113 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092979007] [2021-12-07 01:23:48,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:48,113 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:48,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:48,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1540905380, now seen corresponding path program 1 times [2021-12-07 01:23:48,114 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:48,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760065739] [2021-12-07 01:23:48,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:48,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:48,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:48,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:48,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:48,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760065739] [2021-12-07 01:23:48,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760065739] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:48,135 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:48,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:48,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407466507] [2021-12-07 01:23:48,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:48,136 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:48,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:48,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:48,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:48,137 INFO L87 Difference]: Start difference. First operand 38395 states and 55002 transitions. cyclomatic complexity: 16631 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:48,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:48,293 INFO L93 Difference]: Finished difference Result 38449 states and 54838 transitions. [2021-12-07 01:23:48,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:23:48,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38449 states and 54838 transitions. [2021-12-07 01:23:48,405 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:48,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38449 states to 38449 states and 54838 transitions. [2021-12-07 01:23:48,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38449 [2021-12-07 01:23:48,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38449 [2021-12-07 01:23:48,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38449 states and 54838 transitions. [2021-12-07 01:23:48,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:48,511 INFO L681 BuchiCegarLoop]: Abstraction has 38449 states and 54838 transitions. [2021-12-07 01:23:48,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38449 states and 54838 transitions. [2021-12-07 01:23:48,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38449 to 38395. [2021-12-07 01:23:48,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.425446021617398) internal successors, (54730), 38394 states have internal predecessors, (54730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:48,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 54730 transitions. [2021-12-07 01:23:48,836 INFO L704 BuchiCegarLoop]: Abstraction has 38395 states and 54730 transitions. [2021-12-07 01:23:48,836 INFO L587 BuchiCegarLoop]: Abstraction has 38395 states and 54730 transitions. [2021-12-07 01:23:48,836 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-07 01:23:48,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 54730 transitions. [2021-12-07 01:23:48,921 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:48,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:48,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:48,922 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:48,922 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:48,923 INFO L791 eck$LassoCheckResult]: Stem: 2646790#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2646740#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2646223#L256 assume !(1 == ~main_in1_req_up~0); 2646188#L256-2 assume !(1 == ~main_in2_req_up~0); 2646190#L267-1 assume !(1 == ~main_sum_req_up~0); 2646213#L278-1 assume !(1 == ~main_diff_req_up~0); 2646172#L289-1 assume !(1 == ~main_pres_req_up~0); 2646173#L300-1 assume !(1 == ~main_dbl_req_up~0); 2646268#L311-1 assume !(1 == ~main_zero_req_up~0); 2646692#L322-1 assume !(1 == ~main_clk_req_up~0); 2646693#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2647168#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2647167#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2647166#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2647085#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2647086#L371-1 assume !(0 == ~main_in1_ev~0); 2646251#L376-1 assume !(0 == ~main_in2_ev~0); 2646252#L381-1 assume !(0 == ~main_sum_ev~0); 2646659#L386-1 assume !(0 == ~main_diff_ev~0); 2646686#L391-1 assume !(0 == ~main_pres_ev~0); 2646687#L396-1 assume !(0 == ~main_dbl_ev~0); 2652361#L401-1 assume !(0 == ~main_zero_ev~0); 2652357#L406-1 assume !(0 == ~main_clk_ev~0); 2652353#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2652349#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2652345#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2652340#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2652335#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2652331#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2652329#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2652327#L446-1 assume !(1 == ~main_in1_ev~0); 2652325#L451-1 assume !(1 == ~main_in2_ev~0); 2652323#L456-1 assume !(1 == ~main_sum_ev~0); 2652321#L461-1 assume !(1 == ~main_diff_ev~0); 2652319#L466-1 assume !(1 == ~main_pres_ev~0); 2652317#L471-1 assume !(1 == ~main_dbl_ev~0); 2652315#L476-1 assume !(1 == ~main_zero_ev~0); 2652313#L481-1 assume !(1 == ~main_clk_ev~0); 2652311#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2652309#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2652307#L742-1 assume !false; 2652305#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2652303#L229 assume !false; 2652301#L147 assume !(0 == ~N_generate_st~0); 2652299#L151 assume !(0 == ~S1_addsub_st~0); 2652297#L154 assume !(0 == ~S2_presdbl_st~0); 2652295#L157 assume !(0 == ~S3_zero_st~0); 2652293#L160 assume !(0 == ~D_print_st~0); 2652291#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2652290#L509 assume !(1 == ~main_in1_req_up~0); 2652287#L509-2 assume !(1 == ~main_in2_req_up~0); 2652284#L520-1 assume !(1 == ~main_sum_req_up~0); 2652280#L531-1 assume !(1 == ~main_diff_req_up~0); 2652278#L542-1 assume !(1 == ~main_pres_req_up~0); 2652274#L553-1 assume !(1 == ~main_dbl_req_up~0); 2652270#L564-1 assume !(1 == ~main_zero_req_up~0); 2652268#L575-1 assume !(1 == ~main_clk_req_up~0); 2652263#L586-1 start_simulation_~kernel_st~0#1 := 3; 2652260#L605 assume !(0 == ~main_in1_ev~0); 2652257#L605-2 assume !(0 == ~main_in2_ev~0); 2652254#L610-1 assume !(0 == ~main_sum_ev~0); 2652250#L615-1 assume !(0 == ~main_diff_ev~0); 2652248#L620-1 assume !(0 == ~main_pres_ev~0); 2652246#L625-1 assume !(0 == ~main_dbl_ev~0); 2652244#L630-1 assume !(0 == ~main_zero_ev~0); 2652242#L635-1 assume !(0 == ~main_clk_ev~0); 2652240#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2652238#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2652236#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2652234#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2652232#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2652230#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2652228#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2652226#L675-1 assume !(1 == ~main_in1_ev~0); 2652224#L680-1 assume !(1 == ~main_in2_ev~0); 2652222#L685-1 assume !(1 == ~main_sum_ev~0); 2652215#L690-1 assume !(1 == ~main_diff_ev~0); 2652209#L695-1 assume !(1 == ~main_pres_ev~0); 2652203#L700-1 assume !(1 == ~main_dbl_ev~0); 2652197#L705-1 assume !(1 == ~main_zero_ev~0); 2652191#L710-1 assume !(1 == ~main_clk_ev~0); 2652185#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2652179#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2652173#L725-1 assume !(0 == ~N_generate_st~0); 2652167#L733 assume !(0 == ~S1_addsub_st~0); 2652161#L736 assume !(0 == ~S2_presdbl_st~0); 2652155#L739 assume !(0 == ~S3_zero_st~0); 2652149#L742 assume !(0 == ~D_print_st~0); 2652143#L752 assume { :end_inline_start_simulation } true; 2652138#L795-2 [2021-12-07 01:23:48,923 INFO L793 eck$LassoCheckResult]: Loop: 2652138#L795-2 assume !false; 2652134#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2652130#L256-3 assume !(1 == ~main_in1_req_up~0); 2652124#L256-5 assume !(1 == ~main_in2_req_up~0); 2652125#L267-3 assume !(1 == ~main_sum_req_up~0); 2653027#L278-3 assume !(1 == ~main_diff_req_up~0); 2653024#L289-3 assume !(1 == ~main_pres_req_up~0); 2653020#L300-3 assume !(1 == ~main_dbl_req_up~0); 2653017#L311-3 assume !(1 == ~main_zero_req_up~0); 2653013#L322-3 assume !(1 == ~main_clk_req_up~0); 2653011#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2653010#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2653009#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2653006#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2653003#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2653000#L371-3 assume !(0 == ~main_in1_ev~0); 2652997#L376-3 assume !(0 == ~main_in2_ev~0); 2652994#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652991#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2652988#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652985#L396-3 assume !(0 == ~main_dbl_ev~0); 2652982#L401-3 assume !(0 == ~main_zero_ev~0); 2652979#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652976#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2652973#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2652970#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2652967#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2652964#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2652961#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2652958#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2652955#L446-3 assume !(1 == ~main_in1_ev~0); 2652952#L451-3 assume !(1 == ~main_in2_ev~0); 2652949#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2652946#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2652944#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2652942#L471-3 assume !(1 == ~main_dbl_ev~0); 2652940#L476-3 assume !(1 == ~main_zero_ev~0); 2652938#L481-3 assume !(1 == ~main_clk_ev~0); 2652936#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2652934#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2652932#L742-3 assume !false; 2652930#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2652928#L229-1 assume !false; 2652926#L147-1 assume !(0 == ~N_generate_st~0); 2652924#L151-2 assume !(0 == ~S1_addsub_st~0); 2652922#L154-2 assume !(0 == ~S2_presdbl_st~0); 2652920#L157-2 assume !(0 == ~S3_zero_st~0); 2652918#L160-2 assume !(0 == ~D_print_st~0); 2652916#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2652914#L509-3 assume !(1 == ~main_in1_req_up~0); 2652912#L509-5 assume !(1 == ~main_in2_req_up~0); 2652907#L520-3 assume !(1 == ~main_sum_req_up~0); 2652900#L531-3 assume !(1 == ~main_diff_req_up~0); 2652891#L542-3 assume !(1 == ~main_pres_req_up~0); 2652880#L553-3 assume !(1 == ~main_dbl_req_up~0); 2652869#L564-3 assume !(1 == ~main_zero_req_up~0); 2652860#L575-3 assume !(1 == ~main_clk_req_up~0); 2652853#L586-3 start_simulation_~kernel_st~0#1 := 3; 2652850#L605-3 assume !(0 == ~main_in1_ev~0); 2652847#L605-5 assume !(0 == ~main_in2_ev~0); 2652844#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652841#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2652838#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652835#L625-3 assume !(0 == ~main_dbl_ev~0); 2652832#L630-3 assume !(0 == ~main_zero_ev~0); 2652829#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652826#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2652823#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2652820#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2652817#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2652814#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2652811#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2652808#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2652805#L675-3 assume !(1 == ~main_in1_ev~0); 2652802#L680-3 assume !(1 == ~main_in2_ev~0); 2652799#L685-3 assume !(1 == ~main_sum_ev~0); 2652796#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2652794#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2652792#L700-3 assume !(1 == ~main_dbl_ev~0); 2652790#L705-3 assume !(1 == ~main_zero_ev~0); 2652788#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2652786#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2652784#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2652782#L725-3 assume !(0 == ~N_generate_st~0); 2652780#L733-2 assume !(0 == ~S1_addsub_st~0); 2652778#L736-2 assume !(0 == ~S2_presdbl_st~0); 2652776#L739-2 assume !(0 == ~S3_zero_st~0); 2652774#L742-2 assume !(0 == ~D_print_st~0); 2652771#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2652767#L803 assume !(5 == main_~count~0#1); 2652763#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2652758#L256-6 assume !(1 == ~main_in1_req_up~0); 2652755#L256-8 assume !(1 == ~main_in2_req_up~0); 2652753#L267-5 assume !(1 == ~main_sum_req_up~0); 2652574#L278-5 assume !(1 == ~main_diff_req_up~0); 2652568#L289-5 assume !(1 == ~main_pres_req_up~0); 2652560#L300-5 assume !(1 == ~main_dbl_req_up~0); 2652552#L311-5 assume !(1 == ~main_zero_req_up~0); 2652545#L322-5 assume !(1 == ~main_clk_req_up~0); 2652539#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2652534#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2652529#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2652525#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2652521#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2652517#L371-5 assume !(0 == ~main_in1_ev~0); 2652513#L376-5 assume !(0 == ~main_in2_ev~0); 2652509#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652503#L386-5 assume !(0 == ~main_diff_ev~0); 2652494#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652485#L396-5 assume !(0 == ~main_dbl_ev~0); 2652475#L401-5 assume !(0 == ~main_zero_ev~0); 2652474#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652465#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2652458#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2652453#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2652447#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2652441#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2652434#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2652428#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2652424#L446-5 assume !(1 == ~main_in1_ev~0); 2652420#L451-5 assume !(1 == ~main_in2_ev~0); 2652416#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2652412#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2652408#L466-5 assume !(1 == ~main_pres_ev~0); 2652404#L471-5 assume !(1 == ~main_dbl_ev~0); 2652400#L476-5 assume !(1 == ~main_zero_ev~0); 2652396#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2652392#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2652388#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2652384#L742-5 assume !false; 2652380#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2652376#L229-2 assume !false; 2652372#L147-2 assume !(0 == ~N_generate_st~0); 2652370#L151-4 assume !(0 == ~S1_addsub_st~0); 2652368#L154-4 assume !(0 == ~S2_presdbl_st~0); 2652366#L157-4 assume !(0 == ~S3_zero_st~0); 2652364#L160-4 assume !(0 == ~D_print_st~0); 2652362#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2652358#L509-6 assume !(1 == ~main_in1_req_up~0); 2652354#L509-8 assume !(1 == ~main_in2_req_up~0); 2652351#L520-5 assume !(1 == ~main_sum_req_up~0); 2652347#L531-5 assume !(1 == ~main_diff_req_up~0); 2652343#L542-5 assume !(1 == ~main_pres_req_up~0); 2652338#L553-5 assume !(1 == ~main_dbl_req_up~0); 2652333#L564-5 assume !(1 == ~main_zero_req_up~0); 2652330#L575-5 assume !(1 == ~main_clk_req_up~0); 2652328#L586-5 start_simulation_~kernel_st~0#1 := 3; 2652326#L605-6 assume !(0 == ~main_in1_ev~0); 2652324#L605-8 assume !(0 == ~main_in2_ev~0); 2652322#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652320#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2652318#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652316#L625-5 assume !(0 == ~main_dbl_ev~0); 2652314#L630-5 assume !(0 == ~main_zero_ev~0); 2652312#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652310#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2652308#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2652306#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2652304#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2652302#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2652300#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2652298#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2652296#L675-5 assume !(1 == ~main_in1_ev~0); 2652294#L680-5 assume !(1 == ~main_in2_ev~0); 2652292#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2652216#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2652210#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2652204#L700-5 assume !(1 == ~main_dbl_ev~0); 2652198#L705-5 assume !(1 == ~main_zero_ev~0); 2652192#L710-5 assume !(1 == ~main_clk_ev~0); 2652186#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2652180#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2652174#L725-5 assume !(0 == ~N_generate_st~0); 2652168#L733-4 assume !(0 == ~S1_addsub_st~0); 2652162#L736-4 assume !(0 == ~S2_presdbl_st~0); 2652156#L739-4 assume !(0 == ~S3_zero_st~0); 2652150#L742-4 assume !(0 == ~D_print_st~0); 2652144#L752-2 assume { :end_inline_start_simulation } true; 2652138#L795-2 [2021-12-07 01:23:48,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:48,924 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 1 times [2021-12-07 01:23:48,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:48,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13505369] [2021-12-07 01:23:48,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:48,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:48,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:48,932 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:48,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:48,947 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:48,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:48,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1203387996, now seen corresponding path program 1 times [2021-12-07 01:23:48,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:48,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402074604] [2021-12-07 01:23:48,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:48,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:48,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:48,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:48,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:48,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402074604] [2021-12-07 01:23:48,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402074604] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:48,963 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:48,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:48,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473010349] [2021-12-07 01:23:48,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:48,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:48,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:48,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:48,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:48,964 INFO L87 Difference]: Start difference. First operand 38395 states and 54730 transitions. cyclomatic complexity: 16359 Second operand has 3 states, 3 states have (on average 59.333333333333336) internal successors, (178), 3 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:49,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:49,047 INFO L93 Difference]: Finished difference Result 38395 states and 54568 transitions. [2021-12-07 01:23:49,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:49,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38395 states and 54568 transitions. [2021-12-07 01:23:49,173 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:49,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38395 states to 38395 states and 54568 transitions. [2021-12-07 01:23:49,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38395 [2021-12-07 01:23:49,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38395 [2021-12-07 01:23:49,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38395 states and 54568 transitions. [2021-12-07 01:23:49,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:49,298 INFO L681 BuchiCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2021-12-07 01:23:49,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38395 states and 54568 transitions. [2021-12-07 01:23:49,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38395 to 38395. [2021-12-07 01:23:49,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.421226722229457) internal successors, (54568), 38394 states have internal predecessors, (54568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:49,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 54568 transitions. [2021-12-07 01:23:49,670 INFO L704 BuchiCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2021-12-07 01:23:49,670 INFO L587 BuchiCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2021-12-07 01:23:49,670 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-07 01:23:49,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 54568 transitions. [2021-12-07 01:23:49,755 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2021-12-07 01:23:49,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:49,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:49,756 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:49,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:49,757 INFO L791 eck$LassoCheckResult]: Stem: 2723530#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2723491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2723019#L256 assume !(1 == ~main_in1_req_up~0); 2722984#L256-2 assume !(1 == ~main_in2_req_up~0); 2722986#L267-1 assume !(1 == ~main_sum_req_up~0); 2723009#L278-1 assume !(1 == ~main_diff_req_up~0); 2722968#L289-1 assume !(1 == ~main_pres_req_up~0); 2722969#L300-1 assume !(1 == ~main_dbl_req_up~0); 2723067#L311-1 assume !(1 == ~main_zero_req_up~0); 2723457#L322-1 assume !(1 == ~main_clk_req_up~0); 2723458#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2723890#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2723889#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2723888#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2723823#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2723824#L371-1 assume !(0 == ~main_in1_ev~0); 2723047#L376-1 assume !(0 == ~main_in2_ev~0); 2723048#L381-1 assume !(0 == ~main_sum_ev~0); 2731399#L386-1 assume !(0 == ~main_diff_ev~0); 2731398#L391-1 assume !(0 == ~main_pres_ev~0); 2731397#L396-1 assume !(0 == ~main_dbl_ev~0); 2731396#L401-1 assume !(0 == ~main_zero_ev~0); 2731395#L406-1 assume !(0 == ~main_clk_ev~0); 2731393#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2731351#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2731293#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2731291#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2731245#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2731243#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2731241#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2731166#L446-1 assume !(1 == ~main_in1_ev~0); 2731120#L451-1 assume !(1 == ~main_in2_ev~0); 2731118#L456-1 assume !(1 == ~main_sum_ev~0); 2731091#L461-1 assume !(1 == ~main_diff_ev~0); 2731089#L466-1 assume !(1 == ~main_pres_ev~0); 2731076#L471-1 assume !(1 == ~main_dbl_ev~0); 2731067#L476-1 assume !(1 == ~main_zero_ev~0); 2731058#L481-1 assume !(1 == ~main_clk_ev~0); 2731051#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2731045#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2731037#L742-1 assume !false; 2730997#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2730995#L229 assume !false; 2730993#L147 assume !(0 == ~N_generate_st~0); 2730991#L151 assume !(0 == ~S1_addsub_st~0); 2730989#L154 assume !(0 == ~S2_presdbl_st~0); 2730987#L157 assume !(0 == ~S3_zero_st~0); 2730985#L160 assume !(0 == ~D_print_st~0); 2730981#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2730930#L509 assume !(1 == ~main_in1_req_up~0); 2730927#L509-2 assume !(1 == ~main_in2_req_up~0); 2730924#L520-1 assume !(1 == ~main_sum_req_up~0); 2730920#L531-1 assume !(1 == ~main_diff_req_up~0); 2730864#L542-1 assume !(1 == ~main_pres_req_up~0); 2730810#L553-1 assume !(1 == ~main_dbl_req_up~0); 2730806#L564-1 assume !(1 == ~main_zero_req_up~0); 2730803#L575-1 assume !(1 == ~main_clk_req_up~0); 2730801#L586-1 start_simulation_~kernel_st~0#1 := 3; 2730799#L605 assume !(0 == ~main_in1_ev~0); 2730797#L605-2 assume !(0 == ~main_in2_ev~0); 2730795#L610-1 assume !(0 == ~main_sum_ev~0); 2730741#L615-1 assume !(0 == ~main_diff_ev~0); 2730739#L620-1 assume !(0 == ~main_pres_ev~0); 2730737#L625-1 assume !(0 == ~main_dbl_ev~0); 2730656#L630-1 assume !(0 == ~main_zero_ev~0); 2730655#L635-1 assume !(0 == ~main_clk_ev~0); 2730653#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2730651#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2730649#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2730473#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2730471#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2730469#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2730436#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2730434#L675-1 assume !(1 == ~main_in1_ev~0); 2730409#L680-1 assume !(1 == ~main_in2_ev~0); 2730407#L685-1 assume !(1 == ~main_sum_ev~0); 2730405#L690-1 assume !(1 == ~main_diff_ev~0); 2730370#L695-1 assume !(1 == ~main_pres_ev~0); 2730360#L700-1 assume !(1 == ~main_dbl_ev~0); 2730352#L705-1 assume !(1 == ~main_zero_ev~0); 2730345#L710-1 assume !(1 == ~main_clk_ev~0); 2730337#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2730335#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2730333#L725-1 assume !(0 == ~N_generate_st~0); 2730331#L733 assume !(0 == ~S1_addsub_st~0); 2730329#L736 assume !(0 == ~S2_presdbl_st~0); 2730327#L739 assume !(0 == ~S3_zero_st~0); 2730319#L742 assume !(0 == ~D_print_st~0); 2730307#L752 assume { :end_inline_start_simulation } true; 2730288#L795-2 [2021-12-07 01:23:49,757 INFO L793 eck$LassoCheckResult]: Loop: 2730288#L795-2 assume !false; 2730287#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2730264#L256-3 assume !(1 == ~main_in1_req_up~0); 2730262#L256-5 assume !(1 == ~main_in2_req_up~0); 2730259#L267-3 assume !(1 == ~main_sum_req_up~0); 2730239#L278-3 assume !(1 == ~main_diff_req_up~0); 2730234#L289-3 assume !(1 == ~main_pres_req_up~0); 2730201#L300-3 assume !(1 == ~main_dbl_req_up~0); 2730180#L311-3 assume !(1 == ~main_zero_req_up~0); 2730170#L322-3 assume 1 == ~main_clk_req_up~0; 2730168#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2730166#L334-3 ~main_clk_req_up~0 := 0; 2730150#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2730137#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2730135#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2730133#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2730131#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2730129#L371-3 assume !(0 == ~main_in1_ev~0); 2730127#L376-3 assume !(0 == ~main_in2_ev~0); 2730125#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2730123#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2730121#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2730095#L396-3 assume !(0 == ~main_dbl_ev~0); 2730058#L401-3 assume !(0 == ~main_zero_ev~0); 2730056#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2730054#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2730052#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2730050#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2730048#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2730046#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2730044#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2730042#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2730040#L446-3 assume !(1 == ~main_in1_ev~0); 2730038#L451-3 assume !(1 == ~main_in2_ev~0); 2730036#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2730034#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2730032#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2730030#L471-3 assume !(1 == ~main_dbl_ev~0); 2730028#L476-3 assume !(1 == ~main_zero_ev~0); 2730027#L481-3 assume !(1 == ~main_clk_ev~0); 2730016#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2730015#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2730014#L742-3 assume !false; 2730013#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2730012#L229-1 assume !false; 2730011#L147-1 assume !(0 == ~N_generate_st~0); 2730009#L151-2 assume !(0 == ~S1_addsub_st~0); 2729811#L154-2 assume !(0 == ~S2_presdbl_st~0); 2729809#L157-2 assume !(0 == ~S3_zero_st~0); 2729807#L160-2 assume !(0 == ~D_print_st~0); 2729805#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2729803#L509-3 assume !(1 == ~main_in1_req_up~0); 2729796#L509-5 assume !(1 == ~main_in2_req_up~0); 2729793#L520-3 assume !(1 == ~main_sum_req_up~0); 2729789#L531-3 assume !(1 == ~main_diff_req_up~0); 2729631#L542-3 assume !(1 == ~main_pres_req_up~0); 2729505#L553-3 assume !(1 == ~main_dbl_req_up~0); 2729501#L564-3 assume !(1 == ~main_zero_req_up~0); 2729502#L575-3 assume !(1 == ~main_clk_req_up~0); 2730167#L586-3 start_simulation_~kernel_st~0#1 := 3; 2730165#L605-3 assume !(0 == ~main_in1_ev~0); 2730145#L605-5 assume !(0 == ~main_in2_ev~0); 2730143#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2730109#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2730107#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2730105#L625-3 assume !(0 == ~main_dbl_ev~0); 2730103#L630-3 assume !(0 == ~main_zero_ev~0); 2730101#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2730100#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2730098#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2730068#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2730064#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2730062#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2730061#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2730059#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2730057#L675-3 assume !(1 == ~main_in1_ev~0); 2730055#L680-3 assume !(1 == ~main_in2_ev~0); 2730053#L685-3 assume !(1 == ~main_sum_ev~0); 2730051#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2730049#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2730047#L700-3 assume !(1 == ~main_dbl_ev~0); 2730045#L705-3 assume !(1 == ~main_zero_ev~0); 2730043#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2730041#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2730039#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2730037#L725-3 assume !(0 == ~N_generate_st~0); 2730035#L733-2 assume !(0 == ~S1_addsub_st~0); 2730033#L736-2 assume !(0 == ~S2_presdbl_st~0); 2730031#L739-2 assume !(0 == ~S3_zero_st~0); 2730029#L742-2 assume !(0 == ~D_print_st~0); 2730017#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2729849#L803 assume !(5 == main_~count~0#1); 2729845#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2729843#L256-6 assume !(1 == ~main_in1_req_up~0); 2729840#L256-8 assume !(1 == ~main_in2_req_up~0); 2729836#L267-5 assume !(1 == ~main_sum_req_up~0); 2729830#L278-5 assume !(1 == ~main_diff_req_up~0); 2729827#L289-5 assume !(1 == ~main_pres_req_up~0); 2729823#L300-5 assume !(1 == ~main_dbl_req_up~0); 2729824#L311-5 assume !(1 == ~main_zero_req_up~0); 2731450#L322-5 assume 1 == ~main_clk_req_up~0; 2731443#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2731437#L334-5 ~main_clk_req_up~0 := 0; 2731428#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2731421#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2731415#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2731410#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2731370#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2731369#L371-5 assume !(0 == ~main_in1_ev~0); 2731367#L376-5 assume !(0 == ~main_in2_ev~0); 2731365#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2731318#L386-5 assume !(0 == ~main_diff_ev~0); 2731316#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2731268#L396-5 assume !(0 == ~main_dbl_ev~0); 2731216#L401-5 assume !(0 == ~main_zero_ev~0); 2731214#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2731160#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2731158#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2731156#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2731154#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2731152#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2731111#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2731109#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2731084#L446-5 assume !(1 == ~main_in1_ev~0); 2731082#L451-5 assume !(1 == ~main_in2_ev~0); 2731072#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2731063#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2731054#L466-5 assume !(1 == ~main_pres_ev~0); 2731048#L471-5 assume !(1 == ~main_dbl_ev~0); 2731041#L476-5 assume !(1 == ~main_zero_ev~0); 2731040#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2731007#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2731005#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2731003#L742-5 assume !false; 2731001#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2730999#L229-2 assume !false; 2730957#L147-2 assume !(0 == ~N_generate_st~0); 2730955#L151-4 assume !(0 == ~S1_addsub_st~0); 2730953#L154-4 assume !(0 == ~S2_presdbl_st~0); 2730949#L157-4 assume !(0 == ~S3_zero_st~0); 2730893#L160-4 assume !(0 == ~D_print_st~0); 2730889#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2730887#L509-6 assume !(1 == ~main_in1_req_up~0); 2730880#L509-8 assume !(1 == ~main_in2_req_up~0); 2730822#L520-5 assume !(1 == ~main_sum_req_up~0); 2730819#L531-5 assume !(1 == ~main_diff_req_up~0); 2730759#L542-5 assume !(1 == ~main_pres_req_up~0); 2730755#L553-5 assume !(1 == ~main_dbl_req_up~0); 2730756#L564-5 assume !(1 == ~main_zero_req_up~0); 2730813#L575-5 assume !(1 == ~main_clk_req_up~0); 2730935#L586-5 start_simulation_~kernel_st~0#1 := 3; 2730934#L605-6 assume !(0 == ~main_in1_ev~0); 2730933#L605-8 assume !(0 == ~main_in2_ev~0); 2730932#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2730871#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2730869#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2730812#L625-5 assume !(0 == ~main_dbl_ev~0); 2730808#L630-5 assume !(0 == ~main_zero_ev~0); 2730804#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2730802#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2730800#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2730798#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2730796#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2730742#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2730740#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2730657#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2730482#L675-5 assume !(1 == ~main_in1_ev~0); 2730480#L680-5 assume !(1 == ~main_in2_ev~0); 2730478#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2730476#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2730439#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2730412#L700-5 assume !(1 == ~main_dbl_ev~0); 2730374#L705-5 assume !(1 == ~main_zero_ev~0); 2730371#L710-5 assume !(1 == ~main_clk_ev~0); 2730361#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2730353#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2730346#L725-5 assume !(0 == ~N_generate_st~0); 2730341#L733-4 assume !(0 == ~S1_addsub_st~0); 2730340#L736-4 assume !(0 == ~S2_presdbl_st~0); 2730312#L739-4 assume !(0 == ~S3_zero_st~0); 2730310#L742-4 assume !(0 == ~D_print_st~0); 2730308#L752-2 assume { :end_inline_start_simulation } true; 2730288#L795-2 [2021-12-07 01:23:49,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:49,758 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 2 times [2021-12-07 01:23:49,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:49,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439554041] [2021-12-07 01:23:49,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:49,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:49,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:49,765 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:49,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:49,778 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:49,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:49,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1107524580, now seen corresponding path program 1 times [2021-12-07 01:23:49,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:49,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771731415] [2021-12-07 01:23:49,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:49,779 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:49,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:49,797 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:49,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771731415] [2021-12-07 01:23:49,797 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771731415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:49,797 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:49,798 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:49,798 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111376737] [2021-12-07 01:23:49,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:49,798 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:49,798 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:49,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:49,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:49,799 INFO L87 Difference]: Start difference. First operand 38395 states and 54568 transitions. cyclomatic complexity: 16197 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:49,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:49,914 INFO L93 Difference]: Finished difference Result 50093 states and 69934 transitions. [2021-12-07 01:23:49,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:49,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50093 states and 69934 transitions. [2021-12-07 01:23:50,089 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47876 [2021-12-07 01:23:50,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50093 states to 50093 states and 69934 transitions. [2021-12-07 01:23:50,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50093 [2021-12-07 01:23:50,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50093 [2021-12-07 01:23:50,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50093 states and 69934 transitions. [2021-12-07 01:23:50,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:50,242 INFO L681 BuchiCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2021-12-07 01:23:50,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50093 states and 69934 transitions. [2021-12-07 01:23:50,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50093 to 50093. [2021-12-07 01:23:50,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50093 states, 50093 states have (on average 1.3960832850897331) internal successors, (69934), 50092 states have internal predecessors, (69934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:50,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50093 states to 50093 states and 69934 transitions. [2021-12-07 01:23:50,755 INFO L704 BuchiCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2021-12-07 01:23:50,755 INFO L587 BuchiCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2021-12-07 01:23:50,755 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-07 01:23:50,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50093 states and 69934 transitions. [2021-12-07 01:23:50,873 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47876 [2021-12-07 01:23:50,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:50,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:50,875 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:50,875 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:50,875 INFO L791 eck$LassoCheckResult]: Stem: 2812096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2812037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2811513#L256 assume !(1 == ~main_in1_req_up~0); 2811478#L256-2 assume !(1 == ~main_in2_req_up~0); 2811480#L267-1 assume !(1 == ~main_sum_req_up~0); 2811503#L278-1 assume !(1 == ~main_diff_req_up~0); 2811462#L289-1 assume !(1 == ~main_pres_req_up~0); 2811463#L300-1 assume !(1 == ~main_dbl_req_up~0); 2811558#L311-1 assume !(1 == ~main_zero_req_up~0); 2812422#L322-1 assume !(1 == ~main_clk_req_up~0); 2812466#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2812513#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2812512#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2812511#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2812456#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2812457#L371-1 assume !(0 == ~main_in1_ev~0); 2811541#L376-1 assume !(0 == ~main_in2_ev~0); 2811542#L381-1 assume !(0 == ~main_sum_ev~0); 2811965#L386-1 assume !(0 == ~main_diff_ev~0); 2811990#L391-1 assume !(0 == ~main_pres_ev~0); 2811991#L396-1 assume !(0 == ~main_dbl_ev~0); 2817340#L401-1 assume !(0 == ~main_zero_ev~0); 2817338#L406-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2817335#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2817332#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2817329#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2817326#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2817323#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2817319#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2817315#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2817312#L446-1 assume !(1 == ~main_in1_ev~0); 2817309#L451-1 assume !(1 == ~main_in2_ev~0); 2817306#L456-1 assume !(1 == ~main_sum_ev~0); 2817303#L461-1 assume !(1 == ~main_diff_ev~0); 2817300#L466-1 assume !(1 == ~main_pres_ev~0); 2817297#L471-1 assume !(1 == ~main_dbl_ev~0); 2817294#L476-1 assume !(1 == ~main_zero_ev~0); 2817291#L481-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2817289#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2817287#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2817280#L742-1 assume !false; 2817165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2817157#L229 assume !false; 2817142#L147 assume !(0 == ~N_generate_st~0); 2817137#L151 assume !(0 == ~S1_addsub_st~0); 2817136#L154 assume !(0 == ~S2_presdbl_st~0); 2817133#L157 assume !(0 == ~S3_zero_st~0); 2817128#L160 assume !(0 == ~D_print_st~0); 2817124#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2817120#L509 assume !(1 == ~main_in1_req_up~0); 2817113#L509-2 assume !(1 == ~main_in2_req_up~0); 2817105#L520-1 assume !(1 == ~main_sum_req_up~0); 2817096#L531-1 assume !(1 == ~main_diff_req_up~0); 2817087#L542-1 assume !(1 == ~main_pres_req_up~0); 2817068#L553-1 assume !(1 == ~main_dbl_req_up~0); 2817065#L564-1 assume !(1 == ~main_zero_req_up~0); 2817050#L575-1 assume !(1 == ~main_clk_req_up~0); 2817035#L586-1 start_simulation_~kernel_st~0#1 := 3; 2817031#L605 assume !(0 == ~main_in1_ev~0); 2817030#L605-2 assume !(0 == ~main_in2_ev~0); 2817008#L610-1 assume !(0 == ~main_sum_ev~0); 2816984#L615-1 assume !(0 == ~main_diff_ev~0); 2816982#L620-1 assume !(0 == ~main_pres_ev~0); 2816959#L625-1 assume !(0 == ~main_dbl_ev~0); 2816957#L630-1 assume !(0 == ~main_zero_ev~0); 2816935#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2816936#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2816985#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2816983#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2816981#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2816979#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2816954#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2816929#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2816905#L675-1 assume !(1 == ~main_in1_ev~0); 2816880#L680-1 assume !(1 == ~main_in2_ev~0); 2816878#L685-1 assume !(1 == ~main_sum_ev~0); 2816876#L690-1 assume !(1 == ~main_diff_ev~0); 2816874#L695-1 assume !(1 == ~main_pres_ev~0); 2816845#L700-1 assume !(1 == ~main_dbl_ev~0); 2816809#L705-1 assume !(1 == ~main_zero_ev~0); 2816796#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2816794#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2816792#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2816782#L725-1 assume !(0 == ~N_generate_st~0); 2816776#L733 assume !(0 == ~S1_addsub_st~0); 2816772#L736 assume !(0 == ~S2_presdbl_st~0); 2816768#L739 assume !(0 == ~S3_zero_st~0); 2816764#L742 assume !(0 == ~D_print_st~0); 2816760#L752 assume { :end_inline_start_simulation } true; 2816757#L795-2 [2021-12-07 01:23:50,876 INFO L793 eck$LassoCheckResult]: Loop: 2816757#L795-2 assume !false; 2816754#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2816751#L256-3 assume !(1 == ~main_in1_req_up~0); 2816746#L256-5 assume !(1 == ~main_in2_req_up~0); 2816742#L267-3 assume !(1 == ~main_sum_req_up~0); 2816738#L278-3 assume !(1 == ~main_diff_req_up~0); 2816733#L289-3 assume !(1 == ~main_pres_req_up~0); 2816726#L300-3 assume !(1 == ~main_dbl_req_up~0); 2816719#L311-3 assume !(1 == ~main_zero_req_up~0); 2816720#L322-3 assume 1 == ~main_clk_req_up~0; 2817263#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2817262#L334-3 ~main_clk_req_up~0 := 0; 2817261#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2817259#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2817258#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2817257#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2817256#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2817254#L371-3 assume !(0 == ~main_in1_ev~0); 2817253#L376-3 assume !(0 == ~main_in2_ev~0); 2817250#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2817248#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2817245#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2817243#L396-3 assume !(0 == ~main_dbl_ev~0); 2817241#L401-3 assume !(0 == ~main_zero_ev~0); 2817239#L406-3 assume !(0 == ~main_clk_ev~0); 2817236#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2817233#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2817230#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2817227#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2817224#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2817221#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2817218#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2817215#L446-3 assume !(1 == ~main_in1_ev~0); 2817212#L451-3 assume !(1 == ~main_in2_ev~0); 2817209#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2817205#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2817202#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2817199#L471-3 assume !(1 == ~main_dbl_ev~0); 2817196#L476-3 assume !(1 == ~main_zero_ev~0); 2817193#L481-3 assume !(1 == ~main_clk_ev~0); 2817191#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2817189#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2817187#L742-3 assume !false; 2817185#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2817183#L229-1 assume !false; 2817181#L147-1 assume !(0 == ~N_generate_st~0); 2817179#L151-2 assume !(0 == ~S1_addsub_st~0); 2817177#L154-2 assume !(0 == ~S2_presdbl_st~0); 2817175#L157-2 assume !(0 == ~S3_zero_st~0); 2817173#L160-2 assume !(0 == ~D_print_st~0); 2817164#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2817156#L509-3 assume !(1 == ~main_in1_req_up~0); 2817138#L509-5 assume !(1 == ~main_in2_req_up~0); 2817139#L520-3 assume !(1 == ~main_sum_req_up~0); 2816586#L531-3 assume !(1 == ~main_diff_req_up~0); 2816585#L542-3 assume !(1 == ~main_pres_req_up~0); 2816562#L553-3 assume !(1 == ~main_dbl_req_up~0); 2816561#L564-3 assume !(1 == ~main_zero_req_up~0); 2816544#L575-3 assume !(1 == ~main_clk_req_up~0); 2816545#L586-3 start_simulation_~kernel_st~0#1 := 3; 2816534#L605-3 assume !(0 == ~main_in1_ev~0); 2816535#L605-5 assume !(0 == ~main_in2_ev~0); 2816526#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2816527#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2816517#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2816518#L625-3 assume !(0 == ~main_dbl_ev~0); 2816507#L630-3 assume !(0 == ~main_zero_ev~0); 2816508#L635-3 assume !(0 == ~main_clk_ev~0); 2817277#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2817576#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2817574#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2817572#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2817570#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2817569#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2817567#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2817566#L675-3 assume !(1 == ~main_in1_ev~0); 2817564#L680-3 assume !(1 == ~main_in2_ev~0); 2817562#L685-3 assume !(1 == ~main_sum_ev~0); 2817560#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2817558#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2817143#L700-3 assume !(1 == ~main_dbl_ev~0); 2817144#L705-3 assume !(1 == ~main_zero_ev~0); 2816441#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2816440#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2816426#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2816427#L725-3 assume !(0 == ~N_generate_st~0); 2816418#L733-2 assume !(0 == ~S1_addsub_st~0); 2816419#L736-2 assume !(0 == ~S2_presdbl_st~0); 2816410#L739-2 assume !(0 == ~S3_zero_st~0); 2816411#L742-2 assume !(0 == ~D_print_st~0); 2816402#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2816403#L803 assume !(5 == main_~count~0#1); 2816388#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2816389#L256-6 assume !(1 == ~main_in1_req_up~0); 2816377#L256-8 assume !(1 == ~main_in2_req_up~0); 2816376#L267-5 assume !(1 == ~main_sum_req_up~0); 2816353#L278-5 assume !(1 == ~main_diff_req_up~0); 2816354#L289-5 assume !(1 == ~main_pres_req_up~0); 2816330#L300-5 assume !(1 == ~main_dbl_req_up~0); 2816329#L311-5 assume !(1 == ~main_zero_req_up~0); 2817249#L322-5 assume 1 == ~main_clk_req_up~0; 2817246#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2817244#L334-5 ~main_clk_req_up~0 := 0; 2817242#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2817240#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2817238#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2817235#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2817232#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2817229#L371-5 assume !(0 == ~main_in1_ev~0); 2817226#L376-5 assume !(0 == ~main_in2_ev~0); 2817223#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2817220#L386-5 assume !(0 == ~main_diff_ev~0); 2817217#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2817214#L396-5 assume !(0 == ~main_dbl_ev~0); 2817211#L401-5 assume !(0 == ~main_zero_ev~0); 2817207#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2817208#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2817522#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2817517#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2817512#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2817507#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2817502#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2817497#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2817492#L446-5 assume !(1 == ~main_in1_ev~0); 2817487#L451-5 assume !(1 == ~main_in2_ev~0); 2817482#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2817477#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2817472#L466-5 assume !(1 == ~main_pres_ev~0); 2817469#L471-5 assume !(1 == ~main_dbl_ev~0); 2817286#L476-5 assume !(1 == ~main_zero_ev~0); 2817171#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2817163#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2817155#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2817132#L742-5 assume !false; 2817127#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2817123#L229-2 assume !false; 2817118#L147-2 assume !(0 == ~N_generate_st~0); 2817111#L151-4 assume !(0 == ~S1_addsub_st~0); 2817103#L154-4 assume !(0 == ~S2_presdbl_st~0); 2817095#L157-4 assume !(0 == ~S3_zero_st~0); 2817094#L160-4 assume !(0 == ~D_print_st~0); 2817079#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2817061#L509-6 assume !(1 == ~main_in1_req_up~0); 2817058#L509-8 assume !(1 == ~main_in2_req_up~0); 2817041#L520-5 assume !(1 == ~main_sum_req_up~0); 2817027#L531-5 assume !(1 == ~main_diff_req_up~0); 2817024#L542-5 assume !(1 == ~main_pres_req_up~0); 2817004#L553-5 assume !(1 == ~main_dbl_req_up~0); 2817000#L564-5 assume !(1 == ~main_zero_req_up~0); 2816976#L575-5 assume !(1 == ~main_clk_req_up~0); 2816974#L586-5 start_simulation_~kernel_st~0#1 := 3; 2816972#L605-6 assume !(0 == ~main_in1_ev~0); 2816970#L605-8 assume !(0 == ~main_in2_ev~0); 2816968#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2816947#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2816945#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2816943#L625-5 assume !(0 == ~main_dbl_ev~0); 2816921#L630-5 assume !(0 == ~main_zero_ev~0); 2816918#L635-5 assume !(0 == ~main_clk_ev~0); 2816919#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2816941#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2816939#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2816937#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2816913#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2816911#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2816909#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2816887#L675-5 assume !(1 == ~main_in1_ev~0); 2816859#L680-5 assume !(1 == ~main_in2_ev~0); 2816855#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2816853#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2816851#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2816849#L700-5 assume !(1 == ~main_dbl_ev~0); 2816847#L705-5 assume !(1 == ~main_zero_ev~0); 2816818#L710-5 assume !(1 == ~main_clk_ev~0); 2816816#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2816799#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2816783#L725-5 assume !(0 == ~N_generate_st~0); 2816777#L733-4 assume !(0 == ~S1_addsub_st~0); 2816773#L736-4 assume !(0 == ~S2_presdbl_st~0); 2816769#L739-4 assume !(0 == ~S3_zero_st~0); 2816765#L742-4 assume !(0 == ~D_print_st~0); 2816761#L752-2 assume { :end_inline_start_simulation } true; 2816757#L795-2 [2021-12-07 01:23:50,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:50,876 INFO L85 PathProgramCache]: Analyzing trace with hash -1704529589, now seen corresponding path program 1 times [2021-12-07 01:23:50,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:50,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634413333] [2021-12-07 01:23:50,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:50,876 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:50,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:50,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:50,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:50,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634413333] [2021-12-07 01:23:50,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634413333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:50,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:50,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-07 01:23:50,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780531845] [2021-12-07 01:23:50,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:50,896 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:23:50,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:50,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1507834726, now seen corresponding path program 1 times [2021-12-07 01:23:50,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:50,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541487972] [2021-12-07 01:23:50,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:50,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:50,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:50,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:50,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:50,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541487972] [2021-12-07 01:23:50,922 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541487972] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:50,922 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:50,922 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:50,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219274888] [2021-12-07 01:23:50,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:50,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:50,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:50,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:23:50,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:23:50,923 INFO L87 Difference]: Start difference. First operand 50093 states and 69934 transitions. cyclomatic complexity: 19865 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:51,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:51,077 INFO L93 Difference]: Finished difference Result 51445 states and 71874 transitions. [2021-12-07 01:23:51,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-07 01:23:51,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51445 states and 71874 transitions. [2021-12-07 01:23:51,247 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48892 [2021-12-07 01:23:51,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51445 states to 51445 states and 71874 transitions. [2021-12-07 01:23:51,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51445 [2021-12-07 01:23:51,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51445 [2021-12-07 01:23:51,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51445 states and 71874 transitions. [2021-12-07 01:23:51,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:51,400 INFO L681 BuchiCegarLoop]: Abstraction has 51445 states and 71874 transitions. [2021-12-07 01:23:51,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51445 states and 71874 transitions. [2021-12-07 01:23:51,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51445 to 46347. [2021-12-07 01:23:51,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46347 states, 46347 states have (on average 1.4040606727512028) internal successors, (65074), 46346 states have internal predecessors, (65074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:51,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46347 states to 46347 states and 65074 transitions. [2021-12-07 01:23:51,799 INFO L704 BuchiCegarLoop]: Abstraction has 46347 states and 65074 transitions. [2021-12-07 01:23:51,799 INFO L587 BuchiCegarLoop]: Abstraction has 46347 states and 65074 transitions. [2021-12-07 01:23:51,799 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-07 01:23:51,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46347 states and 65074 transitions. [2021-12-07 01:23:51,950 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 44800 [2021-12-07 01:23:51,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:51,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:51,951 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:51,951 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:51,951 INFO L791 eck$LassoCheckResult]: Stem: 2913623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2913553#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2913061#L256 assume !(1 == ~main_in1_req_up~0); 2913026#L256-2 assume !(1 == ~main_in2_req_up~0); 2913028#L267-1 assume !(1 == ~main_sum_req_up~0); 2913051#L278-1 assume !(1 == ~main_diff_req_up~0); 2913010#L289-1 assume !(1 == ~main_pres_req_up~0); 2913011#L300-1 assume !(1 == ~main_dbl_req_up~0); 2913106#L311-1 assume !(1 == ~main_zero_req_up~0); 2913765#L322-1 assume !(1 == ~main_clk_req_up~0); 2913818#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2913890#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2913889#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2913888#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2913808#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2913809#L371-1 assume !(0 == ~main_in1_ev~0); 2913089#L376-1 assume !(0 == ~main_in2_ev~0); 2913090#L381-1 assume !(0 == ~main_sum_ev~0); 2913490#L386-1 assume !(0 == ~main_diff_ev~0); 2913506#L391-1 assume !(0 == ~main_pres_ev~0); 2913507#L396-1 assume !(0 == ~main_dbl_ev~0); 2917383#L401-1 assume !(0 == ~main_zero_ev~0); 2917382#L406-1 assume !(0 == ~main_clk_ev~0); 2917381#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2917380#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2917379#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2917378#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2917377#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2917376#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2917375#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2917374#L446-1 assume !(1 == ~main_in1_ev~0); 2917373#L451-1 assume !(1 == ~main_in2_ev~0); 2917372#L456-1 assume !(1 == ~main_sum_ev~0); 2917371#L461-1 assume !(1 == ~main_diff_ev~0); 2917370#L466-1 assume !(1 == ~main_pres_ev~0); 2917369#L471-1 assume !(1 == ~main_dbl_ev~0); 2917368#L476-1 assume !(1 == ~main_zero_ev~0); 2917367#L481-1 assume !(1 == ~main_clk_ev~0); 2917365#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2917363#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2917361#L742-1 assume !false; 2917359#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2917357#L229 assume !false; 2917355#L147 assume !(0 == ~N_generate_st~0); 2917353#L151 assume !(0 == ~S1_addsub_st~0); 2917351#L154 assume !(0 == ~S2_presdbl_st~0); 2917349#L157 assume !(0 == ~S3_zero_st~0); 2917347#L160 assume !(0 == ~D_print_st~0); 2917345#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2917342#L509 assume !(1 == ~main_in1_req_up~0); 2917336#L509-2 assume !(1 == ~main_in2_req_up~0); 2917330#L520-1 assume !(1 == ~main_sum_req_up~0); 2917323#L531-1 assume !(1 == ~main_diff_req_up~0); 2917318#L542-1 assume !(1 == ~main_pres_req_up~0); 2917310#L553-1 assume !(1 == ~main_dbl_req_up~0); 2917303#L564-1 assume !(1 == ~main_zero_req_up~0); 2917300#L575-1 assume !(1 == ~main_clk_req_up~0); 2917298#L586-1 start_simulation_~kernel_st~0#1 := 3; 2917296#L605 assume !(0 == ~main_in1_ev~0); 2917294#L605-2 assume !(0 == ~main_in2_ev~0); 2917292#L610-1 assume !(0 == ~main_sum_ev~0); 2917290#L615-1 assume !(0 == ~main_diff_ev~0); 2917288#L620-1 assume !(0 == ~main_pres_ev~0); 2917286#L625-1 assume !(0 == ~main_dbl_ev~0); 2917284#L630-1 assume !(0 == ~main_zero_ev~0); 2917282#L635-1 assume !(0 == ~main_clk_ev~0); 2917280#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2917278#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2917276#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2917274#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2917272#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2917270#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2917268#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2917266#L675-1 assume !(1 == ~main_in1_ev~0); 2917264#L680-1 assume !(1 == ~main_in2_ev~0); 2917262#L685-1 assume !(1 == ~main_sum_ev~0); 2917260#L690-1 assume !(1 == ~main_diff_ev~0); 2917258#L695-1 assume !(1 == ~main_pres_ev~0); 2917256#L700-1 assume !(1 == ~main_dbl_ev~0); 2917254#L705-1 assume !(1 == ~main_zero_ev~0); 2917252#L710-1 assume !(1 == ~main_clk_ev~0); 2917250#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2917248#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2917246#L725-1 assume !(0 == ~N_generate_st~0); 2917244#L733 assume !(0 == ~S1_addsub_st~0); 2917242#L736 assume !(0 == ~S2_presdbl_st~0); 2917240#L739 assume !(0 == ~S3_zero_st~0); 2917238#L742 assume !(0 == ~D_print_st~0); 2917236#L752 assume { :end_inline_start_simulation } true; 2917235#L795-2 [2021-12-07 01:23:51,952 INFO L793 eck$LassoCheckResult]: Loop: 2917235#L795-2 assume !false; 2917234#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2917233#L256-3 assume !(1 == ~main_in1_req_up~0); 2917230#L256-5 assume !(1 == ~main_in2_req_up~0); 2917227#L267-3 assume !(1 == ~main_sum_req_up~0); 2917224#L278-3 assume !(1 == ~main_diff_req_up~0); 2917221#L289-3 assume !(1 == ~main_pres_req_up~0); 2917217#L300-3 assume !(1 == ~main_dbl_req_up~0); 2917213#L311-3 assume !(1 == ~main_zero_req_up~0); 2917211#L322-3 assume 1 == ~main_clk_req_up~0; 2917209#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2917208#L334-3 ~main_clk_req_up~0 := 0; 2917207#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2917206#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2917205#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2917204#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2917203#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2917202#L371-3 assume !(0 == ~main_in1_ev~0); 2917201#L376-3 assume !(0 == ~main_in2_ev~0); 2917200#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917199#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2917198#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917197#L396-3 assume !(0 == ~main_dbl_ev~0); 2917196#L401-3 assume !(0 == ~main_zero_ev~0); 2917195#L406-3 assume !(0 == ~main_clk_ev~0); 2917194#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2917193#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2917192#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2917191#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2917190#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2917189#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2917188#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2917187#L446-3 assume !(1 == ~main_in1_ev~0); 2917186#L451-3 assume !(1 == ~main_in2_ev~0); 2917185#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2917184#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917183#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2917182#L471-3 assume !(1 == ~main_dbl_ev~0); 2917181#L476-3 assume !(1 == ~main_zero_ev~0); 2917180#L481-3 assume !(1 == ~main_clk_ev~0); 2917179#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2917178#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2917177#L742-3 assume !false; 2917176#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2917175#L229-1 assume !false; 2917174#L147-1 assume !(0 == ~N_generate_st~0); 2917173#L151-2 assume !(0 == ~S1_addsub_st~0); 2917172#L154-2 assume !(0 == ~S2_presdbl_st~0); 2917171#L157-2 assume !(0 == ~S3_zero_st~0); 2917170#L160-2 assume !(0 == ~D_print_st~0); 2917169#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2917168#L509-3 assume !(1 == ~main_in1_req_up~0); 2917164#L509-5 assume !(1 == ~main_in2_req_up~0); 2917160#L520-3 assume !(1 == ~main_sum_req_up~0); 2917157#L531-3 assume !(1 == ~main_diff_req_up~0); 2917154#L542-3 assume !(1 == ~main_pres_req_up~0); 2917149#L553-3 assume !(1 == ~main_dbl_req_up~0); 2917145#L564-3 assume !(1 == ~main_zero_req_up~0); 2917144#L575-3 assume !(1 == ~main_clk_req_up~0); 2917143#L586-3 start_simulation_~kernel_st~0#1 := 3; 2917142#L605-3 assume !(0 == ~main_in1_ev~0); 2917141#L605-5 assume !(0 == ~main_in2_ev~0); 2917140#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917139#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2917138#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917137#L625-3 assume !(0 == ~main_dbl_ev~0); 2917136#L630-3 assume !(0 == ~main_zero_ev~0); 2917135#L635-3 assume !(0 == ~main_clk_ev~0); 2917134#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2917133#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2917132#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2917131#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2917130#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2917129#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2917128#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2917127#L675-3 assume !(1 == ~main_in1_ev~0); 2917126#L680-3 assume !(1 == ~main_in2_ev~0); 2917125#L685-3 assume !(1 == ~main_sum_ev~0); 2917124#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917123#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2917122#L700-3 assume !(1 == ~main_dbl_ev~0); 2917121#L705-3 assume !(1 == ~main_zero_ev~0); 2917120#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2917119#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2917118#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2917117#L725-3 assume !(0 == ~N_generate_st~0); 2917116#L733-2 assume !(0 == ~S1_addsub_st~0); 2917115#L736-2 assume !(0 == ~S2_presdbl_st~0); 2917114#L739-2 assume !(0 == ~S3_zero_st~0); 2917113#L742-2 assume !(0 == ~D_print_st~0); 2917112#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2917110#L803 assume !(5 == main_~count~0#1); 2917108#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2917107#L256-6 assume !(1 == ~main_in1_req_up~0); 2917104#L256-8 assume !(1 == ~main_in2_req_up~0); 2917101#L267-5 assume !(1 == ~main_sum_req_up~0); 2917097#L278-5 assume !(1 == ~main_diff_req_up~0); 2917094#L289-5 assume !(1 == ~main_pres_req_up~0); 2917091#L300-5 assume !(1 == ~main_dbl_req_up~0); 2917087#L311-5 assume !(1 == ~main_zero_req_up~0); 2917084#L322-5 assume 1 == ~main_clk_req_up~0; 2917085#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2917412#L334-5 ~main_clk_req_up~0 := 0; 2917411#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2917410#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2917409#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2917408#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2917407#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2917406#L371-5 assume !(0 == ~main_in1_ev~0); 2917405#L376-5 assume !(0 == ~main_in2_ev~0); 2917404#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917403#L386-5 assume !(0 == ~main_diff_ev~0); 2917402#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917401#L396-5 assume !(0 == ~main_dbl_ev~0); 2917400#L401-5 assume !(0 == ~main_zero_ev~0); 2917399#L406-5 assume !(0 == ~main_clk_ev~0); 2917398#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2917397#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2917396#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2917395#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2917394#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2917393#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2917392#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2917391#L446-5 assume !(1 == ~main_in1_ev~0); 2917390#L451-5 assume !(1 == ~main_in2_ev~0); 2917389#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2917388#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917387#L466-5 assume !(1 == ~main_pres_ev~0); 2917386#L471-5 assume !(1 == ~main_dbl_ev~0); 2917385#L476-5 assume !(1 == ~main_zero_ev~0); 2917384#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2917366#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2917364#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2917362#L742-5 assume !false; 2917360#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2917358#L229-2 assume !false; 2917356#L147-2 assume !(0 == ~N_generate_st~0); 2917354#L151-4 assume !(0 == ~S1_addsub_st~0); 2917352#L154-4 assume !(0 == ~S2_presdbl_st~0); 2917350#L157-4 assume !(0 == ~S3_zero_st~0); 2917348#L160-4 assume !(0 == ~D_print_st~0); 2917346#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2917343#L509-6 assume !(1 == ~main_in1_req_up~0); 2917338#L509-8 assume !(1 == ~main_in2_req_up~0); 2917333#L520-5 assume !(1 == ~main_sum_req_up~0); 2917327#L531-5 assume !(1 == ~main_diff_req_up~0); 2917321#L542-5 assume !(1 == ~main_pres_req_up~0); 2917314#L553-5 assume !(1 == ~main_dbl_req_up~0); 2917306#L564-5 assume !(1 == ~main_zero_req_up~0); 2917301#L575-5 assume !(1 == ~main_clk_req_up~0); 2917299#L586-5 start_simulation_~kernel_st~0#1 := 3; 2917297#L605-6 assume !(0 == ~main_in1_ev~0); 2917295#L605-8 assume !(0 == ~main_in2_ev~0); 2917293#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917291#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2917289#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917287#L625-5 assume !(0 == ~main_dbl_ev~0); 2917285#L630-5 assume !(0 == ~main_zero_ev~0); 2917283#L635-5 assume !(0 == ~main_clk_ev~0); 2917281#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2917279#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2917277#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2917275#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2917273#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2917271#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2917269#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2917267#L675-5 assume !(1 == ~main_in1_ev~0); 2917265#L680-5 assume !(1 == ~main_in2_ev~0); 2917263#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2917261#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917259#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2917257#L700-5 assume !(1 == ~main_dbl_ev~0); 2917255#L705-5 assume !(1 == ~main_zero_ev~0); 2917253#L710-5 assume !(1 == ~main_clk_ev~0); 2917251#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2917249#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2917247#L725-5 assume !(0 == ~N_generate_st~0); 2917245#L733-4 assume !(0 == ~S1_addsub_st~0); 2917243#L736-4 assume !(0 == ~S2_presdbl_st~0); 2917241#L739-4 assume !(0 == ~S3_zero_st~0); 2917239#L742-4 assume !(0 == ~D_print_st~0); 2917237#L752-2 assume { :end_inline_start_simulation } true; 2917235#L795-2 [2021-12-07 01:23:51,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:51,952 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 3 times [2021-12-07 01:23:51,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:51,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352227168] [2021-12-07 01:23:51,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:51,952 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:51,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:51,958 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:51,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:51,971 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:51,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:51,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1570978844, now seen corresponding path program 1 times [2021-12-07 01:23:51,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:51,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20193246] [2021-12-07 01:23:51,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:51,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:51,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:51,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:51,990 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:51,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20193246] [2021-12-07 01:23:51,990 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20193246] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:51,990 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:51,990 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:51,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089270839] [2021-12-07 01:23:51,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:51,991 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:51,991 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:51,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:51,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:51,991 INFO L87 Difference]: Start difference. First operand 46347 states and 65074 transitions. cyclomatic complexity: 18751 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:52,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:52,197 INFO L93 Difference]: Finished difference Result 92683 states and 128236 transitions. [2021-12-07 01:23:52,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:52,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92683 states and 128236 transitions. [2021-12-07 01:23:52,499 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 89600 [2021-12-07 01:23:52,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92683 states to 92683 states and 128236 transitions. [2021-12-07 01:23:52,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92683 [2021-12-07 01:23:52,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92683 [2021-12-07 01:23:52,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92683 states and 128236 transitions. [2021-12-07 01:23:52,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:52,779 INFO L681 BuchiCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2021-12-07 01:23:52,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92683 states and 128236 transitions. [2021-12-07 01:23:53,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92683 to 92683. [2021-12-07 01:23:53,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92683 states, 92683 states have (on average 1.3835978550543249) internal successors, (128236), 92682 states have internal predecessors, (128236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:53,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92683 states to 92683 states and 128236 transitions. [2021-12-07 01:23:53,681 INFO L704 BuchiCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2021-12-07 01:23:53,681 INFO L587 BuchiCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2021-12-07 01:23:53,681 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-07 01:23:53,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92683 states and 128236 transitions. [2021-12-07 01:23:53,879 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 89600 [2021-12-07 01:23:53,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:53,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:53,881 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:53,881 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:53,881 INFO L791 eck$LassoCheckResult]: Stem: 3052675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3052609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3052098#L256 assume !(1 == ~main_in1_req_up~0); 3052062#L256-2 assume !(1 == ~main_in2_req_up~0); 3052064#L267-1 assume !(1 == ~main_sum_req_up~0); 3052455#L278-1 assume !(1 == ~main_diff_req_up~0); 3052046#L289-1 assume !(1 == ~main_pres_req_up~0); 3052047#L300-1 assume !(1 == ~main_dbl_req_up~0); 3052144#L311-1 assume !(1 == ~main_zero_req_up~0); 3052309#L322-1 assume !(1 == ~main_clk_req_up~0); 3052391#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3052279#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3052079#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3052080#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3052269#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3053400#L371-1 assume !(0 == ~main_in1_ev~0); 3053401#L376-1 assume !(0 == ~main_in2_ev~0); 3053479#L381-1 assume !(0 == ~main_sum_ev~0); 3052288#L386-1 assume !(0 == ~main_diff_ev~0); 3052289#L391-1 assume !(0 == ~main_pres_ev~0); 3053473#L396-1 assume !(0 == ~main_dbl_ev~0); 3053474#L401-1 assume !(0 == ~main_zero_ev~0); 3066741#L406-1 assume !(0 == ~main_clk_ev~0); 3066740#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3066739#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3066738#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3066737#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3052248#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3052249#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3052226#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3052227#L446-1 assume !(1 == ~main_in1_ev~0); 3065384#L451-1 assume !(1 == ~main_in2_ev~0); 3065382#L456-1 assume !(1 == ~main_sum_ev~0); 3065378#L461-1 assume !(1 == ~main_diff_ev~0); 3065376#L466-1 assume !(1 == ~main_pres_ev~0); 3065374#L471-1 assume !(1 == ~main_dbl_ev~0); 3065372#L476-1 assume !(1 == ~main_zero_ev~0); 3065370#L481-1 assume !(1 == ~main_clk_ev~0); 3065368#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3065364#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3065360#L742-1 assume !false; 3065359#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3065358#L229 assume !false; 3065354#L147 assume !(0 == ~N_generate_st~0); 3065350#L151 assume !(0 == ~S1_addsub_st~0); 3065349#L154 assume !(0 == ~S2_presdbl_st~0); 3065348#L157 assume !(0 == ~S3_zero_st~0); 3065347#L160 assume !(0 == ~D_print_st~0); 3065346#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3065345#L509 assume !(1 == ~main_in1_req_up~0); 3065342#L509-2 assume !(1 == ~main_in2_req_up~0); 3065339#L520-1 assume !(1 == ~main_sum_req_up~0); 3065335#L531-1 assume !(1 == ~main_diff_req_up~0); 3065333#L542-1 assume !(1 == ~main_pres_req_up~0); 3065330#L553-1 assume !(1 == ~main_dbl_req_up~0); 3065331#L564-1 assume !(1 == ~main_zero_req_up~0); 3065859#L575-1 assume !(1 == ~main_clk_req_up~0); 3065857#L586-1 start_simulation_~kernel_st~0#1 := 3; 3065854#L605 assume !(0 == ~main_in1_ev~0); 3065851#L605-2 assume !(0 == ~main_in2_ev~0); 3065848#L610-1 assume !(0 == ~main_sum_ev~0); 3065845#L615-1 assume !(0 == ~main_diff_ev~0); 3065842#L620-1 assume !(0 == ~main_pres_ev~0); 3065839#L625-1 assume !(0 == ~main_dbl_ev~0); 3065836#L630-1 assume !(0 == ~main_zero_ev~0); 3065833#L635-1 assume !(0 == ~main_clk_ev~0); 3065830#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3065827#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3065824#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3065821#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3065818#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3065815#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3065812#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3065809#L675-1 assume !(1 == ~main_in1_ev~0); 3065806#L680-1 assume !(1 == ~main_in2_ev~0); 3065803#L685-1 assume !(1 == ~main_sum_ev~0); 3065797#L690-1 assume !(1 == ~main_diff_ev~0); 3065795#L695-1 assume !(1 == ~main_pres_ev~0); 3065793#L700-1 assume !(1 == ~main_dbl_ev~0); 3065791#L705-1 assume !(1 == ~main_zero_ev~0); 3065789#L710-1 assume !(1 == ~main_clk_ev~0); 3065787#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3065785#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3065783#L725-1 assume !(0 == ~N_generate_st~0); 3065781#L733 assume !(0 == ~S1_addsub_st~0); 3065779#L736 assume !(0 == ~S2_presdbl_st~0); 3065777#L739 assume !(0 == ~S3_zero_st~0); 3065775#L742 assume !(0 == ~D_print_st~0); 3065771#L752 assume { :end_inline_start_simulation } true; 3065772#L795-2 [2021-12-07 01:23:53,881 INFO L793 eck$LassoCheckResult]: Loop: 3065772#L795-2 assume !false; 3067721#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3065763#L256-3 assume !(1 == ~main_in1_req_up~0); 3065760#L256-5 assume !(1 == ~main_in2_req_up~0); 3065761#L267-3 assume !(1 == ~main_sum_req_up~0); 3068099#L278-3 assume !(1 == ~main_diff_req_up~0); 3068205#L289-3 assume !(1 == ~main_pres_req_up~0); 3068199#L300-3 assume !(1 == ~main_dbl_req_up~0); 3068195#L311-3 assume !(1 == ~main_zero_req_up~0); 3068192#L322-3 assume 1 == ~main_clk_req_up~0; 3068188#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3068185#L334-3 ~main_clk_req_up~0 := 0; 3068184#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3068180#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3068179#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3068178#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3068174#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3068170#L371-3 assume !(0 == ~main_in1_ev~0); 3068167#L376-3 assume !(0 == ~main_in2_ev~0); 3068164#L381-3 assume !(0 == ~main_sum_ev~0); 3068163#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3068159#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3068157#L396-3 assume !(0 == ~main_dbl_ev~0); 3068154#L401-3 assume !(0 == ~main_zero_ev~0); 3068152#L406-3 assume !(0 == ~main_clk_ev~0); 3068150#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3068148#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3068146#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3068144#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3068142#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3068140#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3068138#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3068136#L446-3 assume !(1 == ~main_in1_ev~0); 3068134#L451-3 assume !(1 == ~main_in2_ev~0); 3068132#L456-3 assume !(1 == ~main_sum_ev~0); 3068021#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3068129#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3068127#L471-3 assume !(1 == ~main_dbl_ev~0); 3068125#L476-3 assume !(1 == ~main_zero_ev~0); 3068123#L481-3 assume !(1 == ~main_clk_ev~0); 3068121#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3068119#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3068117#L742-3 assume !false; 3068115#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3068114#L229-1 assume !false; 3068113#L147-1 assume !(0 == ~N_generate_st~0); 3068112#L151-2 assume !(0 == ~S1_addsub_st~0); 3068111#L154-2 assume !(0 == ~S2_presdbl_st~0); 3068110#L157-2 assume !(0 == ~S3_zero_st~0); 3068109#L160-2 assume !(0 == ~D_print_st~0); 3068108#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3068107#L509-3 assume !(1 == ~main_in1_req_up~0); 3068104#L509-5 assume !(1 == ~main_in2_req_up~0); 3068103#L520-3 assume !(1 == ~main_sum_req_up~0); 3060736#L531-3 assume !(1 == ~main_diff_req_up~0); 3060735#L542-3 assume !(1 == ~main_pres_req_up~0); 3060711#L553-3 assume !(1 == ~main_dbl_req_up~0); 3060705#L564-3 assume !(1 == ~main_zero_req_up~0); 3060706#L575-3 assume !(1 == ~main_clk_req_up~0); 3060776#L586-3 start_simulation_~kernel_st~0#1 := 3; 3060766#L605-3 assume !(0 == ~main_in1_ev~0); 3060756#L605-5 assume !(0 == ~main_in2_ev~0); 3060634#L610-3 assume !(0 == ~main_sum_ev~0); 3060622#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3060611#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3060596#L625-3 assume !(0 == ~main_dbl_ev~0); 3060584#L630-3 assume !(0 == ~main_zero_ev~0); 3060574#L635-3 assume !(0 == ~main_clk_ev~0); 3060564#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3060554#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3060544#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3060534#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3060524#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3060514#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3060504#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3060494#L675-3 assume !(1 == ~main_in1_ev~0); 3060483#L680-3 assume !(1 == ~main_in2_ev~0); 3060484#L685-3 assume !(1 == ~main_sum_ev~0); 3067681#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3067680#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3060445#L700-3 assume !(1 == ~main_dbl_ev~0); 3060433#L705-3 assume !(1 == ~main_zero_ev~0); 3060422#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3060423#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3067667#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3067664#L725-3 assume !(0 == ~N_generate_st~0); 3060384#L733-2 assume !(0 == ~S1_addsub_st~0); 3060376#L736-2 assume !(0 == ~S2_presdbl_st~0); 3060367#L739-2 assume !(0 == ~S3_zero_st~0); 3060368#L742-2 assume !(0 == ~D_print_st~0); 3067619#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3067618#L803 assume !(5 == main_~count~0#1); 3067617#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3067616#L256-6 assume !(1 == ~main_in1_req_up~0); 3060314#L256-8 assume !(1 == ~main_in2_req_up~0); 3060301#L267-5 assume !(1 == ~main_sum_req_up~0); 3060302#L278-5 assume !(1 == ~main_diff_req_up~0); 3060703#L289-5 assume !(1 == ~main_pres_req_up~0); 3060702#L300-5 assume !(1 == ~main_dbl_req_up~0); 3060091#L311-5 assume !(1 == ~main_zero_req_up~0); 3069803#L322-5 assume 1 == ~main_clk_req_up~0; 3069800#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3069798#L334-5 ~main_clk_req_up~0 := 0; 3069794#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3069791#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3069709#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3069706#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3069703#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3069701#L371-5 assume !(0 == ~main_in1_ev~0); 3069699#L376-5 assume !(0 == ~main_in2_ev~0); 3069697#L381-5 assume !(0 == ~main_sum_ev~0); 3069695#L386-5 assume !(0 == ~main_diff_ev~0); 3069693#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3069691#L396-5 assume !(0 == ~main_dbl_ev~0); 3069689#L401-5 assume !(0 == ~main_zero_ev~0); 3069687#L406-5 assume !(0 == ~main_clk_ev~0); 3069685#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3069684#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3069683#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3069682#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3069681#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3069680#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3069679#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3069678#L446-5 assume !(1 == ~main_in1_ev~0); 3069677#L451-5 assume !(1 == ~main_in2_ev~0); 3069673#L456-5 assume !(1 == ~main_sum_ev~0); 3067360#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3069663#L466-5 assume !(1 == ~main_pres_ev~0); 3069500#L471-5 assume !(1 == ~main_dbl_ev~0); 3069499#L476-5 assume !(1 == ~main_zero_ev~0); 3069498#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3069497#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3069496#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3069495#L742-5 assume !false; 3069494#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3069493#L229-2 assume !false; 3069492#L147-2 assume !(0 == ~N_generate_st~0); 3069491#L151-4 assume !(0 == ~S1_addsub_st~0); 3067882#L154-4 assume !(0 == ~S2_presdbl_st~0); 3067593#L157-4 assume !(0 == ~S3_zero_st~0); 3065888#L160-4 assume !(0 == ~D_print_st~0); 3065886#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3065883#L509-6 assume !(1 == ~main_in1_req_up~0); 3065884#L509-8 assume !(1 == ~main_in2_req_up~0); 3067003#L520-5 assume !(1 == ~main_sum_req_up~0); 3068740#L531-5 assume !(1 == ~main_diff_req_up~0); 3068737#L542-5 assume !(1 == ~main_pres_req_up~0); 3068735#L553-5 assume !(1 == ~main_dbl_req_up~0); 3065866#L564-5 assume !(1 == ~main_zero_req_up~0); 3069442#L575-5 assume !(1 == ~main_clk_req_up~0); 3069441#L586-5 start_simulation_~kernel_st~0#1 := 3; 3065852#L605-6 assume !(0 == ~main_in1_ev~0); 3065853#L605-8 assume !(0 == ~main_in2_ev~0); 3065846#L610-5 assume !(0 == ~main_sum_ev~0); 3065847#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3065840#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3065841#L625-5 assume !(0 == ~main_dbl_ev~0); 3065834#L630-5 assume !(0 == ~main_zero_ev~0); 3065835#L635-5 assume !(0 == ~main_clk_ev~0); 3065828#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3065829#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3065822#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3065823#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3065816#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3065817#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3065810#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3065811#L675-5 assume !(1 == ~main_in1_ev~0); 3065804#L680-5 assume !(1 == ~main_in2_ev~0); 3065805#L685-5 assume !(1 == ~main_sum_ev~0); 3067734#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3067733#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3067732#L700-5 assume !(1 == ~main_dbl_ev~0); 3067731#L705-5 assume !(1 == ~main_zero_ev~0); 3067730#L710-5 assume !(1 == ~main_clk_ev~0); 3067729#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3067728#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3067727#L725-5 assume !(0 == ~N_generate_st~0); 3067726#L733-4 assume !(0 == ~S1_addsub_st~0); 3067725#L736-4 assume !(0 == ~S2_presdbl_st~0); 3067724#L739-4 assume !(0 == ~S3_zero_st~0); 3067723#L742-4 assume !(0 == ~D_print_st~0); 3067722#L752-2 assume { :end_inline_start_simulation } true; 3065772#L795-2 [2021-12-07 01:23:53,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:53,882 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 4 times [2021-12-07 01:23:53,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:53,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560579734] [2021-12-07 01:23:53,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:53,882 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:53,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:53,888 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:53,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:53,903 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:53,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:53,903 INFO L85 PathProgramCache]: Analyzing trace with hash -1869810150, now seen corresponding path program 1 times [2021-12-07 01:23:53,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:53,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850767396] [2021-12-07 01:23:53,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:53,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:53,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:53,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:53,923 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:53,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850767396] [2021-12-07 01:23:53,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850767396] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:53,923 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:53,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:53,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010936831] [2021-12-07 01:23:53,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:53,924 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:53,924 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:53,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:53,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:53,924 INFO L87 Difference]: Start difference. First operand 92683 states and 128236 transitions. cyclomatic complexity: 35577 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:54,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:54,502 INFO L93 Difference]: Finished difference Result 185343 states and 252645 transitions. [2021-12-07 01:23:54,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:54,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 185343 states and 252645 transitions. [2021-12-07 01:23:55,132 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 179200 [2021-12-07 01:23:55,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 185343 states to 185343 states and 252645 transitions. [2021-12-07 01:23:55,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185343 [2021-12-07 01:23:55,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185343 [2021-12-07 01:23:55,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 185343 states and 252645 transitions. [2021-12-07 01:23:55,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:23:55,655 INFO L681 BuchiCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2021-12-07 01:23:55,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185343 states and 252645 transitions. [2021-12-07 01:23:56,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185343 to 185343. [2021-12-07 01:23:57,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185343 states, 185343 states have (on average 1.3631213479872453) internal successors, (252645), 185342 states have internal predecessors, (252645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:57,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185343 states to 185343 states and 252645 transitions. [2021-12-07 01:23:57,298 INFO L704 BuchiCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2021-12-07 01:23:57,298 INFO L587 BuchiCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2021-12-07 01:23:57,298 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-07 01:23:57,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185343 states and 252645 transitions. [2021-12-07 01:23:57,743 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 179200 [2021-12-07 01:23:57,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:23:57,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:23:57,746 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:57,746 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:23:57,746 INFO L791 eck$LassoCheckResult]: Stem: 3330698#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3330641#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3330131#L256 assume !(1 == ~main_in1_req_up~0); 3330094#L256-2 assume !(1 == ~main_in2_req_up~0); 3330096#L267-1 assume !(1 == ~main_sum_req_up~0); 3330484#L278-1 assume !(1 == ~main_diff_req_up~0); 3330078#L289-1 assume !(1 == ~main_pres_req_up~0); 3330079#L300-1 assume !(1 == ~main_dbl_req_up~0); 3330179#L311-1 assume !(1 == ~main_zero_req_up~0); 3330340#L322-1 assume !(1 == ~main_clk_req_up~0); 3330421#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3330311#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3330111#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3330112#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3330301#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3332333#L371-1 assume !(0 == ~main_in1_ev~0); 3330160#L376-1 assume !(0 == ~main_in2_ev~0); 3330161#L381-1 assume !(0 == ~main_sum_ev~0); 3330571#L386-1 assume !(0 == ~main_diff_ev~0); 3330600#L391-1 assume !(0 == ~main_pres_ev~0); 3330601#L396-1 assume !(0 == ~main_dbl_ev~0); 3344977#L401-1 assume !(0 == ~main_zero_ev~0); 3344975#L406-1 assume !(0 == ~main_clk_ev~0); 3344973#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3344971#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3344969#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3344966#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3344963#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3344960#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3344957#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3344954#L446-1 assume !(1 == ~main_in1_ev~0); 3344951#L451-1 assume !(1 == ~main_in2_ev~0); 3344948#L456-1 assume !(1 == ~main_sum_ev~0); 3344944#L461-1 assume !(1 == ~main_diff_ev~0); 3344939#L466-1 assume !(1 == ~main_pres_ev~0); 3344941#L471-1 assume !(1 == ~main_dbl_ev~0); 3344938#L476-1 assume !(1 == ~main_zero_ev~0); 3344933#L481-1 assume !(1 == ~main_clk_ev~0); 3344928#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3344924#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3344920#L742-1 assume !false; 3344916#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3344912#L229 assume !false; 3344908#L147 assume !(0 == ~N_generate_st~0); 3344904#L151 assume !(0 == ~S1_addsub_st~0); 3344900#L154 assume !(0 == ~S2_presdbl_st~0); 3344896#L157 assume !(0 == ~S3_zero_st~0); 3344892#L160 assume !(0 == ~D_print_st~0); 3344888#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3344884#L509 assume !(1 == ~main_in1_req_up~0); 3344878#L509-2 assume !(1 == ~main_in2_req_up~0); 3344871#L520-1 assume !(1 == ~main_sum_req_up~0); 3344872#L531-1 assume !(1 == ~main_diff_req_up~0); 3345085#L542-1 assume !(1 == ~main_pres_req_up~0); 3345331#L553-1 assume !(1 == ~main_dbl_req_up~0); 3345327#L564-1 assume !(1 == ~main_zero_req_up~0); 3345325#L575-1 assume !(1 == ~main_clk_req_up~0); 3345324#L586-1 start_simulation_~kernel_st~0#1 := 3; 3345323#L605 assume !(0 == ~main_in1_ev~0); 3345322#L605-2 assume !(0 == ~main_in2_ev~0); 3345321#L610-1 assume !(0 == ~main_sum_ev~0); 3345320#L615-1 assume !(0 == ~main_diff_ev~0); 3345319#L620-1 assume !(0 == ~main_pres_ev~0); 3345318#L625-1 assume !(0 == ~main_dbl_ev~0); 3345317#L630-1 assume !(0 == ~main_zero_ev~0); 3345316#L635-1 assume !(0 == ~main_clk_ev~0); 3345315#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3345314#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3345313#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3345312#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3345311#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3345310#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3345309#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3345308#L675-1 assume !(1 == ~main_in1_ev~0); 3345307#L680-1 assume !(1 == ~main_in2_ev~0); 3345306#L685-1 assume !(1 == ~main_sum_ev~0); 3345006#L690-1 assume !(1 == ~main_diff_ev~0); 3345049#L695-1 assume !(1 == ~main_pres_ev~0); 3345305#L700-1 assume !(1 == ~main_dbl_ev~0); 3345304#L705-1 assume !(1 == ~main_zero_ev~0); 3345303#L710-1 assume !(1 == ~main_clk_ev~0); 3345302#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3345301#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3345300#L725-1 assume !(0 == ~N_generate_st~0); 3345299#L733 assume !(0 == ~S1_addsub_st~0); 3345298#L736 assume !(0 == ~S2_presdbl_st~0); 3345297#L739 assume !(0 == ~S3_zero_st~0); 3345296#L742 assume !(0 == ~D_print_st~0); 3345294#L752 assume { :end_inline_start_simulation } true; 3345292#L795-2 [2021-12-07 01:23:57,747 INFO L793 eck$LassoCheckResult]: Loop: 3345292#L795-2 assume !false; 3345290#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3344786#L256-3 assume !(1 == ~main_in1_req_up~0); 3344787#L256-5 assume !(1 == ~main_in2_req_up~0); 3362703#L267-3 assume !(1 == ~main_sum_req_up~0); 3362704#L278-3 assume !(1 == ~main_diff_req_up~0); 3364899#L289-3 assume !(1 == ~main_pres_req_up~0); 3354440#L300-3 assume !(1 == ~main_dbl_req_up~0); 3354442#L311-3 assume !(1 == ~main_zero_req_up~0); 3369406#L322-3 assume 1 == ~main_clk_req_up~0; 3373214#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3373197#L334-3 ~main_clk_req_up~0 := 0; 3372554#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3371090#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3371089#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3371087#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3371085#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3371084#L371-3 assume !(0 == ~main_in1_ev~0); 3371083#L376-3 assume !(0 == ~main_in2_ev~0); 3371081#L381-3 assume !(0 == ~main_sum_ev~0); 3371079#L386-3 assume !(0 == ~main_diff_ev~0); 3369447#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3369445#L396-3 assume !(0 == ~main_dbl_ev~0); 3369442#L401-3 assume !(0 == ~main_zero_ev~0); 3367510#L406-3 assume !(0 == ~main_clk_ev~0); 3367509#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3367508#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3367506#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3367504#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3367503#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3367502#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3367500#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3367498#L446-3 assume !(1 == ~main_in1_ev~0); 3367496#L451-3 assume !(1 == ~main_in2_ev~0); 3367494#L456-3 assume !(1 == ~main_sum_ev~0); 3364870#L461-3 assume !(1 == ~main_diff_ev~0); 3362207#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3367489#L471-3 assume !(1 == ~main_dbl_ev~0); 3367487#L476-3 assume !(1 == ~main_zero_ev~0); 3367485#L481-3 assume !(1 == ~main_clk_ev~0); 3367483#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3367481#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3367479#L742-3 assume !false; 3367477#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3367475#L229-1 assume !false; 3367473#L147-1 assume !(0 == ~N_generate_st~0); 3367472#L151-2 assume !(0 == ~S1_addsub_st~0); 3366082#L154-2 assume !(0 == ~S2_presdbl_st~0); 3366080#L157-2 assume !(0 == ~S3_zero_st~0); 3364735#L160-2 assume !(0 == ~D_print_st~0); 3364734#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3340817#L509-3 assume !(1 == ~main_in1_req_up~0); 3340818#L509-5 assume !(1 == ~main_in2_req_up~0); 3340802#L520-3 assume !(1 == ~main_sum_req_up~0); 3340803#L531-3 assume !(1 == ~main_diff_req_up~0); 3341099#L542-3 assume !(1 == ~main_pres_req_up~0); 3363907#L553-3 assume !(1 == ~main_dbl_req_up~0); 3363900#L564-3 assume !(1 == ~main_zero_req_up~0); 3363899#L575-3 assume !(1 == ~main_clk_req_up~0); 3363898#L586-3 start_simulation_~kernel_st~0#1 := 3; 3363897#L605-3 assume !(0 == ~main_in1_ev~0); 3363896#L605-5 assume !(0 == ~main_in2_ev~0); 3363895#L610-3 assume !(0 == ~main_sum_ev~0); 3363894#L615-3 assume !(0 == ~main_diff_ev~0); 3363893#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3363892#L625-3 assume !(0 == ~main_dbl_ev~0); 3363891#L630-3 assume !(0 == ~main_zero_ev~0); 3363890#L635-3 assume !(0 == ~main_clk_ev~0); 3363889#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3363888#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3363887#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3363886#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3363885#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3363884#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3363883#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3363882#L675-3 assume !(1 == ~main_in1_ev~0); 3363881#L680-3 assume !(1 == ~main_in2_ev~0); 3363878#L685-3 assume !(1 == ~main_sum_ev~0); 3340493#L690-3 assume !(1 == ~main_diff_ev~0); 3363877#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3363876#L700-3 assume !(1 == ~main_dbl_ev~0); 3363875#L705-3 assume !(1 == ~main_zero_ev~0); 3363874#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3363873#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3363872#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3363871#L725-3 assume !(0 == ~N_generate_st~0); 3363870#L733-2 assume !(0 == ~S1_addsub_st~0); 3363869#L736-2 assume !(0 == ~S2_presdbl_st~0); 3363868#L739-2 assume !(0 == ~S3_zero_st~0); 3363866#L742-2 assume !(0 == ~D_print_st~0); 3340457#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3340458#L803 assume !(5 == main_~count~0#1); 3363304#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3363303#L256-6 assume !(1 == ~main_in1_req_up~0); 3363300#L256-8 assume !(1 == ~main_in2_req_up~0); 3363294#L267-5 assume !(1 == ~main_sum_req_up~0); 3363282#L278-5 assume !(1 == ~main_diff_req_up~0); 3363277#L289-5 assume !(1 == ~main_pres_req_up~0); 3363271#L300-5 assume !(1 == ~main_dbl_req_up~0); 3363265#L311-5 assume !(1 == ~main_zero_req_up~0); 3363262#L322-5 assume 1 == ~main_clk_req_up~0; 3363258#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3363256#L334-5 ~main_clk_req_up~0 := 0; 3363254#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3363252#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3363250#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3363248#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3363246#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3363244#L371-5 assume !(0 == ~main_in1_ev~0); 3363242#L376-5 assume !(0 == ~main_in2_ev~0); 3363240#L381-5 assume !(0 == ~main_sum_ev~0); 3363238#L386-5 assume !(0 == ~main_diff_ev~0); 3363236#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3363234#L396-5 assume !(0 == ~main_dbl_ev~0); 3363232#L401-5 assume !(0 == ~main_zero_ev~0); 3363230#L406-5 assume !(0 == ~main_clk_ev~0); 3363228#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3363226#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3363224#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3363222#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3363220#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3363218#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3363216#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3363214#L446-5 assume !(1 == ~main_in1_ev~0); 3363212#L451-5 assume !(1 == ~main_in2_ev~0); 3363211#L456-5 assume !(1 == ~main_sum_ev~0); 3363208#L461-5 assume !(1 == ~main_diff_ev~0); 3363205#L466-5 assume !(1 == ~main_pres_ev~0); 3363204#L471-5 assume !(1 == ~main_dbl_ev~0); 3363203#L476-5 assume !(1 == ~main_zero_ev~0); 3363202#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3363201#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3363200#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3363199#L742-5 assume !false; 3363198#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3363197#L229-2 assume !false; 3363196#L147-2 assume !(0 == ~N_generate_st~0); 3363195#L151-4 assume !(0 == ~S1_addsub_st~0); 3363194#L154-4 assume !(0 == ~S2_presdbl_st~0); 3363192#L157-4 assume !(0 == ~S3_zero_st~0); 3345288#L160-4 assume !(0 == ~D_print_st~0); 3345287#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3345281#L509-6 assume !(1 == ~main_in1_req_up~0); 3345282#L509-8 assume !(1 == ~main_in2_req_up~0); 3363180#L520-5 assume !(1 == ~main_sum_req_up~0); 3363177#L531-5 assume !(1 == ~main_diff_req_up~0); 3345388#L542-5 assume !(1 == ~main_pres_req_up~0); 3345384#L553-5 assume !(1 == ~main_dbl_req_up~0); 3345378#L564-5 assume !(1 == ~main_zero_req_up~0); 3345376#L575-5 assume !(1 == ~main_clk_req_up~0); 3345375#L586-5 start_simulation_~kernel_st~0#1 := 3; 3345374#L605-6 assume !(0 == ~main_in1_ev~0); 3345373#L605-8 assume !(0 == ~main_in2_ev~0); 3345372#L610-5 assume !(0 == ~main_sum_ev~0); 3345371#L615-5 assume !(0 == ~main_diff_ev~0); 3345370#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3345369#L625-5 assume !(0 == ~main_dbl_ev~0); 3345368#L630-5 assume !(0 == ~main_zero_ev~0); 3345367#L635-5 assume !(0 == ~main_clk_ev~0); 3345366#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3345365#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3345364#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3345363#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3345362#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3345361#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3345360#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3345359#L675-5 assume !(1 == ~main_in1_ev~0); 3345358#L680-5 assume !(1 == ~main_in2_ev~0); 3345356#L685-5 assume !(1 == ~main_sum_ev~0); 3345357#L690-5 assume !(1 == ~main_diff_ev~0); 3364543#L695-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3364541#L700-5 assume !(1 == ~main_dbl_ev~0); 3364539#L705-5 assume !(1 == ~main_zero_ev~0); 3345352#L710-5 assume !(1 == ~main_clk_ev~0); 3345351#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3345349#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3345347#L725-5 assume !(0 == ~N_generate_st~0); 3345344#L733-4 assume !(0 == ~S1_addsub_st~0); 3345345#L736-4 assume !(0 == ~S2_presdbl_st~0); 3364487#L739-4 assume !(0 == ~S3_zero_st~0); 3364485#L742-4 assume !(0 == ~D_print_st~0); 3345295#L752-2 assume { :end_inline_start_simulation } true; 3345292#L795-2 [2021-12-07 01:23:57,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:57,747 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 5 times [2021-12-07 01:23:57,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:57,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774157627] [2021-12-07 01:23:57,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:57,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:57,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:57,756 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:23:57,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:23:57,775 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:23:57,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:23:57,775 INFO L85 PathProgramCache]: Analyzing trace with hash -316895336, now seen corresponding path program 1 times [2021-12-07 01:23:57,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:23:57,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312021957] [2021-12-07 01:23:57,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:23:57,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:23:57,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:23:57,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:23:57,793 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:23:57,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312021957] [2021-12-07 01:23:57,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312021957] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:23:57,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:23:57,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:23:57,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743267167] [2021-12-07 01:23:57,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:23:57,794 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:23:57,794 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:23:57,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:23:57,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:23:57,794 INFO L87 Difference]: Start difference. First operand 185343 states and 252645 transitions. cyclomatic complexity: 67326 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:23:59,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:23:59,007 INFO L93 Difference]: Finished difference Result 370639 states and 497633 transitions. [2021-12-07 01:23:59,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:23:59,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370639 states and 497633 transitions. [2021-12-07 01:24:00,507 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2021-12-07 01:24:01,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370639 states to 370639 states and 497633 transitions. [2021-12-07 01:24:01,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370639 [2021-12-07 01:24:01,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370639 [2021-12-07 01:24:01,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370639 states and 497633 transitions. [2021-12-07 01:24:01,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:01,520 INFO L681 BuchiCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2021-12-07 01:24:01,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370639 states and 497633 transitions. [2021-12-07 01:24:03,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370639 to 370639. [2021-12-07 01:24:03,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370639 states, 370639 states have (on average 1.3426352866266098) internal successors, (497633), 370638 states have internal predecessors, (497633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:04,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370639 states to 370639 states and 497633 transitions. [2021-12-07 01:24:04,514 INFO L704 BuchiCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2021-12-07 01:24:04,514 INFO L587 BuchiCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2021-12-07 01:24:04,514 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-07 01:24:04,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370639 states and 497633 transitions. [2021-12-07 01:24:05,590 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2021-12-07 01:24:05,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:24:05,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:24:05,592 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:05,592 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:05,593 INFO L791 eck$LassoCheckResult]: Stem: 3886699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3886635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3886119#L256 assume !(1 == ~main_in1_req_up~0); 3886082#L256-2 assume !(1 == ~main_in2_req_up~0); 3886084#L267-1 assume !(1 == ~main_sum_req_up~0); 3886478#L278-1 assume !(1 == ~main_diff_req_up~0); 3886066#L289-1 assume !(1 == ~main_pres_req_up~0); 3886067#L300-1 assume !(1 == ~main_dbl_req_up~0); 3886166#L311-1 assume !(1 == ~main_zero_req_up~0); 3886334#L322-1 assume !(1 == ~main_clk_req_up~0); 3886411#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3886412#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3886100#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3886101#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3886292#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3886285#L371-1 assume !(0 == ~main_in1_ev~0); 3886286#L376-1 assume !(0 == ~main_in2_ev~0); 3889633#L381-1 assume !(0 == ~main_sum_ev~0); 3886313#L386-1 assume !(0 == ~main_diff_ev~0); 3886314#L391-1 assume !(0 == ~main_pres_ev~0); 3889640#L396-1 assume !(0 == ~main_dbl_ev~0); 3889641#L401-1 assume !(0 == ~main_zero_ev~0); 3902454#L406-1 assume !(0 == ~main_clk_ev~0); 3902452#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3902450#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3902448#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3902446#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3902444#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3902442#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3902440#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3902438#L446-1 assume !(1 == ~main_in1_ev~0); 3902436#L451-1 assume !(1 == ~main_in2_ev~0); 3902434#L456-1 assume !(1 == ~main_sum_ev~0); 3901673#L461-1 assume !(1 == ~main_diff_ev~0); 3902431#L466-1 assume !(1 == ~main_pres_ev~0); 3901649#L471-1 assume !(1 == ~main_dbl_ev~0); 3902402#L476-1 assume !(1 == ~main_zero_ev~0); 3902401#L481-1 assume !(1 == ~main_clk_ev~0); 3902400#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3902399#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3902398#L742-1 assume !false; 3902397#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3902396#L229 assume !false; 3902395#L147 assume !(0 == ~N_generate_st~0); 3902394#L151 assume !(0 == ~S1_addsub_st~0); 3902393#L154 assume !(0 == ~S2_presdbl_st~0); 3902392#L157 assume !(0 == ~S3_zero_st~0); 3902391#L160 assume !(0 == ~D_print_st~0); 3902390#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3902389#L509 assume !(1 == ~main_in1_req_up~0); 3887227#L509-2 assume !(1 == ~main_in2_req_up~0); 3887228#L520-1 assume !(1 == ~main_sum_req_up~0); 3903135#L531-1 assume !(1 == ~main_diff_req_up~0); 3904295#L542-1 assume !(1 == ~main_pres_req_up~0); 3904167#L553-1 assume !(1 == ~main_dbl_req_up~0); 3904152#L564-1 assume !(1 == ~main_zero_req_up~0); 3904153#L575-1 assume !(1 == ~main_clk_req_up~0); 3904388#L586-1 start_simulation_~kernel_st~0#1 := 3; 3904389#L605 assume !(0 == ~main_in1_ev~0); 3904380#L605-2 assume !(0 == ~main_in2_ev~0); 3904381#L610-1 assume !(0 == ~main_sum_ev~0); 3904372#L615-1 assume !(0 == ~main_diff_ev~0); 3904373#L620-1 assume !(0 == ~main_pres_ev~0); 3904364#L625-1 assume !(0 == ~main_dbl_ev~0); 3904365#L630-1 assume !(0 == ~main_zero_ev~0); 3904358#L635-1 assume !(0 == ~main_clk_ev~0); 3904359#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3904350#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3904351#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3904342#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3904343#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3904331#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3904332#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3904320#L675-1 assume !(1 == ~main_in1_ev~0); 3904321#L680-1 assume !(1 == ~main_in2_ev~0); 3904191#L685-1 assume !(1 == ~main_sum_ev~0); 3903041#L690-1 assume !(1 == ~main_diff_ev~0); 3904182#L695-1 assume !(1 == ~main_pres_ev~0); 3904183#L700-1 assume !(1 == ~main_dbl_ev~0); 3904045#L705-1 assume !(1 == ~main_zero_ev~0); 3904046#L710-1 assume !(1 == ~main_clk_ev~0); 3904040#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3904041#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3904036#L725-1 assume !(0 == ~N_generate_st~0); 3904037#L733 assume !(0 == ~S1_addsub_st~0); 3904032#L736 assume !(0 == ~S2_presdbl_st~0); 3904033#L739 assume !(0 == ~S3_zero_st~0); 3904028#L742 assume !(0 == ~D_print_st~0); 3904029#L752 assume { :end_inline_start_simulation } true; 3904020#L795-2 [2021-12-07 01:24:05,593 INFO L793 eck$LassoCheckResult]: Loop: 3904020#L795-2 assume !false; 3904021#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3903254#L256-3 assume !(1 == ~main_in1_req_up~0); 3903255#L256-5 assume !(1 == ~main_in2_req_up~0); 3945379#L267-3 assume !(1 == ~main_sum_req_up~0); 3945380#L278-3 assume !(1 == ~main_diff_req_up~0); 3947104#L289-3 assume !(1 == ~main_pres_req_up~0); 3947105#L300-3 assume !(1 == ~main_dbl_req_up~0); 3956401#L311-3 assume !(1 == ~main_zero_req_up~0); 3956399#L322-3 assume 1 == ~main_clk_req_up~0; 3956396#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3956394#L334-3 ~main_clk_req_up~0 := 0; 3956392#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3956390#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3956389#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3956388#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3956381#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3956377#L371-3 assume !(0 == ~main_in1_ev~0); 3955123#L376-3 assume !(0 == ~main_in2_ev~0); 3953274#L381-3 assume !(0 == ~main_sum_ev~0); 3953272#L386-3 assume !(0 == ~main_diff_ev~0); 3951964#L391-3 assume !(0 == ~main_pres_ev~0); 3951269#L396-3 assume !(0 == ~main_dbl_ev~0); 3950707#L401-3 assume !(0 == ~main_zero_ev~0); 3950703#L406-3 assume !(0 == ~main_clk_ev~0); 3950699#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3950695#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3950692#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3950691#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3950689#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3950688#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3950687#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3950684#L446-3 assume !(1 == ~main_in1_ev~0); 3950683#L451-3 assume !(1 == ~main_in2_ev~0); 3950681#L456-3 assume !(1 == ~main_sum_ev~0); 3947227#L461-3 assume !(1 == ~main_diff_ev~0); 3947896#L466-3 assume !(1 == ~main_pres_ev~0); 3947016#L471-3 assume !(1 == ~main_dbl_ev~0); 3950679#L476-3 assume !(1 == ~main_zero_ev~0); 3950677#L481-3 assume !(1 == ~main_clk_ev~0); 3950675#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3950673#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3950671#L742-3 assume !false; 3950669#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3950667#L229-1 assume !false; 3950665#L147-1 assume !(0 == ~N_generate_st~0); 3949956#L151-2 assume !(0 == ~S1_addsub_st~0); 3947222#L154-2 assume !(0 == ~S2_presdbl_st~0); 3947218#L157-2 assume !(0 == ~S3_zero_st~0); 3918536#L160-2 assume !(0 == ~D_print_st~0); 3918534#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3918532#L509-3 assume !(1 == ~main_in1_req_up~0); 3918525#L509-5 assume !(1 == ~main_in2_req_up~0); 3918522#L520-3 assume !(1 == ~main_sum_req_up~0); 3918523#L531-3 assume !(1 == ~main_diff_req_up~0); 3919195#L542-3 assume !(1 == ~main_pres_req_up~0); 3948179#L553-3 assume !(1 == ~main_dbl_req_up~0); 3950120#L564-3 assume !(1 == ~main_zero_req_up~0); 3950119#L575-3 assume !(1 == ~main_clk_req_up~0); 3950118#L586-3 start_simulation_~kernel_st~0#1 := 3; 3950117#L605-3 assume !(0 == ~main_in1_ev~0); 3950116#L605-5 assume !(0 == ~main_in2_ev~0); 3950115#L610-3 assume !(0 == ~main_sum_ev~0); 3950114#L615-3 assume !(0 == ~main_diff_ev~0); 3950113#L620-3 assume !(0 == ~main_pres_ev~0); 3950112#L625-3 assume !(0 == ~main_dbl_ev~0); 3950111#L630-3 assume !(0 == ~main_zero_ev~0); 3950110#L635-3 assume !(0 == ~main_clk_ev~0); 3950109#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3950108#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3950107#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3950106#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3950105#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3950104#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3950103#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3950102#L675-3 assume !(1 == ~main_in1_ev~0); 3950101#L680-3 assume !(1 == ~main_in2_ev~0); 3950100#L685-3 assume !(1 == ~main_sum_ev~0); 3918606#L690-3 assume !(1 == ~main_diff_ev~0); 3918600#L695-3 assume !(1 == ~main_pres_ev~0); 3948143#L700-3 assume !(1 == ~main_dbl_ev~0); 3950099#L705-3 assume !(1 == ~main_zero_ev~0); 3950098#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3950097#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3950096#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3950095#L725-3 assume !(0 == ~N_generate_st~0); 3950093#L733-2 assume !(0 == ~S1_addsub_st~0); 3950091#L736-2 assume !(0 == ~S2_presdbl_st~0); 3950089#L739-2 assume !(0 == ~S3_zero_st~0); 3950087#L742-2 assume !(0 == ~D_print_st~0); 3950085#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3918567#L803 assume !(5 == main_~count~0#1); 3918565#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3918563#L256-6 assume !(1 == ~main_in1_req_up~0); 3918561#L256-8 assume !(1 == ~main_in2_req_up~0); 3918556#L267-5 assume !(1 == ~main_sum_req_up~0); 3918557#L278-5 assume !(1 == ~main_diff_req_up~0); 3948213#L289-5 assume !(1 == ~main_pres_req_up~0); 3948688#L300-5 assume !(1 == ~main_dbl_req_up~0); 3948682#L311-5 assume !(1 == ~main_zero_req_up~0); 3948677#L322-5 assume 1 == ~main_clk_req_up~0; 3948672#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3948668#L334-5 ~main_clk_req_up~0 := 0; 3948666#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3948663#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3948661#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3948659#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3948657#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3948655#L371-5 assume !(0 == ~main_in1_ev~0); 3948653#L376-5 assume !(0 == ~main_in2_ev~0); 3948651#L381-5 assume !(0 == ~main_sum_ev~0); 3948649#L386-5 assume !(0 == ~main_diff_ev~0); 3948647#L391-5 assume !(0 == ~main_pres_ev~0); 3948645#L396-5 assume !(0 == ~main_dbl_ev~0); 3948643#L401-5 assume !(0 == ~main_zero_ev~0); 3948641#L406-5 assume !(0 == ~main_clk_ev~0); 3948639#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3948637#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3948635#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3948633#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3948631#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3948629#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3948627#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3948625#L446-5 assume !(1 == ~main_in1_ev~0); 3948623#L451-5 assume !(1 == ~main_in2_ev~0); 3948621#L456-5 assume !(1 == ~main_sum_ev~0); 3948617#L461-5 assume !(1 == ~main_diff_ev~0); 3946686#L466-5 assume !(1 == ~main_pres_ev~0); 3946684#L471-5 assume !(1 == ~main_dbl_ev~0); 3946682#L476-5 assume !(1 == ~main_zero_ev~0); 3946680#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3946679#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3946678#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3946677#L742-5 assume !false; 3946676#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3946675#L229-2 assume !false; 3946674#L147-2 assume !(0 == ~N_generate_st~0); 3946673#L151-4 assume !(0 == ~S1_addsub_st~0); 3946672#L154-4 assume !(0 == ~S2_presdbl_st~0); 3946671#L157-4 assume !(0 == ~S3_zero_st~0); 3936374#L160-4 assume !(0 == ~D_print_st~0); 3936373#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3936372#L509-6 assume !(1 == ~main_in1_req_up~0); 3936371#L509-8 assume !(1 == ~main_in2_req_up~0); 3903570#L520-5 assume !(1 == ~main_sum_req_up~0); 3904682#L531-5 assume !(1 == ~main_diff_req_up~0); 3904677#L542-5 assume !(1 == ~main_pres_req_up~0); 3904678#L553-5 assume !(1 == ~main_dbl_req_up~0); 3946080#L564-5 assume !(1 == ~main_zero_req_up~0); 3904864#L575-5 assume !(1 == ~main_clk_req_up~0); 3904854#L586-5 start_simulation_~kernel_st~0#1 := 3; 3904855#L605-6 assume !(0 == ~main_in1_ev~0); 3904837#L605-8 assume !(0 == ~main_in2_ev~0); 3904838#L610-5 assume !(0 == ~main_sum_ev~0); 3904820#L615-5 assume !(0 == ~main_diff_ev~0); 3904821#L620-5 assume !(0 == ~main_pres_ev~0); 3904805#L625-5 assume !(0 == ~main_dbl_ev~0); 3904806#L630-5 assume !(0 == ~main_zero_ev~0); 3904791#L635-5 assume !(0 == ~main_clk_ev~0); 3904792#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3904778#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3904779#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3904764#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3904765#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3904750#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3904751#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3938326#L675-5 assume !(1 == ~main_in1_ev~0); 3947428#L680-5 assume !(1 == ~main_in2_ev~0); 3904718#L685-5 assume !(1 == ~main_sum_ev~0); 3904719#L690-5 assume !(1 == ~main_diff_ev~0); 3904697#L695-5 assume !(1 == ~main_pres_ev~0); 3904698#L700-5 assume !(1 == ~main_dbl_ev~0); 3904482#L705-5 assume !(1 == ~main_zero_ev~0); 3904483#L710-5 assume !(1 == ~main_clk_ev~0); 3904458#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3904459#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3904444#L725-5 assume !(0 == ~N_generate_st~0); 3904445#L733-4 assume !(0 == ~S1_addsub_st~0); 3904427#L736-4 assume !(0 == ~S2_presdbl_st~0); 3904428#L739-4 assume !(0 == ~S3_zero_st~0); 3904406#L742-4 assume !(0 == ~D_print_st~0); 3904407#L752-2 assume { :end_inline_start_simulation } true; 3904020#L795-2 [2021-12-07 01:24:05,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:05,593 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 6 times [2021-12-07 01:24:05,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:05,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862144544] [2021-12-07 01:24:05,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:05,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:05,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:05,600 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:24:05,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:05,613 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:24:05,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:05,614 INFO L85 PathProgramCache]: Analyzing trace with hash -22223594, now seen corresponding path program 1 times [2021-12-07 01:24:05,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:05,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169191458] [2021-12-07 01:24:05,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:05,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:05,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:24:05,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:24:05,633 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:24:05,633 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169191458] [2021-12-07 01:24:05,633 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169191458] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:24:05,633 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:24:05,634 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:24:05,634 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [441120203] [2021-12-07 01:24:05,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:24:05,634 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:24:05,634 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:24:05,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:24:05,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:24:05,634 INFO L87 Difference]: Start difference. First operand 370639 states and 497633 transitions. cyclomatic complexity: 127018 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:06,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:24:06,620 INFO L93 Difference]: Finished difference Result 370639 states and 495201 transitions. [2021-12-07 01:24:06,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:24:06,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370639 states and 495201 transitions. [2021-12-07 01:24:07,989 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2021-12-07 01:24:08,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370639 states to 370639 states and 495201 transitions. [2021-12-07 01:24:08,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370639 [2021-12-07 01:24:08,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370639 [2021-12-07 01:24:08,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370639 states and 495201 transitions. [2021-12-07 01:24:09,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:09,020 INFO L681 BuchiCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2021-12-07 01:24:09,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370639 states and 495201 transitions. [2021-12-07 01:24:11,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370639 to 370639. [2021-12-07 01:24:11,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370639 states, 370639 states have (on average 1.3360736457847124) internal successors, (495201), 370638 states have internal predecessors, (495201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:12,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370639 states to 370639 states and 495201 transitions. [2021-12-07 01:24:12,412 INFO L704 BuchiCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2021-12-07 01:24:12,412 INFO L587 BuchiCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2021-12-07 01:24:12,412 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-07 01:24:12,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370639 states and 495201 transitions. [2021-12-07 01:24:13,399 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2021-12-07 01:24:13,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:24:13,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:24:13,400 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:13,401 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:13,401 INFO L791 eck$LassoCheckResult]: Stem: 4627968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4627907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4627403#L256 assume !(1 == ~main_in1_req_up~0); 4627366#L256-2 assume !(1 == ~main_in2_req_up~0); 4627368#L267-1 assume !(1 == ~main_sum_req_up~0); 4627759#L278-1 assume !(1 == ~main_diff_req_up~0); 4627350#L289-1 assume !(1 == ~main_pres_req_up~0); 4627351#L300-1 assume !(1 == ~main_dbl_req_up~0); 4627450#L311-1 assume !(1 == ~main_zero_req_up~0); 4627612#L322-1 assume !(1 == ~main_clk_req_up~0); 4627691#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4627692#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4627384#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4627385#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4627573#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4627564#L371-1 assume !(0 == ~main_in1_ev~0); 4627565#L376-1 assume !(0 == ~main_in2_ev~0); 4631015#L381-1 assume !(0 == ~main_sum_ev~0); 4627593#L386-1 assume !(0 == ~main_diff_ev~0); 4627594#L391-1 assume !(0 == ~main_pres_ev~0); 4631023#L396-1 assume !(0 == ~main_dbl_ev~0); 4631024#L401-1 assume !(0 == ~main_zero_ev~0); 4643752#L406-1 assume !(0 == ~main_clk_ev~0); 4643749#L411-1 assume !(0 == ~main_clk_pos_edge~0); 4643750#L416-1 assume !(0 == ~main_clk_neg_edge~0); 4643745#L421-1 assume !(1 == ~main_clk_pos_edge~0); 4643746#L426-1 assume !(1 == ~main_clk_pos_edge~0); 4643741#L431-1 assume !(1 == ~main_clk_pos_edge~0); 4643742#L436-1 assume !(1 == ~main_clk_pos_edge~0); 4643737#L441-1 assume !(1 == ~main_clk_pos_edge~0); 4643738#L446-1 assume !(1 == ~main_in1_ev~0); 4643733#L451-1 assume !(1 == ~main_in2_ev~0); 4643734#L456-1 assume !(1 == ~main_sum_ev~0); 4643731#L461-1 assume !(1 == ~main_diff_ev~0); 4643449#L466-1 assume !(1 == ~main_pres_ev~0); 4643728#L471-1 assume !(1 == ~main_dbl_ev~0); 4643729#L476-1 assume !(1 == ~main_zero_ev~0); 4643711#L481-1 assume !(1 == ~main_clk_ev~0); 4643712#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4643707#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4643708#L742-1 assume !false; 4643703#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4643704#L229 assume !false; 4643699#L147 assume !(0 == ~N_generate_st~0); 4643700#L151 assume !(0 == ~S1_addsub_st~0); 4643695#L154 assume !(0 == ~S2_presdbl_st~0); 4643696#L157 assume !(0 == ~S3_zero_st~0); 4643691#L160 assume !(0 == ~D_print_st~0); 4643692#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4643687#L509 assume !(1 == ~main_in1_req_up~0); 4643688#L509-2 assume !(1 == ~main_in2_req_up~0); 4644125#L520-1 assume !(1 == ~main_sum_req_up~0); 4644126#L531-1 assume !(1 == ~main_diff_req_up~0); 4671764#L542-1 assume !(1 == ~main_pres_req_up~0); 4671765#L553-1 assume !(1 == ~main_dbl_req_up~0); 4647406#L564-1 assume !(1 == ~main_zero_req_up~0); 4647407#L575-1 assume !(1 == ~main_clk_req_up~0); 4647503#L586-1 start_simulation_~kernel_st~0#1 := 3; 4647504#L605 assume !(0 == ~main_in1_ev~0); 4647495#L605-2 assume !(0 == ~main_in2_ev~0); 4647496#L610-1 assume !(0 == ~main_sum_ev~0); 4647487#L615-1 assume !(0 == ~main_diff_ev~0); 4647488#L620-1 assume !(0 == ~main_pres_ev~0); 4647479#L625-1 assume !(0 == ~main_dbl_ev~0); 4647480#L630-1 assume !(0 == ~main_zero_ev~0); 4647472#L635-1 assume !(0 == ~main_clk_ev~0); 4647473#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4647465#L645-1 assume !(0 == ~main_clk_neg_edge~0); 4647466#L650-1 assume !(1 == ~main_clk_pos_edge~0); 4647457#L655-1 assume !(1 == ~main_clk_pos_edge~0); 4647458#L660-1 assume !(1 == ~main_clk_pos_edge~0); 4647445#L665-1 assume !(1 == ~main_clk_pos_edge~0); 4647446#L670-1 assume !(1 == ~main_clk_pos_edge~0); 4647430#L675-1 assume !(1 == ~main_in1_ev~0); 4647431#L680-1 assume !(1 == ~main_in2_ev~0); 4647423#L685-1 assume !(1 == ~main_sum_ev~0); 4643972#L690-1 assume !(1 == ~main_diff_ev~0); 4647416#L695-1 assume !(1 == ~main_pres_ev~0); 4647417#L700-1 assume !(1 == ~main_dbl_ev~0); 4647354#L705-1 assume !(1 == ~main_zero_ev~0); 4647355#L710-1 assume !(1 == ~main_clk_ev~0); 4647349#L715-1 assume !(1 == ~main_clk_pos_edge~0); 4647350#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4647345#L725-1 assume !(0 == ~N_generate_st~0); 4647346#L733 assume !(0 == ~S1_addsub_st~0); 4647341#L736 assume !(0 == ~S2_presdbl_st~0); 4647342#L739 assume !(0 == ~S3_zero_st~0); 4647337#L742 assume !(0 == ~D_print_st~0); 4647338#L752 assume { :end_inline_start_simulation } true; 4672721#L795-2 [2021-12-07 01:24:13,401 INFO L793 eck$LassoCheckResult]: Loop: 4672721#L795-2 assume !false; 4714829#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4714827#L256-3 assume !(1 == ~main_in1_req_up~0); 4672714#L256-5 assume !(1 == ~main_in2_req_up~0); 4672715#L267-3 assume !(1 == ~main_sum_req_up~0); 4715403#L278-3 assume !(1 == ~main_diff_req_up~0); 4715400#L289-3 assume !(1 == ~main_pres_req_up~0); 4715401#L300-3 assume !(1 == ~main_dbl_req_up~0); 4723356#L311-3 assume !(1 == ~main_zero_req_up~0); 4723353#L322-3 assume 1 == ~main_clk_req_up~0; 4723350#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 4723348#L334-3 ~main_clk_req_up~0 := 0; 4723347#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4723345#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4723343#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4723341#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4723339#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4723337#L371-3 assume !(0 == ~main_in1_ev~0); 4723335#L376-3 assume !(0 == ~main_in2_ev~0); 4723333#L381-3 assume !(0 == ~main_sum_ev~0); 4723331#L386-3 assume !(0 == ~main_diff_ev~0); 4723329#L391-3 assume !(0 == ~main_pres_ev~0); 4723327#L396-3 assume !(0 == ~main_dbl_ev~0); 4723325#L401-3 assume !(0 == ~main_zero_ev~0); 4723323#L406-3 assume !(0 == ~main_clk_ev~0); 4723321#L411-3 assume !(0 == ~main_clk_pos_edge~0); 4723319#L416-3 assume !(0 == ~main_clk_neg_edge~0); 4723317#L421-3 assume !(1 == ~main_clk_pos_edge~0); 4723315#L426-3 assume !(1 == ~main_clk_pos_edge~0); 4723312#L431-3 assume !(1 == ~main_clk_pos_edge~0); 4723310#L436-3 assume !(1 == ~main_clk_pos_edge~0); 4723309#L441-3 assume !(1 == ~main_clk_pos_edge~0); 4723307#L446-3 assume !(1 == ~main_in1_ev~0); 4723305#L451-3 assume !(1 == ~main_in2_ev~0); 4715474#L456-3 assume !(1 == ~main_sum_ev~0); 4715470#L461-3 assume !(1 == ~main_diff_ev~0); 4714248#L466-3 assume !(1 == ~main_pres_ev~0); 4715280#L471-3 assume !(1 == ~main_dbl_ev~0); 4715466#L476-3 assume !(1 == ~main_zero_ev~0); 4715464#L481-3 assume !(1 == ~main_clk_ev~0); 4715462#L486-3 assume !(1 == ~main_clk_pos_edge~0); 4715460#L491-3 assume !(1 == ~main_clk_neg_edge~0); 4715458#L742-3 assume !false; 4715457#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4715455#L229-1 assume !false; 4715453#L147-1 assume !(0 == ~N_generate_st~0); 4714311#L151-2 assume !(0 == ~S1_addsub_st~0); 4713850#L154-2 assume !(0 == ~S2_presdbl_st~0); 4713849#L157-2 assume !(0 == ~S3_zero_st~0); 4713848#L160-2 assume !(0 == ~D_print_st~0); 4713847#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4713846#L509-3 assume !(1 == ~main_in1_req_up~0); 4663840#L509-5 assume !(1 == ~main_in2_req_up~0); 4663841#L520-3 assume !(1 == ~main_sum_req_up~0); 4717150#L531-3 assume !(1 == ~main_diff_req_up~0); 4717151#L542-3 assume !(1 == ~main_pres_req_up~0); 4718391#L553-3 assume !(1 == ~main_dbl_req_up~0); 4722483#L564-3 assume !(1 == ~main_zero_req_up~0); 4722482#L575-3 assume !(1 == ~main_clk_req_up~0); 4722481#L586-3 start_simulation_~kernel_st~0#1 := 3; 4722480#L605-3 assume !(0 == ~main_in1_ev~0); 4722479#L605-5 assume !(0 == ~main_in2_ev~0); 4722478#L610-3 assume !(0 == ~main_sum_ev~0); 4722477#L615-3 assume !(0 == ~main_diff_ev~0); 4722476#L620-3 assume !(0 == ~main_pres_ev~0); 4722475#L625-3 assume !(0 == ~main_dbl_ev~0); 4722474#L630-3 assume !(0 == ~main_zero_ev~0); 4722473#L635-3 assume !(0 == ~main_clk_ev~0); 4722472#L640-3 assume !(0 == ~main_clk_pos_edge~0); 4722471#L645-3 assume !(0 == ~main_clk_neg_edge~0); 4664315#L650-3 assume !(1 == ~main_clk_pos_edge~0); 4664313#L655-3 assume !(1 == ~main_clk_pos_edge~0); 4664311#L660-3 assume !(1 == ~main_clk_pos_edge~0); 4664294#L665-3 assume !(1 == ~main_clk_pos_edge~0); 4664291#L670-3 assume !(1 == ~main_clk_pos_edge~0); 4664287#L675-3 assume !(1 == ~main_in1_ev~0); 4664288#L680-3 assume !(1 == ~main_in2_ev~0); 4664273#L685-3 assume !(1 == ~main_sum_ev~0); 4663249#L690-3 assume !(1 == ~main_diff_ev~0); 4663244#L695-3 assume !(1 == ~main_pres_ev~0); 4663240#L700-3 assume !(1 == ~main_dbl_ev~0); 4663238#L705-3 assume !(1 == ~main_zero_ev~0); 4663236#L710-3 assume !(1 == ~main_clk_ev~0); 4663234#L715-3 assume !(1 == ~main_clk_pos_edge~0); 4663232#L720-3 assume !(1 == ~main_clk_neg_edge~0); 4663230#L725-3 assume !(0 == ~N_generate_st~0); 4663228#L733-2 assume !(0 == ~S1_addsub_st~0); 4663226#L736-2 assume !(0 == ~S2_presdbl_st~0); 4663225#L739-2 assume !(0 == ~S3_zero_st~0); 4663223#L742-2 assume !(0 == ~D_print_st~0); 4663221#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 4663218#L803 assume !(5 == main_~count~0#1); 4663215#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4663213#L256-6 assume !(1 == ~main_in1_req_up~0); 4663210#L256-8 assume !(1 == ~main_in2_req_up~0); 4663206#L267-5 assume !(1 == ~main_sum_req_up~0); 4663202#L278-5 assume !(1 == ~main_diff_req_up~0); 4663203#L289-5 assume !(1 == ~main_pres_req_up~0); 4663260#L300-5 assume !(1 == ~main_dbl_req_up~0); 4723967#L311-5 assume !(1 == ~main_zero_req_up~0); 4723961#L322-5 assume 1 == ~main_clk_req_up~0; 4723955#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 4723950#L334-5 ~main_clk_req_up~0 := 0; 4723945#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4723940#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4723935#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4723931#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4723930#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4723929#L371-5 assume !(0 == ~main_in1_ev~0); 4723927#L376-5 assume !(0 == ~main_in2_ev~0); 4723926#L381-5 assume !(0 == ~main_sum_ev~0); 4723925#L386-5 assume !(0 == ~main_diff_ev~0); 4723924#L391-5 assume !(0 == ~main_pres_ev~0); 4723919#L396-5 assume !(0 == ~main_dbl_ev~0); 4723912#L401-5 assume !(0 == ~main_zero_ev~0); 4723909#L406-5 assume !(0 == ~main_clk_ev~0); 4723904#L411-5 assume !(0 == ~main_clk_pos_edge~0); 4723901#L416-5 assume !(0 == ~main_clk_neg_edge~0); 4723898#L421-5 assume !(1 == ~main_clk_pos_edge~0); 4723895#L426-5 assume !(1 == ~main_clk_pos_edge~0); 4723892#L431-5 assume !(1 == ~main_clk_pos_edge~0); 4723889#L436-5 assume !(1 == ~main_clk_pos_edge~0); 4723886#L441-5 assume !(1 == ~main_clk_pos_edge~0); 4723883#L446-5 assume !(1 == ~main_in1_ev~0); 4723880#L451-5 assume !(1 == ~main_in2_ev~0); 4723877#L456-5 assume !(1 == ~main_sum_ev~0); 4723247#L461-5 assume !(1 == ~main_diff_ev~0); 4723098#L466-5 assume !(1 == ~main_pres_ev~0); 4716250#L471-5 assume !(1 == ~main_dbl_ev~0); 4723868#L476-5 assume !(1 == ~main_zero_ev~0); 4723865#L481-5 assume !(1 == ~main_clk_ev~0); 4723862#L486-5 assume !(1 == ~main_clk_pos_edge~0); 4723859#L491-5 assume !(1 == ~main_clk_neg_edge~0); 4723856#L742-5 assume !false; 4723852#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4723847#L229-2 assume !false; 4723843#L147-2 assume !(0 == ~N_generate_st~0); 4723838#L151-4 assume !(0 == ~S1_addsub_st~0); 4723060#L154-4 assume !(0 == ~S2_presdbl_st~0); 4715104#L157-4 assume !(0 == ~S3_zero_st~0); 4715102#L160-4 assume !(0 == ~D_print_st~0); 4715100#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4715098#L509-6 assume !(1 == ~main_in1_req_up~0); 4715090#L509-8 assume !(1 == ~main_in2_req_up~0); 4715088#L520-5 assume !(1 == ~main_sum_req_up~0); 4715085#L531-5 assume !(1 == ~main_diff_req_up~0); 4715086#L542-5 assume !(1 == ~main_pres_req_up~0); 4718190#L553-5 assume !(1 == ~main_dbl_req_up~0); 4647625#L564-5 assume !(1 == ~main_zero_req_up~0); 4647626#L575-5 assume !(1 == ~main_clk_req_up~0); 4647701#L586-5 start_simulation_~kernel_st~0#1 := 3; 4647702#L605-6 assume !(0 == ~main_in1_ev~0); 4647695#L605-8 assume !(0 == ~main_in2_ev~0); 4647696#L610-5 assume !(0 == ~main_sum_ev~0); 4647689#L615-5 assume !(0 == ~main_diff_ev~0); 4647690#L620-5 assume !(0 == ~main_pres_ev~0); 4647683#L625-5 assume !(0 == ~main_dbl_ev~0); 4647684#L630-5 assume !(0 == ~main_zero_ev~0); 4647677#L635-5 assume !(0 == ~main_clk_ev~0); 4647678#L640-5 assume !(0 == ~main_clk_pos_edge~0); 4647672#L645-5 assume !(0 == ~main_clk_neg_edge~0); 4647673#L650-5 assume !(1 == ~main_clk_pos_edge~0); 4647666#L655-5 assume !(1 == ~main_clk_pos_edge~0); 4647667#L660-5 assume !(1 == ~main_clk_pos_edge~0); 4647658#L665-5 assume !(1 == ~main_clk_pos_edge~0); 4647659#L670-5 assume !(1 == ~main_clk_pos_edge~0); 4647650#L675-5 assume !(1 == ~main_in1_ev~0); 4647651#L680-5 assume !(1 == ~main_in2_ev~0); 4647644#L685-5 assume !(1 == ~main_sum_ev~0); 4647645#L690-5 assume !(1 == ~main_diff_ev~0); 4647634#L695-5 assume !(1 == ~main_pres_ev~0); 4646802#L700-5 assume !(1 == ~main_dbl_ev~0); 4647594#L705-5 assume !(1 == ~main_zero_ev~0); 4647560#L710-5 assume !(1 == ~main_clk_ev~0); 4647558#L715-5 assume !(1 == ~main_clk_pos_edge~0); 4647555#L720-5 assume !(1 == ~main_clk_neg_edge~0); 4647553#L725-5 assume !(0 == ~N_generate_st~0); 4647551#L733-4 assume !(0 == ~S1_addsub_st~0); 4647548#L736-4 assume !(0 == ~S2_presdbl_st~0); 4647546#L739-4 assume !(0 == ~S3_zero_st~0); 4647543#L742-4 assume !(0 == ~D_print_st~0); 4647544#L752-2 assume { :end_inline_start_simulation } true; 4672721#L795-2 [2021-12-07 01:24:13,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:13,401 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 7 times [2021-12-07 01:24:13,402 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:13,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957994051] [2021-12-07 01:24:13,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:13,402 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:13,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:13,407 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:24:13,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:13,419 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:24:13,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:13,420 INFO L85 PathProgramCache]: Analyzing trace with hash -881354094, now seen corresponding path program 1 times [2021-12-07 01:24:13,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:13,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250650451] [2021-12-07 01:24:13,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:13,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:13,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:24:13,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:24:13,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:24:13,452 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250650451] [2021-12-07 01:24:13,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250650451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:24:13,452 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:24:13,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:24:13,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591929523] [2021-12-07 01:24:13,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:24:13,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:24:13,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:24:13,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 01:24:13,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 01:24:13,453 INFO L87 Difference]: Start difference. First operand 370639 states and 495201 transitions. cyclomatic complexity: 124586 Second operand has 5 states, 5 states have (on average 36.4) internal successors, (182), 5 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:14,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:24:14,427 INFO L93 Difference]: Finished difference Result 383287 states and 511929 transitions. [2021-12-07 01:24:14,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 01:24:14,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 383287 states and 511929 transitions. [2021-12-07 01:24:15,774 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 352064 [2021-12-07 01:24:16,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 383287 states to 383287 states and 511929 transitions. [2021-12-07 01:24:16,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 383287 [2021-12-07 01:24:16,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 383287 [2021-12-07 01:24:16,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 383287 states and 511929 transitions. [2021-12-07 01:24:16,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:16,842 INFO L681 BuchiCegarLoop]: Abstraction has 383287 states and 511929 transitions. [2021-12-07 01:24:16,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383287 states and 511929 transitions. [2021-12-07 01:24:19,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383287 to 340767. [2021-12-07 01:24:19,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340767 states, 340767 states have (on average 1.3432433304868137) internal successors, (457733), 340766 states have internal predecessors, (457733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:19,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340767 states to 340767 states and 457733 transitions. [2021-12-07 01:24:19,824 INFO L704 BuchiCegarLoop]: Abstraction has 340767 states and 457733 transitions. [2021-12-07 01:24:19,825 INFO L587 BuchiCegarLoop]: Abstraction has 340767 states and 457733 transitions. [2021-12-07 01:24:19,825 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-12-07 01:24:19,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340767 states and 457733 transitions. [2021-12-07 01:24:20,756 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 318160 [2021-12-07 01:24:20,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:24:20,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:24:20,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:20,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:20,763 INFO L791 eck$LassoCheckResult]: Stem: 5381944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 5381889#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 5381342#L256 assume !(1 == ~main_in1_req_up~0); 5381304#L256-2 assume !(1 == ~main_in2_req_up~0); 5381306#L267-1 assume !(1 == ~main_sum_req_up~0); 5381715#L278-1 assume !(1 == ~main_diff_req_up~0); 5381438#L289-1 assume !(1 == ~main_pres_req_up~0); 5381321#L300-1 assume !(1 == ~main_dbl_req_up~0); 5381388#L311-1 assume !(1 == ~main_zero_req_up~0); 5381845#L322-1 assume !(1 == ~main_clk_req_up~0); 5381846#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 5381525#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 5381526#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 5384991#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 5384992#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 5384987#L371-1 assume !(0 == ~main_in1_ev~0); 5384988#L376-1 assume !(0 == ~main_in2_ev~0); 5385004#L381-1 assume !(0 == ~main_sum_ev~0); 5381535#L386-1 assume !(0 == ~main_diff_ev~0); 5381536#L391-1 assume !(0 == ~main_pres_ev~0); 5381697#L396-1 assume !(0 == ~main_dbl_ev~0); 5381698#L401-1 assume !(0 == ~main_zero_ev~0); 5394800#L406-1 assume !(0 == ~main_clk_ev~0); 5394796#L411-1 assume !(0 == ~main_clk_pos_edge~0); 5394792#L416-1 assume !(0 == ~main_clk_neg_edge~0); 5394784#L421-1 assume !(1 == ~main_clk_pos_edge~0); 5394776#L426-1 assume !(1 == ~main_clk_pos_edge~0); 5394768#L431-1 assume !(1 == ~main_clk_pos_edge~0); 5394760#L436-1 assume !(1 == ~main_clk_pos_edge~0); 5394752#L441-1 assume !(1 == ~main_clk_pos_edge~0); 5394744#L446-1 assume !(1 == ~main_in1_ev~0); 5394736#L451-1 assume !(1 == ~main_in2_ev~0); 5394728#L456-1 assume !(1 == ~main_sum_ev~0); 5394718#L461-1 assume !(1 == ~main_diff_ev~0); 5394705#L466-1 assume !(1 == ~main_pres_ev~0); 5394706#L471-1 assume !(1 == ~main_dbl_ev~0); 5394700#L476-1 assume !(1 == ~main_zero_ev~0); 5394696#L481-1 assume !(1 == ~main_clk_ev~0); 5394692#L486-1 assume !(1 == ~main_clk_pos_edge~0); 5394688#L491-1 assume !(1 == ~main_clk_neg_edge~0); 5394684#L742-1 assume !false; 5394680#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5394676#L229 assume !false; 5394672#L147 assume !(0 == ~N_generate_st~0); 5394668#L151 assume !(0 == ~S1_addsub_st~0); 5394664#L154 assume !(0 == ~S2_presdbl_st~0); 5394660#L157 assume !(0 == ~S3_zero_st~0); 5394656#L160 assume !(0 == ~D_print_st~0); 5394652#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 5394648#L509 assume !(1 == ~main_in1_req_up~0); 5394643#L509-2 assume !(1 == ~main_in2_req_up~0); 5394644#L520-1 assume !(1 == ~main_sum_req_up~0); 5395937#L531-1 assume !(1 == ~main_diff_req_up~0); 5395938#L542-1 assume !(1 == ~main_pres_req_up~0); 5396895#L553-1 assume !(1 == ~main_dbl_req_up~0); 5396879#L564-1 assume !(1 == ~main_zero_req_up~0); 5396868#L575-1 assume !(1 == ~main_clk_req_up~0); 5396864#L586-1 start_simulation_~kernel_st~0#1 := 3; 5396860#L605 assume !(0 == ~main_in1_ev~0); 5396856#L605-2 assume !(0 == ~main_in2_ev~0); 5396852#L610-1 assume !(0 == ~main_sum_ev~0); 5396848#L615-1 assume !(0 == ~main_diff_ev~0); 5396844#L620-1 assume !(0 == ~main_pres_ev~0); 5396840#L625-1 assume !(0 == ~main_dbl_ev~0); 5396836#L630-1 assume !(0 == ~main_zero_ev~0); 5396832#L635-1 assume !(0 == ~main_clk_ev~0); 5396828#L640-1 assume !(0 == ~main_clk_pos_edge~0); 5396824#L645-1 assume !(0 == ~main_clk_neg_edge~0); 5396820#L650-1 assume !(1 == ~main_clk_pos_edge~0); 5396816#L655-1 assume !(1 == ~main_clk_pos_edge~0); 5396812#L660-1 assume !(1 == ~main_clk_pos_edge~0); 5396808#L665-1 assume !(1 == ~main_clk_pos_edge~0); 5396804#L670-1 assume !(1 == ~main_clk_pos_edge~0); 5396800#L675-1 assume !(1 == ~main_in1_ev~0); 5396796#L680-1 assume !(1 == ~main_in2_ev~0); 5396792#L685-1 assume !(1 == ~main_sum_ev~0); 5396786#L690-1 assume !(1 == ~main_diff_ev~0); 5396498#L695-1 assume !(1 == ~main_pres_ev~0); 5396783#L700-1 assume !(1 == ~main_dbl_ev~0); 5396782#L705-1 assume !(1 == ~main_zero_ev~0); 5396781#L710-1 assume !(1 == ~main_clk_ev~0); 5396780#L715-1 assume !(1 == ~main_clk_pos_edge~0); 5396779#L720-1 assume !(1 == ~main_clk_neg_edge~0); 5396778#L725-1 assume !(0 == ~N_generate_st~0); 5396777#L733 assume !(0 == ~S1_addsub_st~0); 5396776#L736 assume !(0 == ~S2_presdbl_st~0); 5396775#L739 assume !(0 == ~S3_zero_st~0); 5396774#L742 assume !(0 == ~D_print_st~0); 5396771#L752 assume { :end_inline_start_simulation } true; 5396772#L795-2 assume !false; 5569766#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 5569765#L256-3 assume !(1 == ~main_in1_req_up~0); 5569762#L256-5 assume !(1 == ~main_in2_req_up~0); 5569758#L267-3 assume !(1 == ~main_sum_req_up~0); 5569754#L278-3 assume !(1 == ~main_diff_req_up~0); 5569750#L289-3 assume !(1 == ~main_pres_req_up~0); 5569746#L300-3 assume !(1 == ~main_dbl_req_up~0); 5569742#L311-3 assume !(1 == ~main_zero_req_up~0); 5569740#L322-3 assume 1 == ~main_clk_req_up~0; 5448557#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 5448553#L337-3 [2021-12-07 01:24:20,763 INFO L793 eck$LassoCheckResult]: Loop: 5448553#L337-3 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 5448551#L334-3 ~main_clk_req_up~0 := 0; 5448549#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 5448547#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 5448545#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 5448543#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 5448541#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 5448539#L371-3 assume !(0 == ~main_in1_ev~0); 5448537#L376-3 assume !(0 == ~main_in2_ev~0); 5448535#L381-3 assume !(0 == ~main_sum_ev~0); 5448533#L386-3 assume !(0 == ~main_diff_ev~0); 5448531#L391-3 assume !(0 == ~main_pres_ev~0); 5448529#L396-3 assume !(0 == ~main_dbl_ev~0); 5448527#L401-3 assume !(0 == ~main_zero_ev~0); 5448523#L406-3 assume !(0 == ~main_clk_ev~0); 5448519#L411-3 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 5448517#L416-3 assume !(0 == ~main_clk_neg_edge~0); 5448513#L421-3 assume !(1 == ~main_clk_pos_edge~0); 5448514#L426-3 assume !(1 == ~main_clk_pos_edge~0); 5569724#L431-3 assume !(1 == ~main_clk_pos_edge~0); 5569723#L436-3 assume !(1 == ~main_clk_pos_edge~0); 5569722#L441-3 assume !(1 == ~main_clk_pos_edge~0); 5569718#L446-3 assume !(1 == ~main_in1_ev~0); 5550983#L451-3 assume !(1 == ~main_in2_ev~0); 5550984#L456-3 assume !(1 == ~main_sum_ev~0); 5569376#L461-3 assume !(1 == ~main_diff_ev~0); 5550541#L466-3 assume !(1 == ~main_pres_ev~0); 5569189#L471-3 assume !(1 == ~main_dbl_ev~0); 5569375#L476-3 assume !(1 == ~main_zero_ev~0); 5569374#L481-3 assume !(1 == ~main_clk_ev~0); 5550972#L486-3 assume !(1 == ~main_clk_pos_edge~0); 5569373#L491-3 assume !(1 == ~main_clk_neg_edge~0); 5550927#L742-3 assume !false; 5569372#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5550919#L229-1 assume !false; 5569371#L147-1 assume !(0 == ~N_generate_st~0); 5452063#L151-2 assume !(0 == ~S1_addsub_st~0); 5551040#L154-2 assume !(0 == ~S2_presdbl_st~0); 5551045#L157-2 assume !(0 == ~S3_zero_st~0); 5551172#L160-2 assume !(0 == ~D_print_st~0); 5551162#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 5569367#L509-3 assume !(1 == ~main_in1_req_up~0); 5535166#L509-5 assume !(1 == ~main_in2_req_up~0); 5535163#L520-3 assume !(1 == ~main_sum_req_up~0); 5535164#L531-3 assume !(1 == ~main_diff_req_up~0); 5536689#L542-3 assume !(1 == ~main_pres_req_up~0); 5537120#L553-3 assume !(1 == ~main_dbl_req_up~0); 5537277#L564-3 assume !(1 == ~main_zero_req_up~0); 5537276#L575-3 assume !(1 == ~main_clk_req_up~0); 5537274#L586-3 start_simulation_~kernel_st~0#1 := 3; 5537272#L605-3 assume !(0 == ~main_in1_ev~0); 5537270#L605-5 assume !(0 == ~main_in2_ev~0); 5537268#L610-3 assume !(0 == ~main_sum_ev~0); 5537266#L615-3 assume !(0 == ~main_diff_ev~0); 5537264#L620-3 assume !(0 == ~main_pres_ev~0); 5537262#L625-3 assume !(0 == ~main_dbl_ev~0); 5537260#L630-3 assume !(0 == ~main_zero_ev~0); 5537258#L635-3 assume !(0 == ~main_clk_ev~0); 5537256#L640-3 assume !(0 == ~main_clk_pos_edge~0); 5537254#L645-3 assume !(0 == ~main_clk_neg_edge~0); 5537252#L650-3 assume !(1 == ~main_clk_pos_edge~0); 5537250#L655-3 assume !(1 == ~main_clk_pos_edge~0); 5537248#L660-3 assume !(1 == ~main_clk_pos_edge~0); 5537245#L665-3 assume !(1 == ~main_clk_pos_edge~0); 5537242#L670-3 assume !(1 == ~main_clk_pos_edge~0); 5537239#L675-3 assume !(1 == ~main_in1_ev~0); 5537236#L680-3 assume !(1 == ~main_in2_ev~0); 5537232#L685-3 assume !(1 == ~main_sum_ev~0); 5537229#L690-3 assume !(1 == ~main_diff_ev~0); 5536505#L695-3 assume !(1 == ~main_pres_ev~0); 5537084#L700-3 assume !(1 == ~main_dbl_ev~0); 5537217#L705-3 assume !(1 == ~main_zero_ev~0); 5537212#L710-3 assume !(1 == ~main_clk_ev~0); 5537206#L715-3 assume !(1 == ~main_clk_pos_edge~0); 5537202#L720-3 assume !(1 == ~main_clk_neg_edge~0); 5537199#L725-3 assume !(0 == ~N_generate_st~0); 5537195#L733-2 assume !(0 == ~S1_addsub_st~0); 5537187#L736-2 assume !(0 == ~S2_presdbl_st~0); 5537180#L739-2 assume !(0 == ~S3_zero_st~0); 5537175#L742-2 assume !(0 == ~D_print_st~0); 5537171#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 5537151#L803 assume !(5 == main_~count~0#1); 5537148#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 5537133#L256-6 assume !(1 == ~main_in1_req_up~0); 5537124#L256-8 assume !(1 == ~main_in2_req_up~0); 5537125#L267-5 assume !(1 == ~main_sum_req_up~0); 5551693#L278-5 assume !(1 == ~main_diff_req_up~0); 5551718#L289-5 assume !(1 == ~main_pres_req_up~0); 5551719#L300-5 assume !(1 == ~main_dbl_req_up~0); 5594993#L311-5 assume !(1 == ~main_zero_req_up~0); 5674219#L322-5 assume 1 == ~main_clk_req_up~0; 5712677#L334-4 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 5712675#L337-6 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 5712676#L334-5 ~main_clk_req_up~0 := 0; 5712826#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 5712823#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 5712820#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 5712817#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 5712814#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 5712811#L371-5 assume !(0 == ~main_in1_ev~0); 5712808#L376-5 assume !(0 == ~main_in2_ev~0); 5712805#L381-5 assume !(0 == ~main_sum_ev~0); 5712802#L386-5 assume !(0 == ~main_diff_ev~0); 5712799#L391-5 assume !(0 == ~main_pres_ev~0); 5712796#L396-5 assume !(0 == ~main_dbl_ev~0); 5712793#L401-5 assume !(0 == ~main_zero_ev~0); 5712790#L406-5 assume !(0 == ~main_clk_ev~0); 5712785#L411-5 assume !(0 == ~main_clk_pos_edge~0); 5712786#L416-5 assume !(0 == ~main_clk_neg_edge~0); 5712579#L421-5 assume !(1 == ~main_clk_pos_edge~0); 5712768#L426-5 assume !(1 == ~main_clk_pos_edge~0); 5712872#L431-5 assume !(1 == ~main_clk_pos_edge~0); 5712871#L436-5 assume !(1 == ~main_clk_pos_edge~0); 5712870#L441-5 assume !(1 == ~main_clk_pos_edge~0); 5712856#L446-5 assume !(1 == ~main_in1_ev~0); 5712850#L451-5 assume !(1 == ~main_in2_ev~0); 5712844#L456-5 assume !(1 == ~main_sum_ev~0); 5676373#L461-5 assume !(1 == ~main_diff_ev~0); 5712836#L466-5 assume !(1 == ~main_pres_ev~0); 5712833#L471-5 assume !(1 == ~main_dbl_ev~0); 5712831#L476-5 assume !(1 == ~main_zero_ev~0); 5712829#L481-5 assume !(1 == ~main_clk_ev~0); 5712680#L486-5 assume !(1 == ~main_clk_pos_edge~0); 5712548#L491-5 assume !(1 == ~main_clk_neg_edge~0); 5712546#L742-5 assume !false; 5712542#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5708523#L229-2 assume !false; 5397808#L147-2 assume !(0 == ~N_generate_st~0); 5397148#L151-4 assume !(0 == ~S1_addsub_st~0); 5396704#L154-4 assume !(0 == ~S2_presdbl_st~0); 5396078#L157-4 assume !(0 == ~S3_zero_st~0); 5395211#L160-4 assume !(0 == ~D_print_st~0); 5395209#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 5395207#L509-6 assume !(1 == ~main_in1_req_up~0); 5395204#L509-8 assume !(1 == ~main_in2_req_up~0); 5395205#L520-5 assume !(1 == ~main_sum_req_up~0); 5396068#L531-5 assume !(1 == ~main_diff_req_up~0); 5396069#L542-5 assume !(1 == ~main_pres_req_up~0); 5397031#L553-5 assume !(1 == ~main_dbl_req_up~0); 5397013#L564-5 assume !(1 == ~main_zero_req_up~0); 5397002#L575-5 assume !(1 == ~main_clk_req_up~0); 5396998#L586-5 start_simulation_~kernel_st~0#1 := 3; 5396994#L605-6 assume !(0 == ~main_in1_ev~0); 5396990#L605-8 assume !(0 == ~main_in2_ev~0); 5396986#L610-5 assume !(0 == ~main_sum_ev~0); 5396982#L615-5 assume !(0 == ~main_diff_ev~0); 5396978#L620-5 assume !(0 == ~main_pres_ev~0); 5396974#L625-5 assume !(0 == ~main_dbl_ev~0); 5396970#L630-5 assume !(0 == ~main_zero_ev~0); 5396966#L635-5 assume !(0 == ~main_clk_ev~0); 5396962#L640-5 assume !(0 == ~main_clk_pos_edge~0); 5396958#L645-5 assume !(0 == ~main_clk_neg_edge~0); 5396954#L650-5 assume !(1 == ~main_clk_pos_edge~0); 5396950#L655-5 assume !(1 == ~main_clk_pos_edge~0); 5396946#L660-5 assume !(1 == ~main_clk_pos_edge~0); 5396942#L665-5 assume !(1 == ~main_clk_pos_edge~0); 5396938#L670-5 assume !(1 == ~main_clk_pos_edge~0); 5396934#L675-5 assume !(1 == ~main_in1_ev~0); 5396930#L680-5 assume !(1 == ~main_in2_ev~0); 5396926#L685-5 assume !(1 == ~main_sum_ev~0); 5396920#L690-5 assume !(1 == ~main_diff_ev~0); 5396564#L695-5 assume !(1 == ~main_pres_ev~0); 5396917#L700-5 assume !(1 == ~main_dbl_ev~0); 5396916#L705-5 assume !(1 == ~main_zero_ev~0); 5396915#L710-5 assume !(1 == ~main_clk_ev~0); 5396914#L715-5 assume !(1 == ~main_clk_pos_edge~0); 5396913#L720-5 assume !(1 == ~main_clk_neg_edge~0); 5396912#L725-5 assume !(0 == ~N_generate_st~0); 5396911#L733-4 assume !(0 == ~S1_addsub_st~0); 5396910#L736-4 assume !(0 == ~S2_presdbl_st~0); 5396909#L739-4 assume !(0 == ~S3_zero_st~0); 5396908#L742-4 assume !(0 == ~D_print_st~0); 5396773#L752-2 assume { :end_inline_start_simulation } true; 5396735#L795-2 assume !false; 5396731#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 5396727#L256-3 assume !(1 == ~main_in1_req_up~0); 5396720#L256-5 assume !(1 == ~main_in2_req_up~0); 5396721#L267-3 assume !(1 == ~main_sum_req_up~0); 5406428#L278-3 assume !(1 == ~main_diff_req_up~0); 5448920#L289-3 assume !(1 == ~main_pres_req_up~0); 5448878#L300-3 assume !(1 == ~main_dbl_req_up~0); 5448872#L311-3 assume !(1 == ~main_zero_req_up~0); 5448853#L322-3 assume 1 == ~main_clk_req_up~0; 5448854#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 5448553#L337-3 [2021-12-07 01:24:20,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:20,763 INFO L85 PathProgramCache]: Analyzing trace with hash 698617653, now seen corresponding path program 1 times [2021-12-07 01:24:20,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:20,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960965686] [2021-12-07 01:24:20,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:20,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:20,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:20,772 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:24:20,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:20,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:24:20,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:20,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1773476009, now seen corresponding path program 1 times [2021-12-07 01:24:20,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:20,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735574448] [2021-12-07 01:24:20,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:20,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:20,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:24:20,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:24:20,809 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:24:20,809 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735574448] [2021-12-07 01:24:20,809 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735574448] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:24:20,809 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:24:20,809 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:24:20,809 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4117390] [2021-12-07 01:24:20,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:24:20,810 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:24:20,810 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:24:20,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:24:20,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:24:20,810 INFO L87 Difference]: Start difference. First operand 340767 states and 457733 transitions. cyclomatic complexity: 116982 Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:21,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:24:21,661 INFO L93 Difference]: Finished difference Result 283807 states and 377797 transitions. [2021-12-07 01:24:21,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:24:21,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283807 states and 377797 transitions. [2021-12-07 01:24:22,782 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 261200 [2021-12-07 01:24:23,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283807 states to 283807 states and 377797 transitions. [2021-12-07 01:24:23,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283807 [2021-12-07 01:24:23,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283807 [2021-12-07 01:24:23,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283807 states and 377797 transitions. [2021-12-07 01:24:23,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:23,772 INFO L681 BuchiCegarLoop]: Abstraction has 283807 states and 377797 transitions. [2021-12-07 01:24:23,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283807 states and 377797 transitions. [2021-12-07 01:24:25,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283807 to 283807. [2021-12-07 01:24:25,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 283807 states, 283807 states have (on average 1.3311757638113224) internal successors, (377797), 283806 states have internal predecessors, (377797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:26,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 283807 states to 283807 states and 377797 transitions. [2021-12-07 01:24:26,221 INFO L704 BuchiCegarLoop]: Abstraction has 283807 states and 377797 transitions. [2021-12-07 01:24:26,221 INFO L587 BuchiCegarLoop]: Abstraction has 283807 states and 377797 transitions. [2021-12-07 01:24:26,221 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-12-07 01:24:26,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 283807 states and 377797 transitions. [2021-12-07 01:24:27,079 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 261200 [2021-12-07 01:24:27,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:24:27,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:24:27,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:27,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:27,085 INFO L791 eck$LassoCheckResult]: Stem: 6006504#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 6006439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6005921#L256 assume !(1 == ~main_in1_req_up~0); 6005884#L256-2 assume !(1 == ~main_in2_req_up~0); 6005886#L267-1 assume !(1 == ~main_sum_req_up~0); 6006281#L278-1 assume !(1 == ~main_diff_req_up~0); 6005868#L289-1 assume !(1 == ~main_pres_req_up~0); 6005869#L300-1 assume !(1 == ~main_dbl_req_up~0); 6005970#L311-1 assume !(1 == ~main_zero_req_up~0); 6006133#L322-1 assume !(1 == ~main_clk_req_up~0); 6006212#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6006213#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6005902#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6005903#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6006090#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6006083#L371-1 assume !(0 == ~main_in1_ev~0); 6006084#L376-1 assume !(0 == ~main_in2_ev~0); 6009363#L381-1 assume !(0 == ~main_sum_ev~0); 6032415#L386-1 assume !(0 == ~main_diff_ev~0); 6032413#L391-1 assume !(0 == ~main_pres_ev~0); 6032411#L396-1 assume !(0 == ~main_dbl_ev~0); 6032410#L401-1 assume !(0 == ~main_zero_ev~0); 6031646#L406-1 assume !(0 == ~main_clk_ev~0); 6031645#L411-1 assume !(0 == ~main_clk_pos_edge~0); 6031643#L416-1 assume !(0 == ~main_clk_neg_edge~0); 6030503#L421-1 assume !(1 == ~main_clk_pos_edge~0); 6030501#L426-1 assume !(1 == ~main_clk_pos_edge~0); 6030499#L431-1 assume !(1 == ~main_clk_pos_edge~0); 6030497#L436-1 assume !(1 == ~main_clk_pos_edge~0); 6030495#L441-1 assume !(1 == ~main_clk_pos_edge~0); 6030493#L446-1 assume !(1 == ~main_in1_ev~0); 6030491#L451-1 assume !(1 == ~main_in2_ev~0); 6030490#L456-1 assume !(1 == ~main_sum_ev~0); 6030031#L461-1 assume !(1 == ~main_diff_ev~0); 6029987#L466-1 assume !(1 == ~main_pres_ev~0); 6030230#L471-1 assume !(1 == ~main_dbl_ev~0); 6030123#L476-1 assume !(1 == ~main_zero_ev~0); 6030120#L481-1 assume !(1 == ~main_clk_ev~0); 6030118#L486-1 assume !(1 == ~main_clk_pos_edge~0); 6030033#L491-1 assume !(1 == ~main_clk_neg_edge~0); 6029969#L742-1 assume !false; 6029920#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6029918#L229 assume !false; 6029875#L147 assume !(0 == ~N_generate_st~0); 6029873#L151 assume !(0 == ~S1_addsub_st~0); 6029809#L154 assume !(0 == ~S2_presdbl_st~0); 6029807#L157 assume !(0 == ~S3_zero_st~0); 6029740#L160 assume !(0 == ~D_print_st~0); 6029738#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6029636#L509 assume !(1 == ~main_in1_req_up~0); 6029633#L509-2 assume !(1 == ~main_in2_req_up~0); 6029629#L520-1 assume !(1 == ~main_sum_req_up~0); 6029626#L531-1 assume !(1 == ~main_diff_req_up~0); 6029627#L542-1 assume !(1 == ~main_pres_req_up~0); 6029534#L553-1 assume !(1 == ~main_dbl_req_up~0); 6029530#L564-1 assume !(1 == ~main_zero_req_up~0); 6029528#L575-1 assume !(1 == ~main_clk_req_up~0); 6029464#L586-1 start_simulation_~kernel_st~0#1 := 3; 6029460#L605 assume !(0 == ~main_in1_ev~0); 6029459#L605-2 assume !(0 == ~main_in2_ev~0); 6029403#L610-1 assume !(0 == ~main_sum_ev~0); 6029350#L615-1 assume !(0 == ~main_diff_ev~0); 6029348#L620-1 assume !(0 == ~main_pres_ev~0); 6029305#L625-1 assume !(0 == ~main_dbl_ev~0); 6029304#L630-1 assume !(0 == ~main_zero_ev~0); 6029255#L635-1 assume !(0 == ~main_clk_ev~0); 6029209#L640-1 assume !(0 == ~main_clk_pos_edge~0); 6029166#L645-1 assume !(0 == ~main_clk_neg_edge~0); 6029164#L650-1 assume !(1 == ~main_clk_pos_edge~0); 6029162#L655-1 assume !(1 == ~main_clk_pos_edge~0); 6029122#L660-1 assume !(1 == ~main_clk_pos_edge~0); 6029120#L665-1 assume !(1 == ~main_clk_pos_edge~0); 6029118#L670-1 assume !(1 == ~main_clk_pos_edge~0); 6029116#L675-1 assume !(1 == ~main_in1_ev~0); 6029114#L680-1 assume !(1 == ~main_in2_ev~0); 6029112#L685-1 assume !(1 == ~main_sum_ev~0); 6028964#L690-1 assume !(1 == ~main_diff_ev~0); 6029029#L695-1 assume !(1 == ~main_pres_ev~0); 6028998#L700-1 assume !(1 == ~main_dbl_ev~0); 6028971#L705-1 assume !(1 == ~main_zero_ev~0); 6028930#L710-1 assume !(1 == ~main_clk_ev~0); 6028914#L715-1 assume !(1 == ~main_clk_pos_edge~0); 6028904#L720-1 assume !(1 == ~main_clk_neg_edge~0); 6028899#L725-1 assume !(0 == ~N_generate_st~0); 6028894#L733 assume !(0 == ~S1_addsub_st~0); 6028890#L736 assume !(0 == ~S2_presdbl_st~0); 6028886#L739 assume !(0 == ~S3_zero_st~0); 6028882#L742 assume !(0 == ~D_print_st~0); 6028878#L752 assume { :end_inline_start_simulation } true; 6028874#L795-2 assume !false; 6028870#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6028866#L256-3 assume !(1 == ~main_in1_req_up~0); 6028860#L256-5 assume !(1 == ~main_in2_req_up~0); 6028853#L267-3 assume !(1 == ~main_sum_req_up~0); 6028854#L278-3 assume !(1 == ~main_diff_req_up~0); 6032838#L289-3 assume !(1 == ~main_pres_req_up~0); 6032835#L300-3 assume !(1 == ~main_dbl_req_up~0); 6032831#L311-3 assume !(1 == ~main_zero_req_up~0); 6032832#L322-3 assume 1 == ~main_clk_req_up~0; 6033841#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6033842#L337-3 [2021-12-07 01:24:27,085 INFO L793 eck$LassoCheckResult]: Loop: 6033842#L337-3 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 6154441#L334-3 ~main_clk_req_up~0 := 0; 6154534#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6154532#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6154530#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6154528#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6154526#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6154524#L371-3 assume !(0 == ~main_in1_ev~0); 6154522#L376-3 assume !(0 == ~main_in2_ev~0); 6154520#L381-3 assume !(0 == ~main_sum_ev~0); 6154518#L386-3 assume !(0 == ~main_diff_ev~0); 6154516#L391-3 assume !(0 == ~main_pres_ev~0); 6154514#L396-3 assume !(0 == ~main_dbl_ev~0); 6154512#L401-3 assume !(0 == ~main_zero_ev~0); 6154508#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 6154509#L411-3 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 6154578#L416-3 assume !(0 == ~main_clk_neg_edge~0); 6154632#L421-3 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 6154624#L426-3 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 6154616#L431-3 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 6154608#L436-3 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 6154600#L441-3 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 6154592#L446-3 assume !(1 == ~main_in1_ev~0); 6154584#L451-3 assume !(1 == ~main_in2_ev~0); 6154538#L456-3 assume !(1 == ~main_sum_ev~0); 6154480#L461-3 assume !(1 == ~main_diff_ev~0); 6048222#L466-3 assume !(1 == ~main_pres_ev~0); 6154472#L471-3 assume !(1 == ~main_dbl_ev~0); 6154468#L476-3 assume !(1 == ~main_zero_ev~0); 6154464#L481-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 6154460#L486-3 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 6154461#L491-3 assume !(1 == ~main_clk_neg_edge~0); 6154810#L742-3 assume !false; 6154802#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6154801#L229-1 assume !false; 6154798#L147-1 assume !(0 == ~N_generate_st~0); 6154799#L151-2 assume !(0 == ~S1_addsub_st~0); 6154856#L154-2 assume !(0 == ~S2_presdbl_st~0); 6154883#L157-2 assume !(0 == ~S3_zero_st~0); 6019539#L160-2 assume !(0 == ~D_print_st~0); 6019354#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6019355#L509-3 assume !(1 == ~main_in1_req_up~0); 6019346#L509-5 assume !(1 == ~main_in2_req_up~0); 6019347#L520-3 assume !(1 == ~main_sum_req_up~0); 6027952#L531-3 assume !(1 == ~main_diff_req_up~0); 6031275#L542-3 assume !(1 == ~main_pres_req_up~0); 6031269#L553-3 assume !(1 == ~main_dbl_req_up~0); 6031230#L564-3 assume !(1 == ~main_zero_req_up~0); 6031229#L575-3 assume !(1 == ~main_clk_req_up~0); 6031227#L586-3 start_simulation_~kernel_st~0#1 := 3; 6031223#L605-3 assume !(0 == ~main_in1_ev~0); 6031221#L605-5 assume !(0 == ~main_in2_ev~0); 6031219#L610-3 assume !(0 == ~main_sum_ev~0); 6031217#L615-3 assume !(0 == ~main_diff_ev~0); 6031215#L620-3 assume !(0 == ~main_pres_ev~0); 6031213#L625-3 assume !(0 == ~main_dbl_ev~0); 6031211#L630-3 assume !(0 == ~main_zero_ev~0); 6031209#L635-3 assume !(0 == ~main_clk_ev~0); 6031207#L640-3 assume !(0 == ~main_clk_pos_edge~0); 6031205#L645-3 assume !(0 == ~main_clk_neg_edge~0); 6031203#L650-3 assume !(1 == ~main_clk_pos_edge~0); 6031201#L655-3 assume !(1 == ~main_clk_pos_edge~0); 6031199#L660-3 assume !(1 == ~main_clk_pos_edge~0); 6031197#L665-3 assume !(1 == ~main_clk_pos_edge~0); 6031195#L670-3 assume !(1 == ~main_clk_pos_edge~0); 6031193#L675-3 assume !(1 == ~main_in1_ev~0); 6031191#L680-3 assume !(1 == ~main_in2_ev~0); 6031185#L685-3 assume !(1 == ~main_sum_ev~0); 6031183#L690-3 assume !(1 == ~main_diff_ev~0); 6031179#L695-3 assume !(1 == ~main_pres_ev~0); 6030395#L700-3 assume !(1 == ~main_dbl_ev~0); 6031176#L705-3 assume !(1 == ~main_zero_ev~0); 6031174#L710-3 assume !(1 == ~main_clk_ev~0); 6031172#L715-3 assume !(1 == ~main_clk_pos_edge~0); 6031170#L720-3 assume !(1 == ~main_clk_neg_edge~0); 6031168#L725-3 assume !(0 == ~N_generate_st~0); 6031167#L733-2 assume !(0 == ~S1_addsub_st~0); 6031165#L736-2 assume !(0 == ~S2_presdbl_st~0); 6031163#L739-2 assume !(0 == ~S3_zero_st~0); 6031161#L742-2 assume !(0 == ~D_print_st~0); 6031159#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 6031156#L803 assume !(5 == main_~count~0#1); 6031153#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6031151#L256-6 assume !(1 == ~main_in1_req_up~0); 6031148#L256-8 assume !(1 == ~main_in2_req_up~0); 6031144#L267-5 assume !(1 == ~main_sum_req_up~0); 6031145#L278-5 assume !(1 == ~main_diff_req_up~0); 6049904#L289-5 assume !(1 == ~main_pres_req_up~0); 6053458#L300-5 assume !(1 == ~main_dbl_req_up~0); 6059525#L311-5 assume !(1 == ~main_zero_req_up~0); 6059526#L322-5 assume 1 == ~main_clk_req_up~0; 6181587#L334-4 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6181584#L337-6 assume !(1 == ~main_clk_val~0);~main_clk_neg_edge~0 := 0;~main_clk_pos_edge~0 := 2; 6181585#L334-5 ~main_clk_req_up~0 := 0; 6185860#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6185858#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6185856#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6185854#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6185852#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6185850#L371-5 assume !(0 == ~main_in1_ev~0); 6185848#L376-5 assume !(0 == ~main_in2_ev~0); 6185846#L381-5 assume !(0 == ~main_sum_ev~0); 6185844#L386-5 assume !(0 == ~main_diff_ev~0); 6185842#L391-5 assume !(0 == ~main_pres_ev~0); 6185840#L396-5 assume !(0 == ~main_dbl_ev~0); 6185838#L401-5 assume !(0 == ~main_zero_ev~0); 6185836#L406-5 assume !(0 == ~main_clk_ev~0); 6185834#L411-5 assume !(0 == ~main_clk_pos_edge~0); 6185830#L416-5 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 6185822#L421-5 assume !(1 == ~main_clk_pos_edge~0); 6185814#L426-5 assume !(1 == ~main_clk_pos_edge~0); 6185806#L431-5 assume !(1 == ~main_clk_pos_edge~0); 6185798#L436-5 assume !(1 == ~main_clk_pos_edge~0); 6185790#L441-5 assume !(1 == ~main_clk_pos_edge~0); 6185782#L446-5 assume !(1 == ~main_in1_ev~0); 6185774#L451-5 assume !(1 == ~main_in2_ev~0); 6185766#L456-5 assume !(1 == ~main_sum_ev~0); 6052293#L461-5 assume !(1 == ~main_diff_ev~0); 6185756#L466-5 assume !(1 == ~main_pres_ev~0); 6158115#L471-5 assume !(1 == ~main_dbl_ev~0); 6185752#L476-5 assume !(1 == ~main_zero_ev~0); 6185748#L481-5 assume !(1 == ~main_clk_ev~0); 6185745#L486-5 assume !(1 == ~main_clk_pos_edge~0); 6185743#L491-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 6185742#L742-5 assume !false; 6185738#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6185726#L229-2 assume !false; 6185727#L147-2 assume !(0 == ~N_generate_st~0); 6039167#L151-4 assume !(0 == ~S1_addsub_st~0); 6039168#L154-4 assume !(0 == ~S2_presdbl_st~0); 6186253#L157-4 assume !(0 == ~S3_zero_st~0); 6021970#L160-4 assume !(0 == ~D_print_st~0); 6021971#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6021859#L509-6 assume !(1 == ~main_in1_req_up~0); 6021860#L509-8 assume !(1 == ~main_in2_req_up~0); 6043700#L520-5 assume !(1 == ~main_sum_req_up~0); 6043701#L531-5 assume !(1 == ~main_diff_req_up~0); 6043769#L542-5 assume !(1 == ~main_pres_req_up~0); 6043770#L553-5 assume !(1 == ~main_dbl_req_up~0); 6044021#L564-5 assume !(1 == ~main_zero_req_up~0); 6044015#L575-5 assume !(1 == ~main_clk_req_up~0); 6044010#L586-5 start_simulation_~kernel_st~0#1 := 3; 6044005#L605-6 assume !(0 == ~main_in1_ev~0); 6044000#L605-8 assume !(0 == ~main_in2_ev~0); 6043999#L610-5 assume !(0 == ~main_sum_ev~0); 6043994#L615-5 assume !(0 == ~main_diff_ev~0); 6043989#L620-5 assume !(0 == ~main_pres_ev~0); 6043984#L625-5 assume !(0 == ~main_dbl_ev~0); 6043979#L630-5 assume !(0 == ~main_zero_ev~0); 6043974#L635-5 assume !(0 == ~main_clk_ev~0); 6043969#L640-5 assume !(0 == ~main_clk_pos_edge~0); 6043964#L645-5 assume !(0 == ~main_clk_neg_edge~0); 6043959#L650-5 assume !(1 == ~main_clk_pos_edge~0); 6043954#L655-5 assume !(1 == ~main_clk_pos_edge~0); 6043949#L660-5 assume !(1 == ~main_clk_pos_edge~0); 6043942#L665-5 assume !(1 == ~main_clk_pos_edge~0); 6043939#L670-5 assume !(1 == ~main_clk_pos_edge~0); 6043286#L675-5 assume !(1 == ~main_in1_ev~0); 6043283#L680-5 assume !(1 == ~main_in2_ev~0); 6043281#L685-5 assume !(1 == ~main_sum_ev~0); 6043277#L690-5 assume !(1 == ~main_diff_ev~0); 6043126#L695-5 assume !(1 == ~main_pres_ev~0); 6043122#L700-5 assume !(1 == ~main_dbl_ev~0); 6043120#L705-5 assume !(1 == ~main_zero_ev~0); 6043118#L710-5 assume !(1 == ~main_clk_ev~0); 6043052#L715-5 assume !(1 == ~main_clk_pos_edge~0); 6043045#L720-5 assume !(1 == ~main_clk_neg_edge~0); 6043039#L725-5 assume !(0 == ~N_generate_st~0); 6043033#L733-4 assume !(0 == ~S1_addsub_st~0); 6043027#L736-4 assume !(0 == ~S2_presdbl_st~0); 6043020#L739-4 assume !(0 == ~S3_zero_st~0); 6043012#L742-4 assume !(0 == ~D_print_st~0); 6043005#L752-2 assume { :end_inline_start_simulation } true; 6042996#L795-2 assume !false; 6042995#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6042993#L256-3 assume !(1 == ~main_in1_req_up~0); 6042991#L256-5 assume !(1 == ~main_in2_req_up~0); 6042987#L267-3 assume !(1 == ~main_sum_req_up~0); 6042988#L278-3 assume !(1 == ~main_diff_req_up~0); 6048308#L289-3 assume !(1 == ~main_pres_req_up~0); 6056368#L300-3 assume !(1 == ~main_dbl_req_up~0); 6154453#L311-3 assume !(1 == ~main_zero_req_up~0); 6154449#L322-3 assume 1 == ~main_clk_req_up~0; 6154446#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6033842#L337-3 [2021-12-07 01:24:27,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:27,085 INFO L85 PathProgramCache]: Analyzing trace with hash 698617653, now seen corresponding path program 2 times [2021-12-07 01:24:27,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:27,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726855550] [2021-12-07 01:24:27,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:27,086 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:27,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:27,094 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:24:27,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:27,118 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:24:27,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:27,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1202891431, now seen corresponding path program 1 times [2021-12-07 01:24:27,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:27,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586980053] [2021-12-07 01:24:27,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:27,119 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:27,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:24:27,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:24:27,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:24:27,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586980053] [2021-12-07 01:24:27,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586980053] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:24:27,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:24:27,137 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:24:27,137 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892121739] [2021-12-07 01:24:27,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:24:27,137 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:24:27,137 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:24:27,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:24:27,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:24:27,138 INFO L87 Difference]: Start difference. First operand 283807 states and 377797 transitions. cyclomatic complexity: 94006 Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:27,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:24:27,803 INFO L93 Difference]: Finished difference Result 258335 states and 334021 transitions. [2021-12-07 01:24:27,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:24:27,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 258335 states and 334021 transitions. [2021-12-07 01:24:28,841 INFO L131 ngComponentsAnalysis]: Automaton has 2064 accepting balls. 219472 [2021-12-07 01:24:29,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 258335 states to 258335 states and 334021 transitions. [2021-12-07 01:24:29,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 258335 [2021-12-07 01:24:29,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 258335 [2021-12-07 01:24:29,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 258335 states and 334021 transitions. [2021-12-07 01:24:29,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:29,576 INFO L681 BuchiCegarLoop]: Abstraction has 258335 states and 334021 transitions. [2021-12-07 01:24:29,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258335 states and 334021 transitions. [2021-12-07 01:24:31,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258335 to 221599. [2021-12-07 01:24:31,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221599 states, 221599 states have (on average 1.2888370434884633) internal successors, (285605), 221598 states have internal predecessors, (285605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:31,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221599 states to 221599 states and 285605 transitions. [2021-12-07 01:24:31,629 INFO L704 BuchiCegarLoop]: Abstraction has 221599 states and 285605 transitions. [2021-12-07 01:24:31,629 INFO L587 BuchiCegarLoop]: Abstraction has 221599 states and 285605 transitions. [2021-12-07 01:24:31,629 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-12-07 01:24:31,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 221599 states and 285605 transitions. [2021-12-07 01:24:32,171 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 198992 [2021-12-07 01:24:32,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:24:32,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:24:32,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:32,174 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:24:32,174 INFO L791 eck$LassoCheckResult]: Stem: 6548624#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 6548568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6548070#L256 assume !(1 == ~main_in1_req_up~0); 6548032#L256-2 assume !(1 == ~main_in2_req_up~0); 6548034#L267-1 assume !(1 == ~main_sum_req_up~0); 6548417#L278-1 assume !(1 == ~main_diff_req_up~0); 6549866#L289-1 assume !(1 == ~main_pres_req_up~0); 6548049#L300-1 assume !(1 == ~main_dbl_req_up~0); 6548117#L311-1 assume !(1 == ~main_zero_req_up~0); 6550528#L322-1 assume !(1 == ~main_clk_req_up~0); 6551463#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6551462#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6551461#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6551460#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6551459#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6551458#L371-1 assume !(0 == ~main_in1_ev~0); 6551457#L376-1 assume !(0 == ~main_in2_ev~0); 6551455#L381-1 assume !(0 == ~main_sum_ev~0); 6551456#L386-1 assume !(0 == ~main_diff_ev~0); 6551451#L391-1 assume !(0 == ~main_pres_ev~0); 6551452#L396-1 assume !(0 == ~main_dbl_ev~0); 6577219#L401-1 assume !(0 == ~main_zero_ev~0); 6577217#L406-1 assume !(0 == ~main_clk_ev~0); 6577215#L411-1 assume !(0 == ~main_clk_pos_edge~0); 6577213#L416-1 assume !(0 == ~main_clk_neg_edge~0); 6577211#L421-1 assume !(1 == ~main_clk_pos_edge~0); 6577209#L426-1 assume !(1 == ~main_clk_pos_edge~0); 6577207#L431-1 assume !(1 == ~main_clk_pos_edge~0); 6577205#L436-1 assume !(1 == ~main_clk_pos_edge~0); 6577203#L441-1 assume !(1 == ~main_clk_pos_edge~0); 6577201#L446-1 assume !(1 == ~main_in1_ev~0); 6577199#L451-1 assume !(1 == ~main_in2_ev~0); 6577197#L456-1 assume !(1 == ~main_sum_ev~0); 6577186#L461-1 assume !(1 == ~main_diff_ev~0); 6577192#L466-1 assume !(1 == ~main_pres_ev~0); 6576774#L471-1 assume !(1 == ~main_dbl_ev~0); 6577187#L476-1 assume !(1 == ~main_zero_ev~0); 6577182#L481-1 assume !(1 == ~main_clk_ev~0); 6577178#L486-1 assume !(1 == ~main_clk_pos_edge~0); 6577176#L491-1 assume !(1 == ~main_clk_neg_edge~0); 6577169#L742-1 assume !false; 6577165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6577162#L229 assume !false; 6577159#L147 assume !(0 == ~N_generate_st~0); 6577156#L151 assume !(0 == ~S1_addsub_st~0); 6577153#L154 assume !(0 == ~S2_presdbl_st~0); 6577150#L157 assume !(0 == ~S3_zero_st~0); 6577147#L160 assume !(0 == ~D_print_st~0); 6577144#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6577141#L509 assume !(1 == ~main_in1_req_up~0); 6577132#L509-2 assume !(1 == ~main_in2_req_up~0); 6577127#L520-1 assume !(1 == ~main_sum_req_up~0); 6577128#L531-1 assume !(1 == ~main_diff_req_up~0); 6577789#L542-1 assume !(1 == ~main_pres_req_up~0); 6579969#L553-1 assume !(1 == ~main_dbl_req_up~0); 6579965#L564-1 assume !(1 == ~main_zero_req_up~0); 6579962#L575-1 assume !(1 == ~main_clk_req_up~0); 6579960#L586-1 start_simulation_~kernel_st~0#1 := 3; 6579958#L605 assume !(0 == ~main_in1_ev~0); 6579956#L605-2 assume !(0 == ~main_in2_ev~0); 6579954#L610-1 assume !(0 == ~main_sum_ev~0); 6579952#L615-1 assume !(0 == ~main_diff_ev~0); 6579950#L620-1 assume !(0 == ~main_pres_ev~0); 6579948#L625-1 assume !(0 == ~main_dbl_ev~0); 6579947#L630-1 assume !(0 == ~main_zero_ev~0); 6579945#L635-1 assume !(0 == ~main_clk_ev~0); 6579944#L640-1 assume !(0 == ~main_clk_pos_edge~0); 6579943#L645-1 assume !(0 == ~main_clk_neg_edge~0); 6579940#L650-1 assume !(1 == ~main_clk_pos_edge~0); 6579938#L655-1 assume !(1 == ~main_clk_pos_edge~0); 6579936#L660-1 assume !(1 == ~main_clk_pos_edge~0); 6579934#L665-1 assume !(1 == ~main_clk_pos_edge~0); 6579932#L670-1 assume !(1 == ~main_clk_pos_edge~0); 6579930#L675-1 assume !(1 == ~main_in1_ev~0); 6579928#L680-1 assume !(1 == ~main_in2_ev~0); 6579926#L685-1 assume !(1 == ~main_sum_ev~0); 6579922#L690-1 assume !(1 == ~main_diff_ev~0); 6579918#L695-1 assume !(1 == ~main_pres_ev~0); 6579070#L700-1 assume !(1 == ~main_dbl_ev~0); 6579915#L705-1 assume !(1 == ~main_zero_ev~0); 6579913#L710-1 assume !(1 == ~main_clk_ev~0); 6579911#L715-1 assume !(1 == ~main_clk_pos_edge~0); 6579909#L720-1 assume !(1 == ~main_clk_neg_edge~0); 6579907#L725-1 assume !(0 == ~N_generate_st~0); 6579905#L733 assume !(0 == ~S1_addsub_st~0); 6579903#L736 assume !(0 == ~S2_presdbl_st~0); 6579901#L739 assume !(0 == ~S3_zero_st~0); 6579899#L742 assume !(0 == ~D_print_st~0); 6579530#L752 assume { :end_inline_start_simulation } true; 6579531#L795-2 assume !false; 6641903#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6641902#L256-3 assume !(1 == ~main_in1_req_up~0); 6641901#L256-5 assume !(1 == ~main_in2_req_up~0); 6579516#L267-3 assume !(1 == ~main_sum_req_up~0); 6579517#L278-3 assume !(1 == ~main_diff_req_up~0); 6581490#L289-3 assume !(1 == ~main_pres_req_up~0); 6581492#L300-3 assume !(1 == ~main_dbl_req_up~0); 6581480#L311-3 assume !(1 == ~main_zero_req_up~0); 6642104#L322-3 assume 1 == ~main_clk_req_up~0; 6642103#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6581454#L337-3 [2021-12-07 01:24:32,174 INFO L793 eck$LassoCheckResult]: Loop: 6581454#L337-3 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 6581452#L334-3 ~main_clk_req_up~0 := 0; 6581450#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6581448#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6581446#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6581444#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6581440#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6581436#L371-3 assume !(0 == ~main_in1_ev~0); 6581432#L376-3 assume !(0 == ~main_in2_ev~0); 6581428#L381-3 assume !(0 == ~main_sum_ev~0); 6581422#L386-3 assume !(0 == ~main_diff_ev~0); 6581415#L391-3 assume !(0 == ~main_pres_ev~0); 6581407#L396-3 assume !(0 == ~main_dbl_ev~0); 6581400#L401-3 assume !(0 == ~main_zero_ev~0); 6581388#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 6581378#L411-3 assume !(0 == ~main_clk_pos_edge~0); 6580235#L416-3 assume !(0 == ~main_clk_neg_edge~0); 6580233#L421-3 assume !(1 == ~main_clk_pos_edge~0); 6580231#L426-3 assume !(1 == ~main_clk_pos_edge~0); 6580229#L431-3 assume !(1 == ~main_clk_pos_edge~0); 6580227#L436-3 assume !(1 == ~main_clk_pos_edge~0); 6580225#L441-3 assume !(1 == ~main_clk_pos_edge~0); 6580223#L446-3 assume !(1 == ~main_in1_ev~0); 6580221#L451-3 assume !(1 == ~main_in2_ev~0); 6580219#L456-3 assume !(1 == ~main_sum_ev~0); 6580196#L461-3 assume !(1 == ~main_diff_ev~0); 6579596#L466-3 assume !(1 == ~main_pres_ev~0); 6580212#L471-3 assume !(1 == ~main_dbl_ev~0); 6580210#L476-3 assume !(1 == ~main_zero_ev~0); 6579113#L481-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 6579110#L486-3 assume !(1 == ~main_clk_pos_edge~0); 6579107#L491-3 assume !(1 == ~main_clk_neg_edge~0); 6579103#L742-3 assume !false; 6579101#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6579099#L229-1 assume !false; 6579097#L147-1 assume !(0 == ~N_generate_st~0); 6579095#L151-2 assume !(0 == ~S1_addsub_st~0); 6579093#L154-2 assume !(0 == ~S2_presdbl_st~0); 6579091#L157-2 assume !(0 == ~S3_zero_st~0); 6579089#L160-2 assume !(0 == ~D_print_st~0); 6579087#L245-1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6579084#L509-3 assume !(1 == ~main_in1_req_up~0); 6574678#L509-5 assume !(1 == ~main_in2_req_up~0); 6574676#L520-3 assume !(1 == ~main_sum_req_up~0); 6574672#L531-3 assume !(1 == ~main_diff_req_up~0); 6574668#L542-3 assume !(1 == ~main_pres_req_up~0); 6574665#L553-3 assume !(1 == ~main_dbl_req_up~0); 6574648#L564-3 assume !(1 == ~main_zero_req_up~0); 6574644#L575-3 assume !(1 == ~main_clk_req_up~0); 6574640#L586-3 start_simulation_~kernel_st~0#1 := 3; 6574636#L605-3 assume !(0 == ~main_in1_ev~0); 6574632#L605-5 assume !(0 == ~main_in2_ev~0); 6574631#L610-3 assume !(0 == ~main_sum_ev~0); 6574629#L615-3 assume !(0 == ~main_diff_ev~0); 6574625#L620-3 assume !(0 == ~main_pres_ev~0); 6574623#L625-3 assume !(0 == ~main_dbl_ev~0); 6574621#L630-3 assume !(0 == ~main_zero_ev~0); 6574619#L635-3 assume !(0 == ~main_clk_ev~0); 6574617#L640-3 assume !(0 == ~main_clk_pos_edge~0); 6574615#L645-3 assume !(0 == ~main_clk_neg_edge~0); 6574613#L650-3 assume !(1 == ~main_clk_pos_edge~0); 6574611#L655-3 assume !(1 == ~main_clk_pos_edge~0); 6574609#L660-3 assume !(1 == ~main_clk_pos_edge~0); 6574607#L665-3 assume !(1 == ~main_clk_pos_edge~0); 6574605#L670-3 assume !(1 == ~main_clk_pos_edge~0); 6574603#L675-3 assume !(1 == ~main_in1_ev~0); 6574601#L680-3 assume !(1 == ~main_in2_ev~0); 6574599#L685-3 assume !(1 == ~main_sum_ev~0); 6574583#L690-3 assume !(1 == ~main_diff_ev~0); 6574594#L695-3 assume !(1 == ~main_pres_ev~0); 6574590#L700-3 assume !(1 == ~main_dbl_ev~0); 6574588#L705-3 assume !(1 == ~main_zero_ev~0); 6574586#L710-3 assume !(1 == ~main_clk_ev~0); 6574584#L715-3 assume !(1 == ~main_clk_pos_edge~0); 6574581#L720-3 assume !(1 == ~main_clk_neg_edge~0); 6574577#L725-3 assume !(0 == ~N_generate_st~0); 6574573#L733-2 assume !(0 == ~S1_addsub_st~0); 6574571#L736-2 assume !(0 == ~S2_presdbl_st~0); 6574569#L739-2 assume !(0 == ~S3_zero_st~0); 6574567#L742-2 assume !(0 == ~D_print_st~0); 6574565#L752-1 assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 6574562#L803 assume !(5 == main_~count~0#1); 6574559#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6574557#L256-6 assume !(1 == ~main_in1_req_up~0); 6574554#L256-8 assume !(1 == ~main_in2_req_up~0); 6574550#L267-5 assume !(1 == ~main_sum_req_up~0); 6574551#L278-5 assume !(1 == ~main_diff_req_up~0); 6575757#L289-5 assume !(1 == ~main_pres_req_up~0); 6575753#L300-5 assume !(1 == ~main_dbl_req_up~0); 6575749#L311-5 assume !(1 == ~main_zero_req_up~0); 6575746#L322-5 assume 1 == ~main_clk_req_up~0; 6575744#L334-4 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6575741#L337-6 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 6575742#L334-5 ~main_clk_req_up~0 := 0; 6575837#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 6575835#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 6575833#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 6575831#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 6575827#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 6575825#L371-5 assume !(0 == ~main_in1_ev~0); 6575824#L376-5 assume !(0 == ~main_in2_ev~0); 6575823#L381-5 assume !(0 == ~main_sum_ev~0); 6575822#L386-5 assume !(0 == ~main_diff_ev~0); 6575819#L391-5 assume !(0 == ~main_pres_ev~0); 6575817#L396-5 assume !(0 == ~main_dbl_ev~0); 6575815#L401-5 assume !(0 == ~main_zero_ev~0); 6575812#L406-5 assume !(0 == ~main_clk_ev~0); 6575813#L411-5 assume !(0 == ~main_clk_pos_edge~0); 6576271#L416-5 assume !(0 == ~main_clk_neg_edge~0); 6575821#L421-5 assume !(1 == ~main_clk_pos_edge~0); 6576269#L426-5 assume !(1 == ~main_clk_pos_edge~0); 6576268#L431-5 assume !(1 == ~main_clk_pos_edge~0); 6576265#L436-5 assume !(1 == ~main_clk_pos_edge~0); 6576264#L441-5 assume !(1 == ~main_clk_pos_edge~0); 6576262#L446-5 assume !(1 == ~main_in1_ev~0); 6576261#L451-5 assume !(1 == ~main_in2_ev~0); 6574265#L456-5 assume !(1 == ~main_sum_ev~0); 6574261#L461-5 assume !(1 == ~main_diff_ev~0); 6573677#L466-5 assume !(1 == ~main_pres_ev~0); 6573673#L471-5 assume !(1 == ~main_dbl_ev~0); 6573670#L476-5 assume !(1 == ~main_zero_ev~0); 6573389#L481-5 assume !(1 == ~main_clk_ev~0); 6573386#L486-5 assume !(1 == ~main_clk_pos_edge~0); 6573383#L491-5 assume !(1 == ~main_clk_neg_edge~0); 6573380#L742-5 assume !false; 6573378#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 6573376#L229-2 assume !false; 6573374#L147-2 assume !(0 == ~N_generate_st~0); 6573372#L151-4 assume !(0 == ~S1_addsub_st~0); 6573370#L154-4 assume !(0 == ~S2_presdbl_st~0); 6573368#L157-4 assume !(0 == ~S3_zero_st~0); 6573366#L160-4 assume !(0 == ~D_print_st~0); 6573364#L245-2 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 6573362#L509-6 assume !(1 == ~main_in1_req_up~0); 6573357#L509-8 assume !(1 == ~main_in2_req_up~0); 6573352#L520-5 assume !(1 == ~main_sum_req_up~0); 6573353#L531-5 assume !(1 == ~main_diff_req_up~0); 6577792#L542-5 assume !(1 == ~main_pres_req_up~0); 6580064#L553-5 assume !(1 == ~main_dbl_req_up~0); 6580077#L564-5 assume !(1 == ~main_zero_req_up~0); 6580677#L575-5 assume !(1 == ~main_clk_req_up~0); 6580676#L586-5 start_simulation_~kernel_st~0#1 := 3; 6580674#L605-6 assume !(0 == ~main_in1_ev~0); 6580673#L605-8 assume !(0 == ~main_in2_ev~0); 6580672#L610-5 assume !(0 == ~main_sum_ev~0); 6580670#L615-5 assume !(0 == ~main_diff_ev~0); 6580669#L620-5 assume !(0 == ~main_pres_ev~0); 6580667#L625-5 assume !(0 == ~main_dbl_ev~0); 6580666#L630-5 assume !(0 == ~main_zero_ev~0); 6580665#L635-5 assume !(0 == ~main_clk_ev~0); 6580664#L640-5 assume !(0 == ~main_clk_pos_edge~0); 6580662#L645-5 assume !(0 == ~main_clk_neg_edge~0); 6580659#L650-5 assume !(1 == ~main_clk_pos_edge~0); 6580657#L655-5 assume !(1 == ~main_clk_pos_edge~0); 6580656#L660-5 assume !(1 == ~main_clk_pos_edge~0); 6580654#L665-5 assume !(1 == ~main_clk_pos_edge~0); 6580653#L670-5 assume !(1 == ~main_clk_pos_edge~0); 6580652#L675-5 assume !(1 == ~main_in1_ev~0); 6580649#L680-5 assume !(1 == ~main_in2_ev~0); 6580647#L685-5 assume !(1 == ~main_sum_ev~0); 6580644#L690-5 assume !(1 == ~main_diff_ev~0); 6579444#L695-5 assume !(1 == ~main_pres_ev~0); 6579552#L700-5 assume !(1 == ~main_dbl_ev~0); 6579550#L705-5 assume !(1 == ~main_zero_ev~0); 6579548#L710-5 assume !(1 == ~main_clk_ev~0); 6579546#L715-5 assume !(1 == ~main_clk_pos_edge~0); 6579544#L720-5 assume !(1 == ~main_clk_neg_edge~0); 6579542#L725-5 assume !(0 == ~N_generate_st~0); 6579540#L733-4 assume !(0 == ~S1_addsub_st~0); 6579538#L736-4 assume !(0 == ~S2_presdbl_st~0); 6579536#L739-4 assume !(0 == ~S3_zero_st~0); 6579534#L742-4 assume !(0 == ~D_print_st~0); 6579532#L752-2 assume { :end_inline_start_simulation } true; 6579528#L795-2 assume !false; 6579526#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 6579524#L256-3 assume !(1 == ~main_in1_req_up~0); 6579520#L256-5 assume !(1 == ~main_in2_req_up~0); 6579521#L267-3 assume !(1 == ~main_sum_req_up~0); 6579512#L278-3 assume !(1 == ~main_diff_req_up~0); 6579513#L289-3 assume !(1 == ~main_pres_req_up~0); 6581481#L300-3 assume !(1 == ~main_dbl_req_up~0); 6581471#L311-3 assume !(1 == ~main_zero_req_up~0); 6581465#L322-3 assume 1 == ~main_clk_req_up~0; 6581455#L334-2 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 6581454#L337-3 [2021-12-07 01:24:32,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:32,174 INFO L85 PathProgramCache]: Analyzing trace with hash 698617653, now seen corresponding path program 3 times [2021-12-07 01:24:32,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:32,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229620119] [2021-12-07 01:24:32,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:32,175 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:32,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:32,181 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:24:32,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:24:32,197 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:24:32,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:24:32,198 INFO L85 PathProgramCache]: Analyzing trace with hash 841138923, now seen corresponding path program 1 times [2021-12-07 01:24:32,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:24:32,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285205439] [2021-12-07 01:24:32,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:24:32,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:24:32,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:24:32,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:24:32,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:24:32,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285205439] [2021-12-07 01:24:32,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285205439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:24:32,212 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:24:32,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:24:32,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111871712] [2021-12-07 01:24:32,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:24:32,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:24:32,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:24:32,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:24:32,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:24:32,212 INFO L87 Difference]: Start difference. First operand 221599 states and 285605 transitions. cyclomatic complexity: 64022 Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 2 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:33,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:24:33,088 INFO L93 Difference]: Finished difference Result 219919 states and 281685 transitions. [2021-12-07 01:24:33,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:24:33,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219919 states and 281685 transitions. [2021-12-07 01:24:33,868 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 189248 [2021-12-07 01:24:34,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219919 states to 219919 states and 281685 transitions. [2021-12-07 01:24:34,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219919 [2021-12-07 01:24:34,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219919 [2021-12-07 01:24:34,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219919 states and 281685 transitions. [2021-12-07 01:24:34,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:24:34,656 INFO L681 BuchiCegarLoop]: Abstraction has 219919 states and 281685 transitions. [2021-12-07 01:24:34,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219919 states and 281685 transitions. [2021-12-07 01:24:36,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219919 to 211855. [2021-12-07 01:24:36,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 211855 states, 211855 states have (on average 1.2813905737414741) internal successors, (271469), 211854 states have internal predecessors, (271469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:24:36,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211855 states to 211855 states and 271469 transitions. [2021-12-07 01:24:36,501 INFO L704 BuchiCegarLoop]: Abstraction has 211855 states and 271469 transitions. [2021-12-07 01:24:36,501 INFO L587 BuchiCegarLoop]: Abstraction has 211855 states and 271469 transitions. [2021-12-07 01:24:36,501 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-12-07 01:24:36,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211855 states and 271469 transitions.