./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-07 01:43:50,482 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-07 01:43:50,485 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-07 01:43:50,513 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-07 01:43:50,513 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-07 01:43:50,514 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-07 01:43:50,516 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-07 01:43:50,517 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-07 01:43:50,519 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-07 01:43:50,520 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-07 01:43:50,521 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-07 01:43:50,522 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-07 01:43:50,522 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-07 01:43:50,523 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-07 01:43:50,524 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-07 01:43:50,525 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-07 01:43:50,526 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-07 01:43:50,527 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-07 01:43:50,529 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-07 01:43:50,530 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-07 01:43:50,532 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-07 01:43:50,533 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-07 01:43:50,534 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-07 01:43:50,535 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-07 01:43:50,538 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-07 01:43:50,538 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-07 01:43:50,538 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-07 01:43:50,539 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-07 01:43:50,539 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-07 01:43:50,540 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-07 01:43:50,541 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-07 01:43:50,541 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-07 01:43:50,542 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-07 01:43:50,542 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-07 01:43:50,543 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-07 01:43:50,544 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-07 01:43:50,544 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-07 01:43:50,544 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-07 01:43:50,545 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-07 01:43:50,545 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-07 01:43:50,546 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-07 01:43:50,546 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-07 01:43:50,565 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-07 01:43:50,565 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-07 01:43:50,566 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-07 01:43:50,566 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-07 01:43:50,567 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * Use SBE=true [2021-12-07 01:43:50,567 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-07 01:43:50,567 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-07 01:43:50,568 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-07 01:43:50,568 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-07 01:43:50,569 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-07 01:43:50,569 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-07 01:43:50,570 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-07 01:43:50,570 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-07 01:43:50,570 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-07 01:43:50,571 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-07 01:43:50,571 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd [2021-12-07 01:43:50,762 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-07 01:43:50,777 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-07 01:43:50,779 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-07 01:43:50,780 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-07 01:43:50,781 INFO L275 PluginConnector]: CDTParser initialized [2021-12-07 01:43:50,781 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-12-07 01:43:50,827 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/data/bdccc1c12/54012c5fb8c24410955de922221ddf14/FLAG839ad590d [2021-12-07 01:43:51,249 INFO L306 CDTParser]: Found 1 translation units. [2021-12-07 01:43:51,250 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-12-07 01:43:51,258 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/data/bdccc1c12/54012c5fb8c24410955de922221ddf14/FLAG839ad590d [2021-12-07 01:43:51,270 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/data/bdccc1c12/54012c5fb8c24410955de922221ddf14 [2021-12-07 01:43:51,273 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-07 01:43:51,274 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-07 01:43:51,276 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-07 01:43:51,276 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-07 01:43:51,279 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-07 01:43:51,280 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,281 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1d40b6e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51, skipping insertion in model container [2021-12-07 01:43:51,281 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,286 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-07 01:43:51,308 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-07 01:43:51,413 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2021-12-07 01:43:51,451 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 01:43:51,458 INFO L203 MainTranslator]: Completed pre-run [2021-12-07 01:43:51,467 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2021-12-07 01:43:51,487 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 01:43:51,499 INFO L208 MainTranslator]: Completed translation [2021-12-07 01:43:51,499 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51 WrapperNode [2021-12-07 01:43:51,500 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-07 01:43:51,500 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-07 01:43:51,501 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-07 01:43:51,501 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-07 01:43:51,506 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,513 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,540 INFO L137 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 49, statements flattened = 594 [2021-12-07 01:43:51,540 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-07 01:43:51,541 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-07 01:43:51,541 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-07 01:43:51,541 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-07 01:43:51,550 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,551 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,556 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,556 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,569 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,577 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,580 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,584 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-07 01:43:51,585 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-07 01:43:51,585 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-07 01:43:51,585 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-07 01:43:51,586 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (1/1) ... [2021-12-07 01:43:51,593 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-07 01:43:51,607 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/z3 [2021-12-07 01:43:51,618 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-07 01:43:51,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-07 01:43:51,668 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-07 01:43:51,669 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-07 01:43:51,669 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-07 01:43:51,669 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-07 01:43:51,727 INFO L236 CfgBuilder]: Building ICFG [2021-12-07 01:43:51,728 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-07 01:43:52,070 INFO L277 CfgBuilder]: Performing block encoding [2021-12-07 01:43:52,078 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-07 01:43:52,079 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-12-07 01:43:52,081 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:43:52 BoogieIcfgContainer [2021-12-07 01:43:52,081 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-07 01:43:52,082 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-07 01:43:52,082 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-07 01:43:52,085 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-07 01:43:52,086 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:43:52,086 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 01:43:51" (1/3) ... [2021-12-07 01:43:52,087 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1edf6342 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:43:52, skipping insertion in model container [2021-12-07 01:43:52,087 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:43:52,087 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:43:51" (2/3) ... [2021-12-07 01:43:52,087 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1edf6342 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:43:52, skipping insertion in model container [2021-12-07 01:43:52,087 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 01:43:52,087 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:43:52" (3/3) ... [2021-12-07 01:43:52,088 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2021-12-07 01:43:52,122 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-07 01:43:52,122 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-07 01:43:52,122 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-07 01:43:52,123 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-07 01:43:52,123 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-07 01:43:52,123 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-07 01:43:52,123 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-07 01:43:52,123 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-07 01:43:52,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2021-12-07 01:43:52,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,178 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,179 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-07 01:43:52,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2021-12-07 01:43:52,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,190 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,190 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,195 INFO L791 eck$LassoCheckResult]: Stem: 220#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 161#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 189#L516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186#L224true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77#L231true assume !(1 == ~m_i~0);~m_st~0 := 2; 4#L231-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 129#L236-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 126#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29#L344true assume !(0 == ~M_E~0); 182#L344-2true assume !(0 == ~T1_E~0); 156#L349-1true assume !(0 == ~T2_E~0); 38#L354-1true assume 0 == ~E_M~0;~E_M~0 := 1; 193#L359-1true assume !(0 == ~E_1~0); 36#L364-1true assume !(0 == ~E_2~0); 164#L369-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L166true assume 1 == ~m_pc~0; 151#L167true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 167#L177true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28#L178true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 210#L425true assume !(0 != activate_threads_~tmp~1#1); 226#L425-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101#L185true assume !(1 == ~t1_pc~0); 41#L185-2true is_transmit1_triggered_~__retres1~1#1 := 0; 61#L196true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70#L197true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 66#L433true assume !(0 != activate_threads_~tmp___0~0#1); 165#L433-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111#L204true assume 1 == ~t2_pc~0; 71#L205true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 130#L215true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208#L216true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19#L441true assume !(0 != activate_threads_~tmp___1~0#1); 95#L441-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116#L382true assume !(1 == ~M_E~0); 13#L382-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L387-1true assume !(1 == ~T2_E~0); 190#L392-1true assume !(1 == ~E_M~0); 106#L397-1true assume !(1 == ~E_1~0); 135#L402-1true assume !(1 == ~E_2~0); 96#L407-1true assume { :end_inline_reset_delta_events } true; 178#L553-2true [2021-12-07 01:43:52,196 INFO L793 eck$LassoCheckResult]: Loop: 178#L553-2true assume !false; 231#L554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232#L319true assume !true; 32#L334true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 221#L224-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 196#L344-3true assume !(0 == ~M_E~0); 3#L344-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 78#L349-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 31#L354-3true assume 0 == ~E_M~0;~E_M~0 := 1; 103#L359-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L364-3true assume 0 == ~E_2~0;~E_2~0 := 1; 74#L369-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59#L166-12true assume !(1 == ~m_pc~0); 172#L166-14true is_master_triggered_~__retres1~0#1 := 0; 44#L177-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82#L178-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 56#L425-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119#L425-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 204#L185-12true assume !(1 == ~t1_pc~0); 34#L185-14true is_transmit1_triggered_~__retres1~1#1 := 0; 146#L196-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200#L197-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 197#L433-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136#L433-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199#L204-12true assume !(1 == ~t2_pc~0); 49#L204-14true is_transmit2_triggered_~__retres1~2#1 := 0; 104#L215-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42#L216-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93#L441-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69#L441-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30#L382-3true assume 1 == ~M_E~0;~M_E~0 := 2; 79#L382-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 115#L387-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 143#L392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 9#L397-3true assume 1 == ~E_1~0;~E_1~0 := 2; 122#L402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 15#L407-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8#L254-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20#L271-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 133#L272-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 108#L572true assume !(0 == start_simulation_~tmp~3#1); 150#L572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27#L254-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 80#L271-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18#L272-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 198#L527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87#L534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191#L535true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 184#L585true assume !(0 != start_simulation_~tmp___0~1#1); 178#L553-2true [2021-12-07 01:43:52,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,201 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2021-12-07 01:43:52,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462110996] [2021-12-07 01:43:52,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,209 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462110996] [2021-12-07 01:43:52,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462110996] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,328 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,328 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:52,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442876598] [2021-12-07 01:43:52,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,334 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:52,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,335 INFO L85 PathProgramCache]: Analyzing trace with hash -152738315, now seen corresponding path program 1 times [2021-12-07 01:43:52,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644610982] [2021-12-07 01:43:52,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,358 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1644610982] [2021-12-07 01:43:52,358 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1644610982] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,358 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,358 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:43:52,358 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903273748] [2021-12-07 01:43:52,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,359 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:52,360 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:52,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:52,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:52,387 INFO L87 Difference]: Start difference. First operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:52,422 INFO L93 Difference]: Finished difference Result 230 states and 340 transitions. [2021-12-07 01:43:52,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:52,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 340 transitions. [2021-12-07 01:43:52,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-07 01:43:52,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 225 states and 335 transitions. [2021-12-07 01:43:52,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2021-12-07 01:43:52,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2021-12-07 01:43:52,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 335 transitions. [2021-12-07 01:43:52,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:52,438 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-07 01:43:52,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 335 transitions. [2021-12-07 01:43:52,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2021-12-07 01:43:52,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 335 transitions. [2021-12-07 01:43:52,468 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-07 01:43:52,468 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-07 01:43:52,468 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-07 01:43:52,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 335 transitions. [2021-12-07 01:43:52,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-07 01:43:52,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,473 INFO L791 eck$LassoCheckResult]: Stem: 694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 673#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473#L236-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 648#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 520#L344 assume !(0 == ~M_E~0); 521#L344-2 assume !(0 == ~T1_E~0); 669#L349-1 assume !(0 == ~T2_E~0); 539#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 540#L359-1 assume !(0 == ~E_1~0); 534#L364-1 assume !(0 == ~E_2~0); 535#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L166 assume 1 == ~m_pc~0; 614#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 662#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 519#L425 assume !(0 != activate_threads_~tmp~1#1); 692#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623#L185 assume !(1 == ~t1_pc~0); 545#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 546#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 588#L433 assume !(0 != activate_threads_~tmp___0~0#1); 589#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634#L204 assume 1 == ~t2_pc~0; 592#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 593#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 501#L441 assume !(0 != activate_threads_~tmp___1~0#1); 502#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 617#L382 assume !(1 == ~M_E~0); 491#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 492#L387-1 assume !(1 == ~T2_E~0); 603#L392-1 assume !(1 == ~E_M~0); 627#L397-1 assume !(1 == ~E_1~0); 628#L402-1 assume !(1 == ~E_2~0); 618#L407-1 assume { :end_inline_reset_delta_events } true; 619#L553-2 [2021-12-07 01:43:52,473 INFO L793 eck$LassoCheckResult]: Loop: 619#L553-2 assume !false; 679#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L319 assume !false; 651#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 553#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 554#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 543#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 544#L286 assume !(0 != eval_~tmp~0#1); 526#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 527#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688#L344-3 assume !(0 == ~M_E~0); 470#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 524#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 525#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 599#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 597#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 579#L166-12 assume 1 == ~m_pc~0; 580#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 549#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 550#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 573#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 574#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643#L185-12 assume !(1 == ~t1_pc~0); 531#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 532#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 660#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 689#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 653#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 654#L204-12 assume 1 == ~t2_pc~0; 675#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 558#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 548#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 591#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 523#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 601#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 637#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 484#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 485#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 495#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 481#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 482#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 503#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 631#L572 assume !(0 == start_simulation_~tmp~3#1); 542#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 515#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 516#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 499#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 500#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 610#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 682#L585 assume !(0 != start_simulation_~tmp___0~1#1); 619#L553-2 [2021-12-07 01:43:52,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,474 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2021-12-07 01:43:52,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600403032] [2021-12-07 01:43:52,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,474 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,505 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600403032] [2021-12-07 01:43:52,505 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600403032] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:52,506 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251104713] [2021-12-07 01:43:52,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:52,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,507 INFO L85 PathProgramCache]: Analyzing trace with hash 1606950136, now seen corresponding path program 1 times [2021-12-07 01:43:52,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,507 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042183289] [2021-12-07 01:43:52,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,554 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042183289] [2021-12-07 01:43:52,555 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042183289] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,555 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,555 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:52,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638717169] [2021-12-07 01:43:52,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,555 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:52,556 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:52,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:52,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:52,556 INFO L87 Difference]: Start difference. First operand 225 states and 335 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:52,570 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2021-12-07 01:43:52,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:52,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 334 transitions. [2021-12-07 01:43:52,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-07 01:43:52,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 334 transitions. [2021-12-07 01:43:52,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2021-12-07 01:43:52,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2021-12-07 01:43:52,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 334 transitions. [2021-12-07 01:43:52,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:52,577 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-07 01:43:52,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 334 transitions. [2021-12-07 01:43:52,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2021-12-07 01:43:52,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 334 transitions. [2021-12-07 01:43:52,585 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-07 01:43:52,586 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-07 01:43:52,586 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-07 01:43:52,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 334 transitions. [2021-12-07 01:43:52,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-07 01:43:52,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,588 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,588 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,589 INFO L791 eck$LassoCheckResult]: Stem: 1153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1132#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1142#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1059#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 931#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1107#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 979#L344 assume !(0 == ~M_E~0); 980#L344-2 assume !(0 == ~T1_E~0); 1128#L349-1 assume !(0 == ~T2_E~0); 998#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 999#L359-1 assume !(0 == ~E_1~0); 993#L364-1 assume !(0 == ~E_2~0); 994#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1072#L166 assume 1 == ~m_pc~0; 1073#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1121#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 977#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 978#L425 assume !(0 != activate_threads_~tmp~1#1); 1151#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082#L185 assume !(1 == ~t1_pc~0); 1004#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1005#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1042#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1047#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1048#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1093#L204 assume 1 == ~t2_pc~0; 1051#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1052#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1109#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 960#L441 assume !(0 != activate_threads_~tmp___1~0#1); 961#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1076#L382 assume !(1 == ~M_E~0); 950#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L387-1 assume !(1 == ~T2_E~0); 1062#L392-1 assume !(1 == ~E_M~0); 1086#L397-1 assume !(1 == ~E_1~0); 1087#L402-1 assume !(1 == ~E_2~0); 1077#L407-1 assume { :end_inline_reset_delta_events } true; 1078#L553-2 [2021-12-07 01:43:52,589 INFO L793 eck$LassoCheckResult]: Loop: 1078#L553-2 assume !false; 1138#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1133#L319 assume !false; 1110#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1012#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1013#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1002#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1003#L286 assume !(0 != eval_~tmp~0#1); 985#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 986#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L344-3 assume !(0 == ~M_E~0); 929#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 930#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 983#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 984#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1058#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1056#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1038#L166-12 assume !(1 == ~m_pc~0); 1040#L166-14 is_master_triggered_~__retres1~0#1 := 0; 1008#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1009#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1032#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1033#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102#L185-12 assume 1 == ~t1_pc~0; 1120#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 991#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1119#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1148#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1112#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1113#L204-12 assume !(1 == ~t2_pc~0); 1016#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1017#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1007#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1050#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 981#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 982#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1060#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1096#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 943#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 944#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 954#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 940#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 941#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 962#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1090#L572 assume !(0 == start_simulation_~tmp~3#1); 1001#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 974#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 975#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 958#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 959#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1068#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1069#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1141#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L553-2 [2021-12-07 01:43:52,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2021-12-07 01:43:52,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129293495] [2021-12-07 01:43:52,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,590 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,626 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129293495] [2021-12-07 01:43:52,626 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2129293495] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,626 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:52,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504036856] [2021-12-07 01:43:52,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,627 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:52,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,627 INFO L85 PathProgramCache]: Analyzing trace with hash -1848890247, now seen corresponding path program 1 times [2021-12-07 01:43:52,627 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723237178] [2021-12-07 01:43:52,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,664 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723237178] [2021-12-07 01:43:52,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723237178] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,664 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:52,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564582543] [2021-12-07 01:43:52,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,665 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:52,665 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:52,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:43:52,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:43:52,666 INFO L87 Difference]: Start difference. First operand 225 states and 334 transitions. cyclomatic complexity: 110 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:52,746 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2021-12-07 01:43:52,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:43:52,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 362 states and 534 transitions. [2021-12-07 01:43:52,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2021-12-07 01:43:52,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 362 states to 362 states and 534 transitions. [2021-12-07 01:43:52,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 362 [2021-12-07 01:43:52,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 362 [2021-12-07 01:43:52,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 534 transitions. [2021-12-07 01:43:52,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:52,755 INFO L681 BuchiCegarLoop]: Abstraction has 362 states and 534 transitions. [2021-12-07 01:43:52,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 534 transitions. [2021-12-07 01:43:52,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 361. [2021-12-07 01:43:52,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 361 states to 361 states and 533 transitions. [2021-12-07 01:43:52,768 INFO L704 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2021-12-07 01:43:52,768 INFO L587 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2021-12-07 01:43:52,769 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-07 01:43:52,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 361 states and 533 transitions. [2021-12-07 01:43:52,770 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2021-12-07 01:43:52,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,772 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,772 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,772 INFO L791 eck$LassoCheckResult]: Stem: 1776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1749#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1659#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 1530#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1531#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1716#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1578#L344 assume !(0 == ~M_E~0); 1579#L344-2 assume !(0 == ~T1_E~0); 1743#L349-1 assume !(0 == ~T2_E~0); 1598#L354-1 assume !(0 == ~E_M~0); 1599#L359-1 assume !(0 == ~E_1~0); 1593#L364-1 assume !(0 == ~E_2~0); 1594#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1675#L166 assume 1 == ~m_pc~0; 1676#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1736#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1576#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1577#L425 assume !(0 != activate_threads_~tmp~1#1); 1774#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1685#L185 assume !(1 == ~t1_pc~0); 1604#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1605#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1642#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1647#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1648#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1697#L204 assume 1 == ~t2_pc~0; 1651#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1652#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1718#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1559#L441 assume !(0 != activate_threads_~tmp___1~0#1); 1560#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1679#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 1701#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1826#L387-1 assume !(1 == ~T2_E~0); 1765#L392-1 assume !(1 == ~E_M~0); 1689#L397-1 assume !(1 == ~E_1~0); 1690#L402-1 assume !(1 == ~E_2~0); 1722#L407-1 assume { :end_inline_reset_delta_events } true; 1791#L553-2 [2021-12-07 01:43:52,772 INFO L793 eck$LassoCheckResult]: Loop: 1791#L553-2 assume !false; 1779#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1750#L319 assume !false; 1719#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1720#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1746#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1747#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1663#L286 assume !(0 != eval_~tmp~0#1); 1665#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1777#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1778#L344-3 assume !(0 == ~M_E~0); 1528#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1529#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1583#L354-3 assume !(0 == ~E_M~0); 1584#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1658#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1656#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1638#L166-12 assume 1 == ~m_pc~0; 1639#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1608#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1609#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1632#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1633#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1707#L185-12 assume !(1 == ~t1_pc~0); 1590#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1591#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1873#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1872#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1871#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1870#L204-12 assume 1 == ~t2_pc~0; 1868#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1867#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1866#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1865#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1864#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1863#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1581#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1862#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1861#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1731#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1860#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1859#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1856#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1855#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1854#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1853#L572 assume !(0 == start_simulation_~tmp~3#1); 1601#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1573#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1574#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1557#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1558#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1671#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1672#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1766#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1791#L553-2 [2021-12-07 01:43:52,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2021-12-07 01:43:52,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239576130] [2021-12-07 01:43:52,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239576130] [2021-12-07 01:43:52,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239576130] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:43:52,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210154892] [2021-12-07 01:43:52,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,800 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:52,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,800 INFO L85 PathProgramCache]: Analyzing trace with hash 2030596858, now seen corresponding path program 1 times [2021-12-07 01:43:52,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190185157] [2021-12-07 01:43:52,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,839 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190185157] [2021-12-07 01:43:52,839 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190185157] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,840 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,840 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:52,840 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339362805] [2021-12-07 01:43:52,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,840 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:52,840 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:52,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:52,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:52,841 INFO L87 Difference]: Start difference. First operand 361 states and 533 transitions. cyclomatic complexity: 174 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:52,881 INFO L93 Difference]: Finished difference Result 658 states and 955 transitions. [2021-12-07 01:43:52,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:52,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 658 states and 955 transitions. [2021-12-07 01:43:52,889 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2021-12-07 01:43:52,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 658 states to 658 states and 955 transitions. [2021-12-07 01:43:52,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 658 [2021-12-07 01:43:52,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 658 [2021-12-07 01:43:52,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 658 states and 955 transitions. [2021-12-07 01:43:52,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:52,898 INFO L681 BuchiCegarLoop]: Abstraction has 658 states and 955 transitions. [2021-12-07 01:43:52,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 658 states and 955 transitions. [2021-12-07 01:43:52,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 658 to 618. [2021-12-07 01:43:52,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:52,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 618 states to 618 states and 901 transitions. [2021-12-07 01:43:52,923 INFO L704 BuchiCegarLoop]: Abstraction has 618 states and 901 transitions. [2021-12-07 01:43:52,923 INFO L587 BuchiCegarLoop]: Abstraction has 618 states and 901 transitions. [2021-12-07 01:43:52,924 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-07 01:43:52,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 618 states and 901 transitions. [2021-12-07 01:43:52,928 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 568 [2021-12-07 01:43:52,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:52,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:52,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:52,930 INFO L791 eck$LassoCheckResult]: Stem: 2842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2792#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2814#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2696#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 2558#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2559#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2758#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2609#L344 assume !(0 == ~M_E~0); 2610#L344-2 assume !(0 == ~T1_E~0); 2786#L349-1 assume !(0 == ~T2_E~0); 2629#L354-1 assume !(0 == ~E_M~0); 2630#L359-1 assume !(0 == ~E_1~0); 2624#L364-1 assume !(0 == ~E_2~0); 2625#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2718#L166 assume !(1 == ~m_pc~0); 2719#L166-2 is_master_triggered_~__retres1~0#1 := 0; 2795#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2607#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2608#L425 assume !(0 != activate_threads_~tmp~1#1); 2831#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2728#L185 assume !(1 == ~t1_pc~0); 2635#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2636#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2674#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2678#L433 assume !(0 != activate_threads_~tmp___0~0#1); 2679#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2741#L204 assume 1 == ~t2_pc~0; 2685#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2686#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2760#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2589#L441 assume !(0 != activate_threads_~tmp___1~0#1); 2590#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2722#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 2577#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2578#L387-1 assume !(1 == ~T2_E~0); 2955#L392-1 assume !(1 == ~E_M~0); 2817#L397-1 assume !(1 == ~E_1~0); 2767#L402-1 assume !(1 == ~E_2~0); 2725#L407-1 assume { :end_inline_reset_delta_events } true; 2726#L553-2 [2021-12-07 01:43:52,930 INFO L793 eck$LassoCheckResult]: Loop: 2726#L553-2 assume !false; 2806#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2793#L319 assume !false; 2761#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2645#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2646#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2633#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2634#L286 assume !(0 != eval_~tmp~0#1); 2701#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2960#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2920#L344-3 assume !(0 == ~M_E~0); 2921#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3128#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3127#L354-3 assume !(0 == ~E_M~0); 3126#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3125#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3124#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3123#L166-12 assume !(1 == ~m_pc~0); 3122#L166-14 is_master_triggered_~__retres1~0#1 := 0; 2639#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2640#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2664#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2665#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2752#L185-12 assume 1 == ~t1_pc~0; 2780#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2622#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3002#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3003#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2896#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2897#L204-12 assume 1 == ~t2_pc~0; 2890#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2891#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2886#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2887#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2681#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2682#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2612#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2744#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2745#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2570#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2571#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3008#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2567#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2568#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2591#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2737#L572 assume !(0 == start_simulation_~tmp~3#1); 2632#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2604#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2605#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2587#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2588#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2707#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2708#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2812#L585 assume !(0 != start_simulation_~tmp___0~1#1); 2726#L553-2 [2021-12-07 01:43:52,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,931 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2021-12-07 01:43:52,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55295698] [2021-12-07 01:43:52,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55295698] [2021-12-07 01:43:52,968 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55295698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,968 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:52,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:52,968 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137743879] [2021-12-07 01:43:52,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:52,968 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:52,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:52,969 INFO L85 PathProgramCache]: Analyzing trace with hash 632360506, now seen corresponding path program 1 times [2021-12-07 01:43:52,969 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:52,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709518629] [2021-12-07 01:43:52,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:52,969 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:52,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:52,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:52,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:52,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709518629] [2021-12-07 01:43:52,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709518629] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:52,999 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195930230] [2021-12-07 01:43:53,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,000 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,000 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:43:53,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:43:53,001 INFO L87 Difference]: Start difference. First operand 618 states and 901 transitions. cyclomatic complexity: 287 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,073 INFO L93 Difference]: Finished difference Result 1401 states and 2004 transitions. [2021-12-07 01:43:53,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:43:53,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1401 states and 2004 transitions. [2021-12-07 01:43:53,082 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1296 [2021-12-07 01:43:53,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1401 states to 1401 states and 2004 transitions. [2021-12-07 01:43:53,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1401 [2021-12-07 01:43:53,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1401 [2021-12-07 01:43:53,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1401 states and 2004 transitions. [2021-12-07 01:43:53,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,094 INFO L681 BuchiCegarLoop]: Abstraction has 1401 states and 2004 transitions. [2021-12-07 01:43:53,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1401 states and 2004 transitions. [2021-12-07 01:43:53,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1401 to 1118. [2021-12-07 01:43:53,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1615 transitions. [2021-12-07 01:43:53,117 INFO L704 BuchiCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2021-12-07 01:43:53,117 INFO L587 BuchiCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2021-12-07 01:43:53,117 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-07 01:43:53,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1118 states and 1615 transitions. [2021-12-07 01:43:53,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1067 [2021-12-07 01:43:53,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,123 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,123 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,124 INFO L791 eck$LassoCheckResult]: Stem: 4851#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4815#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4834#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4721#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 4589#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4590#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4640#L344 assume !(0 == ~M_E~0); 4641#L344-2 assume !(0 == ~T1_E~0); 4809#L349-1 assume !(0 == ~T2_E~0); 4659#L354-1 assume !(0 == ~E_M~0); 4660#L359-1 assume !(0 == ~E_1~0); 4654#L364-1 assume !(0 == ~E_2~0); 4655#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4738#L166 assume !(1 == ~m_pc~0); 4739#L166-2 is_master_triggered_~__retres1~0#1 := 0; 4821#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4638#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4639#L425 assume !(0 != activate_threads_~tmp~1#1); 4846#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4749#L185 assume !(1 == ~t1_pc~0); 4665#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4666#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4705#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4711#L433 assume !(0 != activate_threads_~tmp___0~0#1); 4712#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4766#L204 assume !(1 == ~t2_pc~0); 4747#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4748#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4787#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4620#L441 assume !(0 != activate_threads_~tmp___1~0#1); 4621#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4741#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 4608#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4609#L387-1 assume !(1 == ~T2_E~0); 4836#L392-1 assume !(1 == ~E_M~0); 4837#L397-1 assume !(1 == ~E_1~0); 4792#L402-1 assume !(1 == ~E_2~0); 4793#L407-1 assume { :end_inline_reset_delta_events } true; 5629#L553-2 [2021-12-07 01:43:53,124 INFO L793 eck$LassoCheckResult]: Loop: 5629#L553-2 assume !false; 5628#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4840#L319 assume !false; 5627#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5623#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5619#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5609#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5606#L286 assume !(0 != eval_~tmp~0#1); 5607#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5653#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5652#L344-3 assume !(0 == ~M_E~0); 4587#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4588#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4644#L354-3 assume !(0 == ~E_M~0); 4645#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4719#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4718#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4701#L166-12 assume !(1 == ~m_pc~0); 4702#L166-14 is_master_triggered_~__retres1~0#1 := 0; 4671#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4672#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4695#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4696#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4776#L185-12 assume 1 == ~t1_pc~0; 4801#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4652#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4800#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4843#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4790#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4791#L204-12 assume !(1 == ~t2_pc~0); 4680#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4681#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4667#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4668#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4713#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4642#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4643#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4720#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4769#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4601#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4602#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4779#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5649#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5648#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5647#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5646#L572 assume !(0 == start_simulation_~tmp~3#1); 4662#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5643#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5640#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5638#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5636#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5634#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5633#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5630#L585 assume !(0 != start_simulation_~tmp___0~1#1); 5629#L553-2 [2021-12-07 01:43:53,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,124 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2021-12-07 01:43:53,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189550369] [2021-12-07 01:43:53,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,125 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189550369] [2021-12-07 01:43:53,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189550369] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:43:53,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147518812] [2021-12-07 01:43:53,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:53,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1425243525, now seen corresponding path program 1 times [2021-12-07 01:43:53,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860265674] [2021-12-07 01:43:53,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860265674] [2021-12-07 01:43:53,174 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [860265674] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,175 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,175 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,175 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101460465] [2021-12-07 01:43:53,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,175 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,175 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:53,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:53,176 INFO L87 Difference]: Start difference. First operand 1118 states and 1615 transitions. cyclomatic complexity: 501 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,195 INFO L93 Difference]: Finished difference Result 1641 states and 2364 transitions. [2021-12-07 01:43:53,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:53,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1641 states and 2364 transitions. [2021-12-07 01:43:53,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1591 [2021-12-07 01:43:53,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1641 states to 1641 states and 2364 transitions. [2021-12-07 01:43:53,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1641 [2021-12-07 01:43:53,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1641 [2021-12-07 01:43:53,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1641 states and 2364 transitions. [2021-12-07 01:43:53,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,218 INFO L681 BuchiCegarLoop]: Abstraction has 1641 states and 2364 transitions. [2021-12-07 01:43:53,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1641 states and 2364 transitions. [2021-12-07 01:43:53,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1641 to 1181. [2021-12-07 01:43:53,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1704 transitions. [2021-12-07 01:43:53,237 INFO L704 BuchiCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2021-12-07 01:43:53,238 INFO L587 BuchiCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2021-12-07 01:43:53,238 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-07 01:43:53,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1704 transitions. [2021-12-07 01:43:53,242 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2021-12-07 01:43:53,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,243 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,243 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,243 INFO L791 eck$LassoCheckResult]: Stem: 7629#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7589#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7608#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7492#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 7357#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7358#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7556#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7408#L344 assume !(0 == ~M_E~0); 7409#L344-2 assume !(0 == ~T1_E~0); 7583#L349-1 assume !(0 == ~T2_E~0); 7428#L354-1 assume !(0 == ~E_M~0); 7429#L359-1 assume !(0 == ~E_1~0); 7423#L364-1 assume !(0 == ~E_2~0); 7424#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7513#L166 assume !(1 == ~m_pc~0); 7514#L166-2 is_master_triggered_~__retres1~0#1 := 0; 7592#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7406#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7407#L425 assume !(0 != activate_threads_~tmp~1#1); 7624#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7525#L185 assume !(1 == ~t1_pc~0); 7434#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7435#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7474#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7481#L433 assume !(0 != activate_threads_~tmp___0~0#1); 7482#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7542#L204 assume !(1 == ~t2_pc~0); 7523#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7524#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7558#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7388#L441 assume !(0 != activate_threads_~tmp___1~0#1); 7389#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7517#L382 assume !(1 == ~M_E~0); 7376#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7377#L387-1 assume !(1 == ~T2_E~0); 7496#L392-1 assume !(1 == ~E_M~0); 7531#L397-1 assume !(1 == ~E_1~0); 7532#L402-1 assume !(1 == ~E_2~0); 7518#L407-1 assume { :end_inline_reset_delta_events } true; 7519#L553-2 [2021-12-07 01:43:53,243 INFO L793 eck$LassoCheckResult]: Loop: 7519#L553-2 assume !false; 8483#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7596#L319 assume !false; 7559#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7444#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7445#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8372#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7497#L286 assume !(0 != eval_~tmp~0#1); 7498#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8535#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7615#L344-3 assume !(0 == ~M_E~0); 7355#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7356#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7412#L354-3 assume !(0 == ~E_M~0); 7413#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7491#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7471#L166-12 assume !(1 == ~m_pc~0); 7472#L166-14 is_master_triggered_~__retres1~0#1 := 0; 7440#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7441#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7465#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7466#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7551#L185-12 assume !(1 == ~t1_pc~0); 8503#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8502#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8498#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8496#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8494#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8492#L204-12 assume !(1 == ~t2_pc~0); 8401#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8482#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7436#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7437#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7484#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7410#L382-3 assume !(1 == ~M_E~0); 7411#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8392#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8384#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8371#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8367#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8364#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8356#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8353#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8349#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7536#L572 assume !(0 == start_simulation_~tmp~3#1); 7538#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8500#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8497#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8495#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8493#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8490#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8487#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8485#L585 assume !(0 != start_simulation_~tmp___0~1#1); 7519#L553-2 [2021-12-07 01:43:53,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2021-12-07 01:43:53,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388595524] [2021-12-07 01:43:53,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,265 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388595524] [2021-12-07 01:43:53,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388595524] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:53,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177193905] [2021-12-07 01:43:53,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,266 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:53,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,266 INFO L85 PathProgramCache]: Analyzing trace with hash -590690946, now seen corresponding path program 1 times [2021-12-07 01:43:53,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192542241] [2021-12-07 01:43:53,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,288 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192542241] [2021-12-07 01:43:53,288 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192542241] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,288 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,289 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275819128] [2021-12-07 01:43:53,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,289 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,289 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:43:53,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:43:53,290 INFO L87 Difference]: Start difference. First operand 1181 states and 1704 transitions. cyclomatic complexity: 525 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,335 INFO L93 Difference]: Finished difference Result 1930 states and 2751 transitions. [2021-12-07 01:43:53,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:43:53,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1930 states and 2751 transitions. [2021-12-07 01:43:53,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1852 [2021-12-07 01:43:53,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1930 states to 1930 states and 2751 transitions. [2021-12-07 01:43:53,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1930 [2021-12-07 01:43:53,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1930 [2021-12-07 01:43:53,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1930 states and 2751 transitions. [2021-12-07 01:43:53,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,360 INFO L681 BuchiCegarLoop]: Abstraction has 1930 states and 2751 transitions. [2021-12-07 01:43:53,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1930 states and 2751 transitions. [2021-12-07 01:43:53,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1930 to 1423. [2021-12-07 01:43:53,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1423 states, 1423 states have (on average 1.4265635980323261) internal successors, (2030), 1422 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1423 states to 1423 states and 2030 transitions. [2021-12-07 01:43:53,385 INFO L704 BuchiCegarLoop]: Abstraction has 1423 states and 2030 transitions. [2021-12-07 01:43:53,385 INFO L587 BuchiCegarLoop]: Abstraction has 1423 states and 2030 transitions. [2021-12-07 01:43:53,385 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-07 01:43:53,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1423 states and 2030 transitions. [2021-12-07 01:43:53,390 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1352 [2021-12-07 01:43:53,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,391 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,391 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,391 INFO L791 eck$LassoCheckResult]: Stem: 10749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10705#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10724#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10611#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 10481#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10482#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10672#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10529#L344 assume !(0 == ~M_E~0); 10530#L344-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10696#L349-1 assume !(0 == ~T2_E~0); 10697#L354-1 assume !(0 == ~E_M~0); 10729#L359-1 assume !(0 == ~E_1~0); 10730#L364-1 assume !(0 == ~E_2~0); 10707#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10708#L166 assume !(1 == ~m_pc~0); 10767#L166-2 is_master_triggered_~__retres1~0#1 := 0; 10711#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10527#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10528#L425 assume !(0 != activate_threads_~tmp~1#1); 10765#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10638#L185 assume !(1 == ~t1_pc~0); 10639#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10764#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10604#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10605#L433 assume !(0 != activate_threads_~tmp___0~0#1); 10709#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10655#L204 assume !(1 == ~t2_pc~0); 10656#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10762#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10761#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10510#L441 assume !(0 != activate_threads_~tmp___1~0#1); 10511#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10630#L382 assume !(1 == ~M_E~0); 10661#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10501#L387-1 assume !(1 == ~T2_E~0); 10615#L392-1 assume !(1 == ~E_M~0); 10644#L397-1 assume !(1 == ~E_1~0); 10645#L402-1 assume !(1 == ~E_2~0); 10631#L407-1 assume { :end_inline_reset_delta_events } true; 10632#L553-2 [2021-12-07 01:43:53,391 INFO L793 eck$LassoCheckResult]: Loop: 10632#L553-2 assume !false; 11381#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11377#L319 assume !false; 11375#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11372#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11369#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11368#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11365#L286 assume !(0 != eval_~tmp~0#1); 11363#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11361#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11359#L344-3 assume !(0 == ~M_E~0); 11356#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11355#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11354#L354-3 assume !(0 == ~E_M~0); 11353#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11352#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11351#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11350#L166-12 assume !(1 == ~m_pc~0); 11349#L166-14 is_master_triggered_~__retres1~0#1 := 0; 11348#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11347#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11346#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11345#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11344#L185-12 assume !(1 == ~t1_pc~0); 11342#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 11341#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11340#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11339#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11338#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11337#L204-12 assume !(1 == ~t2_pc~0); 10905#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 11336#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11335#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11334#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11333#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11332#L382-3 assume !(1 == ~M_E~0); 11196#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11331#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11330#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11329#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11327#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11326#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11323#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11322#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11321#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10648#L572 assume !(0 == start_simulation_~tmp~3#1); 10650#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11404#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11401#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11399#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11397#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11395#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11393#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11391#L585 assume !(0 != start_simulation_~tmp___0~1#1); 10632#L553-2 [2021-12-07 01:43:53,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,392 INFO L85 PathProgramCache]: Analyzing trace with hash 318575881, now seen corresponding path program 1 times [2021-12-07 01:43:53,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940420845] [2021-12-07 01:43:53,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,392 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940420845] [2021-12-07 01:43:53,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940420845] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:53,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97396413] [2021-12-07 01:43:53,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,410 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:53,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,411 INFO L85 PathProgramCache]: Analyzing trace with hash -590690946, now seen corresponding path program 2 times [2021-12-07 01:43:53,411 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740729941] [2021-12-07 01:43:53,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,434 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740729941] [2021-12-07 01:43:53,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740729941] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,434 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,435 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248742021] [2021-12-07 01:43:53,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,435 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,435 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 01:43:53,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 01:43:53,436 INFO L87 Difference]: Start difference. First operand 1423 states and 2030 transitions. cyclomatic complexity: 609 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,470 INFO L93 Difference]: Finished difference Result 1683 states and 2386 transitions. [2021-12-07 01:43:53,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 01:43:53,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1683 states and 2386 transitions. [2021-12-07 01:43:53,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1636 [2021-12-07 01:43:53,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1683 states to 1683 states and 2386 transitions. [2021-12-07 01:43:53,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1683 [2021-12-07 01:43:53,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1683 [2021-12-07 01:43:53,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1683 states and 2386 transitions. [2021-12-07 01:43:53,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,493 INFO L681 BuchiCegarLoop]: Abstraction has 1683 states and 2386 transitions. [2021-12-07 01:43:53,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1683 states and 2386 transitions. [2021-12-07 01:43:53,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1683 to 1181. [2021-12-07 01:43:53,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1678 transitions. [2021-12-07 01:43:53,515 INFO L704 BuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2021-12-07 01:43:53,515 INFO L587 BuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2021-12-07 01:43:53,515 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-07 01:43:53,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1678 transitions. [2021-12-07 01:43:53,519 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2021-12-07 01:43:53,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,520 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,520 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,520 INFO L791 eck$LassoCheckResult]: Stem: 13850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13812#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13833#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13730#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 13598#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13599#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13787#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13646#L344 assume !(0 == ~M_E~0); 13647#L344-2 assume !(0 == ~T1_E~0); 13807#L349-1 assume !(0 == ~T2_E~0); 13665#L354-1 assume !(0 == ~E_M~0); 13666#L359-1 assume !(0 == ~E_1~0); 13660#L364-1 assume !(0 == ~E_2~0); 13661#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13745#L166 assume !(1 == ~m_pc~0); 13746#L166-2 is_master_triggered_~__retres1~0#1 := 0; 13817#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13644#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13645#L425 assume !(0 != activate_threads_~tmp~1#1); 13845#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13757#L185 assume !(1 == ~t1_pc~0); 13671#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13672#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13711#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13717#L433 assume !(0 != activate_threads_~tmp___0~0#1); 13718#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13769#L204 assume !(1 == ~t2_pc~0); 13755#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13756#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13789#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13627#L441 assume !(0 != activate_threads_~tmp___1~0#1); 13628#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13749#L382 assume !(1 == ~M_E~0); 13617#L382-2 assume !(1 == ~T1_E~0); 13618#L387-1 assume !(1 == ~T2_E~0); 13732#L392-1 assume !(1 == ~E_M~0); 13762#L397-1 assume !(1 == ~E_1~0); 13763#L402-1 assume !(1 == ~E_2~0); 13752#L407-1 assume { :end_inline_reset_delta_events } true; 13753#L553-2 [2021-12-07 01:43:53,520 INFO L793 eck$LassoCheckResult]: Loop: 13753#L553-2 assume !false; 14378#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14375#L319 assume !false; 14374#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14372#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14370#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14369#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14367#L286 assume !(0 != eval_~tmp~0#1); 14366#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14365#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14363#L344-3 assume !(0 == ~M_E~0); 14361#L344-5 assume !(0 == ~T1_E~0); 14359#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14357#L354-3 assume !(0 == ~E_M~0); 14355#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14353#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14351#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14349#L166-12 assume !(1 == ~m_pc~0); 14347#L166-14 is_master_triggered_~__retres1~0#1 := 0; 14345#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14343#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14341#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14339#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14337#L185-12 assume !(1 == ~t1_pc~0); 14334#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14331#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14329#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14327#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14325#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14220#L204-12 assume !(1 == ~t2_pc~0); 14219#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14218#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14217#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14216#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14215#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14214#L382-3 assume !(1 == ~M_E~0); 14175#L382-5 assume !(1 == ~T1_E~0); 14213#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14212#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14211#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14210#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14208#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13933#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13927#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13922#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13891#L572 assume !(0 == start_simulation_~tmp~3#1); 13893#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14400#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14397#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14395#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 14393#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14391#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14387#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 14385#L585 assume !(0 != start_simulation_~tmp___0~1#1); 13753#L553-2 [2021-12-07 01:43:53,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2021-12-07 01:43:53,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330259404] [2021-12-07 01:43:53,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,529 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:53,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,556 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:53,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,557 INFO L85 PathProgramCache]: Analyzing trace with hash 812738366, now seen corresponding path program 1 times [2021-12-07 01:43:53,557 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694878877] [2021-12-07 01:43:53,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,558 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,585 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,585 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694878877] [2021-12-07 01:43:53,586 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694878877] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,586 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,586 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,586 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374507499] [2021-12-07 01:43:53,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,586 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 01:43:53,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 01:43:53,587 INFO L87 Difference]: Start difference. First operand 1181 states and 1678 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,655 INFO L93 Difference]: Finished difference Result 2033 states and 2838 transitions. [2021-12-07 01:43:53,655 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-07 01:43:53,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2033 states and 2838 transitions. [2021-12-07 01:43:53,669 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1984 [2021-12-07 01:43:53,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2033 states to 2033 states and 2838 transitions. [2021-12-07 01:43:53,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2033 [2021-12-07 01:43:53,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2033 [2021-12-07 01:43:53,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2033 states and 2838 transitions. [2021-12-07 01:43:53,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,686 INFO L681 BuchiCegarLoop]: Abstraction has 2033 states and 2838 transitions. [2021-12-07 01:43:53,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2033 states and 2838 transitions. [2021-12-07 01:43:53,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2033 to 1205. [2021-12-07 01:43:53,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1205 states to 1205 states and 1702 transitions. [2021-12-07 01:43:53,708 INFO L704 BuchiCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2021-12-07 01:43:53,708 INFO L587 BuchiCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2021-12-07 01:43:53,708 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-07 01:43:53,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1205 states and 1702 transitions. [2021-12-07 01:43:53,713 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1160 [2021-12-07 01:43:53,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,714 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,714 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,714 INFO L791 eck$LassoCheckResult]: Stem: 17102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17058#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17077#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16963#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 16828#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16829#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17027#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16878#L344 assume !(0 == ~M_E~0); 16879#L344-2 assume !(0 == ~T1_E~0); 17052#L349-1 assume !(0 == ~T2_E~0); 16897#L354-1 assume !(0 == ~E_M~0); 16898#L359-1 assume !(0 == ~E_1~0); 16892#L364-1 assume !(0 == ~E_2~0); 16893#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16982#L166 assume !(1 == ~m_pc~0); 16983#L166-2 is_master_triggered_~__retres1~0#1 := 0; 17061#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16876#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16877#L425 assume !(0 != activate_threads_~tmp~1#1); 17097#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16994#L185 assume !(1 == ~t1_pc~0); 16903#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16904#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16943#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16948#L433 assume !(0 != activate_threads_~tmp___0~0#1); 16949#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17012#L204 assume !(1 == ~t2_pc~0); 16992#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16993#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17029#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16858#L441 assume !(0 != activate_threads_~tmp___1~0#1); 16859#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16986#L382 assume !(1 == ~M_E~0); 16847#L382-2 assume !(1 == ~T1_E~0); 16848#L387-1 assume !(1 == ~T2_E~0); 16967#L392-1 assume !(1 == ~E_M~0); 17002#L397-1 assume !(1 == ~E_1~0); 17003#L402-1 assume !(1 == ~E_2~0); 16989#L407-1 assume { :end_inline_reset_delta_events } true; 16990#L553-2 [2021-12-07 01:43:53,715 INFO L793 eck$LassoCheckResult]: Loop: 16990#L553-2 assume !false; 17897#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17891#L319 assume !false; 17817#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17796#L254 assume !(0 == ~m_st~0); 17797#L258 assume !(0 == ~t1_st~0); 17798#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 17799#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17544#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17545#L286 assume !(0 != eval_~tmp~0#1); 17781#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17780#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17084#L344-3 assume !(0 == ~M_E~0); 16826#L344-5 assume !(0 == ~T1_E~0); 16827#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16882#L354-3 assume !(0 == ~E_M~0); 16883#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16957#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16958#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16939#L166-12 assume !(1 == ~m_pc~0); 16940#L166-14 is_master_triggered_~__retres1~0#1 := 0; 16909#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16910#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16933#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16934#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17092#L185-12 assume !(1 == ~t1_pc~0); 17093#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17042#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17043#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18012#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17034#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17035#L204-12 assume !(1 == ~t2_pc~0); 16917#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 16918#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16905#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16906#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16951#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16880#L382-3 assume !(1 == ~M_E~0); 16881#L382-5 assume !(1 == ~T1_E~0); 18030#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18029#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18028#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18027#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18026#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18023#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18022#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17031#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 17032#L572 assume !(0 == start_simulation_~tmp~3#1); 16900#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16873#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16874#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16856#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 16857#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16973#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16974#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17944#L585 assume !(0 != start_simulation_~tmp___0~1#1); 16990#L553-2 [2021-12-07 01:43:53,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2021-12-07 01:43:53,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582703934] [2021-12-07 01:43:53,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,722 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:53,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,737 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:53,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,738 INFO L85 PathProgramCache]: Analyzing trace with hash -60432105, now seen corresponding path program 1 times [2021-12-07 01:43:53,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203948918] [2021-12-07 01:43:53,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,738 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203948918] [2021-12-07 01:43:53,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203948918] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 01:43:53,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143163185] [2021-12-07 01:43:53,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,800 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 01:43:53,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 01:43:53,801 INFO L87 Difference]: Start difference. First operand 1205 states and 1702 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:53,901 INFO L93 Difference]: Finished difference Result 2347 states and 3283 transitions. [2021-12-07 01:43:53,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 01:43:53,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2347 states and 3283 transitions. [2021-12-07 01:43:53,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2302 [2021-12-07 01:43:53,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2347 states to 2347 states and 3283 transitions. [2021-12-07 01:43:53,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2347 [2021-12-07 01:43:53,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2347 [2021-12-07 01:43:53,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2347 states and 3283 transitions. [2021-12-07 01:43:53,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:53,928 INFO L681 BuchiCegarLoop]: Abstraction has 2347 states and 3283 transitions. [2021-12-07 01:43:53,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2347 states and 3283 transitions. [2021-12-07 01:43:53,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2347 to 1253. [2021-12-07 01:43:53,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:53,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 1737 transitions. [2021-12-07 01:43:53,953 INFO L704 BuchiCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2021-12-07 01:43:53,953 INFO L587 BuchiCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2021-12-07 01:43:53,953 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-07 01:43:53,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1253 states and 1737 transitions. [2021-12-07 01:43:53,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1208 [2021-12-07 01:43:53,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:53,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:53,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:53,957 INFO L791 eck$LassoCheckResult]: Stem: 20679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 20626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20627#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20652#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20525#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 20393#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20394#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20589#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20443#L344 assume !(0 == ~M_E~0); 20444#L344-2 assume !(0 == ~T1_E~0); 20621#L349-1 assume !(0 == ~T2_E~0); 20463#L354-1 assume !(0 == ~E_M~0); 20464#L359-1 assume !(0 == ~E_1~0); 20458#L364-1 assume !(0 == ~E_2~0); 20459#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20546#L166 assume !(1 == ~m_pc~0); 20547#L166-2 is_master_triggered_~__retres1~0#1 := 0; 20634#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20441#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20442#L425 assume !(0 != activate_threads_~tmp~1#1); 20670#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20558#L185 assume !(1 == ~t1_pc~0); 20469#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20470#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20507#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20514#L433 assume !(0 != activate_threads_~tmp___0~0#1); 20515#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20573#L204 assume !(1 == ~t2_pc~0); 20556#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20557#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20591#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20424#L441 assume !(0 != activate_threads_~tmp___1~0#1); 20425#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20549#L382 assume !(1 == ~M_E~0); 20412#L382-2 assume !(1 == ~T1_E~0); 20413#L387-1 assume !(1 == ~T2_E~0); 20532#L392-1 assume !(1 == ~E_M~0); 20562#L397-1 assume !(1 == ~E_1~0); 20563#L402-1 assume !(1 == ~E_2~0); 20550#L407-1 assume { :end_inline_reset_delta_events } true; 20551#L553-2 [2021-12-07 01:43:53,957 INFO L793 eck$LassoCheckResult]: Loop: 20551#L553-2 assume !false; 21014#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21011#L319 assume !false; 21010#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21009#L254 assume !(0 == ~m_st~0); 21008#L258 assume !(0 == ~t1_st~0); 21005#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 21003#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21001#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20996#L286 assume !(0 != eval_~tmp~0#1); 20992#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20987#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20981#L344-3 assume !(0 == ~M_E~0); 20982#L344-5 assume !(0 == ~T1_E~0); 20972#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20973#L354-3 assume !(0 == ~E_M~0); 20968#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20969#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20955#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20956#L166-12 assume !(1 == ~m_pc~0); 20921#L166-14 is_master_triggered_~__retres1~0#1 := 0; 20922#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20915#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20916#L425-12 assume !(0 != activate_threads_~tmp~1#1); 20910#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20906#L185-12 assume !(1 == ~t1_pc~0); 20907#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 20886#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20887#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20878#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20879#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20871#L204-12 assume !(1 == ~t2_pc~0); 20869#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 20867#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20865#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20863#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20861#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20859#L382-3 assume !(1 == ~M_E~0); 20858#L382-5 assume !(1 == ~T1_E~0); 21088#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21087#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21086#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21085#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21084#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21042#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21041#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21040#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21039#L572 assume !(0 == start_simulation_~tmp~3#1); 21037#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21035#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21033#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21032#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21030#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21028#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21025#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21024#L585 assume !(0 != start_simulation_~tmp___0~1#1); 20551#L553-2 [2021-12-07 01:43:53,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2021-12-07 01:43:53,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717024182] [2021-12-07 01:43:53,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,962 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:53,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:53,971 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:53,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:53,971 INFO L85 PathProgramCache]: Analyzing trace with hash -132818663, now seen corresponding path program 1 times [2021-12-07 01:43:53,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:53,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509069339] [2021-12-07 01:43:53,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:53,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:53,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:53,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:53,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:53,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509069339] [2021-12-07 01:43:53,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509069339] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:53,988 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:53,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:53,988 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194453976] [2021-12-07 01:43:53,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:53,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 01:43:53,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:53,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:53,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:53,989 INFO L87 Difference]: Start difference. First operand 1253 states and 1737 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:54,014 INFO L93 Difference]: Finished difference Result 1866 states and 2547 transitions. [2021-12-07 01:43:54,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:54,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1866 states and 2547 transitions. [2021-12-07 01:43:54,021 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1821 [2021-12-07 01:43:54,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1866 states to 1866 states and 2547 transitions. [2021-12-07 01:43:54,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1866 [2021-12-07 01:43:54,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1866 [2021-12-07 01:43:54,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1866 states and 2547 transitions. [2021-12-07 01:43:54,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:54,035 INFO L681 BuchiCegarLoop]: Abstraction has 1866 states and 2547 transitions. [2021-12-07 01:43:54,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1866 states and 2547 transitions. [2021-12-07 01:43:54,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1866 to 1804. [2021-12-07 01:43:54,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1804 states to 1804 states and 2465 transitions. [2021-12-07 01:43:54,062 INFO L704 BuchiCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2021-12-07 01:43:54,062 INFO L587 BuchiCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2021-12-07 01:43:54,062 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-07 01:43:54,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1804 states and 2465 transitions. [2021-12-07 01:43:54,066 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1759 [2021-12-07 01:43:54,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:54,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:54,067 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,067 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,067 INFO L791 eck$LassoCheckResult]: Stem: 23804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 23749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 23750#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23776#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23651#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 23518#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23519#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23714#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23567#L344 assume !(0 == ~M_E~0); 23568#L344-2 assume !(0 == ~T1_E~0); 23743#L349-1 assume !(0 == ~T2_E~0); 23587#L354-1 assume !(0 == ~E_M~0); 23588#L359-1 assume !(0 == ~E_1~0); 23582#L364-1 assume !(0 == ~E_2~0); 23583#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23672#L166 assume !(1 == ~m_pc~0); 23673#L166-2 is_master_triggered_~__retres1~0#1 := 0; 23756#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23565#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23566#L425 assume !(0 != activate_threads_~tmp~1#1); 23793#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23684#L185 assume !(1 == ~t1_pc~0); 23593#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23594#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23632#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23639#L433 assume !(0 != activate_threads_~tmp___0~0#1); 23640#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23697#L204 assume !(1 == ~t2_pc~0); 23682#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23683#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23716#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23550#L441 assume !(0 != activate_threads_~tmp___1~0#1); 23551#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23675#L382 assume !(1 == ~M_E~0); 23538#L382-2 assume !(1 == ~T1_E~0); 23539#L387-1 assume !(1 == ~T2_E~0); 23656#L392-1 assume !(1 == ~E_M~0); 23688#L397-1 assume !(1 == ~E_1~0); 23689#L402-1 assume !(1 == ~E_2~0); 23676#L407-1 assume { :end_inline_reset_delta_events } true; 23677#L553-2 assume !false; 24392#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24350#L319 [2021-12-07 01:43:54,067 INFO L793 eck$LassoCheckResult]: Loop: 24350#L319 assume !false; 24388#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24384#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24379#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24375#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 24369#L286 assume 0 != eval_~tmp~0#1; 24363#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24359#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 24355#L291 assume !(0 == ~t1_st~0); 24351#L305 assume !(0 == ~t2_st~0); 24350#L319 [2021-12-07 01:43:54,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,067 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2021-12-07 01:43:54,068 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516847751] [2021-12-07 01:43:54,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,073 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,082 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,082 INFO L85 PathProgramCache]: Analyzing trace with hash 698755222, now seen corresponding path program 1 times [2021-12-07 01:43:54,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610710719] [2021-12-07 01:43:54,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,085 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,088 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1780390720, now seen corresponding path program 1 times [2021-12-07 01:43:54,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352764964] [2021-12-07 01:43:54,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:54,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:54,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:54,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352764964] [2021-12-07 01:43:54,108 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352764964] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:54,108 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:54,108 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:54,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161423991] [2021-12-07 01:43:54,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:54,155 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:54,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:54,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:54,155 INFO L87 Difference]: Start difference. First operand 1804 states and 2465 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:54,193 INFO L93 Difference]: Finished difference Result 3072 states and 4139 transitions. [2021-12-07 01:43:54,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:54,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3072 states and 4139 transitions. [2021-12-07 01:43:54,209 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2988 [2021-12-07 01:43:54,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3072 states to 3072 states and 4139 transitions. [2021-12-07 01:43:54,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3072 [2021-12-07 01:43:54,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3072 [2021-12-07 01:43:54,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3072 states and 4139 transitions. [2021-12-07 01:43:54,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:54,240 INFO L681 BuchiCegarLoop]: Abstraction has 3072 states and 4139 transitions. [2021-12-07 01:43:54,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3072 states and 4139 transitions. [2021-12-07 01:43:54,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3072 to 2925. [2021-12-07 01:43:54,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2925 states to 2925 states and 3964 transitions. [2021-12-07 01:43:54,308 INFO L704 BuchiCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2021-12-07 01:43:54,308 INFO L587 BuchiCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2021-12-07 01:43:54,308 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-07 01:43:54,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2925 states and 3964 transitions. [2021-12-07 01:43:54,317 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2021-12-07 01:43:54,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:54,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:54,318 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,318 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,318 INFO L791 eck$LassoCheckResult]: Stem: 28695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 28640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28641#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28664#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28537#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 28402#L231-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 28403#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28607#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28454#L344 assume !(0 == ~M_E~0); 28455#L344-2 assume !(0 == ~T1_E~0); 28635#L349-1 assume !(0 == ~T2_E~0); 28473#L354-1 assume !(0 == ~E_M~0); 28474#L359-1 assume !(0 == ~E_1~0); 28468#L364-1 assume !(0 == ~E_2~0); 28469#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28558#L166 assume !(1 == ~m_pc~0); 28559#L166-2 is_master_triggered_~__retres1~0#1 := 0; 28646#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28452#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28453#L425 assume !(0 != activate_threads_~tmp~1#1); 28685#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28700#L185 assume !(1 == ~t1_pc~0); 30352#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30351#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28530#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28525#L433 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28526#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28586#L204 assume !(1 == ~t2_pc~0); 28587#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28609#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28610#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28433#L441 assume !(0 != activate_threads_~tmp___1~0#1); 28434#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28594#L382 assume !(1 == ~M_E~0); 28595#L382-2 assume !(1 == ~T1_E~0); 28542#L387-1 assume !(1 == ~T2_E~0); 28543#L392-1 assume !(1 == ~E_M~0); 28574#L397-1 assume !(1 == ~E_1~0); 28575#L402-1 assume !(1 == ~E_2~0); 30320#L407-1 assume { :end_inline_reset_delta_events } true; 30318#L553-2 assume !false; 30298#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30290#L319 [2021-12-07 01:43:54,319 INFO L793 eck$LassoCheckResult]: Loop: 30290#L319 assume !false; 30287#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 30283#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 30278#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 30275#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30273#L286 assume 0 != eval_~tmp~0#1; 30268#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 30264#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 30265#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30313#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 30297#L305 assume !(0 == ~t2_st~0); 30290#L319 [2021-12-07 01:43:54,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,319 INFO L85 PathProgramCache]: Analyzing trace with hash -1720071637, now seen corresponding path program 1 times [2021-12-07 01:43:54,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723957887] [2021-12-07 01:43:54,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:54,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:54,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:54,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723957887] [2021-12-07 01:43:54,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723957887] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:54,335 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:54,335 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 01:43:54,335 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051086678] [2021-12-07 01:43:54,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:54,335 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 01:43:54,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,336 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 1 times [2021-12-07 01:43:54,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434748599] [2021-12-07 01:43:54,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,339 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,343 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:54,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:54,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:54,394 INFO L87 Difference]: Start difference. First operand 2925 states and 3964 transitions. cyclomatic complexity: 1042 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:54,407 INFO L93 Difference]: Finished difference Result 2888 states and 3915 transitions. [2021-12-07 01:43:54,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:54,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2888 states and 3915 transitions. [2021-12-07 01:43:54,416 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2021-12-07 01:43:54,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2888 states to 2888 states and 3915 transitions. [2021-12-07 01:43:54,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2888 [2021-12-07 01:43:54,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2888 [2021-12-07 01:43:54,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2888 states and 3915 transitions. [2021-12-07 01:43:54,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:54,436 INFO L681 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2021-12-07 01:43:54,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2888 states and 3915 transitions. [2021-12-07 01:43:54,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2888 to 2888. [2021-12-07 01:43:54,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2888 states to 2888 states and 3915 transitions. [2021-12-07 01:43:54,473 INFO L704 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2021-12-07 01:43:54,473 INFO L587 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2021-12-07 01:43:54,473 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-07 01:43:54,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2888 states and 3915 transitions. [2021-12-07 01:43:54,479 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2021-12-07 01:43:54,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:54,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:54,480 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,480 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,480 INFO L791 eck$LassoCheckResult]: Stem: 34492#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 34447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 34448#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34472#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34356#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 34221#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34222#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34418#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34272#L344 assume !(0 == ~M_E~0); 34273#L344-2 assume !(0 == ~T1_E~0); 34441#L349-1 assume !(0 == ~T2_E~0); 34291#L354-1 assume !(0 == ~E_M~0); 34292#L359-1 assume !(0 == ~E_1~0); 34286#L364-1 assume !(0 == ~E_2~0); 34287#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34373#L166 assume !(1 == ~m_pc~0); 34374#L166-2 is_master_triggered_~__retres1~0#1 := 0; 34452#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34270#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 34271#L425 assume !(0 != activate_threads_~tmp~1#1); 34486#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34384#L185 assume !(1 == ~t1_pc~0); 34297#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34298#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34336#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34341#L433 assume !(0 != activate_threads_~tmp___0~0#1); 34342#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34400#L204 assume !(1 == ~t2_pc~0); 34382#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34383#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34421#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34251#L441 assume !(0 != activate_threads_~tmp___1~0#1); 34252#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34376#L382 assume !(1 == ~M_E~0); 34240#L382-2 assume !(1 == ~T1_E~0); 34241#L387-1 assume !(1 == ~T2_E~0); 34360#L392-1 assume !(1 == ~E_M~0); 34390#L397-1 assume !(1 == ~E_1~0); 34391#L402-1 assume !(1 == ~E_2~0); 34379#L407-1 assume { :end_inline_reset_delta_events } true; 34380#L553-2 assume !false; 35438#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35434#L319 [2021-12-07 01:43:54,480 INFO L793 eck$LassoCheckResult]: Loop: 35434#L319 assume !false; 35431#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35429#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 35427#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35426#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 35425#L286 assume 0 != eval_~tmp~0#1; 35423#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 35421#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 35422#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 35074#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 35437#L305 assume !(0 == ~t2_st~0); 35434#L319 [2021-12-07 01:43:54,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,481 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 2 times [2021-12-07 01:43:54,481 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108834950] [2021-12-07 01:43:54,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,487 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,497 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,497 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 2 times [2021-12-07 01:43:54,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315751955] [2021-12-07 01:43:54,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,498 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,501 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,504 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,505 INFO L85 PathProgramCache]: Analyzing trace with hash -642569318, now seen corresponding path program 1 times [2021-12-07 01:43:54,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693910032] [2021-12-07 01:43:54,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 01:43:54,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 01:43:54,524 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 01:43:54,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693910032] [2021-12-07 01:43:54,524 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693910032] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 01:43:54,524 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 01:43:54,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 01:43:54,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228272748] [2021-12-07 01:43:54,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 01:43:54,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 01:43:54,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 01:43:54,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 01:43:54,574 INFO L87 Difference]: Start difference. First operand 2888 states and 3915 transitions. cyclomatic complexity: 1030 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 01:43:54,607 INFO L93 Difference]: Finished difference Result 4907 states and 6588 transitions. [2021-12-07 01:43:54,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 01:43:54,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4907 states and 6588 transitions. [2021-12-07 01:43:54,623 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4856 [2021-12-07 01:43:54,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4907 states to 4907 states and 6588 transitions. [2021-12-07 01:43:54,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4907 [2021-12-07 01:43:54,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4907 [2021-12-07 01:43:54,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4907 states and 6588 transitions. [2021-12-07 01:43:54,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 01:43:54,661 INFO L681 BuchiCegarLoop]: Abstraction has 4907 states and 6588 transitions. [2021-12-07 01:43:54,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4907 states and 6588 transitions. [2021-12-07 01:43:54,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4907 to 4851. [2021-12-07 01:43:54,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 01:43:54,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4851 states to 4851 states and 6532 transitions. [2021-12-07 01:43:54,735 INFO L704 BuchiCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2021-12-07 01:43:54,735 INFO L587 BuchiCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2021-12-07 01:43:54,735 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-07 01:43:54,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4851 states and 6532 transitions. [2021-12-07 01:43:54,749 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4800 [2021-12-07 01:43:54,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 01:43:54,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 01:43:54,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 01:43:54,750 INFO L791 eck$LassoCheckResult]: Stem: 42306#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 42255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 42256#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42281#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42157#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 42024#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42025#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42223#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42073#L344 assume !(0 == ~M_E~0); 42074#L344-2 assume !(0 == ~T1_E~0); 42250#L349-1 assume !(0 == ~T2_E~0); 42093#L354-1 assume !(0 == ~E_M~0); 42094#L359-1 assume !(0 == ~E_1~0); 42088#L364-1 assume !(0 == ~E_2~0); 42089#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42176#L166 assume !(1 == ~m_pc~0); 42177#L166-2 is_master_triggered_~__retres1~0#1 := 0; 42264#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42071#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 42072#L425 assume !(0 != activate_threads_~tmp~1#1); 42301#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42188#L185 assume !(1 == ~t1_pc~0); 42099#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42100#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42138#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42143#L433 assume !(0 != activate_threads_~tmp___0~0#1); 42144#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42206#L204 assume !(1 == ~t2_pc~0); 42186#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42187#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42225#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42054#L441 assume !(0 != activate_threads_~tmp___1~0#1); 42055#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42179#L382 assume !(1 == ~M_E~0); 42043#L382-2 assume !(1 == ~T1_E~0); 42044#L387-1 assume !(1 == ~T2_E~0); 42161#L392-1 assume !(1 == ~E_M~0); 42195#L397-1 assume !(1 == ~E_1~0); 42196#L402-1 assume !(1 == ~E_2~0); 42182#L407-1 assume { :end_inline_reset_delta_events } true; 42183#L553-2 assume !false; 44866#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44861#L319 [2021-12-07 01:43:54,750 INFO L793 eck$LassoCheckResult]: Loop: 44861#L319 assume !false; 44857#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 44851#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 44839#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 44836#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44831#L286 assume 0 != eval_~tmp~0#1; 44823#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 44814#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 44808#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 44776#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 44804#L305 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 43328#L322 assume !(0 != eval_~tmp_ndt_3~0#1); 44861#L319 [2021-12-07 01:43:54,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,750 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 3 times [2021-12-07 01:43:54,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466904014] [2021-12-07 01:43:54,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,757 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,767 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1485556888, now seen corresponding path program 1 times [2021-12-07 01:43:54,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163033455] [2021-12-07 01:43:54,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,772 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,775 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:54,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 01:43:54,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1555184834, now seen corresponding path program 1 times [2021-12-07 01:43:54,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 01:43:54,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305659127] [2021-12-07 01:43:54,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 01:43:54,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 01:43:54,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,782 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 01:43:54,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 01:43:54,793 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 01:43:55,314 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 01:43:55 BoogieIcfgContainer [2021-12-07 01:43:55,314 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-07 01:43:55,314 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-07 01:43:55,314 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-07 01:43:55,314 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-07 01:43:55,315 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:43:52" (3/4) ... [2021-12-07 01:43:55,317 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-07 01:43:55,348 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-07 01:43:55,348 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-07 01:43:55,349 INFO L158 Benchmark]: Toolchain (without parser) took 4074.64ms. Allocated memory was 132.1MB in the beginning and 211.8MB in the end (delta: 79.7MB). Free memory was 94.6MB in the beginning and 62.4MB in the end (delta: 32.2MB). Peak memory consumption was 112.6MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,349 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 132.1MB. Free memory is still 111.5MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-07 01:43:55,349 INFO L158 Benchmark]: CACSL2BoogieTranslator took 224.24ms. Allocated memory is still 132.1MB. Free memory was 94.4MB in the beginning and 81.3MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,349 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.58ms. Allocated memory is still 132.1MB. Free memory was 81.2MB in the beginning and 78.2MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,350 INFO L158 Benchmark]: Boogie Preprocessor took 43.89ms. Allocated memory is still 132.1MB. Free memory was 78.1MB in the beginning and 75.8MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,350 INFO L158 Benchmark]: RCFGBuilder took 496.19ms. Allocated memory is still 132.1MB. Free memory was 75.7MB in the beginning and 86.9MB in the end (delta: -11.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,350 INFO L158 Benchmark]: BuchiAutomizer took 3231.87ms. Allocated memory was 132.1MB in the beginning and 211.8MB in the end (delta: 79.7MB). Free memory was 86.9MB in the beginning and 65.5MB in the end (delta: 21.4MB). Peak memory consumption was 102.6MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,350 INFO L158 Benchmark]: Witness Printer took 33.88ms. Allocated memory is still 211.8MB. Free memory was 65.5MB in the beginning and 62.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-07 01:43:55,352 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 132.1MB. Free memory is still 111.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 224.24ms. Allocated memory is still 132.1MB. Free memory was 94.4MB in the beginning and 81.3MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 39.58ms. Allocated memory is still 132.1MB. Free memory was 81.2MB in the beginning and 78.2MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.89ms. Allocated memory is still 132.1MB. Free memory was 78.1MB in the beginning and 75.8MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 496.19ms. Allocated memory is still 132.1MB. Free memory was 75.7MB in the beginning and 86.9MB in the end (delta: -11.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 3231.87ms. Allocated memory was 132.1MB in the beginning and 211.8MB in the end (delta: 79.7MB). Free memory was 86.9MB in the beginning and 65.5MB in the end (delta: 21.4MB). Peak memory consumption was 102.6MB. Max. memory is 16.1GB. * Witness Printer took 33.88ms. Allocated memory is still 211.8MB. Free memory was 65.5MB in the beginning and 62.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4851 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.1s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 14 MinimizatonAttempts, 3980 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 4851 states and ocurred in iteration 14. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6248 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6248 mSDsluCounter, 10093 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5063 mSDsCounter, 126 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 381 IncrementalHoareTripleChecker+Invalid, 507 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 126 mSolverCounterUnsat, 5030 mSDtfsCounter, 381 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 281]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3b950c4f=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7202a8d4=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a6caa06=0, tmp_ndt_2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c819d45=0, E_1=2, __retres1=1, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@630f18de=0, \result=0, m_st=0, NULL=0, __retres1=0, tmp___0=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49888516=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67c3aeac=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72826f64=0, __retres1=0, M_E=2, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ec36712=0, t1_st=0, __retres1=0, local=0, t2_pc=0, E_M=2, kernel_st=1, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 281]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; [L598] int __retres1 ; [L602] CALL init_model() [L512] m_i = 1 [L513] t1_i = 1 [L514] t2_i = 1 [L602] RET init_model() [L603] CALL start_simulation() [L539] int kernel_st ; [L540] int tmp ; [L541] int tmp___0 ; [L545] kernel_st = 0 [L546] FCALL update_channels() [L547] CALL init_threads() [L231] COND TRUE m_i == 1 [L232] m_st = 0 [L236] COND TRUE t1_i == 1 [L237] t1_st = 0 [L241] COND TRUE t2_i == 1 [L242] t2_st = 0 [L547] RET init_threads() [L548] CALL fire_delta_events() [L344] COND FALSE !(M_E == 0) [L349] COND FALSE !(T1_E == 0) [L354] COND FALSE !(T2_E == 0) [L359] COND FALSE !(E_M == 0) [L364] COND FALSE !(E_1 == 0) [L369] COND FALSE !(E_2 == 0) [L548] RET fire_delta_events() [L549] CALL activate_threads() [L417] int tmp ; [L418] int tmp___0 ; [L419] int tmp___1 ; [L423] CALL, EXPR is_master_triggered() [L163] int __retres1 ; [L166] COND FALSE !(m_pc == 1) [L176] __retres1 = 0 [L178] return (__retres1); [L423] RET, EXPR is_master_triggered() [L423] tmp = is_master_triggered() [L425] COND FALSE !(\read(tmp)) [L431] CALL, EXPR is_transmit1_triggered() [L182] int __retres1 ; [L185] COND FALSE !(t1_pc == 1) [L195] __retres1 = 0 [L197] return (__retres1); [L431] RET, EXPR is_transmit1_triggered() [L431] tmp___0 = is_transmit1_triggered() [L433] COND FALSE !(\read(tmp___0)) [L439] CALL, EXPR is_transmit2_triggered() [L201] int __retres1 ; [L204] COND FALSE !(t2_pc == 1) [L214] __retres1 = 0 [L216] return (__retres1); [L439] RET, EXPR is_transmit2_triggered() [L439] tmp___1 = is_transmit2_triggered() [L441] COND FALSE !(\read(tmp___1)) [L549] RET activate_threads() [L550] CALL reset_delta_events() [L382] COND FALSE !(M_E == 1) [L387] COND FALSE !(T1_E == 1) [L392] COND FALSE !(T2_E == 1) [L397] COND FALSE !(E_M == 1) [L402] COND FALSE !(E_1 == 1) [L407] COND FALSE !(E_2 == 1) [L550] RET reset_delta_events() [L553] COND TRUE 1 [L556] kernel_st = 1 [L557] CALL eval() [L277] int tmp ; Loop: [L281] COND TRUE 1 [L284] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE m_st == 0 [L255] __retres1 = 1 [L272] return (__retres1); [L284] RET, EXPR exists_runnable_thread() [L284] tmp = exists_runnable_thread() [L286] COND TRUE \read(tmp) [L291] COND TRUE m_st == 0 [L292] int tmp_ndt_1; [L293] tmp_ndt_1 = __VERIFIER_nondet_int() [L294] COND FALSE !(\read(tmp_ndt_1)) [L305] COND TRUE t1_st == 0 [L306] int tmp_ndt_2; [L307] tmp_ndt_2 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp_ndt_2)) [L319] COND TRUE t2_st == 0 [L320] int tmp_ndt_3; [L321] tmp_ndt_3 = __VERIFIER_nondet_int() [L322] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-07 01:43:55,389 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b4d3b6a-1452-468c-ae7d-e79585db304f/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)